iPXE
params.h
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00001 /*
00002  * Permission is hereby granted, free of charge, to any person obtaining a copy
00003  * of this software and associated documentation files (the "Software"), to
00004  * deal in the Software without restriction, including without limitation the
00005  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
00006  * sell copies of the Software, and to permit persons to whom the Software is
00007  * furnished to do so, subject to the following conditions:
00008  *
00009  * The above copyright notice and this permission notice shall be included in
00010  * all copies or substantial portions of the Software.
00011  *
00012  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00013  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00014  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
00015  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00016  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
00017  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
00018  * DEALINGS IN THE SOFTWARE.
00019  */
00020 
00021 #ifndef __XEN_PUBLIC_HVM_PARAMS_H__
00022 #define __XEN_PUBLIC_HVM_PARAMS_H__
00023 
00024 FILE_LICENCE ( MIT );
00025 
00026 #include "hvm_op.h"
00027 
00028 /*
00029  * Parameter space for HVMOP_{set,get}_param.
00030  */
00031 
00032 /*
00033  * How should CPU0 event-channel notifications be delivered?
00034  * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).
00035  * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:
00036  *                  Domain = val[47:32], Bus  = val[31:16],
00037  *                  DevFn  = val[15: 8], IntX = val[ 1: 0]
00038  * val[63:56] == 2: val[7:0] is a vector number, check for
00039  *                  XENFEAT_hvm_callback_vector to know if this delivery
00040  *                  method is available.
00041  * If val == 0 then CPU0 event-channel notifications are not delivered.
00042  */
00043 #define HVM_PARAM_CALLBACK_IRQ 0
00044 
00045 /*
00046  * These are not used by Xen. They are here for convenience of HVM-guest
00047  * xenbus implementations.
00048  */
00049 #define HVM_PARAM_STORE_PFN    1
00050 #define HVM_PARAM_STORE_EVTCHN 2
00051 
00052 #define HVM_PARAM_PAE_ENABLED  4
00053 
00054 #define HVM_PARAM_IOREQ_PFN    5
00055 
00056 #define HVM_PARAM_BUFIOREQ_PFN 6
00057 #define HVM_PARAM_BUFIOREQ_EVTCHN 26
00058 
00059 #if defined(__i386__) || defined(__x86_64__)
00060 
00061 /* Expose Viridian interfaces to this HVM guest? */
00062 #define HVM_PARAM_VIRIDIAN     9
00063 
00064 #endif
00065 
00066 /*
00067  * Set mode for virtual timers (currently x86 only):
00068  *  delay_for_missed_ticks (default):
00069  *   Do not advance a vcpu's time beyond the correct delivery time for
00070  *   interrupts that have been missed due to preemption. Deliver missed
00071  *   interrupts when the vcpu is rescheduled and advance the vcpu's virtual
00072  *   time stepwise for each one.
00073  *  no_delay_for_missed_ticks:
00074  *   As above, missed interrupts are delivered, but guest time always tracks
00075  *   wallclock (i.e., real) time while doing so.
00076  *  no_missed_ticks_pending:
00077  *   No missed interrupts are held pending. Instead, to ensure ticks are
00078  *   delivered at some non-zero rate, if we detect missed ticks then the
00079  *   internal tick alarm is not disabled if the VCPU is preempted during the
00080  *   next tick period.
00081  *  one_missed_tick_pending:
00082  *   Missed interrupts are collapsed together and delivered as one 'late tick'.
00083  *   Guest time always tracks wallclock (i.e., real) time.
00084  */
00085 #define HVM_PARAM_TIMER_MODE   10
00086 #define HVMPTM_delay_for_missed_ticks    0
00087 #define HVMPTM_no_delay_for_missed_ticks 1
00088 #define HVMPTM_no_missed_ticks_pending   2
00089 #define HVMPTM_one_missed_tick_pending   3
00090 
00091 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
00092 #define HVM_PARAM_HPET_ENABLED 11
00093 
00094 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
00095 #define HVM_PARAM_IDENT_PT     12
00096 
00097 /* Device Model domain, defaults to 0. */
00098 #define HVM_PARAM_DM_DOMAIN    13
00099 
00100 /* ACPI S state: currently support S0 and S3 on x86. */
00101 #define HVM_PARAM_ACPI_S_STATE 14
00102 
00103 /* TSS used on Intel when CR0.PE=0. */
00104 #define HVM_PARAM_VM86_TSS     15
00105 
00106 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
00107 #define HVM_PARAM_VPT_ALIGN    16
00108 
00109 /* Console debug shared memory ring and event channel */
00110 #define HVM_PARAM_CONSOLE_PFN    17
00111 #define HVM_PARAM_CONSOLE_EVTCHN 18
00112 
00113 /*
00114  * Select location of ACPI PM1a and TMR control blocks. Currently two locations
00115  * are supported, specified by version 0 or 1 in this parameter:
00116  *   - 0: default, use the old addresses
00117  *        PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48
00118  *   - 1: use the new default qemu addresses
00119  *        PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008
00120  * You can find these address definitions in <hvm/ioreq.h>
00121  */
00122 #define HVM_PARAM_ACPI_IOPORTS_LOCATION 19
00123 
00124 /* Enable blocking memory events, async or sync (pause vcpu until response)
00125  * onchangeonly indicates messages only on a change of value */
00126 #define HVM_PARAM_MEMORY_EVENT_CR0          20
00127 #define HVM_PARAM_MEMORY_EVENT_CR3          21
00128 #define HVM_PARAM_MEMORY_EVENT_CR4          22
00129 #define HVM_PARAM_MEMORY_EVENT_INT3         23
00130 #define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP  25
00131 #define HVM_PARAM_MEMORY_EVENT_MSR          30
00132 
00133 #define HVMPME_MODE_MASK       (3 << 0)
00134 #define HVMPME_mode_disabled   0
00135 #define HVMPME_mode_async      1
00136 #define HVMPME_mode_sync       2
00137 #define HVMPME_onchangeonly    (1 << 2)
00138 
00139 /* Boolean: Enable nestedhvm (hvm only) */
00140 #define HVM_PARAM_NESTEDHVM    24
00141 
00142 /* Params for the mem event rings */
00143 #define HVM_PARAM_PAGING_RING_PFN   27
00144 #define HVM_PARAM_ACCESS_RING_PFN   28
00145 #define HVM_PARAM_SHARING_RING_PFN  29
00146 
00147 /* SHUTDOWN_* action in case of a triple fault */
00148 #define HVM_PARAM_TRIPLE_FAULT_REASON 31
00149 
00150 #define HVM_PARAM_IOREQ_SERVER_PFN 32
00151 #define HVM_PARAM_NR_IOREQ_SERVER_PAGES 33
00152 
00153 /* Location of the VM Generation ID in guest physical address space. */
00154 #define HVM_PARAM_VM_GENERATION_ID_ADDR 34
00155 
00156 #define HVM_NR_PARAMS          35
00157 
00158 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */