iPXE
Data Structures | Defines | Enumerations | Functions
xhci.h File Reference

USB eXtensible Host Controller Interface (xHCI) driver. More...

#include <assert.h>
#include <ipxe/pci.h>
#include <ipxe/uaccess.h>
#include <ipxe/usb.h>

Go to the source code of this file.

Data Structures

struct  xhci_trb_template
 A transfer request block template. More...
struct  xhci_trb_common
 A transfer request block. More...
struct  xhci_trb_normal
 A normal transfer request block. More...
struct  xhci_trb_setup
 A setup stage transfer request block. More...
struct  xhci_trb_data
 A data stage transfer request block. More...
struct  xhci_trb_status
 A status stage transfer request block. More...
struct  xhci_trb_link
 A link transfer request block. More...
struct  xhci_trb_enable_slot
 An enable slot transfer request block. More...
struct  xhci_trb_disable_slot
 A disable slot transfer request block. More...
struct  xhci_trb_context
 A context transfer request block. More...
struct  xhci_trb_reset_endpoint
 A reset endpoint transfer request block. More...
struct  xhci_trb_stop_endpoint
 A stop endpoint transfer request block. More...
struct  xhci_trb_set_tr_dequeue_pointer
 A set transfer ring dequeue pointer transfer request block. More...
struct  xhci_trb_transfer
 A transfer event transfer request block. More...
struct  xhci_trb_complete
 A command completion event transfer request block. More...
struct  xhci_trb_port_status
 A port status change transfer request block. More...
struct  xhci_trb_host_controller
 A port status change transfer request block. More...
union  xhci_trb
 A transfer request block. More...
struct  xhci_control_context
 An input control context. More...
struct  xhci_slot_context
 A slot context. More...
struct  xhci_endpoint_context
 An endpoint context. More...
struct  xhci_event_ring_segment
 An event ring segment. More...
struct  xhci_trb_ring
 A transfer request block command/transfer ring. More...
struct  xhci_event_ring
 An event ring. More...
struct  xhci_pch
 Intel PCH quirk. More...
struct  xhci_device
 An xHCI device. More...
struct  xhci_slot
 An xHCI device slot. More...
struct  xhci_endpoint
 An xHCI endpoint. More...

Defines

#define XHCI_MIN_ALIGN   64
 Minimum alignment required for data structures.
#define XHCI_MTU   65536
 Maximum transfer size.
#define XHCI_BAR   PCI_BASE_ADDRESS_0
 xHCI PCI BAR
#define XHCI_CAP_CAPLENGTH   0x00
 Capability register length.
#define XHCI_CAP_HCIVERSION   0x02
 Host controller interface version number.
#define XHCI_CAP_HCSPARAMS1   0x04
 Structural parameters 1.
#define XHCI_HCSPARAMS1_SLOTS(params)   ( ( (params) >> 0 ) & 0xff )
 Number of device slots.
#define XHCI_HCSPARAMS1_INTRS(params)   ( ( (params) >> 8 ) & 0x3ff )
 Number of interrupters.
#define XHCI_HCSPARAMS1_PORTS(params)   ( ( (params) >> 24 ) & 0xff )
 Number of ports.
#define XHCI_CAP_HCSPARAMS2   0x08
 Structural parameters 2.
#define XHCI_HCSPARAMS2_SCRATCHPADS(params)   ( ( ( (params) >> 16 ) & 0x3e0 ) | ( ( (params) >> 27 ) & 0x1f ) )
 Number of page-sized scratchpad buffers.
#define XHCI_CAP_HCCPARAMS1   0x10
 Capability parameters.
#define XHCI_HCCPARAMS1_ADDR64(params)   ( ( (params) >> 0 ) & 0x1 )
 64-bit addressing capability
#define XHCI_HCCPARAMS1_CSZ_SHIFT(params)   ( 5 + ( ( (params) >> 2 ) & 0x1 ) )
 Context size shift.
#define XHCI_HCCPARAMS1_XECP(params)   ( ( ( (params) >> 16 ) & 0xffff ) << 2 )
 xHCI extended capabilities pointer
#define XHCI_CAP_DBOFF   0x14
 Doorbell offset.
#define XHCI_CAP_RTSOFF   0x18
 Runtime register space offset.
#define XHCI_XECP_ID(xecp)   ( ( (xecp) >> 0 ) & 0xff )
 xHCI extended capability ID
#define XHCI_XECP_NEXT(xecp)   ( ( ( (xecp) >> 8 ) & 0xff ) << 2 )
 Next xHCI extended capability pointer.
#define XHCI_XECP_ID_LEGACY   1
 USB legacy support extended capability.
#define XHCI_USBLEGSUP_BIOS   0x02
 USB legacy support BIOS owned semaphore.
#define XHCI_USBLEGSUP_BIOS_OWNED   0x01
 USB legacy support BIOS ownership flag.
#define XHCI_USBLEGSUP_OS   0x03
 USB legacy support OS owned semaphore.
#define XHCI_USBLEGSUP_OS_OWNED   0x01
 USB legacy support OS ownership flag.
#define XHCI_USBLEGSUP_CTLSTS   0x04
 USB legacy support control/status.
#define XHCI_XECP_ID_SUPPORTED   2
 Supported protocol extended capability.
#define XHCI_SUPPORTED_REVISION   0x00
 Supported protocol revision.
#define XHCI_SUPPORTED_REVISION_VER(revision)   ( ( (revision) >> 16 ) & 0xffff )
 Supported protocol minor revision.
#define XHCI_SUPPORTED_NAME   0x04
 Supported protocol name.
#define XHCI_SUPPORTED_PORTS   0x08
 Supported protocol ports.
#define XHCI_SUPPORTED_PORTS_OFFSET(ports)   ( ( (ports) >> 0 ) & 0xff )
 Supported protocol port offset.
#define XHCI_SUPPORTED_PORTS_COUNT(ports)   ( ( (ports) >> 8 ) & 0xff )
 Supported protocol port count.
#define XHCI_SUPPORTED_PORTS_PSIC(ports)   ( ( (ports) >> 28 ) & 0x0f )
 Supported protocol PSI count.
#define XHCI_SUPPORTED_SLOT   0x0c
 Supported protocol slot.
#define XHCI_SUPPORTED_SLOT_TYPE(slot)   ( ( (slot) >> 0 ) & 0x1f )
 Supported protocol slot type.
#define XHCI_SUPPORTED_PSI(index)   ( 0x10 + ( (index) * 4 ) )
 Supported protocol PSI.
#define XHCI_SUPPORTED_PSI_VALUE(psi)   ( ( (psi) >> 0 ) & 0x0f )
 Supported protocol PSI value.
#define XHCI_SUPPORTED_PSI_MANTISSA(psi)   ( ( (psi) >> 16 ) & 0xffff )
 Supported protocol PSI mantissa.
#define XHCI_SUPPORTED_PSI_EXPONENT(psi)   ( ( (psi) >> 4 ) & 0x03 )
 Supported protocol PSI exponent.
#define XHCI_OP_USBCMD   0x00
 USB command register.
#define XHCI_USBCMD_RUN   0x00000001UL
 Run/stop.
#define XHCI_USBCMD_HCRST   0x00000002UL
 Host controller reset.
#define XHCI_OP_USBSTS   0x04
 USB status register.
#define XHCI_USBSTS_HCH   0x00000001UL
 Host controller halted.
#define XHCI_OP_PAGESIZE   0x08
 Page size register.
#define XHCI_PAGESIZE(pagesize)   ( (pagesize) << 12 )
 Page size.
#define XHCI_OP_DNCTRL   0x14
 Device notifcation control register.
#define XHCI_OP_CRCR   0x18
 Command ring control register.
#define XHCI_CRCR_RCS   0x00000001UL
 Command ring cycle state.
#define XHCI_CRCR_CA   0x00000004UL
 Command abort.
#define XHCI_CRCR_CRR   0x00000008UL
 Command ring running.
#define XHCI_OP_DCBAAP   0x30
 Device context base address array pointer.
#define XHCI_OP_CONFIG   0x38
 Configure register.
#define XHCI_CONFIG_MAX_SLOTS_EN(slots)   ( (slots) << 0 )
 Maximum device slots enabled.
#define XHCI_CONFIG_MAX_SLOTS_EN_MASK   XHCI_CONFIG_MAX_SLOTS_EN ( 0xff )
 Maximum device slots enabled mask.
#define XHCI_OP_PORTSC(port)   ( 0x400 - 0x10 + ( (port) << 4 ) )
 Port status and control register.
#define XHCI_PORTSC_CCS   0x00000001UL
 Current connect status.
#define XHCI_PORTSC_PED   0x00000002UL
 Port enabled.
#define XHCI_PORTSC_PR   0x00000010UL
 Port reset.
#define XHCI_PORTSC_PLS(pls)   ( (pls) << 5 )
 Port link state.
#define XHCI_PORTSC_PLS_DISABLED   XHCI_PORTSC_PLS ( 4 )
 Disabled port link state.
#define XHCI_PORTSC_PLS_RXDETECT   XHCI_PORTSC_PLS ( 5 )
 RxDetect port link state.
#define XHCI_PORTSC_PLS_MASK   XHCI_PORTSC_PLS ( 0xf )
 Port link state mask.
#define XHCI_PORTSC_PP   0x00000200UL
 Port power.
#define XHCI_PORT_POWER_DELAY_MS   20
 Time to delay after enabling power to a port.
#define XHCI_PORTSC_PSIV(portsc)   ( ( (portsc) >> 10 ) & 0xf )
 Port speed ID value.
#define XHCI_PORTSC_PIC(indicators)   ( (indicators) << 14 )
 Port indicator control.
#define XHCI_PORTSC_PIC_MASK   XHCI_PORTSC_PIC ( 3 )
 Port indicator control mask.
#define XHCI_PORTSC_LWS   0x00010000UL
 Port link state write strobe.
#define XHCI_LINK_STATE_DELAY_MS   20
 Time to delay after writing the port link state.
#define XHCI_PORTSC_CSC   0x00020000UL
 Connect status change.
#define XHCI_PORTSC_PEC   0x00040000UL
 Port enabled/disabled change.
#define XHCI_PORTSC_WRC   0x00080000UL
 Warm port reset change.
#define XHCI_PORTSC_OCC   0x00100000UL
 Over-current change.
#define XHCI_PORTSC_PRC   0x00200000UL
 Port reset change.
#define XHCI_PORTSC_PLC   0x00400000UL
 Port link state change.
#define XHCI_PORTSC_CEC   0x00800000UL
 Port config error change.
#define XHCI_PORTSC_CHANGE
 Port status change mask.
#define XHCI_PORTSC_PRESERVE   ( XHCI_PORTSC_PP | XHCI_PORTSC_PIC_MASK )
 Port status and control bits which should be preserved.
#define XHCI_OP_PORTPMSC(port)   ( 0x404 - 0x10 + ( (port) << 4 ) )
 Port power management status and control register.
#define XHCI_OP_PORTLI(port)   ( 0x408 - 0x10 + ( (port) << 4 ) )
 Port link info register.
#define XHCI_OP_PORTHLPMC(port)   ( 0x40c - 0x10 + ( (port) << 4 ) )
 Port hardware link power management control register.
#define XHCI_RUN_ERSTSZ(intr)   ( 0x28 + ( (intr) << 5 ) )
 Event ring segment table size register.
#define XHCI_RUN_ERSTBA(intr)   ( 0x30 + ( (intr) << 5 ) )
 Event ring segment table base address register.
#define XHCI_RUN_ERDP(intr)   ( 0x38 + ( (intr) << 5 ) )
 Event ring dequeue pointer register.
#define XHCI_TRB_C   0x01
 Transfer request block cycle bit flag.
#define XHCI_TRB_TC   0x02
 Transfer request block toggle cycle bit flag.
#define XHCI_TRB_CH   0x10
 Transfer request block chain flag.
#define XHCI_TRB_IOC   0x20
 Transfer request block interrupt on completion flag.
#define XHCI_TRB_IDT   0x40
 Transfer request block immediate data flag.
#define XHCI_TRB_TYPE(type)   ( (type) << 2 )
 Transfer request block type.
#define XHCI_TRB_TYPE_MASK   XHCI_TRB_TYPE ( 0x3f )
 Transfer request block type mask.
#define XHCI_TRB_NORMAL   XHCI_TRB_TYPE ( 1 )
 A normal transfer request block.
#define XHCI_TD_SIZE(remaining)   ( ( ( (remaining) <= 0xf ) ? remaining : 0xf ) << 17 )
 Construct TD size field.
#define XHCI_TRB_SETUP   XHCI_TRB_TYPE ( 2 )
 A setup stage transfer request block.
#define XHCI_SETUP_IN   3
 Setup stage input data direction.
#define XHCI_SETUP_OUT   2
 Setup stage output data direction.
#define XHCI_TRB_DATA   XHCI_TRB_TYPE ( 3 )
 A data stage transfer request block.
#define XHCI_DATA_IN   0x01
 Input data direction.
#define XHCI_DATA_OUT   0x00
 Output data direction.
#define XHCI_TRB_STATUS   XHCI_TRB_TYPE ( 4 )
 A status stage transfer request block.
#define XHCI_STATUS_IN   0x01
 Input status direction.
#define XHCI_STATUS_OUT   0x00
 Output status direction.
#define XHCI_TRB_LINK   XHCI_TRB_TYPE ( 6 )
 A link transfer request block.
#define XHCI_TRB_NOP   XHCI_TRB_TYPE ( 8 )
 A no-op transfer request block.
#define XHCI_TRB_ENABLE_SLOT   XHCI_TRB_TYPE ( 9 )
 An enable slot transfer request block.
#define XHCI_TRB_DISABLE_SLOT   XHCI_TRB_TYPE ( 10 )
 A disable slot transfer request block.
#define XHCI_TRB_ADDRESS_DEVICE   XHCI_TRB_TYPE ( 11 )
 An address device transfer request block.
#define XHCI_TRB_CONFIGURE_ENDPOINT   XHCI_TRB_TYPE ( 12 )
 A configure endpoint transfer request block.
#define XHCI_TRB_EVALUATE_CONTEXT   XHCI_TRB_TYPE ( 13 )
 An evaluate context transfer request block.
#define XHCI_TRB_RESET_ENDPOINT   XHCI_TRB_TYPE ( 14 )
 A reset endpoint transfer request block.
#define XHCI_TRB_STOP_ENDPOINT   XHCI_TRB_TYPE ( 15 )
 A stop endpoint transfer request block.
#define XHCI_TRB_SET_TR_DEQUEUE_POINTER   XHCI_TRB_TYPE ( 16 )
 A set transfer ring dequeue pointer transfer request block.
#define XHCI_TRB_NOP_CMD   XHCI_TRB_TYPE ( 23 )
 A no-op command transfer request block.
#define XHCI_TRB_TRANSFER   XHCI_TRB_TYPE ( 32 )
 A transfer event transfer request block.
#define XHCI_TRB_COMPLETE   XHCI_TRB_TYPE ( 33 )
 A command completion event transfer request block.
#define XHCI_TRB_PORT_STATUS   XHCI_TRB_TYPE ( 34 )
 A port status change transfer request block.
#define XHCI_TRB_HOST_CONTROLLER   XHCI_TRB_TYPE ( 37 )
 A port status change transfer request block.
#define XHCI_SLOT_INFO(entries, hub, speed, route)   ( ( (entries) << 27 ) | ( (hub) << 26 ) | ( (speed) << 20 ) | (route) )
 Construct slot context device info.
#define XHCI_ENDPOINT_STATE_MASK   0x07
 Endpoint state mask.
#define XHCI_EP_TYPE(type)   ( (type) << 3 )
 Endpoint type.
#define XHCI_EP_TYPE_CONTROL   XHCI_EP_TYPE ( 4 )
 Control endpoint type.
#define XHCI_EP_TYPE_IN   XHCI_EP_TYPE ( 4 )
 Input endpoint type.
#define XHCI_EP_TYPE_PERIODIC   XHCI_EP_TYPE ( 1 )
 Periodic endpoint type.
#define XHCI_EP_DCS   0x00000001UL
 Endpoint dequeue cycle state.
#define XHCI_EP0_TRB_LEN   8
 Control endpoint average TRB length.
#define XHCI_DBVAL(target, stream)   ( (target) | ( (stream) << 16 ) )
 Calculate doorbell register value.
#define XHCI_CTX_SLOT   0
 Slot context index.
#define XHCI_CTX(address)
 Calculate context index from USB endpoint address.
#define XHCI_CTX_EP0   XHCI_CTX ( 0x00 )
 Endpoint zero context index.
#define XHCI_CTX_END   32
 End of contexts.
#define XHCI_DCI(ctx)   ( (ctx) + 0 )
 Device context index.
#define XHCI_ICI(ctx)   ( (ctx) + 1 )
 Input context index.
#define XHCI_CMD_TRBS_LOG2   2
 Number of TRBs (excluding Link TRB) in the command ring.
#define XHCI_EVENT_TRBS_LOG2   6
 Number of TRBs in the event ring.
#define XHCI_TRANSFER_TRBS_LOG2   6
 Number of TRBs in a transfer ring.
#define XHCI_USBLEGSUP_MAX_WAIT_MS   100
 Maximum time to wait for BIOS to release ownership.
#define XHCI_STOP_MAX_WAIT_MS   100
 Maximum time to wait for host controller to stop.
#define XHCI_RESET_MAX_WAIT_MS   500
 Maximum time to wait for reset to complete.
#define XHCI_COMMAND_MAX_WAIT_MS   USB_CONTROL_MAX_WAIT_MS
 Maximum time to wait for a command to complete.
#define XHCI_COMMAND_ABORT_DELAY_MS   500
 Time to delay after aborting a command.
#define XHCI_PORT_RESET_MAX_WAIT_MS   500
 Maximum time to wait for a port reset to complete.
#define XHCI_PCH   0x0001
 Intel PCH quirk flag.
#define XHCI_PCH_XUSB2PR   0xd0
 Intel PCH USB2 port routing register.
#define XHCI_PCH_XUSB2PRM   0xd4
 Intel PCH USB2 port routing mask register.
#define XHCI_PCH_USB3PSSEN   0xd8
 Intel PCH SuperSpeed enable register.
#define XHCI_PCH_USB3PRM   0xdc
 Intel PCH USB3 port routing mask register.
#define XHCI_BAD_PSIV   0x0002
 Invalid protocol speed ID values quirk.

Enumerations

enum  xhci_default_psi_value { XHCI_SPEED_FULL = 1, XHCI_SPEED_LOW = 2, XHCI_SPEED_HIGH = 3, XHCI_SPEED_SUPER = 4 }
 Default PSI values. More...
enum  xhci_completion_code { XHCI_CMPLT_SUCCESS = 1, XHCI_CMPLT_SHORT = 13, XHCI_CMPLT_CMD_STOPPED = 24 }
 xHCI completion codes More...
enum  xhci_endpoint_state {
  XHCI_ENDPOINT_DISABLED = 0, XHCI_ENDPOINT_RUNNING = 1, XHCI_ENDPOINT_HALTED = 2, XHCI_ENDPOINT_STOPPED = 3,
  XHCI_ENDPOINT_ERROR = 4
}
 Endpoint states. More...

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
static unsigned int xhci_ring_fill (struct xhci_trb_ring *ring)
 Calculate space used in TRB ring.
static unsigned int xhci_ring_remaining (struct xhci_trb_ring *ring)
 Calculate space remaining in TRB ring.
static physaddr_t xhci_ring_consumed (struct xhci_trb_ring *ring)
 Calculate physical address of most recently consumed TRB.

Detailed Description

USB eXtensible Host Controller Interface (xHCI) driver.

Definition in file xhci.h.


Define Documentation

#define XHCI_MIN_ALIGN   64

Minimum alignment required for data structures.

With the exception of the scratchpad buffer pages (which are page-aligned), data structures used by xHCI generally require from 16 to 64 byte alignment and must not cross an (xHCI) page boundary. We simplify this requirement by aligning each structure on its own size, with a minimum of a 64 byte alignment.

Definition at line 25 of file xhci.h.

Referenced by xhci_align().

#define XHCI_MTU   65536

Maximum transfer size.

Definition at line 28 of file xhci.h.

Referenced by xhci_endpoint_count(), xhci_endpoint_stream(), and xhci_probe().

xHCI PCI BAR

Definition at line 31 of file xhci.h.

Referenced by xhci_probe().

#define XHCI_CAP_CAPLENGTH   0x00

Capability register length.

Definition at line 34 of file xhci.h.

Referenced by xhci_init().

#define XHCI_CAP_HCIVERSION   0x02

Host controller interface version number.

Definition at line 37 of file xhci.h.

#define XHCI_CAP_HCSPARAMS1   0x04

Structural parameters 1.

Definition at line 40 of file xhci.h.

Referenced by xhci_init().

#define XHCI_HCSPARAMS1_SLOTS (   params)    ( ( (params) >> 0 ) & 0xff )

Number of device slots.

Definition at line 43 of file xhci.h.

Referenced by xhci_init().

#define XHCI_HCSPARAMS1_INTRS (   params)    ( ( (params) >> 8 ) & 0x3ff )

Number of interrupters.

Definition at line 46 of file xhci.h.

Referenced by xhci_init().

#define XHCI_HCSPARAMS1_PORTS (   params)    ( ( (params) >> 24 ) & 0xff )

Number of ports.

Definition at line 49 of file xhci.h.

Referenced by xhci_init().

#define XHCI_CAP_HCSPARAMS2   0x08

Structural parameters 2.

Definition at line 52 of file xhci.h.

Referenced by xhci_init().

#define XHCI_HCSPARAMS2_SCRATCHPADS (   params)    ( ( ( (params) >> 16 ) & 0x3e0 ) | ( ( (params) >> 27 ) & 0x1f ) )

Number of page-sized scratchpad buffers.

Definition at line 55 of file xhci.h.

Referenced by xhci_init().

#define XHCI_CAP_HCCPARAMS1   0x10

Capability parameters.

Definition at line 59 of file xhci.h.

Referenced by xhci_init().

#define XHCI_HCCPARAMS1_ADDR64 (   params)    ( ( (params) >> 0 ) & 0x1 )

64-bit addressing capability

Definition at line 62 of file xhci.h.

Referenced by xhci_init().

#define XHCI_HCCPARAMS1_CSZ_SHIFT (   params)    ( 5 + ( ( (params) >> 2 ) & 0x1 ) )

Context size shift.

Definition at line 65 of file xhci.h.

Referenced by xhci_init().

#define XHCI_HCCPARAMS1_XECP (   params)    ( ( ( (params) >> 16 ) & 0xffff ) << 2 )

xHCI extended capabilities pointer

Definition at line 68 of file xhci.h.

Referenced by xhci_init().

#define XHCI_CAP_DBOFF   0x14

Doorbell offset.

Definition at line 71 of file xhci.h.

Referenced by xhci_init().

#define XHCI_CAP_RTSOFF   0x18

Runtime register space offset.

Definition at line 74 of file xhci.h.

Referenced by xhci_init().

#define XHCI_XECP_ID (   xecp)    ( ( (xecp) >> 0 ) & 0xff )

xHCI extended capability ID

Definition at line 77 of file xhci.h.

Referenced by xhci_extended_capability().

#define XHCI_XECP_NEXT (   xecp)    ( ( ( (xecp) >> 8 ) & 0xff ) << 2 )

Next xHCI extended capability pointer.

Definition at line 80 of file xhci.h.

Referenced by xhci_extended_capability().

#define XHCI_XECP_ID_LEGACY   1

USB legacy support extended capability.

Definition at line 83 of file xhci.h.

Referenced by xhci_legacy_init().

#define XHCI_USBLEGSUP_BIOS   0x02

USB legacy support BIOS owned semaphore.

Definition at line 86 of file xhci.h.

Referenced by xhci_legacy_claim(), and xhci_legacy_init().

#define XHCI_USBLEGSUP_BIOS_OWNED   0x01

USB legacy support BIOS ownership flag.

Definition at line 89 of file xhci.h.

Referenced by xhci_legacy_claim(), and xhci_legacy_init().

#define XHCI_USBLEGSUP_OS   0x03

USB legacy support OS owned semaphore.

Definition at line 92 of file xhci.h.

Referenced by xhci_legacy_claim(), and xhci_legacy_release().

#define XHCI_USBLEGSUP_OS_OWNED   0x01

USB legacy support OS ownership flag.

Definition at line 95 of file xhci.h.

Referenced by xhci_legacy_claim().

#define XHCI_USBLEGSUP_CTLSTS   0x04

USB legacy support control/status.

Definition at line 98 of file xhci.h.

Referenced by xhci_legacy_claim().

#define XHCI_XECP_ID_SUPPORTED   2

Supported protocol extended capability.

Definition at line 101 of file xhci.h.

Referenced by xhci_supported_protocol().

#define XHCI_SUPPORTED_REVISION   0x00

Supported protocol revision.

Definition at line 104 of file xhci.h.

Referenced by xhci_port_protocol().

#define XHCI_SUPPORTED_REVISION_VER (   revision)    ( ( (revision) >> 16 ) & 0xffff )

Supported protocol minor revision.

Definition at line 107 of file xhci.h.

Referenced by xhci_port_protocol().

#define XHCI_SUPPORTED_NAME   0x04

Supported protocol name.

Definition at line 110 of file xhci.h.

Referenced by xhci_port_protocol().

#define XHCI_SUPPORTED_PORTS   0x08

Supported protocol ports.

Definition at line 113 of file xhci.h.

Referenced by xhci_port_protocol(), xhci_port_psiv(), xhci_port_speed(), and xhci_supported_protocol().

#define XHCI_SUPPORTED_PORTS_OFFSET (   ports)    ( ( (ports) >> 0 ) & 0xff )

Supported protocol port offset.

Definition at line 116 of file xhci.h.

Referenced by xhci_supported_protocol().

#define XHCI_SUPPORTED_PORTS_COUNT (   ports)    ( ( (ports) >> 8 ) & 0xff )

Supported protocol port count.

Definition at line 119 of file xhci.h.

Referenced by xhci_supported_protocol().

#define XHCI_SUPPORTED_PORTS_PSIC (   ports)    ( ( (ports) >> 28 ) & 0x0f )

Supported protocol PSI count.

Definition at line 122 of file xhci.h.

Referenced by xhci_port_protocol(), xhci_port_psiv(), and xhci_port_speed().

#define XHCI_SUPPORTED_SLOT   0x0c

Supported protocol slot.

Definition at line 125 of file xhci.h.

Referenced by xhci_port_protocol(), and xhci_port_slot_type().

#define XHCI_SUPPORTED_SLOT_TYPE (   slot)    ( ( (slot) >> 0 ) & 0x1f )

Supported protocol slot type.

Definition at line 128 of file xhci.h.

Referenced by xhci_port_protocol(), and xhci_port_slot_type().

#define XHCI_SUPPORTED_PSI (   index)    ( 0x10 + ( (index) * 4 ) )

Supported protocol PSI.

Definition at line 131 of file xhci.h.

Referenced by xhci_port_protocol(), xhci_port_psiv(), and xhci_port_speed().

#define XHCI_SUPPORTED_PSI_VALUE (   psi)    ( ( (psi) >> 0 ) & 0x0f )

Supported protocol PSI value.

Definition at line 134 of file xhci.h.

Referenced by xhci_port_protocol(), xhci_port_psiv(), and xhci_port_speed().

#define XHCI_SUPPORTED_PSI_MANTISSA (   psi)    ( ( (psi) >> 16 ) & 0xffff )

Supported protocol PSI mantissa.

Definition at line 137 of file xhci.h.

Referenced by xhci_port_psiv(), xhci_port_speed(), and xhci_speed_name().

#define XHCI_SUPPORTED_PSI_EXPONENT (   psi)    ( ( (psi) >> 4 ) & 0x03 )

Supported protocol PSI exponent.

Definition at line 140 of file xhci.h.

Referenced by xhci_port_psiv(), xhci_port_speed(), and xhci_speed_name().

#define XHCI_OP_USBCMD   0x00

USB command register.

Definition at line 155 of file xhci.h.

Referenced by xhci_dump(), xhci_reset(), xhci_run(), and xhci_stop().

#define XHCI_USBCMD_RUN   0x00000001UL

Run/stop.

Definition at line 158 of file xhci.h.

Referenced by xhci_dump(), xhci_run(), and xhci_stop().

#define XHCI_USBCMD_HCRST   0x00000002UL

Host controller reset.

Definition at line 161 of file xhci.h.

Referenced by xhci_dump(), and xhci_reset().

#define XHCI_OP_USBSTS   0x04

USB status register.

Definition at line 164 of file xhci.h.

Referenced by xhci_dump(), and xhci_stop().

#define XHCI_USBSTS_HCH   0x00000001UL

Host controller halted.

Definition at line 167 of file xhci.h.

Referenced by xhci_dump(), and xhci_stop().

#define XHCI_OP_PAGESIZE   0x08

Page size register.

Definition at line 170 of file xhci.h.

Referenced by xhci_dump(), and xhci_init().

#define XHCI_PAGESIZE (   pagesize)    ( (pagesize) << 12 )

Page size.

Definition at line 173 of file xhci.h.

Referenced by xhci_init().

#define XHCI_OP_DNCTRL   0x14

Device notifcation control register.

Definition at line 176 of file xhci.h.

Referenced by xhci_dump().

#define XHCI_OP_CRCR   0x18

Command ring control register.

Definition at line 179 of file xhci.h.

Referenced by xhci_abort(), xhci_command_alloc(), and xhci_command_free().

#define XHCI_CRCR_RCS   0x00000001UL

Command ring cycle state.

Definition at line 182 of file xhci.h.

Referenced by xhci_abort(), and xhci_command_alloc().

#define XHCI_CRCR_CA   0x00000004UL

Command abort.

Definition at line 185 of file xhci.h.

Referenced by xhci_abort().

#define XHCI_CRCR_CRR   0x00000008UL

Command ring running.

Definition at line 188 of file xhci.h.

Referenced by xhci_abort(), and xhci_command_free().

#define XHCI_OP_DCBAAP   0x30

Device context base address array pointer.

Definition at line 191 of file xhci.h.

Referenced by xhci_dcbaa_alloc(), and xhci_dcbaa_free().

#define XHCI_OP_CONFIG   0x38

Configure register.

Definition at line 194 of file xhci.h.

Referenced by xhci_dump(), and xhci_run().

#define XHCI_CONFIG_MAX_SLOTS_EN (   slots)    ( (slots) << 0 )

Maximum device slots enabled.

Definition at line 197 of file xhci.h.

Referenced by xhci_run().

Maximum device slots enabled mask.

Definition at line 200 of file xhci.h.

Referenced by xhci_run().

#define XHCI_OP_PORTSC (   port)    ( 0x400 - 0x10 + ( (port) << 4 ) )

Port status and control register.

Definition at line 204 of file xhci.h.

Referenced by xhci_dump_port(), xhci_port_status(), xhci_root_disable(), xhci_root_enable(), xhci_root_open(), and xhci_root_speed().

#define XHCI_PORTSC_CCS   0x00000001UL

Current connect status.

Definition at line 207 of file xhci.h.

Referenced by xhci_dump_port(), and xhci_root_speed().

#define XHCI_PORTSC_PED   0x00000002UL

Port enabled.

Definition at line 210 of file xhci.h.

Referenced by xhci_dump_port(), xhci_root_disable(), xhci_root_enable(), and xhci_root_speed().

#define XHCI_PORTSC_PR   0x00000010UL

Port reset.

Definition at line 213 of file xhci.h.

Referenced by xhci_dump_port(), and xhci_root_enable().

#define XHCI_PORTSC_PLS (   pls)    ( (pls) << 5 )

Port link state.

Definition at line 216 of file xhci.h.

Disabled port link state.

Definition at line 219 of file xhci.h.

Referenced by xhci_root_open().

RxDetect port link state.

Definition at line 222 of file xhci.h.

Referenced by xhci_root_open().

#define XHCI_PORTSC_PLS_MASK   XHCI_PORTSC_PLS ( 0xf )

Port link state mask.

Definition at line 225 of file xhci.h.

Referenced by xhci_root_open().

#define XHCI_PORTSC_PP   0x00000200UL

Port power.

Definition at line 228 of file xhci.h.

Referenced by xhci_dump_port(), and xhci_root_open().

#define XHCI_PORT_POWER_DELAY_MS   20

Time to delay after enabling power to a port.

Definition at line 231 of file xhci.h.

Referenced by xhci_root_open().

#define XHCI_PORTSC_PSIV (   portsc)    ( ( (portsc) >> 10 ) & 0xf )

Port speed ID value.

Definition at line 234 of file xhci.h.

Referenced by xhci_dump_port(), and xhci_root_speed().

#define XHCI_PORTSC_PIC (   indicators)    ( (indicators) << 14 )

Port indicator control.

Definition at line 237 of file xhci.h.

Port indicator control mask.

Definition at line 240 of file xhci.h.

#define XHCI_PORTSC_LWS   0x00010000UL

Port link state write strobe.

Definition at line 243 of file xhci.h.

Referenced by xhci_root_open().

#define XHCI_LINK_STATE_DELAY_MS   20

Time to delay after writing the port link state.

Definition at line 246 of file xhci.h.

Referenced by xhci_root_open().

#define XHCI_PORTSC_CSC   0x00020000UL

Connect status change.

Definition at line 249 of file xhci.h.

Referenced by xhci_port_status(), and xhci_root_speed().

#define XHCI_PORTSC_PEC   0x00040000UL

Port enabled/disabled change.

Definition at line 252 of file xhci.h.

#define XHCI_PORTSC_WRC   0x00080000UL

Warm port reset change.

Definition at line 255 of file xhci.h.

#define XHCI_PORTSC_OCC   0x00100000UL

Over-current change.

Definition at line 258 of file xhci.h.

#define XHCI_PORTSC_PRC   0x00200000UL

Port reset change.

Definition at line 261 of file xhci.h.

#define XHCI_PORTSC_PLC   0x00400000UL

Port link state change.

Definition at line 264 of file xhci.h.

#define XHCI_PORTSC_CEC   0x00800000UL

Port config error change.

Definition at line 267 of file xhci.h.

Value:
( XHCI_PORTSC_CSC | XHCI_PORTSC_PEC | XHCI_PORTSC_WRC | \
          XHCI_PORTSC_OCC | XHCI_PORTSC_PRC | XHCI_PORTSC_PLC | \
          XHCI_PORTSC_CEC )

Port status change mask.

Definition at line 270 of file xhci.h.

Referenced by xhci_port_status(), and xhci_root_speed().

Port status and control bits which should be preserved.

The port status and control register is a horrendous mix of differing semantics. Some bits are written to only when a separate write strobe bit is set. Some bits should be preserved when modifying other bits. Some bits will be cleared if written back as a one. Most excitingly, the "port enabled" bit has the semantics that 1=enabled, 0=disabled, yet writing a 1 will disable the port.

Definition at line 284 of file xhci.h.

Referenced by xhci_port_status(), xhci_root_disable(), xhci_root_enable(), xhci_root_open(), and xhci_root_speed().

#define XHCI_OP_PORTPMSC (   port)    ( 0x404 - 0x10 + ( (port) << 4 ) )

Port power management status and control register.

Definition at line 287 of file xhci.h.

Referenced by xhci_dump_port().

#define XHCI_OP_PORTLI (   port)    ( 0x408 - 0x10 + ( (port) << 4 ) )

Port link info register.

Definition at line 290 of file xhci.h.

Referenced by xhci_dump_port().

#define XHCI_OP_PORTHLPMC (   port)    ( 0x40c - 0x10 + ( (port) << 4 ) )

Port hardware link power management control register.

Definition at line 293 of file xhci.h.

Referenced by xhci_dump_port().

#define XHCI_RUN_ERSTSZ (   intr)    ( 0x28 + ( (intr) << 5 ) )

Event ring segment table size register.

Definition at line 296 of file xhci.h.

Referenced by xhci_event_alloc(), and xhci_event_free().

#define XHCI_RUN_ERSTBA (   intr)    ( 0x30 + ( (intr) << 5 ) )

Event ring segment table base address register.

Definition at line 299 of file xhci.h.

Referenced by xhci_event_alloc(), and xhci_event_free().

#define XHCI_RUN_ERDP (   intr)    ( 0x38 + ( (intr) << 5 ) )

Event ring dequeue pointer register.

Definition at line 302 of file xhci.h.

Referenced by xhci_event_alloc(), xhci_event_free(), and xhci_event_poll().

#define XHCI_TRB_C   0x01

Transfer request block cycle bit flag.

Definition at line 329 of file xhci.h.

Referenced by xhci_enqueue(), and xhci_event_poll().

#define XHCI_TRB_TC   0x02

Transfer request block toggle cycle bit flag.

Definition at line 332 of file xhci.h.

Referenced by xhci_enqueue(), and xhci_ring_alloc().

#define XHCI_TRB_CH   0x10

Transfer request block chain flag.

Definition at line 335 of file xhci.h.

Referenced by xhci_endpoint_stream().

#define XHCI_TRB_IOC   0x20

Transfer request block interrupt on completion flag.

Definition at line 338 of file xhci.h.

Referenced by xhci_endpoint_message(), xhci_endpoint_stream(), and xhci_nop().

#define XHCI_TRB_IDT   0x40

Transfer request block immediate data flag.

Definition at line 341 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_TRB_TYPE (   type)    ( (type) << 2 )

Transfer request block type.

Definition at line 344 of file xhci.h.

#define XHCI_TRB_TYPE_MASK   XHCI_TRB_TYPE ( 0x3f )

Transfer request block type mask.

Definition at line 347 of file xhci.h.

Referenced by xhci_event_poll().

#define XHCI_TRB_NORMAL   XHCI_TRB_TYPE ( 1 )

A normal transfer request block.

Definition at line 364 of file xhci.h.

Referenced by xhci_endpoint_stream().

#define XHCI_TD_SIZE (   remaining)    ( ( ( (remaining) <= 0xf ) ? remaining : 0xf ) << 17 )

Construct TD size field.

Definition at line 367 of file xhci.h.

#define XHCI_TRB_SETUP   XHCI_TRB_TYPE ( 2 )

A setup stage transfer request block.

Definition at line 387 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_SETUP_IN   3

Setup stage input data direction.

Definition at line 390 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_SETUP_OUT   2

Setup stage output data direction.

Definition at line 393 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_TRB_DATA   XHCI_TRB_TYPE ( 3 )

A data stage transfer request block.

Definition at line 412 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_DATA_IN   0x01

Input data direction.

Definition at line 415 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_DATA_OUT   0x00

Output data direction.

Definition at line 418 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_TRB_STATUS   XHCI_TRB_TYPE ( 4 )

A status stage transfer request block.

Definition at line 437 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_STATUS_IN   0x01

Input status direction.

Definition at line 440 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_STATUS_OUT   0x00

Output status direction.

Definition at line 443 of file xhci.h.

Referenced by xhci_endpoint_message().

#define XHCI_TRB_LINK   XHCI_TRB_TYPE ( 6 )

A link transfer request block.

Definition at line 460 of file xhci.h.

Referenced by xhci_ring_alloc().

#define XHCI_TRB_NOP   XHCI_TRB_TYPE ( 8 )

A no-op transfer request block.

Definition at line 463 of file xhci.h.

#define XHCI_TRB_ENABLE_SLOT   XHCI_TRB_TYPE ( 9 )

An enable slot transfer request block.

Definition at line 482 of file xhci.h.

Referenced by xhci_enable_slot().

#define XHCI_TRB_DISABLE_SLOT   XHCI_TRB_TYPE ( 10 )

A disable slot transfer request block.

Definition at line 501 of file xhci.h.

Referenced by xhci_disable_slot().

An address device transfer request block.

Definition at line 520 of file xhci.h.

Referenced by xhci_address_device().

A configure endpoint transfer request block.

Definition at line 523 of file xhci.h.

Referenced by xhci_configure_endpoint(), and xhci_deconfigure_endpoint().

An evaluate context transfer request block.

Definition at line 526 of file xhci.h.

Referenced by xhci_evaluate_context().

A reset endpoint transfer request block.

Definition at line 545 of file xhci.h.

Referenced by xhci_reset_endpoint().

A stop endpoint transfer request block.

Definition at line 564 of file xhci.h.

Referenced by xhci_stop_endpoint().

A set transfer ring dequeue pointer transfer request block.

Definition at line 583 of file xhci.h.

Referenced by xhci_set_tr_dequeue_pointer().

#define XHCI_TRB_NOP_CMD   XHCI_TRB_TYPE ( 23 )

A no-op command transfer request block.

Definition at line 586 of file xhci.h.

Referenced by xhci_nop().

#define XHCI_TRB_TRANSFER   XHCI_TRB_TYPE ( 32 )

A transfer event transfer request block.

Definition at line 609 of file xhci.h.

Referenced by xhci_event_poll().

#define XHCI_TRB_COMPLETE   XHCI_TRB_TYPE ( 33 )

A command completion event transfer request block.

Definition at line 630 of file xhci.h.

Referenced by xhci_event_poll().

#define XHCI_TRB_PORT_STATUS   XHCI_TRB_TYPE ( 34 )

A port status change transfer request block.

Definition at line 661 of file xhci.h.

Referenced by xhci_event_poll().

A port status change transfer request block.

Definition at line 680 of file xhci.h.

Referenced by xhci_event_poll().

#define XHCI_SLOT_INFO (   entries,
  hub,
  speed,
  route 
)    ( ( (entries) << 27 ) | ( (hub) << 26 ) | ( (speed) << 20 ) | (route) )

Construct slot context device info.

Definition at line 765 of file xhci.h.

Referenced by xhci_address_device_input(), xhci_configure_endpoint_input(), xhci_deconfigure_endpoint_input(), and xhci_evaluate_context_input().

#define XHCI_ENDPOINT_STATE_MASK   0x07

Endpoint state mask.

Definition at line 809 of file xhci.h.

Referenced by xhci_transfer().

#define XHCI_EP_TYPE (   type)    ( (type) << 3 )

Endpoint type.

Definition at line 812 of file xhci.h.

Referenced by xhci_endpoint_open().

#define XHCI_EP_TYPE_CONTROL   XHCI_EP_TYPE ( 4 )

Control endpoint type.

Definition at line 815 of file xhci.h.

Referenced by xhci_address_device_input(), and xhci_endpoint_open().

#define XHCI_EP_TYPE_IN   XHCI_EP_TYPE ( 4 )

Input endpoint type.

Definition at line 818 of file xhci.h.

Referenced by xhci_endpoint_open().

#define XHCI_EP_TYPE_PERIODIC   XHCI_EP_TYPE ( 1 )

Periodic endpoint type.

Definition at line 821 of file xhci.h.

Referenced by xhci_endpoint_open().

#define XHCI_EP_DCS   0x00000001UL

Endpoint dequeue cycle state.

Definition at line 824 of file xhci.h.

Referenced by xhci_address_device_input(), xhci_configure_endpoint_input(), and xhci_set_tr_dequeue_pointer().

#define XHCI_EP0_TRB_LEN   8

Control endpoint average TRB length.

Definition at line 827 of file xhci.h.

Referenced by xhci_address_device_input().

#define XHCI_DBVAL (   target,
  stream 
)    ( (target) | ( (stream) << 16 ) )

Calculate doorbell register value.

Parameters:
targetDoorbell target
streamDoorbell stream ID
Return values:
dbvalDoorbell register value

Definition at line 883 of file xhci.h.

Referenced by xhci_ring_alloc().

#define XHCI_CTX_SLOT   0
#define XHCI_CTX (   address)
Value:
( (address) ? ( ( ( (address) & 0x0f ) << 1 ) |                 \
                        ( ( (address) & 0x80 ) >> 7 ) ) : 1 )

Calculate context index from USB endpoint address.

Definition at line 940 of file xhci.h.

Referenced by xhci_endpoint_open().

#define XHCI_CTX_EP0   XHCI_CTX ( 0x00 )

Endpoint zero context index.

Definition at line 945 of file xhci.h.

Referenced by xhci_address_device(), xhci_address_device_input(), xhci_endpoint_close(), and xhci_endpoint_open().

#define XHCI_CTX_END   32
#define XHCI_DCI (   ctx)    ( (ctx) + 0 )

Device context index.

Definition at line 951 of file xhci.h.

Referenced by xhci_device_context_offset().

#define XHCI_ICI (   ctx)    ( (ctx) + 1 )

Input context index.

Definition at line 954 of file xhci.h.

Referenced by xhci_input_context_offset().

#define XHCI_CMD_TRBS_LOG2   2

Number of TRBs (excluding Link TRB) in the command ring.

This is a policy decision.

Definition at line 960 of file xhci.h.

Referenced by xhci_command_alloc().

#define XHCI_EVENT_TRBS_LOG2   6

Number of TRBs in the event ring.

This is a policy decision.

Definition at line 966 of file xhci.h.

Referenced by xhci_event_alloc(), xhci_event_free(), and xhci_event_poll().

#define XHCI_TRANSFER_TRBS_LOG2   6

Number of TRBs in a transfer ring.

This is a policy decision.

Definition at line 972 of file xhci.h.

Referenced by xhci_endpoint_open().

#define XHCI_USBLEGSUP_MAX_WAIT_MS   100

Maximum time to wait for BIOS to release ownership.

This is a policy decision.

Definition at line 978 of file xhci.h.

Referenced by xhci_legacy_claim().

#define XHCI_STOP_MAX_WAIT_MS   100

Maximum time to wait for host controller to stop.

This is a policy decision.

Definition at line 984 of file xhci.h.

Referenced by xhci_stop().

#define XHCI_RESET_MAX_WAIT_MS   500

Maximum time to wait for reset to complete.

This is a policy decision.

Definition at line 990 of file xhci.h.

Referenced by xhci_reset().

Maximum time to wait for a command to complete.

The "address device" command involves waiting for a response to a USB control transaction, and so we must wait for up to the 5000ms that USB allows for devices to respond to control transactions.

Definition at line 998 of file xhci.h.

Referenced by xhci_command().

#define XHCI_COMMAND_ABORT_DELAY_MS   500

Time to delay after aborting a command.

This is a policy decision

Definition at line 1004 of file xhci.h.

Referenced by xhci_abort().

#define XHCI_PORT_RESET_MAX_WAIT_MS   500

Maximum time to wait for a port reset to complete.

This is a policy decision.

Definition at line 1010 of file xhci.h.

Referenced by xhci_root_enable().

#define XHCI_PCH   0x0001

Intel PCH quirk flag.

Definition at line 1021 of file xhci.h.

Referenced by xhci_probe(), and xhci_remove().

#define XHCI_PCH_XUSB2PR   0xd0

Intel PCH USB2 port routing register.

Definition at line 1024 of file xhci.h.

Referenced by xhci_pch_fix(), and xhci_pch_undo().

#define XHCI_PCH_XUSB2PRM   0xd4

Intel PCH USB2 port routing mask register.

Definition at line 1027 of file xhci.h.

Referenced by xhci_pch_fix().

#define XHCI_PCH_USB3PSSEN   0xd8

Intel PCH SuperSpeed enable register.

Definition at line 1030 of file xhci.h.

Referenced by xhci_pch_fix(), and xhci_pch_undo().

#define XHCI_PCH_USB3PRM   0xdc

Intel PCH USB3 port routing mask register.

Definition at line 1033 of file xhci.h.

Referenced by xhci_pch_fix().

#define XHCI_BAD_PSIV   0x0002

Invalid protocol speed ID values quirk.

Definition at line 1036 of file xhci.h.

Referenced by xhci_port_protocol(), xhci_port_psiv(), and xhci_port_speed().


Enumeration Type Documentation

Default PSI values.

Enumerator:
XHCI_SPEED_FULL 

Full speed (12Mbps)

XHCI_SPEED_LOW 

Low speed (1.5Mbps)

XHCI_SPEED_HIGH 

High speed (480Mbps)

XHCI_SPEED_SUPER 

Super speed.

Definition at line 143 of file xhci.h.

                            {
        /** Full speed (12Mbps) */
        XHCI_SPEED_FULL = 1,
        /** Low speed (1.5Mbps) */
        XHCI_SPEED_LOW = 2,
        /** High speed (480Mbps) */
        XHCI_SPEED_HIGH = 3,
        /** Super speed */
        XHCI_SPEED_SUPER = 4,
};

xHCI completion codes

Enumerator:
XHCI_CMPLT_SUCCESS 

Success.

XHCI_CMPLT_SHORT 

Short packet.

XHCI_CMPLT_CMD_STOPPED 

Command ring stopped.

Definition at line 633 of file xhci.h.

                          {
        /** Success */
        XHCI_CMPLT_SUCCESS = 1,
        /** Short packet */
        XHCI_CMPLT_SHORT = 13,
        /** Command ring stopped */
        XHCI_CMPLT_CMD_STOPPED = 24,
};

Endpoint states.

Enumerator:
XHCI_ENDPOINT_DISABLED 

Endpoint is disabled.

XHCI_ENDPOINT_RUNNING 

Endpoint is running.

XHCI_ENDPOINT_HALTED 

Endpoint is halted due to a USB Halt condition.

XHCI_ENDPOINT_STOPPED 

Endpoint is stopped.

XHCI_ENDPOINT_ERROR 

Endpoint is halted due to a TRB error.

Definition at line 795 of file xhci.h.

                         {
        /** Endpoint is disabled */
        XHCI_ENDPOINT_DISABLED = 0,
        /** Endpoint is running */
        XHCI_ENDPOINT_RUNNING = 1,
        /** Endpoint is halted due to a USB Halt condition */
        XHCI_ENDPOINT_HALTED = 2,
        /** Endpoint is stopped */
        XHCI_ENDPOINT_STOPPED = 3,
        /** Endpoint is halted due to a TRB error */
        XHCI_ENDPOINT_ERROR = 4,
};

Function Documentation

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )
static unsigned int xhci_ring_fill ( struct xhci_trb_ring ring) [inline, static]

Calculate space used in TRB ring.

Parameters:
ringTRB ring
Return values:
fillNumber of entries used

Definition at line 892 of file xhci.h.

Referenced by xhci_dequeue(), xhci_endpoint_close(), and xhci_ring_remaining().

                                              {

        return ( ring->prod - ring->cons );
}
static unsigned int xhci_ring_remaining ( struct xhci_trb_ring ring) [inline, static]

Calculate space remaining in TRB ring.

Parameters:
ringTRB ring
Return values:
remainingNumber of entries remaining

xHCI does not allow us to completely fill a ring; there must be at least one free entry (excluding the Link TRB).

Definition at line 907 of file xhci.h.

References assert, fill, and xhci_ring_fill().

Referenced by xhci_enqueue(), and xhci_enqueue_multi().

                                                   {
        unsigned int fill = xhci_ring_fill ( ring );

        /* We choose to utilise rings with ( 2^n + 1 ) entries, with
         * the final entry being a Link TRB.  The maximum fill level
         * is therefore
         *
         *   ( ( 2^n + 1 ) - 1 (Link TRB) - 1 (one slot always empty)
         *       == ( 2^n - 1 )
         *
         * which is therefore equal to the ring mask.
         */
        assert ( fill <= ring->mask );
        return ( ring->mask - fill );
}
static physaddr_t xhci_ring_consumed ( struct xhci_trb_ring ring) [inline, static]

Calculate physical address of most recently consumed TRB.

Parameters:
ringTRB ring
Return values:
trbTRB physical address

Definition at line 930 of file xhci.h.

References index, and virt_to_phys().

Referenced by xhci_complete(), and xhci_transfer().

                                                  {
        unsigned int index = ( ( ring->cons - 1 ) & ring->mask );

        return virt_to_phys ( &ring->trb[index] );
}