iPXE
MT25218_PRM.h
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1 /*
2  This software is available to you under a choice of one of two
3  licenses. You may choose to be licensed under the terms of the GNU
4  General Public License (GPL) Version 2, available at
5  <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
6  license, available in the LICENSE.TXT file accompanying this
7  software. These details are also available at
8  <http://openib.org/license.html>.
9 
10  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13  NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15  ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16  CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17  SOFTWARE.
18 
19  Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
20 */
21 
22 FILE_LICENCE ( GPL2_ONLY );
23 
24 /***
25  *** This file was generated at "Tue Nov 22 15:21:23 2005"
26  *** by:
27  *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix arbelprm_ -bits -fixnames MT25218_PRM.csp
28  ***/
29 
30 #ifndef H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
31 #define H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H
32 
33 /* UD Address Vector */
34 
35 struct arbelprm_ud_address_vector_st { /* Little Endian */
36  pseudo_bit_t pd[0x00018]; /* Protection Domain */
37  pseudo_bit_t port_number[0x00002]; /* Port number
38  1 - Port 1
39  2 - Port 2
40  other - reserved */
42 /* -------------- */
43  pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
44  pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
45  pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
47 /* -------------- */
48  pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
49  pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control.
50  0 - 4X injection rate
51  1 - 1X injection rate
52  other - reserved
53  */
55  pseudo_bit_t msg[0x00002]; /* Max Message size, size is 256*2^MSG bytes */
57  pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table
58  mgid_index = (port_number-1) * 2^log_max_gid + gid_index
59  Where:
60  1. log_max_gid is taken from QUERY_DEV_LIM command
61  2. gid_index is the index to the GID table */
63 /* -------------- */
64  pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
65  pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
66  pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
67 /* -------------- */
68  pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
69 /* -------------- */
70  pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
71 /* -------------- */
72  pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
73 /* -------------- */
74  pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
75 /* -------------- */
76 };
77 
78 /* Send doorbell */
79 
80 struct arbelprm_send_doorbell_st { /* Little Endian */
81  pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */
82  pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */
84  pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
85  pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */
86 /* -------------- */
87  pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */
89  pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
90 /* -------------- */
91 };
92 
93 /* ACCESS_LAM_inject_errors_input_modifier */
94 
96  pseudo_bit_t index3[0x00007];
97  pseudo_bit_t q3[0x00001];
98  pseudo_bit_t index2[0x00007];
99  pseudo_bit_t q2[0x00001];
101  pseudo_bit_t q1[0x00001];
103  pseudo_bit_t q0[0x00001];
104 /* -------------- */
105 };
106 
107 /* ACCESS_LAM_inject_errors_input_parameter */
108 
110  pseudo_bit_t ba[0x00002]; /* Bank Address */
111  pseudo_bit_t da[0x00002]; /* Dimm Address */
113 /* -------------- */
114  pseudo_bit_t ra[0x00010]; /* Row Address */
115  pseudo_bit_t ca[0x00010]; /* Column Address */
116 /* -------------- */
117 };
118 
119 /* */
120 
121 struct arbelprm_recv_wqe_segment_next_st { /* Little Endian */
123  pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
124 /* -------------- */
125  pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes).
126  Zero value in NDS field signals end of WQEs? chain.
127  */
129 /* -------------- */
130 };
131 
132 /* Send wqe segment data inline */
133 
134 struct arbelprm_wqe_segment_data_inline_st { /* Little Endian */
135  pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */
138 /* -------------- */
139  pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */
141 /* -------------- */
143 /* -------------- */
144 };
145 
146 /* Send wqe segment data ptr */
147 
148 struct arbelprm_wqe_segment_data_ptr_st { /* Little Endian */
151 /* -------------- */
152  pseudo_bit_t l_key[0x00020];
153 /* -------------- */
155 /* -------------- */
157 /* -------------- */
158 };
159 
160 /* Send wqe segment rd */
161 
162 struct arbelprm_local_invalidate_segment_st { /* Little Endian */
164 /* -------------- */
167 /* -------------- */
169 /* -------------- */
170 };
171 
172 /* Fast_Registration_Segment */
173 
174 struct arbelprm_fast_registration_segment_st { /* Little Endian */
176  pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */
177  pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */
178  pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */
179  pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */
180  pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */
181 /* -------------- */
182  pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list */
183 /* -------------- */
184  pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. */
185 /* -------------- */
186  pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
187  page_size should be less than 20. */
189  pseudo_bit_t zb[0x00001]; /* Zero Based Region */
190  pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list */
191 /* -------------- */
192  pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
193 /* -------------- */
194  pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
195 /* -------------- */
196  pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */
197 /* -------------- */
198  pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */
199 /* -------------- */
200 };
201 
202 /* Send wqe segment atomic */
203 
204 struct arbelprm_wqe_segment_atomic_st { /* Little Endian */
206 /* -------------- */
208 /* -------------- */
210 /* -------------- */
212 /* -------------- */
213 };
214 
215 /* Send wqe segment remote address */
216 
217 struct arbelprm_wqe_segment_remote_address_st { /* Little Endian */
219 /* -------------- */
221 /* -------------- */
222  pseudo_bit_t rkey[0x00020];
223 /* -------------- */
225 /* -------------- */
226 };
227 
228 /* end wqe segment bind */
229 
230 struct arbelprm_wqe_segment_bind_st { /* Little Endian */
232  pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */
233  pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window.
234  */
235  pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */
236 /* -------------- */
238  pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */
239  pseudo_bit_t type[0x00001]; /* Window type.
240  0 - Type one window
241  1 - Type two window
242  */
243 /* -------------- */
244  pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */
245 /* -------------- */
246  pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */
247 /* -------------- */
249 /* -------------- */
251 /* -------------- */
253 /* -------------- */
255 /* -------------- */
256 };
257 
258 /* Send wqe segment ud */
259 
260 struct arbelprm_wqe_segment_ud_st { /* Little Endian */
261  struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
262 /* -------------- */
265 /* -------------- */
266  pseudo_bit_t q_key[0x00020];
267 /* -------------- */
269 /* -------------- */
270 };
271 
272 /* Send wqe segment rd */
273 
274 struct arbelprm_wqe_segment_rd_st { /* Little Endian */
277 /* -------------- */
278  pseudo_bit_t q_key[0x00020];
279 /* -------------- */
281 /* -------------- */
282 };
283 
284 /* Send wqe segment ctrl */
285 
286 struct arbelprm_wqe_segment_ctrl_send_st { /* Little Endian */
288  pseudo_bit_t s[0x00001]; /* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */
289  pseudo_bit_t e[0x00001]; /* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */
290  pseudo_bit_t c[0x00001]; /* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */
291  pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
292  pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
294  pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
296 /* -------------- */
297  pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
298 /* -------------- */
299 };
300 
301 /* Send wqe segment next */
302 
303 struct arbelprm_wqe_segment_next_st { /* Little Endian */
304  pseudo_bit_t nopcode[0x00005]; /* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP:
305  ?00000? - NOP. WQE with this opcode creates a completion, but does nothing else
306  ?01000? - RDMA-write
307  ?01001? - RDMA-Write with Immediate
308  ?10000? - RDMA-read
309  ?10001? - Atomic Compare & swap
310  ?10010? - Atomic Fetch & Add
311  ?11000? - Bind memory window
312 
313  The encoding for the following operations depends on the QP type:
314  For RC, UC and RD QP:
315  ?01010? - SEND
316  ?01011? - SEND with Immediate
317 
318  For UD QP:
319  the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of
320  both the current WQE and the next WQE, as follows:
321 
322  If the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set :
323  ?01000? - SEND
324  ?01001? - SEND with Immediate
325 
326  otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set):
327  ?01010? - SEND
328  ?01011? - SEND with Immediate
329 
330  All other opcode values are RESERVED, and will result in invalid operation execution. */
332  pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */
333 /* -------------- */
334  pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes).
335  Zero value in NDS field signals end of WQEs? chain.
336  */
337  pseudo_bit_t f[0x00001]; /* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */
340 /* -------------- */
341 };
342 
343 /* Address Path */
344 
345 struct arbelprm_address_path_st { /* Little Endian */
346  pseudo_bit_t pkey_index[0x00007]; /* PKey table index */
348  pseudo_bit_t port_number[0x00002]; /* Specific port associated with this QP/EE.
349  1 - Port 1
350  2 - Port 2
351  other - reserved */
353 /* -------------- */
354  pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
355  pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
356  pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
358  pseudo_bit_t rnr_retry[0x00003]; /* RNR retry count (see C9-132 in IB spec Vol 1)
359  0-6 - number of retries
360  7 - infinite */
361 /* -------------- */
362  pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
363  pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control.
364  0 - 100% injection rate
365  1 - 25% injection rate
366  2 - 12.5% injection rate
367  3 - 50% injection rate
368  other - reserved */
370  pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table */
372  pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
373  The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
374 /* -------------- */
375  pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
376  pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
377  pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
378 /* -------------- */
379  pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
380 /* -------------- */
381  pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
382 /* -------------- */
383  pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
384 /* -------------- */
385  pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */
386 /* -------------- */
387 };
388 
389 /* HCA Command Register (HCR) */
390 
391 struct arbelprm_hca_command_register_st { /* Little Endian */
392  pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */
393 /* -------------- */
394  pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */
395 /* -------------- */
396  pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */
397 /* -------------- */
398  pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
399 /* -------------- */
400  pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
401 /* -------------- */
403  pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
404 /* -------------- */
405  pseudo_bit_t opcode[0x0000c]; /* Command opcode */
406  pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
408  pseudo_bit_t e[0x00001]; /* Event Request
409  0 - Don't report event (software will poll the GO bit)
410  1 - Report event to EQ when the command completes */
411  pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
412  Software can write to the HCR only if Go bit is cleared.
413  Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
414  pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
415  0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
416 /* -------------- */
417 };
418 
419 /* CQ Doorbell */
420 
421 struct arbelprm_cq_cmd_doorbell_st { /* Little Endian */
422  pseudo_bit_t cqn[0x00018]; /* CQ number accessed */
423  pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ
424  0x0 - Reserved
425  0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter.
426  0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter.
427  0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated
428  Other - Reserved */
430  pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ.
431  This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited
432  completion or Request notification for multiple completions doorbells after receiving completion notification.
433  This field is initialized to Zero */
435 /* -------------- */
436  pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */
437 /* -------------- */
438 };
439 
440 /* RD-send doorbell */
441 
442 struct arbelprm_rd_send_doorbell_st { /* Little Endian */
444  pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram)
445  Must be zero for Nop and Bind operations */
446 /* -------------- */
448  pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
449 /* -------------- */
450  struct arbelprm_send_doorbell_st send_doorbell;/* Send Parameters */
451 /* -------------- */
452 };
453 
454 /* Multicast Group Member QP */
455 
456 struct arbelprm_mgmqp_st { /* Little Endian */
457  pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
459  pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */
460 /* -------------- */
461 };
462 
463 /* vsd */
464 
465 struct arbelprm_vsd_st { /* Little Endian */
467 /* -------------- */
469 /* -------------- */
471 /* -------------- */
473 /* -------------- */
475 /* -------------- */
477 /* -------------- */
479 /* -------------- */
481 /* -------------- */
483 /* -------------- */
485 /* -------------- */
487 /* -------------- */
489 /* -------------- */
491 /* -------------- */
493 /* -------------- */
495 /* -------------- */
497 /* -------------- */
499 /* -------------- */
501 /* -------------- */
503 /* -------------- */
505 /* -------------- */
507 /* -------------- */
509 /* -------------- */
511 /* -------------- */
513 /* -------------- */
515 /* -------------- */
517 /* -------------- */
519 /* -------------- */
521 /* -------------- */
523 /* -------------- */
525 /* -------------- */
527 /* -------------- */
529 /* -------------- */
531 /* -------------- */
533 /* -------------- */
535 /* -------------- */
537 /* -------------- */
539 /* -------------- */
541 /* -------------- */
543 /* -------------- */
545 /* -------------- */
547 /* -------------- */
549 /* -------------- */
551 /* -------------- */
553 /* -------------- */
555 /* -------------- */
557 /* -------------- */
559 /* -------------- */
561 /* -------------- */
563 /* -------------- */
565 /* -------------- */
567 /* -------------- */
569 /* -------------- */
571 /* -------------- */
573 /* -------------- */
575 /* -------------- */
577 /* -------------- */
578 };
579 
580 /* ACCESS_LAM_inject_errors */
581 
582 struct arbelprm_access_lam_inject_errors_st { /* Little Endian */
584 /* -------------- */
586 /* -------------- */
588 /* -------------- */
589 };
590 
591 /* Logical DIMM Information */
592 
593 struct arbelprm_dimminfo_st { /* Little Endian */
594  pseudo_bit_t dimmsize[0x00010]; /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */
596  pseudo_bit_t dimmstatus[0x00001]; /* DIMM Status
597  0 - Enabled
598  1 - Disabled
599  */
600  pseudo_bit_t dh[0x00001]; /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */
601  pseudo_bit_t wo[0x00001]; /* When set, the DIMM is write only.
602  If data integrity is configured (other than none), the DIMM must be
603  only targeted by write transactions where the address and size are multiples of 16 bytes. */
605 /* -------------- */
606  pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM
607  1 - DIMM SPD was read from InfiniHost-III-EX NVMEM */
608  pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits.
609  Valid only if spd bit is 0. */
610  pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */
611  pseudo_bit_t syn[0x00004]; /* Error syndrome (valid regardless of status value)
612  0 - DIMM has no error
613  1 - SPD error (e.g. checksum error, no response, error while reading)
614  2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2)
615  3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict)
616  5 - DIMM size trimmed due to configuration (size exceeds)
617  other - Error, reserved
618  */
620 /* -------------- */
622 /* -------------- */
623  pseudo_bit_t dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */
624 /* -------------- */
625  pseudo_bit_t dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */
626 /* -------------- */
628 /* -------------- */
629 };
630 
631 /* UAR Parameters */
632 
633 struct arbelprm_uar_params_st { /* Little Endian */
634  pseudo_bit_t uar_base_addr_h[0x00020];/* UAR Base (pyhsical) Address [63:32] (QUERY_HCA only) */
635 /* -------------- */
637  pseudo_bit_t uar_base_addr_l[0x0000c];/* UAR Base (pyhsical) Address [31:20] (QUERY_HCA only) */
638 /* -------------- */
639  pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page.
640  Size of UAR Page is 4KB*2^UAR_Page_Size */
641  pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */
643  pseudo_bit_t log_uar_entry_sz[0x00006];/* Size of UAR Context entry is 2^log_uar_sz in 4KByte pages */
645 /* -------------- */
647 /* -------------- */
648  pseudo_bit_t uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32].
649  Number of entries in table is 2^log_max_uars.
650  Table must be aligned to its size */
651 /* -------------- */
652  pseudo_bit_t uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0].
653  Number of entries in table is 2^log_max_uars.
654  Table must be aligned to its size. */
655 /* -------------- */
656  pseudo_bit_t uar_context_base_addr_h[0x00020];/* Base address of UAR Context [63:32].
657  Number of entries in table is 2^log_max_uars.
658  Table must be aligned to its size. */
659 /* -------------- */
660  pseudo_bit_t uar_context_base_addr_l[0x00020];/* Base address of UAR Context [31:0].
661  Number of entries in table is 2^log_max_uars.
662  Table must be aligned to its size. */
663 /* -------------- */
664 };
665 
666 /* Translation and Protection Tables Parameters */
667 
668 struct arbelprm_tptparams_st { /* Little Endian */
669  pseudo_bit_t mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32].
670  Entry size is 64 bytes.
671  Table must be aligned to its size.
672  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
673 /* -------------- */
674  pseudo_bit_t mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0].
675  Entry size is 64 bytes.
676  Table must be aligned to its size.
677  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
678 /* -------------- */
679  pseudo_bit_t log_mpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the MPT table. */
681  pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout -
682  The field returned in RNR Naks generated when a page fault is detected.
683  It has no effect when on-demand-paging is not used. */
685 /* -------------- */
687 /* -------------- */
688  pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].
689  Table must be aligned to its size.
690  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
691 /* -------------- */
692  pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].
693  Table must be aligned to its size.
694  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
695 /* -------------- */
697 /* -------------- */
698 };
699 
700 /* Multicast Support Parameters */
701 
702 struct arbelprm_multicastparam_st { /* Little Endian */
703  pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].
704  The base address must be aligned to the entry size.
705  Address may be set to 0xFFFFFFFF if multicast is not supported. */
706 /* -------------- */
707  pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0].
708  The base address must be aligned to the entry size.
709  Address may be set to 0xFFFFFFFF if multicast is not supported. */
710 /* -------------- */
712 /* -------------- */
713  pseudo_bit_t log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry.
714  Must be greater than 5 (to allow CTRL and GID sections).
715  That implies the number of QPs per MC table entry. */
717 /* -------------- */
718  pseudo_bit_t mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2)
719  INIT_HCA - the required number of entries
720  QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */
722 /* -------------- */
723  pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
725  pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function
726  0 - Default hash function
727  other - reserved */
729 /* -------------- */
731 /* -------------- */
732 };
733 
734 /* QPC/EEC/CQC/EQC/RDB Parameters */
735 
736 struct arbelprm_qpcbaseaddr_st { /* Little Endian */
738 /* -------------- */
739  pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
740  Table must be aligned on its size */
741 /* -------------- */
742  pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
744  pseudo_bit_t qpc_base_addr_l[0x00019];/* QPC Base Address [31:7]
745  Table must be aligned on its size */
746 /* -------------- */
748 /* -------------- */
749  pseudo_bit_t eec_base_addr_h[0x00020];/* EEC Base Address [63:32]
750  Table must be aligned on its size.
751  Address may be set to 0xFFFFFFFF if RD is not supported. */
752 /* -------------- */
753  pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */
755  pseudo_bit_t eec_base_addr_l[0x00019];/* EEC Base Address [31:7]
756  Table must be aligned on its size
757  Address may be set to 0xFFFFFFFF if RD is not supported. */
758 /* -------------- */
759  pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
760  Table must be aligned on its size
761  Address may be set to 0xFFFFFFFF if SRQ is not supported. */
762 /* -------------- */
763  pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
764  pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
765  Table must be aligned on its size
766  Address may be set to 0xFFFFFFFF if SRQ is not supported. */
767 /* -------------- */
768  pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
769  Table must be aligned on its size */
770 /* -------------- */
771  pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
773  pseudo_bit_t cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6]
774  Table must be aligned on its size */
775 /* -------------- */
777 /* -------------- */
778  pseudo_bit_t eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32]
779  Table has same number of entries as QPC table.
780  Table must be aligned to entry size. */
781 /* -------------- */
782  pseudo_bit_t eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0]
783  Table has same number of entries as QPC table.
784  Table must be aligned to entry size. */
785 /* -------------- */
787 /* -------------- */
788  pseudo_bit_t eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32]
789  Table has same number of entries as EEC table.
790  Table must be aligned to entry size.
791  Address may be set to 0xFFFFFFFF if RD is not supported. */
792 /* -------------- */
793  pseudo_bit_t eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0]
794  Table has same number of entries as EEC table.
795  Table must be aligned to entry size.
796  Address may be set to 0xFFFFFFFF if RD is not supported. */
797 /* -------------- */
799 /* -------------- */
800  pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
801  Address may be set to 0xFFFFFFFF if EQs are not supported.
802  Table must be aligned to entry size. */
803 /* -------------- */
804  pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs.
805  Must be 6 or less in InfiniHost-III-EX. */
807  pseudo_bit_t eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6]
808  Address may be set to 0xFFFFFFFF if EQs are not supported.
809  Table must be aligned to entry size. */
810 /* -------------- */
812 /* -------------- */
813  pseudo_bit_t rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32].
814  Address may be set to 0xFFFFFFFF if remote RDMA reads are not supported.
815  Please refer to QP and EE chapter for further explanation on RDB allocation. */
816 /* -------------- */
817  pseudo_bit_t rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0].
818  Table must be aligned to RDB entry size (32 bytes).
819  Address may be set to zero if remote RDMA reads are not supported.
820  Please refer to QP and EE chapter for further explanation on RDB allocation. */
821 /* -------------- */
823 /* -------------- */
824 };
825 
826 /* Header_Log_Register */
827 
828 struct arbelprm_header_log_register_st { /* Little Endian */
830 /* -------------- */
832 /* -------------- */
833 };
834 
835 /* Performance Monitors */
836 
837 struct arbelprm_performance_monitors_st { /* Little Endian */
838  pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */
839  pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */
840  pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */
842  pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
843  pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
844  pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
846  pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
847  pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
848  pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
850  pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
851  pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
852  pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
854  pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
856  pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
858 /* -------------- */
860 /* -------------- */
862 /* -------------- */
863  pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
864 /* -------------- */
865 };
866 
867 /* Receive segment format */
868 
869 struct arbelprm_wqe_segment_ctrl_recv_st { /* Little Endian */
871 /* -------------- */
876 /* -------------- */
878 /* -------------- */
879 };
880 
881 /* MLX WQE segment format */
882 
883 struct arbelprm_wqe_segment_ctrl_mlx_st { /* Little Endian */
885  pseudo_bit_t e[0x00001]; /* WQE event */
886  pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */
887  pseudo_bit_t icrc[0x00002]; /* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved. 3 - Leave last dword as is. Last dword must not be 0x0. */
889  pseudo_bit_t sl[0x00004];
891  pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */
892  pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */
894 /* -------------- */
895  pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */
896  pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */
897 /* -------------- */
898 };
899 
900 /* Send WQE segment format */
901 
902 struct arbelprm_send_wqe_segment_st { /* Little Endian */
903  struct arbelprm_wqe_segment_next_st wqe_segment_next;/* Send wqe segment next */
904 /* -------------- */
905  struct arbelprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */
906 /* -------------- */
907  struct arbelprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */
908 /* -------------- */
909  struct arbelprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */
910 /* -------------- */
911  struct arbelprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */
912 /* -------------- */
914 /* -------------- */
915  struct arbelprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */
916 /* -------------- */
917  struct arbelprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */
918 /* -------------- */
920 /* -------------- */
922 /* -------------- */
923  struct arbelprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */
924 /* -------------- */
925  struct arbelprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */
926 /* -------------- */
928 /* -------------- */
929 };
930 
931 /* QP and EE Context Entry */
932 
933 struct arbelprm_queue_pair_ee_context_entry_st { /* Little Endian */
935  pseudo_bit_t de[0x00001]; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */
937  pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm)
938  11-Migrated
939  00-Armed
940  01-Rearm
941  10-Reserved
942  Should be set to 11 for UD QPs and for QPs which do not support APM */
944  pseudo_bit_t st[0x00003]; /* Service type (invalid in EE context):
945  000-Reliable Connection
946  001-Unreliable Connection
947  010-Reliable Datagram
948  011-Unreliable Datagram
949  111-MLX transport (raw bits injection). Used for management QPs and RAW */
951  pseudo_bit_t state[0x00004]; /* QP/EE state:
952  0 - RST
953  1 - INIT
954  2 - RTR
955  3 - RTS
956  4 - SQEr
957  5 - SQD (Send Queue Drained)
958  6 - ERR
959  7 - Send Queue Draining
960  8 - Reserved
961  9 - Suspended
962  A- F - Reserved
963  (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
964 /* -------------- */
966 /* -------------- */
967  pseudo_bit_t sched_queue[0x00004]; /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */
968  pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */
970  pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes.
971  Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
972  pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */
974  pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes.
975  Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
976  pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */
978  pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
979  Must be equal to MTU for UD and MLX QPs. */
980  pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative):
981  0x1 - 256 bytes
982  0x2 - 512
983  0x3 - 1024
984  0x4 - 2048
985  other - reserved
986 
987  Should be configured to 0x4 for UD and MLX QPs. */
988 /* -------------- */
989  pseudo_bit_t usr_page[0x00018]; /* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
991 /* -------------- */
992  pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
993  This field is valid for QUERY and ERR2RST commands only. */
995 /* -------------- */
996  pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */
998 /* -------------- */
1000 /* -------------- */
1001  struct arbelprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */
1002 /* -------------- */
1003  struct arbelprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */
1004 /* -------------- */
1005  pseudo_bit_t rdd[0x00018]; /* Reliable Datagram Domain */
1007 /* -------------- */
1008  pseudo_bit_t pd[0x00018]; /* QP protection domain. Not valid (reserved) in EE context. */
1010 /* -------------- */
1011  pseudo_bit_t wqe_base_adr_h[0x00020];/* Bits 63:32 of WQE address for both SQ and RQ.
1012  Reserved for EE context. */
1013 /* -------------- */
1014  pseudo_bit_t wqe_lkey[0x00020]; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */
1015 /* -------------- */
1017  pseudo_bit_t ssc[0x00001]; /* Send Signaled Completion
1018  1 - all send WQEs generate CQEs.
1019  0 - only send WQEs with C bit set generate completion.
1020  Not valid (reserved) in EE context. */
1021  pseudo_bit_t sic[0x00001]; /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */
1022  pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
1023  The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
1024  pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
1025  The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
1026  pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */
1028  pseudo_bit_t sae[0x00001]; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */
1029  pseudo_bit_t swe[0x00001]; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */
1030  pseudo_bit_t sre[0x00001]; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */
1031  pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */
1033  pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
1034  pseudo_bit_t flight_lim[0x00004]; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue.
1035  Number of outstanding messages is 2^Flight_Lim.
1036  Use 0xF for unlimited number of outstanding messages. */
1037  pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
1038 /* -------------- */
1040 /* -------------- */
1041  pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */
1043 /* -------------- */
1044  pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
1046 /* -------------- */
1048  pseudo_bit_t snd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
1049 /* -------------- */
1050  pseudo_bit_t snd_db_record_index[0x00020];/* Index in the UAR Context Table Entry.
1051  HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record.
1052  The entry is obtained via the usr_page field.
1053  Not valid for EE. */
1054 /* -------------- */
1055  pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
1057 /* -------------- */
1058  pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */
1060 /* -------------- */
1062  pseudo_bit_t rsc[0x00001]; /* 1 - all receive WQEs generate CQEs.
1063  0 - only receive WQEs with C bit set generate completion.
1064  Not valid (reserved) in EE context.
1065  */
1066  pseudo_bit_t ric[0x00001]; /* Invalid Credits.
1067  1 - place "Invalid Credits" to ACKs sent from this queue.
1068  0 - ACKs report the actual number of end to end credits on the connection.
1069  Not valid (reserved) in EE context.
1070  Must be set to 1 on QPs which are attached to SRQ. */
1072  pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
1073  pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
1074  pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
1076  pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max.
1077  Must be 0 for EE context. */
1079 /* -------------- */
1080  pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */
1081  pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8).
1082  Not valid (reserved) in EE context. */
1084 /* -------------- */
1086  pseudo_bit_t ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer.
1087  This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */
1088 /* -------------- */
1089  pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
1091 /* -------------- */
1093  pseudo_bit_t rcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */
1094 /* -------------- */
1095  pseudo_bit_t rcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
1096  HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record.
1097  The entry is obtained via the usr_page field.
1098  Not valid for EE. */
1099 /* -------------- */
1100  pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams.
1101  On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
1102  Not valid (reserved) in EE context. */
1103 /* -------------- */
1104  pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors.
1105  SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
1106  pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
1108 /* -------------- */
1109  pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */
1111 /* -------------- */
1112  pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
1113  Must be 0x0 in SQ initialization.
1114  (QUERY_QPEE only). */
1115  pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
1116  Must be 0x0 in RQ initialization.
1117  (QUERY_QPEE only). */
1118 /* -------------- */
1120 /* -------------- */
1121 };
1122 
1123 /* Clear Interrupt [63:0] */
1124 
1125 struct arbelprm_clr_int_st { /* Little Endian */
1126  pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32]
1127  Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1128  This register is write-only. Reading from this register will cause undefined result
1129  */
1130 /* -------------- */
1131  pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0]
1132  Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1133  This register is write-only. Reading from this register will cause undefined result */
1134 /* -------------- */
1135 };
1136 
1137 /* EQ_Arm_DB_Region */
1138 
1139 struct arbelprm_eq_arm_db_region_st { /* Little Endian */
1140  pseudo_bit_t eq_x_arm_h[0x00020]; /* EQ[63:32] X state.
1141  This register is used to Arm EQs when setting the appropriate bits. */
1142 /* -------------- */
1143  pseudo_bit_t eq_x_arm_l[0x00020]; /* EQ[31:0] X state.
1144  This register is used to Arm EQs when setting the appropriate bits. */
1145 /* -------------- */
1146 };
1147 
1148 /* EQ Set CI DBs Table */
1149 
1150 struct arbelprm_eq_set_ci_table_st { /* Little Endian */
1151  pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */
1152 /* -------------- */
1154 /* -------------- */
1155  pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */
1156 /* -------------- */
1158 /* -------------- */
1159  pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */
1160 /* -------------- */
1162 /* -------------- */
1163  pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */
1164 /* -------------- */
1166 /* -------------- */
1167  pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */
1168 /* -------------- */
1170 /* -------------- */
1171  pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */
1172 /* -------------- */
1174 /* -------------- */
1175  pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */
1176 /* -------------- */
1178 /* -------------- */
1179  pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */
1180 /* -------------- */
1182 /* -------------- */
1183  pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */
1184 /* -------------- */
1186 /* -------------- */
1187  pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */
1188 /* -------------- */
1190 /* -------------- */
1191  pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */
1192 /* -------------- */
1194 /* -------------- */
1195  pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */
1196 /* -------------- */
1198 /* -------------- */
1199  pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */
1200 /* -------------- */
1202 /* -------------- */
1203  pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */
1204 /* -------------- */
1206 /* -------------- */
1207  pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */
1208 /* -------------- */
1210 /* -------------- */
1211  pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */
1212 /* -------------- */
1214 /* -------------- */
1215  pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */
1216 /* -------------- */
1218 /* -------------- */
1219  pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */
1220 /* -------------- */
1222 /* -------------- */
1223  pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */
1224 /* -------------- */
1226 /* -------------- */
1227  pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */
1228 /* -------------- */
1230 /* -------------- */
1231  pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */
1232 /* -------------- */
1234 /* -------------- */
1235  pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */
1236 /* -------------- */
1238 /* -------------- */
1239  pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */
1240 /* -------------- */
1242 /* -------------- */
1243  pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */
1244 /* -------------- */
1246 /* -------------- */
1247  pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */
1248 /* -------------- */
1250 /* -------------- */
1251  pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */
1252 /* -------------- */
1254 /* -------------- */
1255  pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */
1256 /* -------------- */
1258 /* -------------- */
1259  pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */
1260 /* -------------- */
1262 /* -------------- */
1263  pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */
1264 /* -------------- */
1266 /* -------------- */
1267  pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */
1268 /* -------------- */
1270 /* -------------- */
1271  pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */
1272 /* -------------- */
1274 /* -------------- */
1275  pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */
1276 /* -------------- */
1278 /* -------------- */
1279  pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */
1280 /* -------------- */
1282 /* -------------- */
1283  pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */
1284 /* -------------- */
1286 /* -------------- */
1287  pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */
1288 /* -------------- */
1290 /* -------------- */
1291  pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */
1292 /* -------------- */
1294 /* -------------- */
1295  pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */
1296 /* -------------- */
1298 /* -------------- */
1299  pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */
1300 /* -------------- */
1302 /* -------------- */
1303  pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */
1304 /* -------------- */
1306 /* -------------- */
1307  pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */
1308 /* -------------- */
1310 /* -------------- */
1311  pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */
1312 /* -------------- */
1314 /* -------------- */
1315  pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */
1316 /* -------------- */
1318 /* -------------- */
1319  pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */
1320 /* -------------- */
1322 /* -------------- */
1323  pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */
1324 /* -------------- */
1326 /* -------------- */
1327  pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */
1328 /* -------------- */
1330 /* -------------- */
1331  pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */
1332 /* -------------- */
1334 /* -------------- */
1335  pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */
1336 /* -------------- */
1338 /* -------------- */
1339  pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */
1340 /* -------------- */
1342 /* -------------- */
1343  pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */
1344 /* -------------- */
1346 /* -------------- */
1347  pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */
1348 /* -------------- */
1350 /* -------------- */
1351  pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */
1352 /* -------------- */
1354 /* -------------- */
1355  pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */
1356 /* -------------- */
1358 /* -------------- */
1359  pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */
1360 /* -------------- */
1362 /* -------------- */
1363  pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */
1364 /* -------------- */
1366 /* -------------- */
1367  pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */
1368 /* -------------- */
1370 /* -------------- */
1371  pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */
1372 /* -------------- */
1374 /* -------------- */
1375  pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */
1376 /* -------------- */
1378 /* -------------- */
1379  pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */
1380 /* -------------- */
1382 /* -------------- */
1383  pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */
1384 /* -------------- */
1386 /* -------------- */
1387  pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */
1388 /* -------------- */
1390 /* -------------- */
1391  pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */
1392 /* -------------- */
1394 /* -------------- */
1395  pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */
1396 /* -------------- */
1398 /* -------------- */
1399  pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */
1400 /* -------------- */
1402 /* -------------- */
1403  pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */
1404 /* -------------- */
1406 /* -------------- */
1407 };
1408 
1409 /* InfiniHost-III-EX Configuration Registers */
1410 
1411 struct arbelprm_configuration_registers_st { /* Little Endian */
1413 /* -------------- */
1415 /* -------------- */
1417 /* -------------- */
1418 };
1419 
1420 /* QP_DB_Record */
1421 
1422 struct arbelprm_qp_db_record_st { /* Little Endian */
1423  pseudo_bit_t counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */
1425 /* -------------- */
1427  pseudo_bit_t res[0x00003]; /* 0x3 for SQ
1428  0x4 for RQ
1429  0x5 for SRQ */
1430  pseudo_bit_t qp_number[0x00018]; /* QP number */
1431 /* -------------- */
1432 };
1433 
1434 /* CQ_ARM_DB_Record */
1435 
1436 struct arbelprm_cq_arm_db_record_st { /* Little Endian */
1437  pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */
1438 /* -------------- */
1439  pseudo_bit_t cmd[0x00003]; /* 0x0 - No command
1440  0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter.
1441  0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter.
1442  0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated
1443  Other - Reserved */
1444  pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */
1445  pseudo_bit_t res[0x00003]; /* Must be 0x2 */
1446  pseudo_bit_t cq_number[0x00018]; /* CQ number */
1447 /* -------------- */
1448 };
1449 
1450 /* CQ_CI_DB_Record */
1451 
1452 struct arbelprm_cq_ci_db_record_st { /* Little Endian */
1453  pseudo_bit_t counter[0x00020]; /* CQ counter */
1454 /* -------------- */
1456  pseudo_bit_t res[0x00003]; /* Must be 0x1 */
1457  pseudo_bit_t cq_number[0x00018]; /* CQ number */
1458 /* -------------- */
1459 };
1460 
1461 /* Virtual_Physical_Mapping */
1462 
1463 struct arbelprm_virtual_physical_mapping_st { /* Little Endian */
1464  pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */
1465 /* -------------- */
1467  pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */
1468 /* -------------- */
1469  pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */
1470 /* -------------- */
1471  pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */
1473  pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */
1474 /* -------------- */
1475 };
1476 
1477 /* MOD_STAT_CFG */
1478 
1479 struct arbelprm_mod_stat_cfg_st { /* Little Endian */
1480  pseudo_bit_t log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */
1482  pseudo_bit_t srq[0x00001]; /* When set SRQs are supported */
1483  pseudo_bit_t srq_m[0x00001]; /* Modify SRQ parameters */
1485 /* -------------- */
1487 /* -------------- */
1488 };
1489 
1490 /* SRQ Context */
1491 
1492 struct arbelprm_srq_context_st { /* Little Endian */
1493  pseudo_bit_t srqn[0x00018]; /* SRQ number */
1494  pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue.
1495  Maximum value is 0x10, i.e. 16M WQEs. */
1496  pseudo_bit_t state[0x00004]; /* SRQ State:
1497  1111 - SW Ownership
1498  0000 - HW Ownership
1499  0001 - Error
1500  Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
1501 /* -------------- */
1502  pseudo_bit_t l_key[0x00020]; /* memory key (L-Key) to be used to access WQEs. */
1503 /* -------------- */
1504  pseudo_bit_t srq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue.
1505  HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record.
1506  The entry is obtained via the usr_page field. */
1507 /* -------------- */
1508  pseudo_bit_t usr_page[0x00018]; /* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */
1510  pseudo_bit_t log_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
1511 /* -------------- */
1512  pseudo_bit_t wqe_addr_h[0x00020]; /* Bits 63:32 of WQE address (WQE base address) */
1513 /* -------------- */
1515  pseudo_bit_t srq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */
1516 /* -------------- */
1517  pseudo_bit_t pd[0x00018]; /* SRQ protection domain. */
1519 /* -------------- */
1520  pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ.
1521  Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
1522  pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */
1523 /* -------------- */
1524  pseudo_bit_t srq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
1525  Must be 0x0 in SRQ initialization.
1526  (QUERY_SRQ only). */
1528 /* -------------- */
1530 /* -------------- */
1531 };
1532 
1533 /* PBL */
1534 
1535 struct arbelprm_pbl_st { /* Little Endian */
1536  pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */
1537 /* -------------- */
1538  pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */
1539 /* -------------- */
1540  pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */
1541 /* -------------- */
1542  pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */
1543 /* -------------- */
1544  pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */
1545 /* -------------- */
1546  pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */
1547 /* -------------- */
1548  pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */
1549 /* -------------- */
1550  pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */
1551 /* -------------- */
1552 };
1553 
1554 /* Performance Counters */
1555 
1556 struct arbelprm_performance_counters_st { /* Little Endian */
1557  pseudo_bit_t sqpc_access_cnt[0x00020];/* SQPC cache access count */
1558 /* -------------- */
1559  pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */
1560 /* -------------- */
1562 /* -------------- */
1563  pseudo_bit_t rqpc_access_cnt[0x00020];/* RQPC cache access count */
1564 /* -------------- */
1565  pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */
1566 /* -------------- */
1568 /* -------------- */
1569  pseudo_bit_t cqc_access_cnt[0x00020];/* CQC cache access count */
1570 /* -------------- */
1571  pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */
1572 /* -------------- */
1574 /* -------------- */
1575  pseudo_bit_t tpt_access_cnt[0x00020];/* TPT cache access count */
1576 /* -------------- */
1577  pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */
1578 /* -------------- */
1579  pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */
1580 /* -------------- */
1582 /* -------------- */
1583 };
1584 
1585 /* Transport and CI Error Counters */
1586 
1588  pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */
1589 /* -------------- */
1590  pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */
1591 /* -------------- */
1592  pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */
1593 /* -------------- */
1594  pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */
1595 /* -------------- */
1596  pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */
1597 /* -------------- */
1598  pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */
1599 /* -------------- */
1600  pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */
1601 /* -------------- */
1602  pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */
1603 /* -------------- */
1604  pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error.
1605  Incremented each time a CQE with error is generated */
1606 /* -------------- */
1607  pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error.
1608  Incremented each time a CQE with error is generated */
1609 /* -------------- */
1611 /* -------------- */
1612  pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */
1613 /* -------------- */
1615 /* -------------- */
1616  pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */
1617 /* -------------- */
1618  pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */
1619 /* -------------- */
1621 /* -------------- */
1622  pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors
1623  NAK-Invalid Request on:
1624  1. Unsupported OpCode: Responder detected an unsupported OpCode.
1625  2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such
1626  as a missing "Last" packet.
1627  Note: there is no PSN error, thus this does not indicate a dropped packet. */
1628 /* -------------- */
1629  pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors.
1630  NAK may or may not be sent.
1631  1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only):
1632  Inbound request OpCode was either reserved, or was for a function not supported by this
1633  QP. (E.g. RDMA or ATOMIC on QP not set up for this).
1634  2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion.
1635  3. Too many RDMA READ or ATOMIC Requests: There were more requests received
1636  and not ACKed than allowed for the connection.
1637  4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder
1638  detected an error in the sequence of OpCodes; a missing "Last" packet
1639  5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder
1640  detected an error in the sequence of OpCodes; a missing "First" packet
1641  6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able
1642  buffer space.
1643  7. Length error: RDMA WRITE request message contained too much or too little pay-load
1644  data compared to the DMA length advertised in the first or only packet.
1645  8. Length error: Payload length was not consistent with the opcode:
1646  a: 0 byte <= "only" <= PMTU bytes
1647  b: ("first" or "middle") == PMTU bytes
1648  c: 1byte <= "last" <= PMTU bytes
1649  9. Length error: Inbound message exceeded the size supported by the CA port. */
1650 /* -------------- */
1651  pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors.
1652  NAK-Remote Access Error on:
1653  R_Key Violation: Responder detected an invalid R_Key while executing an RDMA
1654  Request. */
1655 /* -------------- */
1656  pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors.
1657  R_Key Violation Responder detected an R_Key violation while executing an RDMA
1658  request.
1659  NAK may or may not be sent. */
1660 /* -------------- */
1661  pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors.
1662  NAK-Remote Operation Error on:
1663  Remote Operation Error: Responder encountered an error, (local to the responder),
1664  which prevented it from completing the request. */
1665 /* -------------- */
1666  pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors.
1667  NAK-Remote Operation Error on:
1668  1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing
1669  the packet.
1670  2. Remote Operation Error: Responder encountered an error, (local to the responder),
1671  which prevented it from completing the request. */
1672 /* -------------- */
1673  pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */
1674 /* -------------- */
1676 /* -------------- */
1677  pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */
1678 /* -------------- */
1680 /* -------------- */
1681  pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */
1682 /* -------------- */
1683  pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */
1684 /* -------------- */
1686 /* -------------- */
1687  pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */
1688 /* -------------- */
1690 /* -------------- */
1691  pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */
1692 /* -------------- */
1694 /* -------------- */
1695  pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */
1696 /* -------------- */
1698 /* -------------- */
1699  pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */
1700 /* -------------- */
1701  pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */
1702 /* -------------- */
1703  pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */
1704 /* -------------- */
1706 /* -------------- */
1707  pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */
1708 /* -------------- */
1709  pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */
1710 /* -------------- */
1711  pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */
1712 /* -------------- */
1714 /* -------------- */
1715  pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */
1716 /* -------------- */
1718 /* -------------- */
1719  pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */
1720 /* -------------- */
1721  pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */
1722 /* -------------- */
1723  pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */
1724 /* -------------- */
1726 /* -------------- */
1727 };
1728 
1729 /* Event_data Field - HCR Completion Event */
1730 
1731 struct arbelprm_hcr_completion_event_st { /* Little Endian */
1732  pseudo_bit_t token[0x00010]; /* HCR Token */
1734 /* -------------- */
1736 /* -------------- */
1737  pseudo_bit_t status[0x00008]; /* HCR Status */
1739 /* -------------- */
1740  pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */
1741 /* -------------- */
1742  pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */
1743 /* -------------- */
1745 /* -------------- */
1746 };
1747 
1748 /* Completion with Error CQE */
1749 
1750 struct arbelprm_completion_with_error_st { /* Little Endian */
1751  pseudo_bit_t myqpn[0x00018]; /* Indicates the QP for which completion is being reported */
1753 /* -------------- */
1755 /* -------------- */
1758  pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome:
1759  0x01 - Local Length Error
1760  0x02 - Local QP Operation Error
1761  0x03 - Local EE Context Operation Error
1762  0x04 - Local Protection Error
1763  0x05 - Work Request Flushed Error
1764  0x06 - Memory Window Bind Error
1765  0x10 - Bad Response Error
1766  0x11 - Local Access Error
1767  0x12 - Remote Invalid Request Error
1768  0x13 - Remote Access Error
1769  0x14 - Remote Operation Error
1770  0x15 - Transport Retry Counter Exceeded
1771  0x16 - RNR Retry Counter Exceeded
1772  0x20 - Local RDD Violation Error
1773  0x21 - Remote Invalid RD Request
1774  0x22 - Remote Aborted Error
1775  0x23 - Invalid EE Context Number
1776  0x24 - Invalid EE Context State
1777  other - Reserved
1778  Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
1779 /* -------------- */
1781 /* -------------- */
1783  pseudo_bit_t wqe_addr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
1784 /* -------------- */
1786  pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */
1788  pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.
1789 
1790  The following values are reported in case of completion with error:
1791  0xFE - For completion with error on Receive Queues
1792  0xFF - For completion with error on Send Queues */
1793 /* -------------- */
1794 };
1795 
1796 /* Resize CQ Input Mailbox */
1797 
1798 struct arbelprm_resize_cq_st { /* Little Endian */
1800 /* -------------- */
1801  pseudo_bit_t start_addr_h[0x00020]; /* Start address of CQ[63:32].
1802  Must be aligned on CQE size (32 bytes) */
1803 /* -------------- */
1804  pseudo_bit_t start_addr_l[0x00020]; /* Start address of CQ[31:0].
1805  Must be aligned on CQE size (32 bytes) */
1806 /* -------------- */
1808  pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */
1810 /* -------------- */
1812 /* -------------- */
1813  pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */
1814 /* -------------- */
1816 /* -------------- */
1817 };
1818 
1819 /* MAD_IFC Input Modifier */
1820 
1821 struct arbelprm_mad_ifc_input_modifier_st { /* Little Endian */
1822  pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */
1823  pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
1824  Required for trap generation when BKey check is enabled and for global routed packets. */
1826  pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
1827  This field is required for trap generation upon MKey/BKey validation. */
1828 /* -------------- */
1829 };
1830 
1831 /* MAD_IFC Input Mailbox */
1832 
1833 struct arbelprm_mad_ifc_st { /* Little Endian */
1834  pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */
1835 /* -------------- */
1836  pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD.
1837  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1839 /* -------------- */
1840  pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD.
1841  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1843 /* -------------- */
1844  pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
1845  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1846  pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD.
1847  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1848  pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid.
1849  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1851  pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD.
1852  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1853 /* -------------- */
1854  pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD.
1855  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1857 /* -------------- */
1859 /* -------------- */
1860  pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list.
1861  Valid if Mad_extended_info bit (in the input modifier) and g bit are set.
1862  Otherwise this field is reserved. */
1863 /* -------------- */
1865 /* -------------- */
1866 };
1867 
1868 /* Query Debug Message */
1869 
1870 struct arbelprm_query_debug_msg_st { /* Little Endian */
1871  pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */
1872 /* -------------- */
1873  pseudo_bit_t v[0x00001]; /* Physical translation is valid */
1875  pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */
1876 /* -------------- */
1877  pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
1878 /* -------------- */
1879  pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */
1880 /* -------------- */
1881  pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */
1882 /* -------------- */
1883  pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */
1884 /* -------------- */
1886 /* -------------- */
1887  pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */
1888 /* -------------- */
1889  pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */
1890 /* -------------- */
1892 /* -------------- */
1893  pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */
1894 /* -------------- */
1895  pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */
1896 /* -------------- */
1897  pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */
1898 /* -------------- */
1899  pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */
1900 /* -------------- */
1901  pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */
1902 /* -------------- */
1903  pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */
1904 /* -------------- */
1905  pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */
1906 /* -------------- */
1907  pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */
1908 /* -------------- */
1909  pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */
1910 /* -------------- */
1911  pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */
1912 /* -------------- */
1913  pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */
1914 /* -------------- */
1915  pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */
1916 /* -------------- */
1917  pseudo_bit_t buff6_addr[0x00020]; /* Address in firmware area of Trace Buffer 6 */
1918 /* -------------- */
1919  pseudo_bit_t buff6_size[0x00020]; /* Size of Trace Buffer 6 */
1920 /* -------------- */
1921  pseudo_bit_t buff7_addr[0x00020]; /* Address in firmware area of Trace Buffer 7 */
1922 /* -------------- */
1923  pseudo_bit_t buff7_size[0x00020]; /* Size of Trace Buffer 7 */
1924 /* -------------- */
1926 /* -------------- */
1927 };
1928 
1929 /* User Access Region */
1930 
1931 struct arbelprm_uar_st { /* Little Endian */
1932  struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */
1933 /* -------------- */
1934  struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */
1935 /* -------------- */
1937 /* -------------- */
1939 /* -------------- */
1941 /* -------------- */
1942 };
1943 
1944 /* Receive doorbell */
1945 
1946 struct arbelprm_receive_doorbell_st { /* Little Endian */
1948  pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
1950 /* -------------- */
1952  pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */
1954  pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */
1955 /* -------------- */
1956 };
1957 
1958 /* SET_IB Parameters */
1959 
1960 struct arbelprm_set_ib_st { /* Little Endian */
1961  pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */
1963  pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
1964  system_image_guid and sig must be the same for all ports. */
1966 /* -------------- */
1967  pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */
1968 /* -------------- */
1969  pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
1970  Must be the same for both ports. */
1971 /* -------------- */
1972  pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
1973  Must be the same for both ports. */
1974 /* -------------- */
1976 /* -------------- */
1977 };
1978 
1979 /* Multicast Group Member */
1980 
1981 struct arbelprm_mgm_entry_st { /* Little Endian */
1983  pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.
1984  The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.
1985  next_gid_index=0 means end of the chain. */
1986 /* -------------- */
1988 /* -------------- */
1989  pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format.
1990  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1991 /* -------------- */
1992  pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format.
1993  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1994 /* -------------- */
1995  pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format.
1996  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1997 /* -------------- */
1998  pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format.
1999  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
2000 /* -------------- */
2001  struct arbelprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */
2002 /* -------------- */
2003  struct arbelprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */
2004 /* -------------- */
2005  struct arbelprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */
2006 /* -------------- */
2007  struct arbelprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */
2008 /* -------------- */
2009  struct arbelprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */
2010 /* -------------- */
2011  struct arbelprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */
2012 /* -------------- */
2013  struct arbelprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */
2014 /* -------------- */
2015  struct arbelprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */
2016 /* -------------- */
2017 };
2018 
2019 /* INIT_IB Parameters */
2020 
2021 struct arbelprm_init_ib_st { /* Little Endian */
2023  pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15.
2024  Legal values are 1,2,4 and 8. */
2025  pseudo_bit_t port_width_cap[0x00004];/* IB Port Width
2026  1 - 1x
2027  3 - 1x, 4x
2028  11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208)
2029  else - Reserved */
2030  pseudo_bit_t mtu_cap[0x00004]; /* Maximum MTU Supported
2031  0x0 - Reserved
2032  0x1 - 256
2033  0x2 - 512
2034  0x3 - 1024
2035  0x4 - 2048
2036  0x5 - 0xF Reserved */
2037  pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */
2038  pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified.
2039  node_guid and ng must be the same for all ports. */
2040  pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
2041  system_image_guid and sig must be the same for all ports. */
2043 /* -------------- */
2044  pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */
2046 /* -------------- */
2047  pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port.
2048  Must be the same for both ports. */
2050 /* -------------- */
2052 /* -------------- */
2053  pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */
2054 /* -------------- */
2055  pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */
2056 /* -------------- */
2057  pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set
2058  Must be the same for both ports. */
2059 /* -------------- */
2060  pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set
2061  Must be the same for both ports. */
2062 /* -------------- */
2063  pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
2064  Must be the same for both ports. */
2065 /* -------------- */
2066  pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
2067  Must be the same for both ports. */
2068 /* -------------- */
2070 /* -------------- */
2071 };
2072 
2073 /* Query Device Limitations */
2074 
2075 struct arbelprm_query_dev_lim_st { /* Little Endian */
2077 /* -------------- */
2078  pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */
2080  pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
2081  The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
2083  pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
2084  pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
2085 /* -------------- */
2086  pseudo_bit_t log_max_ee[0x00005]; /* Log2 of the Maximum number of EE contexts supported */
2088  pseudo_bit_t log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use
2089  The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */
2091  pseudo_bit_t log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set.
2092  */
2094  pseudo_bit_t log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use
2095  The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1
2096  This parameter is valid only if the SRQ bit is set. */
2097 /* -------------- */
2098  pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */
2100  pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
2101  The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
2103  pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
2105 /* -------------- */
2106  pseudo_bit_t log_max_eq[0x00003]; /* Log2 of the Maximum number of EQs */
2108  pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use
2109  The reserved resources are numbered from 0 to num_rsvd_eqs-1
2110  If 0 - no resources are reserved. */
2112  pseudo_bit_t log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */
2114  pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */
2115 /* -------------- */
2116  pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */
2118  pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
2119  The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
2121  pseudo_bit_t log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */
2123  pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use
2124  The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
2125  */
2126 /* -------------- */
2128 /* -------------- */
2129  pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
2131  pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
2133 /* -------------- */
2134  pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
2136  pseudo_bit_t log2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use
2137  The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */
2138 /* -------------- */
2139  pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */
2141 /* -------------- */
2142  pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */
2143  pseudo_bit_t max_vl[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */
2144  pseudo_bit_t max_port_width[0x00004];/* IB Port Width
2145  1 - 1x
2146  3 - 1x, 4x
2147  11 - 1x, 4x or 12x
2148  else - Reserved */
2149  pseudo_bit_t max_mtu[0x00004]; /* Maximum MTU Supported
2150  0x0 - Reserved
2151  0x1 - 256
2152  0x2 - 512
2153  0x3 - 1024
2154  0x4 - 2048
2155  0x5 - 0xF Reserved */
2156  pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
2157  The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */
2159 /* -------------- */
2160  pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */
2162 /* -------------- */
2163  pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */
2165  pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported
2166  bit 0 - full bw
2167  bit 1 - 1/4 bw
2168  bit 2 - 1/8 bw
2169  bit 3 - 1/2 bw; */
2170 /* -------------- */
2172 /* -------------- */
2173  pseudo_bit_t rc[0x00001]; /* RC Transport supported */
2174  pseudo_bit_t uc[0x00001]; /* UC Transport Supported */
2175  pseudo_bit_t ud[0x00001]; /* UD Transport Supported */
2176  pseudo_bit_t rd[0x00001]; /* RD Transport Supported */
2177  pseudo_bit_t raw_ipv6[0x00001]; /* Raw IPv6 Transport Supported */
2178  pseudo_bit_t raw_ether[0x00001]; /* Raw Ethertype Transport Supported */
2179  pseudo_bit_t srq[0x00001]; /* SRQ is supported
2180  */
2181  pseudo_bit_t ipo_ib_checksum[0x00001];/* IP over IB checksum is supported */
2182  pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */
2183  pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */
2185  pseudo_bit_t mw[0x00001]; /* Memory windows supported */
2186  pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */
2187  pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */
2188  pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */
2189  pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */
2190  pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */
2192  pseudo_bit_t pg[0x00001]; /* Paging on demand supported */
2193  pseudo_bit_t r[0x00001]; /* Router mode supported */
2195 /* -------------- */
2196  pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2).
2197  For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */
2199  pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */
2201  pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use
2202  The reserved resources are numbered from 0 to num_reserved_uars-1
2203  Note that UAR number num_reserved_uars is always for the kernel. */
2204 /* -------------- */
2206 /* -------------- */
2207  pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */
2208  pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */
2210 /* -------------- */
2211  pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */
2212  pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */
2214 /* -------------- */
2216 /* -------------- */
2217  pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */
2218  pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
2219  The reserved resources are numbered from 0 to num_reserved_mcgs-1
2220  If 0 - no resources are reserved. */
2222  pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */
2224 /* -------------- */
2225  pseudo_bit_t log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */
2227  pseudo_bit_t num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use
2228  The reserved resources are numbered from 0 to num_reserved_rdds-1.
2229  If 0 - no resources are reserved. */
2230  pseudo_bit_t log_max_pd[0x00006]; /* Log2 of the maximum number of PDs */
2232  pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use
2233  The reserved resources are numbered from 0 to num_reserved_pds-1
2234  If 0 - no resources are reserved. */
2235 /* -------------- */
2237 /* -------------- */
2238  pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device
2239  For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2240  pseudo_bit_t eec_entry_sz[0x00010]; /* EEC Entry Size for the device
2241  For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2242 /* -------------- */
2243  pseudo_bit_t eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device
2244  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2245  pseudo_bit_t eeec_entry_sz[0x00010];/* Extended EEC entry size for the device
2246  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2247 /* -------------- */
2248  pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device
2249  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2250  pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device
2251  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2252 /* -------------- */
2253  pseudo_bit_t uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size
2254  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2255  pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device
2256  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2257 /* -------------- */
2258  pseudo_bit_t mpt_entry_sz[0x00010]; /* MPT entry size in Bytes for the device.
2259  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2260  pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device.
2261  For the InfiniHost-III-EX MT25208 entry size is 8 bytes */
2262 /* -------------- */
2263  pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */
2264  pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism:
2265  0 - Type 2A - QP Number Association; or
2266  1 - Type 2B - QP Number and PD Association. */
2267  pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */
2268  pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. (The device does not supports Block List) */
2269  pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */
2270  pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */
2272  pseudo_bit_t log_pbl_sz[0x00006]; /* Log2 of the Maximum Physical Buffer List size in Bytes supported by this HCA when invoking the Allocate L_Key verb.
2273  */
2275 /* -------------- */
2276  pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */
2277 /* -------------- */
2278  pseudo_bit_t lamr[0x00001]; /* When set the device requires local attached memory in order to operate.
2279  When set, ICM pages, Firmware Area and ICM auxiliary pages must be allocated in the local attached memory. */
2281 /* -------------- */
2282  pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */
2283 /* -------------- */
2284  pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */
2285 /* -------------- */
2287 /* -------------- */
2288 };
2289 
2290 /* QUERY_ADAPTER Parameters Block */
2291 
2292 struct arbelprm_query_adapter_st { /* Little Endian */
2294 /* -------------- */
2296  pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */
2297 /* -------------- */
2299 /* -------------- */
2301 /* -------------- */
2302 };
2303 
2304 /* QUERY_FW Parameters Block */
2305 
2306 struct arbelprm_query_fw_st { /* Little Endian */
2307  pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */
2308  pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
2309 /* -------------- */
2310  pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */
2311  pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
2312 /* -------------- */
2313  pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
2315  pseudo_bit_t wqe_h_mode[0x00001]; /* Hermon mode. If '1', then WQE and AV format is the advanced format */
2316  pseudo_bit_t zb_wq_cq[0x00001]; /* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */
2317 /* -------------- */
2318  pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
2320  pseudo_bit_t dt[0x00001]; /* Debug Trace Support
2321  0 - Debug trace is not supported
2322  1 - Debug trace is supported */
2323 /* -------------- */
2324  pseudo_bit_t cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */
2326 /* -------------- */
2328 /* -------------- */
2329  pseudo_bit_t clr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address.
2330  Points to 64 bit register. */
2331 /* -------------- */
2332  pseudo_bit_t clr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address.
2333  Points to 64 bit register. */
2334 /* -------------- */
2336 /* -------------- */
2337  pseudo_bit_t error_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
2338 /* -------------- */
2339  pseudo_bit_t error_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */
2340 /* -------------- */
2341  pseudo_bit_t error_buf_size[0x00020];/* Size in words */
2342 /* -------------- */
2344 /* -------------- */
2345  pseudo_bit_t eq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address.
2346  Points to 64 bit register.
2347  Setting bit x in the offset, arms EQ number x.
2348  */
2349 /* -------------- */
2350  pseudo_bit_t eq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address.
2351  Points to 64 bit register.
2352  Setting bit x in the offset, arms EQ number x. */
2353 /* -------------- */
2354  pseudo_bit_t eq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address.
2355  Points to a the EQ Set CI DBs Table base address. */
2356 /* -------------- */
2357  pseudo_bit_t eq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address.
2358  Points to a the EQ Set CI DBs Table base address. */
2359 /* -------------- */
2360  pseudo_bit_t cmd_db_dw1[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2361  pseudo_bit_t cmd_db_dw0[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2362 /* -------------- */
2363  pseudo_bit_t cmd_db_dw3[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2364  pseudo_bit_t cmd_db_dw2[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2365 /* -------------- */
2366  pseudo_bit_t cmd_db_dw5[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2367  pseudo_bit_t cmd_db_dw4[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2368 /* -------------- */
2369  pseudo_bit_t cmd_db_dw7[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2370  pseudo_bit_t cmd_db_dw6[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */
2371 /* -------------- */
2372  pseudo_bit_t cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
2373 /* -------------- */
2374  pseudo_bit_t cmd_db_addr_base_l[0x00020];/* Low bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */
2375 /* -------------- */
2377 /* -------------- */
2378 };
2379 
2380 /* ACCESS_LAM */
2381 
2382 struct arbelprm_access_lam_st { /* Little Endian */
2384 /* -------------- */
2386 /* -------------- */
2387 };
2388 
2389 /* ENABLE_LAM Parameters Block */
2390 
2391 struct arbelprm_enable_lam_st { /* Little Endian */
2392  pseudo_bit_t lam_start_adr_h[0x00020];/* LAM start address [63:32] */
2393 /* -------------- */
2394  pseudo_bit_t lam_start_adr_l[0x00020];/* LAM start address [31:0] */
2395 /* -------------- */
2396  pseudo_bit_t lam_end_adr_h[0x00020];/* LAM end address [63:32] */
2397 /* -------------- */
2398  pseudo_bit_t lam_end_adr_l[0x00020];/* LAM end address [31:0] */
2399 /* -------------- */
2400  pseudo_bit_t di[0x00002]; /* Data Integrity Configuration:
2401  00 - none
2402  01 - Parity
2403  10 - ECC Detection Only
2404  11 - ECC With Correction */
2405  pseudo_bit_t ap[0x00002]; /* Auto Precharge Mode
2406  00 - No auto precharge
2407  01 - Auto precharge per transaction
2408  10 - Auto precharge per 64 bytes
2409  11 - reserved */
2410  pseudo_bit_t dh[0x00001]; /* When set, LAM is Hidden and can not be accessed directly from the PCI bus. */
2412 /* -------------- */
2414 /* -------------- */
2415  struct arbelprm_dimminfo_st dimm0; /* Logical DIMM 0 Parameters */
2416 /* -------------- */
2417  struct arbelprm_dimminfo_st dimm1; /* Logical DIMM 1 Parameters */
2418 /* -------------- */
2420 /* -------------- */
2421 };
2422 
2423 /* Memory Access Parameters for UD Address Vector Table */
2424 
2425 struct arbelprm_udavtable_memory_parameters_st { /* Little Endian */
2426  pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */
2427 /* -------------- */
2428  pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */
2430  pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
2432 /* -------------- */
2433 };
2434 
2435 /* INIT_HCA & QUERY_HCA Parameters Block */
2436 
2437 struct arbelprm_init_hca_st { /* Little Endian */
2439 /* -------------- */
2441  pseudo_bit_t time_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented.
2442  The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond)
2443  When sets to Zero, timestamp reporting in the CQE is disabled.
2444  This feature is currently not supported.
2445  */
2446  pseudo_bit_t hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */
2447 /* -------------- */
2449  pseudo_bit_t router_qp[0x00010]; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet.
2450  Valid only if RE bit is set */
2452  pseudo_bit_t re[0x00001]; /* Router Mode Enable
2453  If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */
2454 /* -------------- */
2455  pseudo_bit_t udp[0x00001]; /* UD Port Check Enable
2456  0 - Port field in Address Vector is ignored
2457  1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
2458  pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations
2459  0 - Host is Little Endian
2460  1 - Host is Big endian
2461  */
2463  pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
2464  pseudo_bit_t sph[0x00001]; /* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet
2465  1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet
2466  */
2467  pseudo_bit_t rph[0x00001]; /* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet
2468  1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet
2469  */
2471  pseudo_bit_t responder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester .
2472  responder_exu/16 = (number of responder exu engines)/(total number of engines)
2473  Legal values are 0x0-0xF. 0 is "auto".
2474 
2475  */
2477  pseudo_bit_t wqe_quota[0x0000f]; /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */
2478  pseudo_bit_t wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */
2479 /* -------------- */
2481 /* -------------- */
2483 /* -------------- */
2485 /* -------------- */
2487 /* -------------- */
2489 /* -------------- */
2491 /* -------------- */
2493 /* -------------- */
2494  struct arbelprm_uar_params_st uar_parameters;/* UAR Parameters */
2495 /* -------------- */
2497 /* -------------- */
2498 };
2499 
2500 /* Event Queue Context Table Entry */
2501 
2502 struct arbelprm_eqc_st { /* Little Endian */
2504  pseudo_bit_t st[0x00004]; /* Event delivery state machine
2505  0x9 - Armed
2506  0xA - Fired
2507  0xB - Always_Armed (auto-rearm)
2508  other - reserved */
2510  pseudo_bit_t oi[0x00001]; /* Oerrun ignore.
2511  If set, HW will not check EQ full condition when writing new EQEs. */
2512  pseudo_bit_t tr[0x00001]; /* Translation Required. If set - EQ access undergo address translation. */
2514  pseudo_bit_t owner[0x00004]; /* 0 - SW ownership
2515  1 - HW ownership
2516  Valid for the QUERY_EQ and HW2SW_EQ commands only */
2517  pseudo_bit_t status[0x00004]; /* EQ status:
2518  0000 - OK
2519  1010 - EQ write failure
2520  Valid for the QUERY_EQ and HW2SW_EQ commands only */
2521 /* -------------- */
2522  pseudo_bit_t start_address_h[0x00020];/* Start Address of Event Queue[63:32]. */
2523 /* -------------- */
2524  pseudo_bit_t start_address_l[0x00020];/* Start Address of Event Queue[31:0].
2525  Must be aligned on 32-byte boundary */
2526 /* -------------- */
2528  pseudo_bit_t log_eq_size[0x00005]; /* Amount of entries in this EQ is 2^log_eq_size.
2529  Log_eq_size must be bigger than 1.
2530  Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */
2532 /* -------------- */
2534 /* -------------- */
2535  pseudo_bit_t intr[0x00008]; /* Interrupt (message) to be generated to report event to INT layer.
2536  00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express.
2537  10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported).
2538  All other values are reserved and should not be used.
2539 
2540  If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */
2542 /* -------------- */
2543  pseudo_bit_t pd[0x00018]; /* PD to be used to access EQ */
2545 /* -------------- */
2546  pseudo_bit_t lkey[0x00020]; /* Memory key (L-Key) to be used to access EQ */
2547 /* -------------- */
2549 /* -------------- */
2550  pseudo_bit_t consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue.
2551  Must be initalized to zero while opening EQ */
2552 /* -------------- */
2553  pseudo_bit_t producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA.
2554  Must be initalized to zero while opening EQ. */
2555 /* -------------- */
2557 /* -------------- */
2558 };
2559 
2560 /* Memory Translation Table (MTT) Entry */
2561 
2562 struct arbelprm_mtt_st { /* Little Endian */
2563  pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2564 /* -------------- */
2565  pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
2567  pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2568 /* -------------- */
2569 };
2570 
2571 /* Memory Protection Table (MPT) Entry */
2572 
2573 struct arbelprm_mpt_st { /* Little Endian */
2575  pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */
2576  pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */
2577  pseudo_bit_t lr[0x00001]; /* If set - local read access enabled */
2578  pseudo_bit_t lw[0x00001]; /* If set - local write access enabled */
2579  pseudo_bit_t rr[0x00001]; /* If set - remote read access enabled. */
2580  pseudo_bit_t rw[0x00001]; /* If set - remote write access enabled */
2581  pseudo_bit_t a[0x00001]; /* If set - remote Atomic access is enabled */
2582  pseudo_bit_t eb[0x00001]; /* If set - Bind is enabled. Valid for region entry only. */
2584  pseudo_bit_t status[0x00004]; /* Region/Window Status
2585  0xF - not valid (SW ownership)
2586  0x3 - FREE state
2587  else - HW ownership
2588  Unbound Type I windows are doneted reg_wnd_len field equals zero.
2589  Unbound Type II windows are donated by Status=FREE. */
2590 /* -------------- */
2591  pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
2592  page_size should be less than 20. */
2594  pseudo_bit_t type[0x00001]; /* Applicable for windows only, must be zero for regions
2595  0 - Type one window
2596  1 - Type two window */
2597  pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */
2598 /* -------------- */
2599  pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}.
2600  */
2601 /* -------------- */
2602  pseudo_bit_t pd[0x00018]; /* Protection Domain */
2604  pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region.
2605  Must be set for type2 windows and non-shared physical memory regions.
2606  Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */
2607  pseudo_bit_t zb[0x00001]; /* When set, this region is Zero Based Region */
2608  pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */
2609  pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region.
2610  Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT.
2611  If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail.
2612  */
2614 /* -------------- */
2615  pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */
2616 /* -------------- */
2617  pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */
2618 /* -------------- */
2619  pseudo_bit_t reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */
2620 /* -------------- */
2621  pseudo_bit_t reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */
2622 /* -------------- */
2623  pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT.
2624  On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.
2625  The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
2626 /* -------------- */
2627  pseudo_bit_t win_cnt[0x00020]; /* Number of windows bound to this region. Valid for regions only.
2628  The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
2629 /* -------------- */
2631 /* -------------- */
2632  pseudo_bit_t mtt_adr_h[0x00006]; /* Base (first) address of the MTT relative to MTT base in the ICM */
2634 /* -------------- */
2636  pseudo_bit_t mtt_adr_l[0x0001d]; /* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */
2637 /* -------------- */
2638  pseudo_bit_t mtt_sz[0x00020]; /* Number of MTT entries allocated for this MR.
2639  When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved.
2640  When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */
2641 /* -------------- */
2643 /* -------------- */
2644 };
2645 
2646 /* Completion Queue Context Table Entry */
2647 
2648 struct arbelprm_completion_queue_context_st { /* Little Endian */
2650  pseudo_bit_t st[0x00004]; /* Event delivery state machine
2651  0x0 - reserved
2652  0x9 - ARMED (Request for Notification)
2653  0x6 - ARMED SOLICITED (Request Solicited Notification)
2654  0xA - FIRED
2655  other - reserved
2656 
2657  Must be 0x0 in CQ initialization.
2658  Valid for the QUERY_CQ and HW2SW_CQ commands only. */
2660  pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled.
2661  When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */
2663  pseudo_bit_t status[0x00004]; /* CQ status
2664  0000 - OK
2665  1001 - CQ overflow
2666  1010 - CQ write failure
2667  Valid for the QUERY_CQ and HW2SW_CQ commands only */
2668 /* -------------- */
2669  pseudo_bit_t start_address_h[0x00020];/* Start address of CQ[63:32].
2670  Must be aligned on CQE size (32 bytes) */
2671 /* -------------- */
2672  pseudo_bit_t start_address_l[0x00020];/* Start address of CQ[31:0].
2673  Must be aligned on CQE size (32 bytes) */
2674 /* -------------- */
2675  pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
2676  pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries).
2677  Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */
2679 /* -------------- */
2681 /* -------------- */
2682  pseudo_bit_t c_eqn[0x00008]; /* Event Queue this CQ reports completion events to.
2683  Valid values are 0 to 63
2684  If configured to value other than 0-63, completion events will not be reported on the CQ. */
2686 /* -------------- */
2687  pseudo_bit_t pd[0x00018]; /* Protection Domain to be used to access CQ.
2688  Must be the same PD of the CQ L_Key. */
2690 /* -------------- */
2691  pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */
2692 /* -------------- */
2693  pseudo_bit_t last_notified_indx[0x00020];/* Maintained by HW.
2694  Valid for QUERY_CQ and HW2SW_CQ commands only. */
2695 /* -------------- */
2696  pseudo_bit_t solicit_producer_indx[0x00020];/* Maintained by HW.
2697  Valid for QUERY_CQ and HW2SW_CQ commands only.
2698  */
2699 /* -------------- */
2700  pseudo_bit_t consumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ.
2701  Must be 0x0 in CQ initialization.
2702  Valid for the QUERY_CQ and HW2SW_CQ commands only. */
2703 /* -------------- */
2704  pseudo_bit_t producer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ.
2705  CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added..
2706  Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
2707 /* -------------- */
2708  pseudo_bit_t cqn[0x00018]; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table
2709  Valid for the QUERY_CQ and HW2SW_CQ commands only */
2711 /* -------------- */
2712  pseudo_bit_t cq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry.
2713  HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record.
2714  This value can be retrieved from the HW in the QUERY_CQ command. */
2715 /* -------------- */
2716  pseudo_bit_t cq_state_db_record[0x00020];/* Index in the UAR Context Table Entry.
2717  HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record.
2718  This value can be retrieved from the HW in the QUERY_CQ command. */
2719 /* -------------- */
2721 /* -------------- */
2722 };
2723 
2724 /* GPIO_event_data */
2725 
2726 struct arbelprm_gpio_event_data_st { /* Little Endian */
2728 /* -------------- */
2729  pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2730 /* -------------- */
2731  pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2732 /* -------------- */
2734 /* -------------- */
2735 };
2736 
2737 /* Event_data Field - QP/EE Events */
2738 
2739 struct arbelprm_qp_ee_event_st { /* Little Endian */
2740  pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for */
2742 /* -------------- */
2744 /* -------------- */
2746  pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field
2747  Not valid on SRQ events */
2749 /* -------------- */
2751 /* -------------- */
2752 };
2753 
2754 /* InfiniHost-III-EX Type0 Configuration Header */
2755 
2756 struct arbelprm_mt25208_type0_st { /* Little Endian */
2757  pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */
2758  pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode
2759  25218 (decimal) - InfiniHost-III EX mode (the mode described in this manual)
2760  25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode
2761  */
2762 /* -------------- */
2763  pseudo_bit_t command[0x00010]; /* PCI Command Register */
2764  pseudo_bit_t status[0x00010]; /* PCI Status Register */
2765 /* -------------- */
2768 /* -------------- */
2769  pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */
2771  pseudo_bit_t header_type[0x00008]; /* hardwired to zero */
2772  pseudo_bit_t bist[0x00008];
2773 /* -------------- */
2774  pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */
2776  pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */
2777 /* -------------- */
2778  pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */
2779 /* -------------- */
2780  pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */
2782  pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */
2783 /* -------------- */
2784  pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */
2785 /* -------------- */
2786  pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */
2788  pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2789 /* -------------- */
2790  pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2791 /* -------------- */
2793 /* -------------- */
2794  pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
2795  pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */
2796 /* -------------- */
2797  pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2799  pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2800 /* -------------- */
2801  pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
2803 /* -------------- */
2805 /* -------------- */
2810 /* -------------- */
2812 /* -------------- */
2820 /* -------------- */
2822 /* -------------- */
2824 /* -------------- */
2827 /* -------------- */
2829 /* -------------- */
2830  pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */
2832  pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h
2833  [3] PME clock - 0h
2834  [4] RsvP
2835  [5] Device specific initialization - 0h
2836  [8:6] AUX current - 0h
2837  [9] D1 support - 0h
2838  [10] D2 support - 0h
2839  [15:11] PME support - 0h */
2840 /* -------------- */
2841  pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */
2843  pseudo_bit_t data[0x00008];
2844 /* -------------- */
2846 /* -------------- */
2847  pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */
2850  pseudo_bit_t f[0x00001];
2851 /* -------------- */
2853 /* -------------- */
2855 /* -------------- */
2856  pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */
2858  pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h
2859  [7:4] Device/Port Type - 0h
2860  [8] Slot implemented - 0h
2861  [13:9] Interrupt message number
2862  */
2863 /* -------------- */
2864  pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h
2865  [4:3] Phantom Function supported - 0h
2866  [5] Extended Tag Filed supported - 0h
2867  [8:6] Endpoint L0s Acceptable Latency - TBD
2868  [11:9] Endpoint L1 Acceptable Latency - TBD
2869  [12] Attention Button Present - configured through InfiniBurn
2870  [13] Attention Indicator Present - configured through InfiniBurn
2871  [14] Power Indicator Present - configured through InfiniBurn
2872  [25:18] Captured Slot Power Limit Value
2873  [27:26] Captured Slot Power Limit Scale */
2874 /* -------------- */
2877 /* -------------- */
2878  pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h
2879  [9:4] Maximum Link Width - 8h
2880  [11:10] Active State Power Management Support - 3h
2881  [14:12] L0s Exit Latency - TBD
2882  [17:15] L1 Exit Latency - TBD
2883  [31:24] Port Number - 0h */
2884 /* -------------- */
2886  pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h
2887  [9:4] Negotiated Link Width
2888  [12] Slot clock configuration - 1h */
2889 /* -------------- */
2891 /* -------------- */
2895 /* -------------- */
2896  pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status
2897  4 Data Link Protocol Error Status
2898  12 Poisoned TLP Status
2899  13 Flow Control Protocol Error Status
2900  14 Completion Timeout Status
2901  15 Completer Abort Status
2902  16 Unexpected Completion Status
2903  17 Receiver Overflow Status
2904  18 Malformed TLP Status
2905  19 ECRC Error Status
2906  20 Unsupported Request Error Status */
2907 /* -------------- */
2908  pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask
2909  4 Data Link Protocol Error Mask
2910  12 Poisoned TLP Mask
2911  13 Flow Control Protocol Error Mask
2912  14 Completion Timeout Mask
2913  15 Completer Abort Mask
2914  16 Unexpected Completion Mask
2915  17 Receiver Overflow Mask
2916  18 Malformed TLP Mask
2917  19 ECRC Error Mask
2918  20 Unsupported Request Error Mask */
2919 /* -------------- */
2920  pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity
2921  4 Data Link Protocol Error Severity
2922  12 Poisoned TLP Severity
2923  13 Flow Control Protocol Error Severity
2924  14 Completion Timeout Severity
2925  15 Completer Abort Severity
2926  16 Unexpected Completion Severity
2927  17 Receiver Overflow Severity
2928  18 Malformed TLP Severity
2929  19 ECRC Error Severity
2930  20 Unsupported Request Error Severity */
2931 /* -------------- */
2932  pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status
2933  6 Bad TLP Status
2934  7 Bad DLLP Status
2935  8 REPLAY_NUM Rollover Status
2936  12 Replay Timer Timeout Status */
2937 /* -------------- */
2938  pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask
2939  6 Bad TLP Mask
2940  7 Bad DLLP Mask
2941  8 REPLAY_NUM Rollover Mask
2942  12 Replay Timer Timeout Mask */
2943 /* -------------- */
2945 /* -------------- */
2947 /* -------------- */
2949 /* -------------- */
2950 };
2951 
2952 /* Event Data Field - Performance Monitor */
2953 
2954 struct arbelprm_performance_monitor_event_st { /* Little Endian */
2955  struct arbelprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */
2956 /* -------------- */
2957  pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC
2958  0x02 - RQPC
2959  0x03 - CQC
2960  0x04 - Rkey
2961  0x05 - TLB
2962  0x06 - port0
2963  0x07 - port1 */
2965 /* -------------- */
2967 /* -------------- */
2968 };
2969 
2970 /* Event_data Field - Page Faults */
2971 
2972 struct arbelprm_page_fault_event_data_st { /* Little Endian */
2973  pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */
2974 /* -------------- */
2975  pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */
2976 /* -------------- */
2977  pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */
2978 /* -------------- */
2979  pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */
2981  pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */
2982  pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */
2983  pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */
2984  pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */
2985  pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */
2986 /* -------------- */
2987  pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */
2989 /* -------------- */
2990  pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
2991 /* -------------- */
2992 };
2993 
2994 /* WQE segments format */
2995 
2996 struct arbelprm_wqe_segment_st { /* Little Endian */
2997  struct arbelprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */
2998 /* -------------- */
3000 /* -------------- */
3001  struct arbelprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */
3002 /* -------------- */
3004 /* -------------- */
3005  struct arbelprm_wqe_segment_ctrl_recv_st recv_wqe_segment_ctrl;/* Receive segment format */
3006 /* -------------- */
3008 /* -------------- */
3009 };
3010 
3011 /* Event_data Field - Port State Change */
3012 
3013 struct arbelprm_port_state_change_st { /* Little Endian */
3015 /* -------------- */
3017  pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */
3019 /* -------------- */
3021 /* -------------- */
3022 };
3023 
3024 /* Event_data Field - Completion Queue Error */
3025 
3026 struct arbelprm_completion_queue_error_st { /* Little Endian */
3027  pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
3029 /* -------------- */
3031 /* -------------- */
3032  pseudo_bit_t syndrome[0x00008]; /* Error syndrome
3033  0x01 - CQ overrun
3034  0x02 - CQ access violation error */
3036 /* -------------- */
3038 /* -------------- */
3039 };
3040 
3041 /* Event_data Field - Completion Event */
3042 
3043 struct arbelprm_completion_event_st { /* Little Endian */
3044  pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
3046 /* -------------- */
3048 /* -------------- */
3049 };
3050 
3051 /* Event Queue Entry */
3052 
3053 struct arbelprm_event_queue_entry_st { /* Little Endian */
3054  pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type.
3055  Defined for events which have sub types, zero elsewhere. */
3057  pseudo_bit_t event_type[0x00008]; /* Event Type */
3059 /* -------------- */
3060  pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */
3061 /* -------------- */
3063  pseudo_bit_t owner[0x00001]; /* Owner of the entry
3064  0 SW
3065  1 HW */
3067 /* -------------- */
3068 };
3069 
3070 /* QP/EE State Transitions Command Parameters */
3071 
3072 struct arbelprm_qp_ee_state_transitions_st { /* Little Endian */
3073  pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
3074 /* -------------- */
3076 /* -------------- */
3078 /* -------------- */
3080 /* -------------- */
3081 };
3082 
3083 /* Completion Queue Entry Format */
3084 
3085 struct arbelprm_completion_queue_entry_st { /* Little Endian */
3086  pseudo_bit_t my_qpn[0x00018]; /* Indicates the QP for which completion is being reported */
3088  pseudo_bit_t ver[0x00004]; /* CQE version.
3089  0 for InfiniHost-III-EX */
3090 /* -------------- */
3091  pseudo_bit_t my_ee[0x00018]; /* EE context (for RD only).
3092  Invalid for Bind and Nop operation on RD.
3093  For non RD services this filed reports the CQE timestamp. The Timestamp is a free running counter that is incremented every TimeStampGranularity tick. The counter rolls-over when it reaches saturation. TimeStampGranularity is configured in the INIT_HCA command. This feature is currently not supported.
3094  */
3095  pseudo_bit_t checksum_15_8[0x00008];/* Checksum[15:8] - See IPoverIB checksum offloading chapter */
3096 /* -------------- */
3097  pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */
3098  pseudo_bit_t checksum_7_0[0x00008]; /* Checksum[7:0] - See IPoverIB checksum offloading chapter */
3099 /* -------------- */
3100  pseudo_bit_t rlid[0x00010]; /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */
3101  pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW.
3102  Valid in responder of UD QP CQE only.
3103  Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */
3104  pseudo_bit_t g[0x00001]; /* GRH present indicator. Valid in Responder of UD QP CQE only. */
3105  pseudo_bit_t ipok[0x00001]; /* IP OK - See IPoverIB checksum offloading chapter */
3107  pseudo_bit_t sl[0x00004]; /* Service Level of the message. Valid in Responder of UD QP CQE only. */
3108 /* -------------- */
3109  pseudo_bit_t immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only.
3110  If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet.
3111  If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet.
3112  If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived.
3113  If Opcode field indicates that this was send and invalidate, this field contains the key that was invalidated.
3114  For CQE of send queue of the reliable connection service (but send and invalide), bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message. */
3115 /* -------------- */
3116  pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data actually transferred (valid for receive queue completions only) */
3117 /* -------------- */
3119  pseudo_bit_t wqe_adr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */
3120 /* -------------- */
3122  pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */
3124  pseudo_bit_t s[0x00001]; /* If set, completion is reported for Send queue, if cleared - receive queue. */
3125  pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for.
3126  For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field.
3127  For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field.
3128  For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only)
3129 
3130  The following values are reported in case of completion with error:
3131  0xFE - For completion with error on Receive Queues
3132  0xFF - For completion with error on Send Queues */
3133 /* -------------- */
3134 };
3135 
3136 /* */
3137 
3138 struct arbelprm_ecc_detect_event_data_st { /* Little Endian */
3140 /* -------------- */
3151 /* -------------- */
3154 /* -------------- */
3155 };
3156 
3157 /* Event_data Field - ECC Detection Event */
3158 
3159 struct arbelprm_scrubbing_event_st { /* Little Endian */
3161 /* -------------- */
3162  pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause:
3163  single ECC error in the 64bit lsb data, on the rise edge of the clock */
3165  pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause:
3166  single ECC error in the 64bit msb data, on the fall edge of the clock */
3168  pseudo_bit_t err_rmw[0x00001]; /* transaction type:
3169  0 - read
3170  1 - read/modify/write */
3171  pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */
3172  pseudo_bit_t err_da[0x00002]; /* Error DIMM address */
3173  pseudo_bit_t err_ba[0x00002]; /* Error bank address */
3175  pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */
3176 /* -------------- */
3177  pseudo_bit_t err_ra[0x00010]; /* Error row address */
3178  pseudo_bit_t err_ca[0x00010]; /* Error column address */
3179 /* -------------- */
3180 };
3181 
3182 /* Miscellaneous Counters */
3183 
3184 struct arbelprm_misc_counters_st { /* Little Endian */
3185  pseudo_bit_t ddr_scan_cnt[0x00020]; /* Number of times whole of LAM was scanned */
3186 /* -------------- */
3188 /* -------------- */
3189 };
3190 
3191 /* LAM_EN Output Parameter */
3192 
3193 struct arbelprm_lam_en_out_param_st { /* Little Endian */
3195 /* -------------- */
3196 };
3197 
3198 /* Extended_Completion_Queue_Entry */
3199 
3202 /* -------------- */
3203 };
3204 
3205 /* */
3206 
3207 struct arbelprm_eq_cmd_doorbell_st { /* Little Endian */
3209 /* -------------- */
3210 };
3211 
3212 /* 0 */
3213 
3214 struct arbelprm_arbel_prm_st { /* Little Endian */
3215  struct arbelprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */
3216 /* -------------- */
3218 /* -------------- */
3219  struct arbelprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */
3220 /* -------------- */
3222 /* -------------- */
3223  struct arbelprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */
3224 /* -------------- */
3226 /* -------------- */
3227  struct arbelprm_completion_event_st completion_event;/* Event_data Field - Completion Event */
3228 /* -------------- */
3230 /* -------------- */
3231  struct arbelprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */
3232 /* -------------- */
3234 /* -------------- */
3235  struct arbelprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */
3236 /* -------------- */
3238 /* -------------- */
3239  struct arbelprm_wqe_segment_st wqe_segment;/* WQE segments format */
3240 /* -------------- */
3242 /* -------------- */
3243  struct arbelprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */
3244 /* -------------- */
3246 /* -------------- */
3247  struct arbelprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */
3248 /* -------------- */
3250 /* -------------- */
3251  struct arbelprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */
3252 /* -------------- */
3254 /* -------------- */
3255  struct arbelprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */
3256 /* -------------- */
3258 /* -------------- */
3260 /* -------------- */
3262 /* -------------- */
3263  struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
3264 /* -------------- */
3266 /* -------------- */
3268 /* -------------- */
3270 /* -------------- */
3271  struct arbelprm_address_path_st address_path;/* Address Path */
3272 /* -------------- */
3274 /* -------------- */
3275  struct arbelprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */
3276 /* -------------- */
3278 /* -------------- */
3279  struct arbelprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */
3280 /* -------------- */
3282 /* -------------- */
3283  struct arbelprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */
3284 /* -------------- */
3286 /* -------------- */
3287  struct arbelprm_eqc_st eqc; /* Event Queue Context Table Entry */
3288 /* -------------- */
3290 /* -------------- */
3291  struct arbelprm_performance_monitors_st performance_monitors;/* Performance Monitors */
3292 /* -------------- */
3294 /* -------------- */
3295  struct arbelprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */
3296 /* -------------- */
3298 /* -------------- */
3299  struct arbelprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */
3300 /* -------------- */
3302 /* -------------- */
3303  struct arbelprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */
3304 /* -------------- */
3306 /* -------------- */
3307  struct arbelprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */
3308 /* -------------- */
3310 /* -------------- */
3311  struct arbelprm_multicastparam_st multicastparam;/* Multicast Support Parameters */
3312 /* -------------- */
3314 /* -------------- */
3315  struct arbelprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */
3316 /* -------------- */
3318 /* -------------- */
3319  struct arbelprm_enable_lam_st enable_lam;/* ENABLE_LAM Parameters Block */
3320 /* -------------- */
3322 /* -------------- */
3324 /* -------------- */
3325  struct arbelprm_dimminfo_st dimminfo;/* Logical DIMM Information */
3326 /* -------------- */
3328 /* -------------- */
3329  struct arbelprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */
3330 /* -------------- */
3332 /* -------------- */
3333  struct arbelprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */
3334 /* -------------- */
3336 /* -------------- */
3337  struct arbelprm_query_dev_lim_st query_dev_lim;/* Query Device Limitations */
3338 /* -------------- */
3340 /* -------------- */
3341  struct arbelprm_uar_params_st uar_params;/* UAR Parameters */
3342 /* -------------- */
3344 /* -------------- */
3345  struct arbelprm_init_ib_st init_ib; /* INIT_IB Parameters */
3346 /* -------------- */
3348 /* -------------- */
3349  struct arbelprm_mgm_entry_st mgm_entry;/* Multicast Group Member */
3350 /* -------------- */
3352 /* -------------- */
3353  struct arbelprm_set_ib_st set_ib; /* SET_IB Parameters */
3354 /* -------------- */
3356 /* -------------- */
3357  struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */
3358 /* -------------- */
3360 /* -------------- */
3361  struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */
3362 /* -------------- */
3364 /* -------------- */
3365  struct arbelprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */
3366 /* -------------- */
3368 /* -------------- */
3370 /* -------------- */
3372 /* -------------- */
3373  struct arbelprm_uar_st uar; /* User Access Region */
3374 /* -------------- */
3376 /* -------------- */
3377  struct arbelprm_mgmqp_st mgmqp; /* Multicast Group Member QP */
3378 /* -------------- */
3380 /* -------------- */
3381  struct arbelprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */
3382 /* -------------- */
3384 /* -------------- */
3385  struct arbelprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */
3386 /* -------------- */
3388 /* -------------- */
3390 /* -------------- */
3392 /* -------------- */
3393  struct arbelprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */
3394 /* -------------- */
3396 /* -------------- */
3397  struct arbelprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */
3398 /* -------------- */
3400 /* -------------- */
3401  struct arbelprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */
3402 /* -------------- */
3404 /* -------------- */
3406 /* -------------- */
3408 /* -------------- */
3409  struct arbelprm_performance_counters_st performance_counters;/* Performance Counters */
3410 /* -------------- */
3412 /* -------------- */
3414 /* -------------- */
3416 /* -------------- */
3417  struct arbelprm_pbl_st pbl; /* Physical Buffer List */
3418 /* -------------- */
3420 /* -------------- */
3421  struct arbelprm_srq_context_st srq_context;/* SRQ Context */
3422 /* -------------- */
3424 /* -------------- */
3425  struct arbelprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */
3426 /* -------------- */
3428 /* -------------- */
3429  struct arbelprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */
3430 /* -------------- */
3432 /* -------------- */
3433  struct arbelprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */
3434 /* -------------- */
3436 /* -------------- */
3437  struct arbelprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */
3438 /* -------------- */
3440 /* -------------- */
3441  struct arbelprm_qp_db_record_st qp_db_record;/* QP_DB_Record */
3442 /* -------------- */
3444 /* -------------- */
3445  struct arbelprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */
3446 /* -------------- */
3447  struct arbelprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */
3448 /* -------------- */
3450 /* -------------- */
3451  struct arbelprm_eq_arm_db_region_st eq_arm_db_region;/* EQ Arm Doorbell Region */
3452 /* -------------- */
3454 /* -------------- */
3455  struct arbelprm_clr_int_st clr_int; /* Clear Interrupt Register */
3456 /* -------------- */
3458 /* -------------- */
3459 };
3460 #endif /* H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H */
pseudo_bit_t reserved1[0x00020]
Definition: MT25218_PRM.h:2743
pseudo_bit_t reserved3[0x00020]
Definition: MT25218_PRM.h:646
pseudo_bit_t reserved34[0x00020]
Definition: MT25218_PRM.h:1289
pseudo_bit_t vsd_dw2[0x00020]
Definition: MT25218_PRM.h:470
pseudo_bit_t reserved5[0x00007]
Definition: MT25218_PRM.h:2093
struct arbelprm_vsd_st vsd
Definition: MT25218_PRM.h:2300
pseudo_bit_t rc[0x00001]
Definition: MT25218_PRM.h:2173
pseudo_bit_t reserved42[0x00020]
Definition: MT25218_PRM.h:1321
pseudo_bit_t reserved15[0x00020]
Definition: MT25218_PRM.h:2127
pseudo_bit_t eq40_set_ci[0x00020]
Definition: MT25218_PRM.h:1311
pseudo_bit_t always1[0x00001]
Definition: MT25218_PRM.h:338
pseudo_bit_t link_status[0x00010]
Definition: MT25218_PRM.h:2886
pseudo_bit_t lkey[0x00020]
Definition: MT25218_PRM.h:2623
pseudo_bit_t reserved4[0x00003]
Definition: MT25218_PRM.h:2531
pseudo_bit_t reserved3[0x00060]
Definition: MT25218_PRM.h:1811
pseudo_bit_t eq33_set_ci[0x00020]
Definition: MT25218_PRM.h:1283
pseudo_bit_t rdd[0x00018]
Definition: MT25218_PRM.h:1005
pseudo_bit_t mgid_index[0x00006]
Definition: MT25218_PRM.h:57
pseudo_bit_t reserved4[0x00180]
Definition: MT25218_PRM.h:1858
struct arbelprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters
Definition: MT25218_PRM.h:2482
pseudo_bit_t reserved13[0x006a0]
Definition: MT25218_PRM.h:2948
pseudo_bit_t reserved5[0x00020]
Definition: MT25218_PRM.h:2630
struct arbelprm_dimminfo_st dimminfo
Definition: MT25218_PRM.h:3325
pseudo_bit_t srqn[0x00018]
Definition: MT25218_PRM.h:1493
pseudo_bit_t r0[0x00001]
Definition: MT25218_PRM.h:842
pseudo_bit_t reserved13[0x00008]
Definition: MT25218_PRM.h:1009
Definition: MT25218_PRM.h:933
struct arbelprm_wqe_segment_atomic_st wqe_segment_atomic
Definition: MT25218_PRM.h:917
pseudo_bit_t log_max_srq_sz[0x00008]
Definition: MT25218_PRM.h:2084
pseudo_bit_t eq16_set_ci[0x00020]
Definition: MT25218_PRM.h:1215
pseudo_bit_t reserved51[0x00020]
Definition: MT25218_PRM.h:1357
pseudo_bit_t cmd_interface_db[0x00001]
Definition: MT25218_PRM.h:2324
pseudo_bit_t reserved56[0x00020]
Definition: MT25218_PRM.h:1377
pseudo_bit_t reserved12[0x00020]
Definition: MT25218_PRM.h:1201
pseudo_bit_t mtt_base_addr_l[0x00020]
Definition: MT25218_PRM.h:692
Definition: MT25218_PRM.h:3053
pseudo_bit_t eq7_set_ci[0x00020]
Definition: MT25218_PRM.h:1179
struct arbelprm_receive_doorbell_st receive_doorbell
Definition: MT25218_PRM.h:3365
pseudo_bit_t system_image_guid_l[0x00020]
Definition: MT25218_PRM.h:2066
pseudo_bit_t lamr[0x00001]
Definition: MT25218_PRM.h:2278
pseudo_bit_t max_pkey[0x00010]
Definition: MT25218_PRM.h:2047
pseudo_bit_t res[0x00003]
Definition: MT25218_PRM.h:1445
pseudo_bit_t eq57_set_ci[0x00020]
Definition: MT25218_PRM.h:1379
pseudo_bit_t byte_cnt[0x00020]
Definition: MT25218_PRM.h:3116
pseudo_bit_t cmd_db_addr_base_l[0x00020]
Definition: MT25218_PRM.h:2374
pseudo_bit_t reserved33[0x7fe00]
Definition: MT25218_PRM.h:3351
pseudo_bit_t reserved2[0x00002]
Definition: MT25218_PRM.h:3167
pseudo_bit_t srq[0x00001]
Definition: MT25218_PRM.h:1482
pseudo_bit_t solicit_producer_indx[0x00020]
Definition: MT25218_PRM.h:2696
pseudo_bit_t reserved10[0x00080]
Definition: MT25218_PRM.h:2492
pseudo_bit_t reserved4[0x00003]
Definition: MT25218_PRM.h:855
pseudo_bit_t reserved8[0x00040]
Definition: MT25218_PRM.h:2642
pseudo_bit_t buff3_addr[0x00020]
Definition: MT25218_PRM.h:1905
pseudo_bit_t dimm_start_adr_h[0x00020]
Definition: MT25218_PRM.h:623
pseudo_bit_t reserved0[0x00008]
Definition: MT25218_PRM.h:934
pseudo_bit_t reserved1[0x00008]
Definition: MT25218_PRM.h:166
pseudo_bit_t max_icm_size_l[0x00020]
Definition: MT25218_PRM.h:2284
pseudo_bit_t vsd_dw34[0x00020]
Definition: MT25218_PRM.h:534
pseudo_bit_t event_counter2[0x00020]
Definition: MT25218_PRM.h:863
struct arbelprm_query_dev_lim_st query_dev_lim
Definition: MT25218_PRM.h:3337
struct arbelprm_uar_params_st uar_params
Definition: MT25218_PRM.h:3341
pseudo_bit_t reserved20[0x00006]
Definition: MT25218_PRM.h:1047
pseudo_bit_t eq34_set_ci[0x00020]
Definition: MT25218_PRM.h:1287
pseudo_bit_t reserved29[0x00008]
Definition: MT25218_PRM.h:1090
pseudo_bit_t reserved40[0x00020]
Definition: MT25218_PRM.h:1313
pseudo_bit_t di[0x00002]
Definition: MT25218_PRM.h:2400
pseudo_bit_t reserved0[0x00008]
Definition: MT25218_PRM.h:2741
pseudo_bit_t reserved49[0x00020]
Definition: MT25218_PRM.h:1349
pseudo_bit_t reserved31[0x00008]
Definition: MT25218_PRM.h:2213
pseudo_bit_t rq_wqe_counter[0x00010]
Definition: MT25218_PRM.h:1115
pseudo_bit_t advanced_error_reporting_cap_id[0x00010]
Definition: MT25218_PRM.h:2892
pseudo_bit_t err_rmw[0x00001]
Definition: MT25218_PRM.h:3168
pseudo_bit_t eq10_set_ci[0x00020]
Definition: MT25218_PRM.h:1191
struct arbelprm_uar_params_st uar_parameters
Definition: MT25218_PRM.h:2494
pseudo_bit_t fw_area_base[0x00020]
Definition: MT25218_PRM.h:1877
pseudo_bit_t reserved6[0x00040]
Definition: MT25218_PRM.h:786
pseudo_bit_t local_ca_ack_delay[0x00005]
Definition: MT25218_PRM.h:2156
pseudo_bit_t log_num_of_srq[0x00005]
Definition: MT25218_PRM.h:763
struct arbelprm_query_fw_st query_fw
Definition: MT25218_PRM.h:3329
pseudo_bit_t reserved14[0x00003]
Definition: MT25218_PRM.h:1016
pseudo_bit_t va_h[0x00020]
Definition: MT25218_PRM.h:2973
pseudo_bit_t vsd_dw6[0x00020]
Definition: MT25218_PRM.h:478
pseudo_bit_t reserved0[0x00003]
Definition: MT25218_PRM.h:2980
pseudo_bit_t reserved4[0x00004]
Definition: MT25218_PRM.h:2090
pseudo_bit_t num_ports[0x00004]
Definition: MT25218_PRM.h:2142
pseudo_bit_t udm[0x00001]
Definition: MT25218_PRM.h:2190
pseudo_bit_t reserved58[0x00fc0]
Definition: MT25218_PRM.h:3453
pseudo_bit_t srq[0x00001]
Definition: MT25218_PRM.h:2179
pseudo_bit_t rlky[0x00001]
Definition: MT25218_PRM.h:968
pseudo_bit_t reserved0[0x403400]
Definition: MT25218_PRM.h:1412
pseudo_bit_t cmd_db_dw7[0x00010]
Definition: MT25218_PRM.h:2369
pseudo_bit_t tclass[0x00008]
Definition: MT25218_PRM.h:65
pseudo_bit_t reserved3[0x00003]
Definition: MT25218_PRM.h:2748
pseudo_bit_t qi[0x00001]
Definition: MT25218_PRM.h:459
struct arbelprm_completion_queue_error_st completion_queue_error
Definition: MT25218_PRM.h:3231
pseudo_bit_t state[0x00004]
Definition: MT25218_PRM.h:1496
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