iPXE
amd8111e.h
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00001 /*
00002  * Advanced  Micro Devices Inc. AMD8111E Linux Network Driver 
00003  * Copyright (C) 2003 Advanced Micro Devices 
00004  *
00005  * This program is free software; you can redistribute it and/or modify
00006  * it under the terms of the GNU General Public License as published by
00007  * the Free Software Foundation; either version 2 of the License, or
00008  * (at your option) any later version.
00009  *
00010  * This program is distributed in the hope that it will be useful,
00011  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00012  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013  * GNU General Public License for more details.
00014  *
00015  * You should have received a copy of the GNU General Public License
00016  * along with this program; if not, write to the Free Software
00017  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00018  * 02110-1301, USA.
00019  *
00020  * You can also choose to distribute this program under the terms of
00021  * the Unmodified Binary Distribution Licence (as given in the file
00022  * COPYING.UBDL), provided that you have satisfied its requirements.
00023  * USA
00024 
00025 Module Name:
00026 
00027     amd8111e.h
00028 
00029 Abstract:
00030         
00031          AMD8111 based 10/100 Ethernet Controller driver definitions. 
00032 
00033 Environment:
00034     
00035         Kernel Mode
00036 
00037 Revision History:
00038         3.0.0
00039            Initial Revision.
00040         3.0.1
00041 */
00042 
00043 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00044 
00045 #ifndef _AMD811E_H
00046 #define _AMD811E_H
00047 
00048 /* Command style register access
00049 
00050 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the  value bit that specifies the value that will be written into the selected bits of register. 
00051 
00052 eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
00053 
00054 */
00055 
00056 /*  Offset for Memory Mapped Registers. */
00057 /* 32 bit registers */
00058 
00059 #define  ASF_STAT               0x00    /* ASF status register */
00060 #define CHIPID                  0x04    /* Chip ID regsiter */
00061 #define MIB_DATA                0x10    /* MIB data register */
00062 #define MIB_ADDR                0x14    /* MIB address register */
00063 #define STAT0                   0x30    /* Status0 register */
00064 #define INT0                    0x38    /* Interrupt0 register */
00065 #define INTEN0                  0x40    /* Interrupt0  enable register*/
00066 #define CMD0                    0x48    /* Command0 register */
00067 #define CMD2                    0x50    /* Command2 register */
00068 #define CMD3                    0x54    /* Command3 resiter */
00069 #define CMD7                    0x64    /* Command7 register */
00070 
00071 #define CTRL1                   0x6C    /* Control1 register */
00072 #define CTRL2                   0x70    /* Control2 register */
00073 
00074 #define XMT_RING_LIMIT          0x7C    /* Transmit ring limit register */
00075 
00076 #define AUTOPOLL0               0x88    /* Auto-poll0 register */
00077 #define AUTOPOLL1               0x8A    /* Auto-poll1 register */
00078 #define AUTOPOLL2               0x8C    /* Auto-poll2 register */
00079 #define AUTOPOLL3               0x8E    /* Auto-poll3 register */
00080 #define AUTOPOLL4               0x90    /* Auto-poll4 register */
00081 #define AUTOPOLL5               0x92    /* Auto-poll5 register */
00082 
00083 #define AP_VALUE                0x98    /* Auto-poll value register */
00084 #define DLY_INT_A               0xA8    /* Group A delayed interrupt register */
00085 #define DLY_INT_B               0xAC    /* Group B delayed interrupt register */
00086 
00087 #define FLOW_CONTROL            0xC8    /* Flow control register */
00088 #define PHY_ACCESS              0xD0    /* PHY access register */
00089 
00090 #define STVAL                   0xD8    /* Software timer value register */
00091 
00092 #define XMT_RING_BASE_ADDR0     0x100   /* Transmit ring0 base addr register */
00093 #define XMT_RING_BASE_ADDR1     0x108   /* Transmit ring1 base addr register */
00094 #define XMT_RING_BASE_ADDR2     0x110   /* Transmit ring2 base addr register */
00095 #define XMT_RING_BASE_ADDR3     0x118   /* Transmit ring2 base addr register */
00096 
00097 #define RCV_RING_BASE_ADDR0     0x120   /* Transmit ring0 base addr register */
00098 
00099 #define PMAT0                   0x190   /* OnNow pattern register0 */
00100 #define PMAT1                   0x194   /* OnNow pattern register1 */
00101 
00102 /* 16bit registers */
00103 
00104 #define XMT_RING_LEN0           0x140   /* Transmit Ring0 length register */
00105 #define XMT_RING_LEN1           0x144   /* Transmit Ring1 length register */
00106 #define XMT_RING_LEN2           0x148   /* Transmit Ring2 length register */
00107 #define XMT_RING_LEN3           0x14C   /* Transmit Ring3 length register */
00108 
00109 #define RCV_RING_LEN0           0x150   /* Receive Ring0 length register */
00110 
00111 #define SRAM_SIZE               0x178   /* SRAM size register */
00112 #define SRAM_BOUNDARY           0x17A   /* SRAM boundary register */
00113 
00114 /* 48bit register */
00115 
00116 #define PADR                    0x160   /* Physical address register */
00117 
00118 #define IFS1                    0x18C   /* Inter-frame spacing Part1 register */
00119 #define IFS                     0x18D   /* Inter-frame spacing register */
00120 #define IPG                     0x18E   /* Inter-frame gap register */
00121 /* 64bit register */
00122 
00123 #define LADRF                   0x168   /* Logical address filter register */
00124 
00125 
00126 /* Register Bit Definitions */
00127 typedef enum {
00128 
00129         ASF_INIT_DONE           = (1 << 1),
00130         ASF_INIT_PRESENT        = (1 << 0),
00131 
00132 }STAT_ASF_BITS; 
00133    
00134 typedef enum {
00135 
00136         MIB_CMD_ACTIVE          = (1 << 15 ),
00137         MIB_RD_CMD              = (1 << 13 ),
00138         MIB_CLEAR               = (1 << 12 ),
00139         MIB_ADDRESS             = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
00140                                         (1 << 4) | (1 << 5),
00141 }MIB_ADDR_BITS;
00142 
00143 
00144 typedef enum {
00145         
00146         PMAT_DET                = (1 << 12),
00147         MP_DET                  = (1 << 11),
00148         LC_DET                  = (1 << 10),
00149         SPEED_MASK              = (1 << 9)|(1 << 8)|(1 << 7),
00150         FULL_DPLX               = (1 << 6),
00151         LINK_STATS              = (1 << 5),
00152         AUTONEG_COMPLETE        = (1 << 4),
00153         MIIPD                   = (1 << 3),
00154         RX_SUSPENDED            = (1 << 2),
00155         TX_SUSPENDED            = (1 << 1),
00156         RUNNING                 = (1 << 0),
00157 
00158 }STAT0_BITS;
00159 
00160 #define PHY_SPEED_10            0x2
00161 #define PHY_SPEED_100           0x3
00162 
00163 /* INT0                         0x38, 32bit register */
00164 typedef enum {
00165 
00166         INTR                    = (1 << 31),
00167         PCSINT                  = (1 << 28), 
00168         LCINT                   = (1 << 27),
00169         APINT5                  = (1 << 26),
00170         APINT4                  = (1 << 25),
00171         APINT3                  = (1 << 24),
00172         TINT_SUM                = (1 << 23),
00173         APINT2                  = (1 << 22),
00174         APINT1                  = (1 << 21),
00175         APINT0                  = (1 << 20),
00176         MIIPDTINT               = (1 << 19),
00177         MCCINT                  = (1 << 17),
00178         MREINT                  = (1 << 16),
00179         RINT_SUM                = (1 << 15),
00180         SPNDINT                 = (1 << 14),
00181         MPINT                   = (1 << 13),
00182         SINT                    = (1 << 12),
00183         TINT3                   = (1 << 11),
00184         TINT2                   = (1 << 10),
00185         TINT1                   = (1 << 9),
00186         TINT0                   = (1 << 8),
00187         UINT                    = (1 << 7),
00188         STINT                   = (1 << 4),
00189         RINT0                   = (1 << 0),
00190 
00191 }INT0_BITS;
00192 
00193 typedef enum {
00194 
00195         VAL3                    = (1 << 31),   /* VAL bit for byte 3 */
00196         VAL2                    = (1 << 23),   /* VAL bit for byte 2 */
00197         VAL1                    = (1 << 15),   /* VAL bit for byte 1 */
00198         VAL0                    = (1 << 7),    /* VAL bit for byte 0 */
00199 
00200 }VAL_BITS;
00201 
00202 typedef enum {
00203 
00204         /* VAL3 */
00205         LCINTEN                 = (1 << 27),
00206         APINT5EN                = (1 << 26),
00207         APINT4EN                = (1 << 25),
00208         APINT3EN                = (1 << 24),
00209         /* VAL2 */
00210         APINT2EN                = (1 << 22),
00211         APINT1EN                = (1 << 21),
00212         APINT0EN                = (1 << 20),
00213         MIIPDTINTEN             = (1 << 19),
00214         MCCIINTEN               = (1 << 18),
00215         MCCINTEN                = (1 << 17),
00216         MREINTEN                = (1 << 16),
00217         /* VAL1 */
00218         SPNDINTEN               = (1 << 14),
00219         MPINTEN                 = (1 << 13),
00220         TINTEN3                 = (1 << 11),
00221         SINTEN                  = (1 << 12),
00222         TINTEN2                 = (1 << 10),
00223         TINTEN1                 = (1 << 9),
00224         TINTEN0                 = (1 << 8),
00225         /* VAL0 */
00226         STINTEN                 = (1 << 4),
00227         RINTEN0                 = (1 << 0),
00228 
00229         INTEN0_CLEAR            = 0x1F7F7F1F, /* Command style register */
00230 
00231 }INTEN0_BITS;           
00232 
00233 typedef enum {
00234         /* VAL2 */
00235         RDMD0                   = (1 << 16),
00236         /* VAL1 */
00237         TDMD3                   = (1 << 11),
00238         TDMD2                   = (1 << 10),
00239         TDMD1                   = (1 << 9),
00240         TDMD0                   = (1 << 8),
00241         /* VAL0 */
00242         UINTCMD                 = (1 << 6),
00243         RX_FAST_SPND            = (1 << 5),
00244         TX_FAST_SPND            = (1 << 4),
00245         RX_SPND                 = (1 << 3),
00246         TX_SPND                 = (1 << 2),
00247         INTREN                  = (1 << 1),
00248         RUN                     = (1 << 0),
00249 
00250         CMD0_CLEAR              = 0x000F0F7F,   /* Command style register */    
00251 
00252 }CMD0_BITS;
00253 
00254 typedef enum {
00255 
00256         /* VAL3 */
00257         CONDUIT_MODE            = (1 << 29),
00258         /* VAL2 */
00259         RPA                     = (1 << 19),
00260         DRCVPA                  = (1 << 18),
00261         DRCVBC                  = (1 << 17),
00262         PROM                    = (1 << 16),
00263         /* VAL1 */
00264         ASTRP_RCV               = (1 << 13),
00265         RCV_DROP0               = (1 << 12),
00266         EMBA                    = (1 << 11),
00267         DXMT2PD                 = (1 << 10),
00268         LTINTEN                 = (1 << 9),
00269         DXMTFCS                 = (1 << 8),
00270         /* VAL0 */
00271         APAD_XMT                = (1 << 6),
00272         DRTY                    = (1 << 5),
00273         INLOOP                  = (1 << 4),
00274         EXLOOP                  = (1 << 3),
00275         REX_RTRY                = (1 << 2),
00276         REX_UFLO                = (1 << 1),
00277         REX_LCOL                = (1 << 0),
00278 
00279         CMD2_CLEAR              = 0x3F7F3F7F,   /* Command style register */
00280 
00281 }CMD2_BITS;
00282 
00283 typedef enum {
00284 
00285         /* VAL3 */
00286         ASF_INIT_DONE_ALIAS     = (1 << 29),
00287         /* VAL2 */
00288         JUMBO                   = (1 << 21),
00289         VSIZE                   = (1 << 20),    
00290         VLONLY                  = (1 << 19),
00291         VL_TAG_DEL              = (1 << 18),    
00292         /* VAL1 */
00293         EN_PMGR                 = (1 << 14),                    
00294         INTLEVEL                = (1 << 13),
00295         FORCE_FULL_DUPLEX       = (1 << 12),    
00296         FORCE_LINK_STATUS       = (1 << 11),    
00297         APEP                    = (1 << 10),    
00298         MPPLBA                  = (1 << 9),     
00299         /* VAL0 */
00300         RESET_PHY_PULSE         = (1 << 2),     
00301         RESET_PHY               = (1 << 1),     
00302         PHY_RST_POL             = (1 << 0),     
00303 
00304 }CMD3_BITS;
00305 
00306 
00307 typedef enum {
00308 
00309         /* VAL0 */
00310         PMAT_SAVE_MATCH         = (1 << 4),
00311         PMAT_MODE               = (1 << 3),
00312         MPEN_SW                 = (1 << 1),
00313         LCMODE_SW               = (1 << 0),
00314 
00315         CMD7_CLEAR              = 0x0000001B    /* Command style register */
00316 
00317 }CMD7_BITS;
00318 
00319 
00320 typedef enum {
00321 
00322         RESET_PHY_WIDTH         = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
00323         XMTSP_MASK              = (1 << 9) | (1 << 8),  /* 9:8 */
00324         XMTSP_128               = (1 << 9),     /* 9 */ 
00325         XMTSP_64                = (1 << 8),
00326         CACHE_ALIGN             = (1 << 4),
00327         BURST_LIMIT_MASK        = (0xF << 0 ),
00328         CTRL1_DEFAULT           = 0x00010111,
00329 
00330 }CTRL1_BITS;
00331 
00332 typedef enum {
00333 
00334         FMDC_MASK               = (1 << 9)|(1 << 8),    /* 9:8 */
00335         XPHYRST                 = (1 << 7),
00336         XPHYANE                 = (1 << 6),
00337         XPHYFD                  = (1 << 5),
00338         XPHYSP                  = (1 << 4) | (1 << 3),  /* 4:3 */
00339         APDW_MASK               = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
00340 
00341 }CTRL2_BITS;
00342 
00343 /* XMT_RING_LIMIT               0x7C, 32bit register */
00344 typedef enum {
00345 
00346         XMT_RING2_LIMIT         = (0xFF << 16), /* 23:16 */
00347         XMT_RING1_LIMIT         = (0xFF << 8),  /* 15:8 */
00348         XMT_RING0_LIMIT         = (0xFF << 0),  /* 7:0 */
00349 
00350 }XMT_RING_LIMIT_BITS;
00351 
00352 typedef enum {
00353 
00354         AP_REG0_EN              = (1 << 15),
00355         AP_REG0_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00356         AP_PHY0_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00357 
00358 }AUTOPOLL0_BITS;
00359 
00360 /* AUTOPOLL1                    0x8A, 16bit register */
00361 typedef enum {
00362 
00363         AP_REG1_EN              = (1 << 15),
00364         AP_REG1_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00365         AP_PRE_SUP1             = (1 << 6),
00366         AP_PHY1_DFLT            = (1 << 5),
00367         AP_PHY1_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00368 
00369 }AUTOPOLL1_BITS;
00370 
00371 
00372 typedef enum {
00373 
00374         AP_REG2_EN              = (1 << 15),
00375         AP_REG2_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00376         AP_PRE_SUP2             = (1 << 6),
00377         AP_PHY2_DFLT            = (1 << 5),
00378         AP_PHY2_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00379 
00380 }AUTOPOLL2_BITS;
00381 
00382 typedef enum {
00383 
00384         AP_REG3_EN              = (1 << 15),
00385         AP_REG3_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00386         AP_PRE_SUP3             = (1 << 6),
00387         AP_PHY3_DFLT            = (1 << 5),
00388         AP_PHY3_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00389 
00390 }AUTOPOLL3_BITS;
00391 
00392 
00393 typedef enum {
00394 
00395         AP_REG4_EN              = (1 << 15),
00396         AP_REG4_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00397         AP_PRE_SUP4             = (1 << 6),
00398         AP_PHY4_DFLT            = (1 << 5),
00399         AP_PHY4_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00400 
00401 }AUTOPOLL4_BITS;
00402 
00403 
00404 typedef enum {
00405 
00406         AP_REG5_EN              = (1 << 15),
00407         AP_REG5_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00408         AP_PRE_SUP5             = (1 << 6),
00409         AP_PHY5_DFLT            = (1 << 5),
00410         AP_PHY5_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00411 
00412 }AUTOPOLL5_BITS;
00413 
00414 
00415 
00416 
00417 /* AP_VALUE                     0x98, 32bit ragister */
00418 typedef enum {
00419 
00420         AP_VAL_ACTIVE           = (1 << 31),
00421         AP_VAL_RD_CMD           = ( 1 << 29),
00422         AP_ADDR                 = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
00423         AP_VAL                  = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
00424                                   (0xF << 12),  /* 15:0 */
00425 
00426 }AP_VALUE_BITS;
00427 
00428 typedef enum {
00429 
00430         DLY_INT_A_R3            = (1 << 31),
00431         DLY_INT_A_R2            = (1 << 30),
00432         DLY_INT_A_R1            = (1 << 29),
00433         DLY_INT_A_R0            = (1 << 28),
00434         DLY_INT_A_T3            = (1 << 27),
00435         DLY_INT_A_T2            = (1 << 26),
00436         DLY_INT_A_T1            = (1 << 25),
00437         DLY_INT_A_T0            = ( 1 << 24),
00438         EVENT_COUNT_A           = (0xF << 16) | (0x1 << 20),/* 20:16 */
00439         MAX_DELAY_TIME_A        = (0xF << 0) | (0xF << 4) | (1 << 8)|
00440                                   (1 << 9) | (1 << 10), /* 10:0 */
00441 
00442 }DLY_INT_A_BITS;
00443 
00444 typedef enum {
00445 
00446         DLY_INT_B_R3            = (1 << 31),
00447         DLY_INT_B_R2            = (1 << 30),
00448         DLY_INT_B_R1            = (1 << 29),
00449         DLY_INT_B_R0            = (1 << 28),
00450         DLY_INT_B_T3            = (1 << 27),
00451         DLY_INT_B_T2            = (1 << 26),
00452         DLY_INT_B_T1            = (1 << 25),
00453         DLY_INT_B_T0            = ( 1 << 24),
00454         EVENT_COUNT_B           = (0xF << 16) | (0x1 << 20),/* 20:16 */
00455         MAX_DELAY_TIME_B        = (0xF << 0) | (0xF << 4) | (1 << 8)| 
00456                                   (1 << 9) | (1 << 10), /* 10:0 */
00457 }DLY_INT_B_BITS;
00458 
00459 
00460 /* FLOW_CONTROL                 0xC8, 32bit register */
00461 typedef enum {
00462 
00463         PAUSE_LEN_CHG           = (1 << 30),
00464         FTPE                    = (1 << 22),
00465         FRPE                    = (1 << 21),
00466         NAPA                    = (1 << 20),
00467         NPA                     = (1 << 19),
00468         FIXP                    = ( 1 << 18),
00469         FCCMD                   = ( 1 << 16),
00470         PAUSE_LEN               = (0xF << 0) | (0xF << 4) |( 0xF << 8) |                                          (0xF << 12),  /* 15:0 */
00471 
00472 }FLOW_CONTROL_BITS;
00473 
00474 /* PHY_ ACCESS                  0xD0, 32bit register */
00475 typedef enum {
00476 
00477         PHY_CMD_ACTIVE          = (1 << 31),
00478         PHY_WR_CMD              = (1 << 30),
00479         PHY_RD_CMD              = (1 << 29),
00480         PHY_RD_ERR              = (1 << 28),
00481         PHY_PRE_SUP             = (1 << 27),
00482         PHY_ADDR                = (1 << 21) | (1 << 22) | (1 << 23)|
00483                                         (1 << 24) |(1 << 25),/* 25:21 */
00484         PHY_REG_ADDR            = (1 << 16) | (1 << 17) | (1 << 18)|                                                    (1 << 19) | (1 << 20),/* 20:16 */
00485         PHY_DATA                = (0xF << 0)|(0xF << 4) |(0xF << 8)|
00486                                         (0xF << 12),/* 15:0 */
00487 
00488 }PHY_ACCESS_BITS;
00489 
00490 
00491 /* PMAT0                        0x190,   32bit register */
00492 typedef enum {
00493         PMR_ACTIVE              = (1 << 31),
00494         PMR_WR_CMD              = (1 << 30),
00495         PMR_RD_CMD              = (1 << 29),
00496         PMR_BANK                = (1 <<28),
00497         PMR_ADDR                = (0xF << 16)|(1 << 20)|(1 << 21)|
00498                                         (1 << 22),/* 22:16 */
00499         PMR_B4                  = (0xF << 0) | (0xF << 4),/* 15:0 */
00500 }PMAT0_BITS;
00501 
00502 
00503 /* PMAT1                        0x194,   32bit register */
00504 typedef enum {
00505         PMR_B3                  = (0xF << 24) | (0xF <<28),/* 31:24 */
00506         PMR_B2                  = (0xF << 16) |(0xF << 20),/* 23:16 */
00507         PMR_B1                  = (0xF << 8) | (0xF <<12), /* 15:8 */
00508         PMR_B0                  = (0xF << 0)|(0xF << 4),/* 7:0 */
00509 }PMAT1_BITS;
00510 
00511 /************************************************************************/
00512 /*                                                                      */
00513 /*                      MIB counter definitions                         */
00514 /*                                                                      */
00515 /************************************************************************/
00516 
00517 #define rcv_miss_pkts                           0x00
00518 #define rcv_octets                              0x01
00519 #define rcv_broadcast_pkts                      0x02
00520 #define rcv_multicast_pkts                      0x03
00521 #define rcv_undersize_pkts                      0x04
00522 #define rcv_oversize_pkts                       0x05
00523 #define rcv_fragments                           0x06
00524 #define rcv_jabbers                             0x07
00525 #define rcv_unicast_pkts                        0x08
00526 #define rcv_alignment_errors                    0x09
00527 #define rcv_fcs_errors                          0x0A
00528 #define rcv_good_octets                         0x0B
00529 #define rcv_mac_ctrl                            0x0C
00530 #define rcv_flow_ctrl                           0x0D
00531 #define rcv_pkts_64_octets                      0x0E
00532 #define rcv_pkts_65to127_octets                 0x0F
00533 #define rcv_pkts_128to255_octets                0x10
00534 #define rcv_pkts_256to511_octets                0x11
00535 #define rcv_pkts_512to1023_octets               0x12
00536 #define rcv_pkts_1024to1518_octets              0x13
00537 #define rcv_unsupported_opcode                  0x14
00538 #define rcv_symbol_errors                       0x15
00539 #define rcv_drop_pkts_ring1                     0x16
00540 #define rcv_drop_pkts_ring2                     0x17
00541 #define rcv_drop_pkts_ring3                     0x18
00542 #define rcv_drop_pkts_ring4                     0x19
00543 #define rcv_jumbo_pkts                          0x1A
00544 
00545 #define xmt_underrun_pkts                       0x20
00546 #define xmt_octets                              0x21
00547 #define xmt_packets                             0x22
00548 #define xmt_broadcast_pkts                      0x23
00549 #define xmt_multicast_pkts                      0x24
00550 #define xmt_collisions                          0x25
00551 #define xmt_unicast_pkts                        0x26
00552 #define xmt_one_collision                       0x27
00553 #define xmt_multiple_collision                  0x28
00554 #define xmt_deferred_transmit                   0x29
00555 #define xmt_late_collision                      0x2A
00556 #define xmt_excessive_defer                     0x2B
00557 #define xmt_loss_carrier                        0x2C
00558 #define xmt_excessive_collision                 0x2D
00559 #define xmt_back_pressure                       0x2E
00560 #define xmt_flow_ctrl                           0x2F
00561 #define xmt_pkts_64_octets                      0x30
00562 #define xmt_pkts_65to127_octets                 0x31
00563 #define xmt_pkts_128to255_octets                0x32
00564 #define xmt_pkts_256to511_octets                0x33
00565 #define xmt_pkts_512to1023_octets               0x34
00566 #define xmt_pkts_1024to1518_octet               0x35
00567 #define xmt_oversize_pkts                       0x36
00568 #define xmt_jumbo_pkts                          0x37
00569 
00570 /* ipg parameters */
00571 #define DEFAULT_IPG                     0x60
00572 #define IFS1_DELTA                      36
00573 #define IPG_CONVERGE_JIFFIES (HZ/2)
00574 #define IPG_STABLE_TIME 5
00575 #define MIN_IPG 96
00576 #define MAX_IPG 255
00577 #define IPG_STEP        16
00578 #define CSTATE  1 
00579 #define SSTATE  2 
00580 
00581 /* amd8111e descriptor flag definitions */
00582 typedef enum {
00583 
00584         OWN_BIT         =       (1 << 15),
00585         ADD_FCS_BIT     =       (1 << 13),
00586         LTINT_BIT       =       (1 << 12),
00587         STP_BIT         =       (1 << 9),
00588         ENP_BIT         =       (1 << 8),
00589         KILL_BIT        =       (1 << 6),
00590         TCC_VLAN_INSERT =       (1 << 1),
00591         TCC_VLAN_REPLACE =      (1 << 1) |( 1<< 0),
00592 
00593 }TX_FLAG_BITS;
00594 
00595 typedef enum {
00596         ERR_BIT         =       (1 << 14),
00597         FRAM_BIT        =       (1 << 13),
00598         OFLO_BIT        =       (1 << 12),
00599         CRC_BIT         =       (1 << 11),
00600         PAM_BIT         =       (1 << 6),
00601         LAFM_BIT        =       (1 << 5),
00602         BAM_BIT         =       (1 << 4),
00603         TT_VLAN_TAGGED  =       (1 << 3) |(1 << 2),/* 0x000 */
00604         TT_PRTY_TAGGED  =       (1 << 3),/* 0x0008 */
00605 
00606 }RX_FLAG_BITS;
00607 
00608 #define RESET_RX_FLAGS          0x0000
00609 #define TT_MASK                 0x000c
00610 #define TCC_MASK                0x0003
00611 
00612 /* driver ioctl parameters */
00613 #define AMD8111E_REG_DUMP_LEN    13*sizeof(u32) 
00614 
00615 /* crc generator constants */
00616 #define CRC32 0xedb88320
00617 #define INITCRC 0xFFFFFFFF
00618 
00619 /* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
00620 BUG? */
00621 #define  amd8111e_writeq(_UlData,_memMap)   \
00622                 writel(*(u32*)(&_UlData), _memMap);     \
00623                 writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)   
00624 
00625 /* maps the external speed options to internal value */
00626 typedef enum {
00627         SPEED_AUTONEG,
00628         SPEED10_HALF,
00629         SPEED10_FULL,
00630         SPEED100_HALF,
00631         SPEED100_FULL,
00632 }EXT_PHY_OPTION;
00633 
00634 
00635 #endif /* _AMD8111E_H */
00636