iPXE
reg.h
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Permission to use, copy, modify, and/or distribute this software for any
00005  * purpose with or without fee is hereby granted, provided that the above
00006  * copyright notice and this permission notice appear in all copies.
00007  *
00008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00015  */
00016 
00017 #ifndef REG_H
00018 #define REG_H
00019 
00020 FILE_LICENCE ( BSD2 );
00021 
00022 #include "../reg.h"
00023 
00024 #define AR_CR                0x0008
00025 #define AR_CR_RXE            (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
00026 #define AR_CR_RXD            0x00000020
00027 #define AR_CR_SWI            0x00000040
00028 
00029 #define AR_RXDP              0x000C
00030 
00031 #define AR_CFG               0x0014
00032 #define AR_CFG_SWTD          0x00000001
00033 #define AR_CFG_SWTB          0x00000002
00034 #define AR_CFG_SWRD          0x00000004
00035 #define AR_CFG_SWRB          0x00000008
00036 #define AR_CFG_SWRG          0x00000010
00037 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020
00038 #define AR_CFG_PHOK          0x00000100
00039 #define AR_CFG_CLK_GATE_DIS  0x00000400
00040 #define AR_CFG_EEBS          0x00000200
00041 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH         0x00060000
00042 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S       17
00043 
00044 #define AR_RXBP_THRESH       0x0018
00045 #define AR_RXBP_THRESH_HP    0x0000000f
00046 #define AR_RXBP_THRESH_HP_S  0
00047 #define AR_RXBP_THRESH_LP    0x00003f00
00048 #define AR_RXBP_THRESH_LP_S  8
00049 
00050 #define AR_MIRT              0x0020
00051 #define AR_MIRT_VAL          0x0000ffff
00052 #define AR_MIRT_VAL_S        16
00053 
00054 #define AR_IER               0x0024
00055 #define AR_IER_ENABLE        0x00000001
00056 #define AR_IER_DISABLE       0x00000000
00057 
00058 #define AR_TIMT              0x0028
00059 #define AR_TIMT_LAST         0x0000ffff
00060 #define AR_TIMT_LAST_S       0
00061 #define AR_TIMT_FIRST        0xffff0000
00062 #define AR_TIMT_FIRST_S      16
00063 
00064 #define AR_RIMT              0x002C
00065 #define AR_RIMT_LAST         0x0000ffff
00066 #define AR_RIMT_LAST_S       0
00067 #define AR_RIMT_FIRST        0xffff0000
00068 #define AR_RIMT_FIRST_S      16
00069 
00070 #define AR_DMASIZE_4B        0x00000000
00071 #define AR_DMASIZE_8B        0x00000001
00072 #define AR_DMASIZE_16B       0x00000002
00073 #define AR_DMASIZE_32B       0x00000003
00074 #define AR_DMASIZE_64B       0x00000004
00075 #define AR_DMASIZE_128B      0x00000005
00076 #define AR_DMASIZE_256B      0x00000006
00077 #define AR_DMASIZE_512B      0x00000007
00078 
00079 #define AR_TXCFG             0x0030
00080 #define AR_TXCFG_DMASZ_MASK  0x00000007
00081 #define AR_TXCFG_DMASZ_4B    0
00082 #define AR_TXCFG_DMASZ_8B    1
00083 #define AR_TXCFG_DMASZ_16B   2
00084 #define AR_TXCFG_DMASZ_32B   3
00085 #define AR_TXCFG_DMASZ_64B   4
00086 #define AR_TXCFG_DMASZ_128B  5
00087 #define AR_TXCFG_DMASZ_256B  6
00088 #define AR_TXCFG_DMASZ_512B  7
00089 #define AR_FTRIG             0x000003F0
00090 #define AR_FTRIG_S           4
00091 #define AR_FTRIG_IMMED       0x00000000
00092 #define AR_FTRIG_64B         0x00000010
00093 #define AR_FTRIG_128B        0x00000020
00094 #define AR_FTRIG_192B        0x00000030
00095 #define AR_FTRIG_256B        0x00000040
00096 #define AR_FTRIG_512B        0x00000080
00097 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800
00098 
00099 #define AR_RXCFG             0x0034
00100 #define AR_RXCFG_CHIRP       0x00000008
00101 #define AR_RXCFG_ZLFDMA      0x00000010
00102 #define AR_RXCFG_DMASZ_MASK  0x00000007
00103 #define AR_RXCFG_DMASZ_4B    0
00104 #define AR_RXCFG_DMASZ_8B    1
00105 #define AR_RXCFG_DMASZ_16B   2
00106 #define AR_RXCFG_DMASZ_32B   3
00107 #define AR_RXCFG_DMASZ_64B   4
00108 #define AR_RXCFG_DMASZ_128B  5
00109 #define AR_RXCFG_DMASZ_256B  6
00110 #define AR_RXCFG_DMASZ_512B  7
00111 
00112 #define AR_TOPS              0x0044
00113 #define AR_TOPS_MASK         0x0000FFFF
00114 
00115 #define AR_RXNPTO            0x0048
00116 #define AR_RXNPTO_MASK       0x000003FF
00117 
00118 #define AR_TXNPTO            0x004C
00119 #define AR_TXNPTO_MASK       0x000003FF
00120 #define AR_TXNPTO_QCU_MASK   0x000FFC00
00121 
00122 #define AR_RPGTO             0x0050
00123 #define AR_RPGTO_MASK        0x000003FF
00124 
00125 #define AR_RPCNT             0x0054
00126 #define AR_RPCNT_MASK        0x0000001F
00127 
00128 #define AR_MACMISC           0x0058
00129 #define AR_MACMISC_PCI_EXT_FORCE        0x00000010
00130 #define AR_MACMISC_DMA_OBS              0x000001E0
00131 #define AR_MACMISC_DMA_OBS_S            5
00132 #define AR_MACMISC_DMA_OBS_LINE_0       0
00133 #define AR_MACMISC_DMA_OBS_LINE_1       1
00134 #define AR_MACMISC_DMA_OBS_LINE_2       2
00135 #define AR_MACMISC_DMA_OBS_LINE_3       3
00136 #define AR_MACMISC_DMA_OBS_LINE_4       4
00137 #define AR_MACMISC_DMA_OBS_LINE_5       5
00138 #define AR_MACMISC_DMA_OBS_LINE_6       6
00139 #define AR_MACMISC_DMA_OBS_LINE_7       7
00140 #define AR_MACMISC_DMA_OBS_LINE_8       8
00141 #define AR_MACMISC_MISC_OBS             0x00000E00
00142 #define AR_MACMISC_MISC_OBS_S           9
00143 #define AR_MACMISC_MISC_OBS_BUS_LSB     0x00007000
00144 #define AR_MACMISC_MISC_OBS_BUS_LSB_S   12
00145 #define AR_MACMISC_MISC_OBS_BUS_MSB     0x00038000
00146 #define AR_MACMISC_MISC_OBS_BUS_MSB_S   15
00147 #define AR_MACMISC_MISC_OBS_BUS_1       1
00148 
00149 #define AR_DATABUF_SIZE         0x0060
00150 #define AR_DATABUF_SIZE_MASK    0x00000FFF
00151 
00152 #define AR_GTXTO    0x0064
00153 #define AR_GTXTO_TIMEOUT_COUNTER    0x0000FFFF
00154 #define AR_GTXTO_TIMEOUT_LIMIT      0xFFFF0000
00155 #define AR_GTXTO_TIMEOUT_LIMIT_S    16
00156 
00157 #define AR_GTTM     0x0068
00158 #define AR_GTTM_USEC          0x00000001
00159 #define AR_GTTM_IGNORE_IDLE   0x00000002
00160 #define AR_GTTM_RESET_IDLE    0x00000004
00161 #define AR_GTTM_CST_USEC      0x00000008
00162 
00163 #define AR_CST         0x006C
00164 #define AR_CST_TIMEOUT_COUNTER    0x0000FFFF
00165 #define AR_CST_TIMEOUT_LIMIT      0xFFFF0000
00166 #define AR_CST_TIMEOUT_LIMIT_S    16
00167 
00168 #define AR_HP_RXDP 0x0074
00169 #define AR_LP_RXDP 0x0078
00170 
00171 #define AR_ISR               0x0080
00172 #define AR_ISR_RXOK          0x00000001
00173 #define AR_ISR_RXDESC        0x00000002
00174 #define AR_ISR_HP_RXOK       0x00000001
00175 #define AR_ISR_LP_RXOK       0x00000002
00176 #define AR_ISR_RXERR         0x00000004
00177 #define AR_ISR_RXNOPKT       0x00000008
00178 #define AR_ISR_RXEOL         0x00000010
00179 #define AR_ISR_RXORN         0x00000020
00180 #define AR_ISR_TXOK          0x00000040
00181 #define AR_ISR_TXDESC        0x00000080
00182 #define AR_ISR_TXERR         0x00000100
00183 #define AR_ISR_TXNOPKT       0x00000200
00184 #define AR_ISR_TXEOL         0x00000400
00185 #define AR_ISR_TXURN         0x00000800
00186 #define AR_ISR_MIB           0x00001000
00187 #define AR_ISR_SWI           0x00002000
00188 #define AR_ISR_RXPHY         0x00004000
00189 #define AR_ISR_RXKCM         0x00008000
00190 #define AR_ISR_SWBA          0x00010000
00191 #define AR_ISR_BRSSI         0x00020000
00192 #define AR_ISR_BMISS         0x00040000
00193 #define AR_ISR_BNR           0x00100000
00194 #define AR_ISR_RXCHIRP       0x00200000
00195 #define AR_ISR_BCNMISC       0x00800000
00196 #define AR_ISR_TIM           0x00800000
00197 #define AR_ISR_QCBROVF       0x02000000
00198 #define AR_ISR_QCBRURN       0x04000000
00199 #define AR_ISR_QTRIG         0x08000000
00200 #define AR_ISR_GENTMR        0x10000000
00201 
00202 #define AR_ISR_TXMINTR       0x00080000
00203 #define AR_ISR_RXMINTR       0x01000000
00204 #define AR_ISR_TXINTM        0x40000000
00205 #define AR_ISR_RXINTM        0x80000000
00206 
00207 #define AR_ISR_S0               0x0084
00208 #define AR_ISR_S0_QCU_TXOK      0x000003FF
00209 #define AR_ISR_S0_QCU_TXOK_S    0
00210 #define AR_ISR_S0_QCU_TXDESC    0x03FF0000
00211 #define AR_ISR_S0_QCU_TXDESC_S  16
00212 
00213 #define AR_ISR_S1              0x0088
00214 #define AR_ISR_S1_QCU_TXERR    0x000003FF
00215 #define AR_ISR_S1_QCU_TXERR_S  0
00216 #define AR_ISR_S1_QCU_TXEOL    0x03FF0000
00217 #define AR_ISR_S1_QCU_TXEOL_S  16
00218 
00219 #define AR_ISR_S2              0x008c
00220 #define AR_ISR_S2_QCU_TXURN    0x000003FF
00221 #define AR_ISR_S2_BB_WATCHDOG  0x00010000
00222 #define AR_ISR_S2_CST          0x00400000
00223 #define AR_ISR_S2_GTT          0x00800000
00224 #define AR_ISR_S2_TIM          0x01000000
00225 #define AR_ISR_S2_CABEND       0x02000000
00226 #define AR_ISR_S2_DTIMSYNC     0x04000000
00227 #define AR_ISR_S2_BCNTO        0x08000000
00228 #define AR_ISR_S2_CABTO        0x10000000
00229 #define AR_ISR_S2_DTIM         0x20000000
00230 #define AR_ISR_S2_TSFOOR       0x40000000
00231 #define AR_ISR_S2_TBTT_TIME    0x80000000
00232 
00233 #define AR_ISR_S3             0x0090
00234 #define AR_ISR_S3_QCU_QCBROVF    0x000003FF
00235 #define AR_ISR_S3_QCU_QCBRURN    0x03FF0000
00236 
00237 #define AR_ISR_S4              0x0094
00238 #define AR_ISR_S4_QCU_QTRIG    0x000003FF
00239 #define AR_ISR_S4_RESV0        0xFFFFFC00
00240 
00241 #define AR_ISR_S5                   0x0098
00242 #define AR_ISR_S5_TIMER_TRIG        0x000000FF
00243 #define AR_ISR_S5_TIMER_THRESH      0x0007FE00
00244 #define AR_ISR_S5_TIM_TIMER         0x00000010
00245 #define AR_ISR_S5_DTIM_TIMER        0x00000020
00246 #define AR_IMR_S5                   0x00b8
00247 #define AR_IMR_S5_TIM_TIMER         0x00000010
00248 #define AR_IMR_S5_DTIM_TIMER        0x00000020
00249 #define AR_ISR_S5_GENTIMER_TRIG     0x0000FF80
00250 #define AR_ISR_S5_GENTIMER_TRIG_S   0
00251 #define AR_ISR_S5_GENTIMER_THRESH   0xFF800000
00252 #define AR_ISR_S5_GENTIMER_THRESH_S 16
00253 #define AR_IMR_S5_GENTIMER_TRIG     0x0000FF80
00254 #define AR_IMR_S5_GENTIMER_TRIG_S   0
00255 #define AR_IMR_S5_GENTIMER_THRESH   0xFF800000
00256 #define AR_IMR_S5_GENTIMER_THRESH_S 16
00257 
00258 #define AR_IMR               0x00a0
00259 #define AR_IMR_RXOK          0x00000001
00260 #define AR_IMR_RXDESC        0x00000002
00261 #define AR_IMR_RXOK_HP       0x00000001
00262 #define AR_IMR_RXOK_LP       0x00000002
00263 #define AR_IMR_RXERR         0x00000004
00264 #define AR_IMR_RXNOPKT       0x00000008
00265 #define AR_IMR_RXEOL         0x00000010
00266 #define AR_IMR_RXORN         0x00000020
00267 #define AR_IMR_TXOK          0x00000040
00268 #define AR_IMR_TXDESC        0x00000080
00269 #define AR_IMR_TXERR         0x00000100
00270 #define AR_IMR_TXNOPKT       0x00000200
00271 #define AR_IMR_TXEOL         0x00000400
00272 #define AR_IMR_TXURN         0x00000800
00273 #define AR_IMR_MIB           0x00001000
00274 #define AR_IMR_SWI           0x00002000
00275 #define AR_IMR_RXPHY         0x00004000
00276 #define AR_IMR_RXKCM         0x00008000
00277 #define AR_IMR_SWBA          0x00010000
00278 #define AR_IMR_BRSSI         0x00020000
00279 #define AR_IMR_BMISS         0x00040000
00280 #define AR_IMR_BNR           0x00100000
00281 #define AR_IMR_RXCHIRP       0x00200000
00282 #define AR_IMR_BCNMISC       0x00800000
00283 #define AR_IMR_TIM           0x00800000
00284 #define AR_IMR_QCBROVF       0x02000000
00285 #define AR_IMR_QCBRURN       0x04000000
00286 #define AR_IMR_QTRIG         0x08000000
00287 #define AR_IMR_GENTMR        0x10000000
00288 
00289 #define AR_IMR_TXMINTR       0x00080000
00290 #define AR_IMR_RXMINTR       0x01000000
00291 #define AR_IMR_TXINTM        0x40000000
00292 #define AR_IMR_RXINTM        0x80000000
00293 
00294 #define AR_IMR_S0               0x00a4
00295 #define AR_IMR_S0_QCU_TXOK      0x000003FF
00296 #define AR_IMR_S0_QCU_TXOK_S    0
00297 #define AR_IMR_S0_QCU_TXDESC    0x03FF0000
00298 #define AR_IMR_S0_QCU_TXDESC_S  16
00299 
00300 #define AR_IMR_S1              0x00a8
00301 #define AR_IMR_S1_QCU_TXERR    0x000003FF
00302 #define AR_IMR_S1_QCU_TXERR_S  0
00303 #define AR_IMR_S1_QCU_TXEOL    0x03FF0000
00304 #define AR_IMR_S1_QCU_TXEOL_S  16
00305 
00306 #define AR_IMR_S2              0x00ac
00307 #define AR_IMR_S2_QCU_TXURN    0x000003FF
00308 #define AR_IMR_S2_QCU_TXURN_S  0
00309 #define AR_IMR_S2_CST          0x00400000
00310 #define AR_IMR_S2_GTT          0x00800000
00311 #define AR_IMR_S2_TIM          0x01000000
00312 #define AR_IMR_S2_CABEND       0x02000000
00313 #define AR_IMR_S2_DTIMSYNC     0x04000000
00314 #define AR_IMR_S2_BCNTO        0x08000000
00315 #define AR_IMR_S2_CABTO        0x10000000
00316 #define AR_IMR_S2_DTIM         0x20000000
00317 #define AR_IMR_S2_TSFOOR       0x40000000
00318 
00319 #define AR_IMR_S3                0x00b0
00320 #define AR_IMR_S3_QCU_QCBROVF    0x000003FF
00321 #define AR_IMR_S3_QCU_QCBRURN    0x03FF0000
00322 #define AR_IMR_S3_QCU_QCBRURN_S  16
00323 
00324 #define AR_IMR_S4              0x00b4
00325 #define AR_IMR_S4_QCU_QTRIG    0x000003FF
00326 #define AR_IMR_S4_RESV0        0xFFFFFC00
00327 
00328 #define AR_IMR_S5              0x00b8
00329 #define AR_IMR_S5_TIMER_TRIG        0x000000FF
00330 #define AR_IMR_S5_TIMER_THRESH      0x0000FF00
00331 
00332 
00333 #define AR_ISR_RAC            0x00c0
00334 #define AR_ISR_S0_S           0x00c4
00335 #define AR_ISR_S0_QCU_TXOK      0x000003FF
00336 #define AR_ISR_S0_QCU_TXOK_S    0
00337 #define AR_ISR_S0_QCU_TXDESC    0x03FF0000
00338 #define AR_ISR_S0_QCU_TXDESC_S  16
00339 
00340 #define AR_ISR_S1_S           0x00c8
00341 #define AR_ISR_S1_QCU_TXERR    0x000003FF
00342 #define AR_ISR_S1_QCU_TXERR_S  0
00343 #define AR_ISR_S1_QCU_TXEOL    0x03FF0000
00344 #define AR_ISR_S1_QCU_TXEOL_S  16
00345 
00346 #define AR_ISR_S2_S           (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
00347 #define AR_ISR_S3_S           (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
00348 #define AR_ISR_S4_S           (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
00349 #define AR_ISR_S5_S           (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
00350 #define AR_DMADBG_0           0x00e0
00351 #define AR_DMADBG_1           0x00e4
00352 #define AR_DMADBG_2           0x00e8
00353 #define AR_DMADBG_3           0x00ec
00354 #define AR_DMADBG_4           0x00f0
00355 #define AR_DMADBG_5           0x00f4
00356 #define AR_DMADBG_6           0x00f8
00357 #define AR_DMADBG_7           0x00fc
00358 
00359 #define AR_NUM_QCU      10
00360 #define AR_QCU_0        0x0001
00361 #define AR_QCU_1        0x0002
00362 #define AR_QCU_2        0x0004
00363 #define AR_QCU_3        0x0008
00364 #define AR_QCU_4        0x0010
00365 #define AR_QCU_5        0x0020
00366 #define AR_QCU_6        0x0040
00367 #define AR_QCU_7        0x0080
00368 #define AR_QCU_8        0x0100
00369 #define AR_QCU_9        0x0200
00370 
00371 #define AR_Q0_TXDP           0x0800
00372 #define AR_Q1_TXDP           0x0804
00373 #define AR_Q2_TXDP           0x0808
00374 #define AR_Q3_TXDP           0x080c
00375 #define AR_Q4_TXDP           0x0810
00376 #define AR_Q5_TXDP           0x0814
00377 #define AR_Q6_TXDP           0x0818
00378 #define AR_Q7_TXDP           0x081c
00379 #define AR_Q8_TXDP           0x0820
00380 #define AR_Q9_TXDP           0x0824
00381 #define AR_QTXDP(_i)    (AR_Q0_TXDP + ((_i)<<2))
00382 
00383 #define AR_Q_STATUS_RING_START  0x830
00384 #define AR_Q_STATUS_RING_END    0x834
00385 
00386 #define AR_Q_TXE             0x0840
00387 #define AR_Q_TXE_M           0x000003FF
00388 
00389 #define AR_Q_TXD             0x0880
00390 #define AR_Q_TXD_M           0x000003FF
00391 
00392 #define AR_Q0_CBRCFG         0x08c0
00393 #define AR_Q1_CBRCFG         0x08c4
00394 #define AR_Q2_CBRCFG         0x08c8
00395 #define AR_Q3_CBRCFG         0x08cc
00396 #define AR_Q4_CBRCFG         0x08d0
00397 #define AR_Q5_CBRCFG         0x08d4
00398 #define AR_Q6_CBRCFG         0x08d8
00399 #define AR_Q7_CBRCFG         0x08dc
00400 #define AR_Q8_CBRCFG         0x08e0
00401 #define AR_Q9_CBRCFG         0x08e4
00402 #define AR_QCBRCFG(_i)      (AR_Q0_CBRCFG + ((_i)<<2))
00403 #define AR_Q_CBRCFG_INTERVAL     0x00FFFFFF
00404 #define AR_Q_CBRCFG_INTERVAL_S   0
00405 #define AR_Q_CBRCFG_OVF_THRESH   0xFF000000
00406 #define AR_Q_CBRCFG_OVF_THRESH_S 24
00407 
00408 #define AR_Q0_RDYTIMECFG         0x0900
00409 #define AR_Q1_RDYTIMECFG         0x0904
00410 #define AR_Q2_RDYTIMECFG         0x0908
00411 #define AR_Q3_RDYTIMECFG         0x090c
00412 #define AR_Q4_RDYTIMECFG         0x0910
00413 #define AR_Q5_RDYTIMECFG         0x0914
00414 #define AR_Q6_RDYTIMECFG         0x0918
00415 #define AR_Q7_RDYTIMECFG         0x091c
00416 #define AR_Q8_RDYTIMECFG         0x0920
00417 #define AR_Q9_RDYTIMECFG         0x0924
00418 #define AR_QRDYTIMECFG(_i)       (AR_Q0_RDYTIMECFG + ((_i)<<2))
00419 #define AR_Q_RDYTIMECFG_DURATION   0x00FFFFFF
00420 #define AR_Q_RDYTIMECFG_DURATION_S 0
00421 #define AR_Q_RDYTIMECFG_EN         0x01000000
00422 
00423 #define AR_Q_ONESHOTARM_SC       0x0940
00424 #define AR_Q_ONESHOTARM_SC_M     0x000003FF
00425 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00
00426 
00427 #define AR_Q_ONESHOTARM_CC       0x0980
00428 #define AR_Q_ONESHOTARM_CC_M     0x000003FF
00429 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00
00430 
00431 #define AR_Q0_MISC         0x09c0
00432 #define AR_Q1_MISC         0x09c4
00433 #define AR_Q2_MISC         0x09c8
00434 #define AR_Q3_MISC         0x09cc
00435 #define AR_Q4_MISC         0x09d0
00436 #define AR_Q5_MISC         0x09d4
00437 #define AR_Q6_MISC         0x09d8
00438 #define AR_Q7_MISC         0x09dc
00439 #define AR_Q8_MISC         0x09e0
00440 #define AR_Q9_MISC         0x09e4
00441 #define AR_QMISC(_i)       (AR_Q0_MISC + ((_i)<<2))
00442 #define AR_Q_MISC_FSP                     0x0000000F
00443 #define AR_Q_MISC_FSP_ASAP                0
00444 #define AR_Q_MISC_FSP_CBR                 1
00445 #define AR_Q_MISC_FSP_DBA_GATED           2
00446 #define AR_Q_MISC_FSP_TIM_GATED           3
00447 #define AR_Q_MISC_FSP_BEACON_SENT_GATED   4
00448 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED   5
00449 #define AR_Q_MISC_ONE_SHOT_EN             0x00000010
00450 #define AR_Q_MISC_CBR_INCR_DIS1           0x00000020
00451 #define AR_Q_MISC_CBR_INCR_DIS0           0x00000040
00452 #define AR_Q_MISC_BEACON_USE              0x00000080
00453 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN   0x00000100
00454 #define AR_Q_MISC_RDYTIME_EXP_POLICY      0x00000200
00455 #define AR_Q_MISC_RESET_CBR_EXP_CTR       0x00000400
00456 #define AR_Q_MISC_DCU_EARLY_TERM_REQ      0x00000800
00457 #define AR_Q_MISC_RESV0                   0xFFFFF000
00458 
00459 #define AR_Q0_STS         0x0a00
00460 #define AR_Q1_STS         0x0a04
00461 #define AR_Q2_STS         0x0a08
00462 #define AR_Q3_STS         0x0a0c
00463 #define AR_Q4_STS         0x0a10
00464 #define AR_Q5_STS         0x0a14
00465 #define AR_Q6_STS         0x0a18
00466 #define AR_Q7_STS         0x0a1c
00467 #define AR_Q8_STS         0x0a20
00468 #define AR_Q9_STS         0x0a24
00469 #define AR_QSTS(_i)       (AR_Q0_STS + ((_i)<<2))
00470 #define AR_Q_STS_PEND_FR_CNT          0x00000003
00471 #define AR_Q_STS_RESV0                0x000000FC
00472 #define AR_Q_STS_CBR_EXP_CNT          0x0000FF00
00473 #define AR_Q_STS_RESV1                0xFFFF0000
00474 
00475 #define AR_Q_RDYTIMESHDN    0x0a40
00476 #define AR_Q_RDYTIMESHDN_M  0x000003FF
00477 
00478 /* MAC Descriptor CRC check */
00479 #define AR_Q_DESC_CRCCHK    0xa44
00480 /* Enable CRC check on the descriptor fetched from host */
00481 #define AR_Q_DESC_CRCCHK_EN 1
00482 
00483 #define AR_NUM_DCU      10
00484 #define AR_DCU_0        0x0001
00485 #define AR_DCU_1        0x0002
00486 #define AR_DCU_2        0x0004
00487 #define AR_DCU_3        0x0008
00488 #define AR_DCU_4        0x0010
00489 #define AR_DCU_5        0x0020
00490 #define AR_DCU_6        0x0040
00491 #define AR_DCU_7        0x0080
00492 #define AR_DCU_8        0x0100
00493 #define AR_DCU_9        0x0200
00494 
00495 #define AR_D0_QCUMASK     0x1000
00496 #define AR_D1_QCUMASK     0x1004
00497 #define AR_D2_QCUMASK     0x1008
00498 #define AR_D3_QCUMASK     0x100c
00499 #define AR_D4_QCUMASK     0x1010
00500 #define AR_D5_QCUMASK     0x1014
00501 #define AR_D6_QCUMASK     0x1018
00502 #define AR_D7_QCUMASK     0x101c
00503 #define AR_D8_QCUMASK     0x1020
00504 #define AR_D9_QCUMASK     0x1024
00505 #define AR_DQCUMASK(_i)   (AR_D0_QCUMASK + ((_i)<<2))
00506 #define AR_D_QCUMASK         0x000003FF
00507 #define AR_D_QCUMASK_RESV0   0xFFFFFC00
00508 
00509 #define AR_D_TXBLK_CMD  0x1038
00510 #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i))
00511 
00512 #define AR_D0_LCL_IFS     0x1040
00513 #define AR_D1_LCL_IFS     0x1044
00514 #define AR_D2_LCL_IFS     0x1048
00515 #define AR_D3_LCL_IFS     0x104c
00516 #define AR_D4_LCL_IFS     0x1050
00517 #define AR_D5_LCL_IFS     0x1054
00518 #define AR_D6_LCL_IFS     0x1058
00519 #define AR_D7_LCL_IFS     0x105c
00520 #define AR_D8_LCL_IFS     0x1060
00521 #define AR_D9_LCL_IFS     0x1064
00522 #define AR_DLCL_IFS(_i)   (AR_D0_LCL_IFS + ((_i)<<2))
00523 #define AR_D_LCL_IFS_CWMIN       0x000003FF
00524 #define AR_D_LCL_IFS_CWMIN_S     0
00525 #define AR_D_LCL_IFS_CWMAX       0x000FFC00
00526 #define AR_D_LCL_IFS_CWMAX_S     10
00527 #define AR_D_LCL_IFS_AIFS        0x0FF00000
00528 #define AR_D_LCL_IFS_AIFS_S      20
00529 
00530 #define AR_D_LCL_IFS_RESV0    0xF0000000
00531 
00532 #define AR_D0_RETRY_LIMIT     0x1080
00533 #define AR_D1_RETRY_LIMIT     0x1084
00534 #define AR_D2_RETRY_LIMIT     0x1088
00535 #define AR_D3_RETRY_LIMIT     0x108c
00536 #define AR_D4_RETRY_LIMIT     0x1090
00537 #define AR_D5_RETRY_LIMIT     0x1094
00538 #define AR_D6_RETRY_LIMIT     0x1098
00539 #define AR_D7_RETRY_LIMIT     0x109c
00540 #define AR_D8_RETRY_LIMIT     0x10a0
00541 #define AR_D9_RETRY_LIMIT     0x10a4
00542 #define AR_DRETRY_LIMIT(_i)   (AR_D0_RETRY_LIMIT + ((_i)<<2))
00543 #define AR_D_RETRY_LIMIT_FR_SH       0x0000000F
00544 #define AR_D_RETRY_LIMIT_FR_SH_S     0
00545 #define AR_D_RETRY_LIMIT_STA_SH      0x00003F00
00546 #define AR_D_RETRY_LIMIT_STA_SH_S    8
00547 #define AR_D_RETRY_LIMIT_STA_LG      0x000FC000
00548 #define AR_D_RETRY_LIMIT_STA_LG_S    14
00549 #define AR_D_RETRY_LIMIT_RESV0       0xFFF00000
00550 
00551 #define AR_D0_CHNTIME     0x10c0
00552 #define AR_D1_CHNTIME     0x10c4
00553 #define AR_D2_CHNTIME     0x10c8
00554 #define AR_D3_CHNTIME     0x10cc
00555 #define AR_D4_CHNTIME     0x10d0
00556 #define AR_D5_CHNTIME     0x10d4
00557 #define AR_D6_CHNTIME     0x10d8
00558 #define AR_D7_CHNTIME     0x10dc
00559 #define AR_D8_CHNTIME     0x10e0
00560 #define AR_D9_CHNTIME     0x10e4
00561 #define AR_DCHNTIME(_i)   (AR_D0_CHNTIME + ((_i)<<2))
00562 #define AR_D_CHNTIME_DUR         0x000FFFFF
00563 #define AR_D_CHNTIME_DUR_S       0
00564 #define AR_D_CHNTIME_EN          0x00100000
00565 #define AR_D_CHNTIME_RESV0       0xFFE00000
00566 
00567 #define AR_D0_MISC        0x1100
00568 #define AR_D1_MISC        0x1104
00569 #define AR_D2_MISC        0x1108
00570 #define AR_D3_MISC        0x110c
00571 #define AR_D4_MISC        0x1110
00572 #define AR_D5_MISC        0x1114
00573 #define AR_D6_MISC        0x1118
00574 #define AR_D7_MISC        0x111c
00575 #define AR_D8_MISC        0x1120
00576 #define AR_D9_MISC        0x1124
00577 #define AR_DMISC(_i)      (AR_D0_MISC + ((_i)<<2))
00578 #define AR_D_MISC_BKOFF_THRESH        0x0000003F
00579 #define AR_D_MISC_RETRY_CNT_RESET_EN  0x00000040
00580 #define AR_D_MISC_CW_RESET_EN         0x00000080
00581 #define AR_D_MISC_FRAG_WAIT_EN        0x00000100
00582 #define AR_D_MISC_FRAG_BKOFF_EN       0x00000200
00583 #define AR_D_MISC_CW_BKOFF_EN         0x00001000
00584 #define AR_D_MISC_VIR_COL_HANDLING    0x0000C000
00585 #define AR_D_MISC_VIR_COL_HANDLING_S  14
00586 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0
00587 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE  1
00588 #define AR_D_MISC_BEACON_USE          0x00010000
00589 #define AR_D_MISC_ARB_LOCKOUT_CNTRL   0x00060000
00590 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17
00591 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE     0
00592 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1
00593 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL   2
00594 #define AR_D_MISC_ARB_LOCKOUT_IGNORE  0x00080000
00595 #define AR_D_MISC_SEQ_NUM_INCR_DIS    0x00100000
00596 #define AR_D_MISC_POST_FR_BKOFF_DIS   0x00200000
00597 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000
00598 #define AR_D_MISC_BLOWN_IFS_RETRY_EN  0x00800000
00599 #define AR_D_MISC_RESV0               0xFF000000
00600 
00601 #define AR_D_SEQNUM      0x1140
00602 
00603 #define AR_D_GBL_IFS_SIFS         0x1030
00604 #define AR_D_GBL_IFS_SIFS_M       0x0000FFFF
00605 #define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB
00606 #define AR_D_GBL_IFS_SIFS_RESV0   0xFFFFFFFF
00607 
00608 #define AR_D_TXBLK_BASE            0x1038
00609 #define AR_D_TXBLK_WRITE_BITMASK    0x0000FFFF
00610 #define AR_D_TXBLK_WRITE_BITMASK_S  0
00611 #define AR_D_TXBLK_WRITE_SLICE      0x000F0000
00612 #define AR_D_TXBLK_WRITE_SLICE_S    16
00613 #define AR_D_TXBLK_WRITE_DCU        0x00F00000
00614 #define AR_D_TXBLK_WRITE_DCU_S      20
00615 #define AR_D_TXBLK_WRITE_COMMAND    0x0F000000
00616 #define AR_D_TXBLK_WRITE_COMMAND_S      24
00617 
00618 #define AR_D_GBL_IFS_SLOT         0x1070
00619 #define AR_D_GBL_IFS_SLOT_M       0x0000FFFF
00620 #define AR_D_GBL_IFS_SLOT_RESV0   0xFFFF0000
00621 #define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR   0x00000420
00622 
00623 #define AR_D_GBL_IFS_EIFS         0x10b0
00624 #define AR_D_GBL_IFS_EIFS_M       0x0000FFFF
00625 #define AR_D_GBL_IFS_EIFS_RESV0   0xFFFF0000
00626 #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR   0x0000A5EB
00627 
00628 #define AR_D_GBL_IFS_MISC        0x10f0
00629 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL        0x00000007
00630 #define AR_D_GBL_IFS_MISC_TURBO_MODE            0x00000008
00631 #define AR_D_GBL_IFS_MISC_USEC_DURATION         0x000FFC00
00632 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY       0x00300000
00633 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000
00634 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN    0x06000000
00635 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000
00636 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF        0x10000000
00637 
00638 #define AR_D_FPCTL                  0x1230
00639 #define AR_D_FPCTL_DCU              0x0000000F
00640 #define AR_D_FPCTL_DCU_S            0
00641 #define AR_D_FPCTL_PREFETCH_EN      0x00000010
00642 #define AR_D_FPCTL_BURST_PREFETCH   0x00007FE0
00643 #define AR_D_FPCTL_BURST_PREFETCH_S 5
00644 
00645 #define AR_D_TXPSE                 0x1270
00646 #define AR_D_TXPSE_CTRL            0x000003FF
00647 #define AR_D_TXPSE_RESV0           0x0000FC00
00648 #define AR_D_TXPSE_STATUS          0x00010000
00649 #define AR_D_TXPSE_RESV1           0xFFFE0000
00650 
00651 #define AR_D_TXSLOTMASK            0x12f0
00652 #define AR_D_TXSLOTMASK_NUM        0x0000000F
00653 
00654 #define AR_CFG_LED                     0x1f04
00655 #define AR_CFG_SCLK_RATE_IND           0x00000003
00656 #define AR_CFG_SCLK_RATE_IND_S         0
00657 #define AR_CFG_SCLK_32MHZ              0x00000000
00658 #define AR_CFG_SCLK_4MHZ               0x00000001
00659 #define AR_CFG_SCLK_1MHZ               0x00000002
00660 #define AR_CFG_SCLK_32KHZ              0x00000003
00661 #define AR_CFG_LED_BLINK_SLOW          0x00000008
00662 #define AR_CFG_LED_BLINK_THRESH_SEL    0x00000070
00663 #define AR_CFG_LED_MODE_SEL            0x00000380
00664 #define AR_CFG_LED_MODE_SEL_S          7
00665 #define AR_CFG_LED_POWER               0x00000280
00666 #define AR_CFG_LED_POWER_S             7
00667 #define AR_CFG_LED_NETWORK             0x00000300
00668 #define AR_CFG_LED_NETWORK_S           7
00669 #define AR_CFG_LED_MODE_PROP           0x0
00670 #define AR_CFG_LED_MODE_RPROP          0x1
00671 #define AR_CFG_LED_MODE_SPLIT          0x2
00672 #define AR_CFG_LED_MODE_RAND           0x3
00673 #define AR_CFG_LED_MODE_POWER_OFF      0x4
00674 #define AR_CFG_LED_MODE_POWER_ON       0x5
00675 #define AR_CFG_LED_MODE_NETWORK_OFF    0x4
00676 #define AR_CFG_LED_MODE_NETWORK_ON     0x6
00677 #define AR_CFG_LED_ASSOC_CTL           0x00000c00
00678 #define AR_CFG_LED_ASSOC_CTL_S         10
00679 #define AR_CFG_LED_ASSOC_NONE          0x0
00680 #define AR_CFG_LED_ASSOC_ACTIVE        0x1
00681 #define AR_CFG_LED_ASSOC_PENDING       0x2
00682 
00683 #define AR_CFG_LED_BLINK_SLOW          0x00000008
00684 #define AR_CFG_LED_BLINK_SLOW_S        3
00685 
00686 #define AR_CFG_LED_BLINK_THRESH_SEL    0x00000070
00687 #define AR_CFG_LED_BLINK_THRESH_SEL_S  4
00688 
00689 #define AR_MAC_SLEEP                0x1f00
00690 #define AR_MAC_SLEEP_MAC_AWAKE      0x00000000
00691 #define AR_MAC_SLEEP_MAC_ASLEEP     0x00000001
00692 
00693 #define AR_RC                0x4000
00694 #define AR_RC_AHB            0x00000001
00695 #define AR_RC_APB            0x00000002
00696 #define AR_RC_HOSTIF         0x00000100
00697 
00698 #define AR_WA                   (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
00699 #define AR_WA_BIT6                      (1 << 6)
00700 #define AR_WA_BIT7                      (1 << 7)
00701 #define AR_WA_BIT23                     (1 << 23)
00702 #define AR_WA_D3_L1_DISABLE             (1 << 14)
00703 #define AR_WA_D3_TO_L1_DISABLE_REAL     (1 << 16)
00704 #define AR_WA_ASPM_TIMER_BASED_DISABLE  (1 << 17)
00705 #define AR_WA_RESET_EN                  (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
00706 #define AR_WA_ANALOG_SHIFT              (1 << 20)
00707 #define AR_WA_POR_SHORT                 (1 << 21) /* PCI-E Phy reset control */
00708 #define AR_WA_BIT22                     (1 << 22)
00709 #define AR9285_WA_DEFAULT               0x004a050b
00710 #define AR9280_WA_DEFAULT               0x0040073b
00711 #define AR_WA_DEFAULT                   0x0000073f
00712 
00713 
00714 #define AR_PM_STATE                 0x4008
00715 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
00716 
00717 #define AR_HOST_TIMEOUT             (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
00718 #define AR_HOST_TIMEOUT_APB_CNTR    0x0000FFFF
00719 #define AR_HOST_TIMEOUT_APB_CNTR_S  0
00720 #define AR_HOST_TIMEOUT_LCL_CNTR    0xFFFF0000
00721 #define AR_HOST_TIMEOUT_LCL_CNTR_S  16
00722 
00723 #define AR_EEPROM                0x401c
00724 #define AR_EEPROM_ABSENT         0x00000100
00725 #define AR_EEPROM_CORRUPT        0x00000200
00726 #define AR_EEPROM_PROT_MASK      0x03FFFC00
00727 #define AR_EEPROM_PROT_MASK_S    10
00728 
00729 #define EEPROM_PROTECT_RP_0_31        0x0001
00730 #define EEPROM_PROTECT_WP_0_31        0x0002
00731 #define EEPROM_PROTECT_RP_32_63       0x0004
00732 #define EEPROM_PROTECT_WP_32_63       0x0008
00733 #define EEPROM_PROTECT_RP_64_127      0x0010
00734 #define EEPROM_PROTECT_WP_64_127      0x0020
00735 #define EEPROM_PROTECT_RP_128_191     0x0040
00736 #define EEPROM_PROTECT_WP_128_191     0x0080
00737 #define EEPROM_PROTECT_RP_192_255     0x0100
00738 #define EEPROM_PROTECT_WP_192_255     0x0200
00739 #define EEPROM_PROTECT_RP_256_511     0x0400
00740 #define EEPROM_PROTECT_WP_256_511     0x0800
00741 #define EEPROM_PROTECT_RP_512_1023    0x1000
00742 #define EEPROM_PROTECT_WP_512_1023    0x2000
00743 #define EEPROM_PROTECT_RP_1024_2047   0x4000
00744 #define EEPROM_PROTECT_WP_1024_2047   0x8000
00745 
00746 #define AR_SREV \
00747         ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
00748                                         ? 0x400c : 0x4020))
00749 
00750 #define AR_SREV_ID \
00751         ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
00752 #define AR_SREV_VERSION                       0x000000F0
00753 #define AR_SREV_VERSION_S                     4
00754 #define AR_SREV_REVISION                      0x00000007
00755 
00756 #define AR_SREV_ID2                           0xFFFFFFFF
00757 #define AR_SREV_VERSION2                      0xFFFC0000
00758 #define AR_SREV_VERSION2_S                    18
00759 #define AR_SREV_TYPE2                         0x0003F000
00760 #define AR_SREV_TYPE2_S                       12
00761 #define AR_SREV_TYPE2_CHAIN                   0x00001000
00762 #define AR_SREV_TYPE2_HOST_MODE               0x00002000
00763 #define AR_SREV_REVISION2                     0x00000F00
00764 #define AR_SREV_REVISION2_S                   8
00765 
00766 #define AR_SREV_VERSION_5416_PCI        0xD
00767 #define AR_SREV_VERSION_5416_PCIE       0xC
00768 #define AR_SREV_REVISION_5416_10        0
00769 #define AR_SREV_REVISION_5416_20        1
00770 #define AR_SREV_REVISION_5416_22        2
00771 #define AR_SREV_VERSION_9100            0x14
00772 #define AR_SREV_VERSION_9160            0x40
00773 #define AR_SREV_REVISION_9160_10        0
00774 #define AR_SREV_REVISION_9160_11        1
00775 #define AR_SREV_VERSION_9280            0x80
00776 #define AR_SREV_REVISION_9280_10        0
00777 #define AR_SREV_REVISION_9280_20        1
00778 #define AR_SREV_REVISION_9280_21        2
00779 #define AR_SREV_VERSION_9285            0xC0
00780 #define AR_SREV_REVISION_9285_10        0
00781 #define AR_SREV_REVISION_9285_11        1
00782 #define AR_SREV_REVISION_9285_12        2
00783 #define AR_SREV_VERSION_9287            0x180
00784 #define AR_SREV_REVISION_9287_10        0
00785 #define AR_SREV_REVISION_9287_11        1
00786 #define AR_SREV_REVISION_9287_12        2
00787 #define AR_SREV_REVISION_9287_13        3
00788 #define AR_SREV_VERSION_9271            0x140
00789 #define AR_SREV_REVISION_9271_10        0
00790 #define AR_SREV_REVISION_9271_11        1
00791 #define AR_SREV_VERSION_9300            0x1c0
00792 #define AR_SREV_REVISION_9300_20        2 /* 2.0 and 2.1 */
00793 #define AR_SREV_VERSION_9485            0x240
00794 #define AR_SREV_REVISION_9485_10        0
00795 #define AR_SREV_REVISION_9485_11        1
00796 #define AR_SREV_VERSION_9340            0x300
00797 
00798 #define AR_SREV_5416(_ah) \
00799         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
00800          ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE))
00801 #define AR_SREV_5416_20_OR_LATER(_ah) \
00802         (((AR_SREV_5416(_ah)) && \
00803          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \
00804          ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
00805 #define AR_SREV_5416_22_OR_LATER(_ah) \
00806         (((AR_SREV_5416(_ah)) && \
00807          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \
00808          ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
00809 
00810 #define AR_SREV_9100(ah) \
00811         ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100)
00812 #define AR_SREV_9100_OR_LATER(_ah) \
00813         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
00814 
00815 #define AR_SREV_9160(_ah) \
00816         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160))
00817 #define AR_SREV_9160_10_OR_LATER(_ah) \
00818         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160))
00819 #define AR_SREV_9160_11(_ah) \
00820         (AR_SREV_9160(_ah) && \
00821          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))
00822 #define AR_SREV_9280(_ah) \
00823         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
00824 #define AR_SREV_9280_20_OR_LATER(_ah) \
00825         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))
00826 #define AR_SREV_9280_20(_ah) \
00827         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
00828 
00829 #define AR_SREV_9285(_ah) \
00830         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))
00831 #define AR_SREV_9285_12_OR_LATER(_ah) \
00832         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
00833 
00834 #define AR_SREV_9287(_ah) \
00835         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))
00836 #define AR_SREV_9287_11_OR_LATER(_ah) \
00837         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))
00838 #define AR_SREV_9287_11(_ah) \
00839         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
00840          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))
00841 #define AR_SREV_9287_12(_ah) \
00842         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
00843          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))
00844 #define AR_SREV_9287_12_OR_LATER(_ah) \
00845         (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
00846          (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
00847           ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))
00848 #define AR_SREV_9287_13_OR_LATER(_ah) \
00849         (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
00850          (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
00851           ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13)))
00852 
00853 #define AR_SREV_9271(_ah) \
00854     (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)
00855 #define AR_SREV_9271_10(_ah) \
00856     (AR_SREV_9271(_ah) && \
00857      ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10))
00858 #define AR_SREV_9271_11(_ah) \
00859     (AR_SREV_9271(_ah) && \
00860      ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))
00861 
00862 #define AR_SREV_9300(_ah) \
00863         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
00864 #define AR_SREV_9300_20_OR_LATER(_ah) \
00865         ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)
00866 
00867 #define AR_SREV_9485(_ah) \
00868         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
00869 #define AR_SREV_9485_10(_ah) \
00870         (AR_SREV_9485(_ah) && \
00871          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))
00872 #define AR_SREV_9485_11(_ah) \
00873         (AR_SREV_9485(_ah) && \
00874          ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))
00875 #define AR_SREV_9485_OR_LATER(_ah) \
00876         (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))
00877 
00878 #define AR_SREV_9340(_ah) \
00879         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
00880 
00881 #define AR_SREV_9285E_20(_ah) \
00882     (AR_SREV_9285_12_OR_LATER(_ah) && \
00883      ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
00884 
00885 enum ath_usb_dev {
00886         AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
00887         AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
00888         STORAGE_DEVICE = 3,
00889 };
00890 
00891 #define AR_DEVID_7010(_ah) \
00892         (((_ah)->hw_version.usbdev == AR9280_USB) || \
00893          ((_ah)->hw_version.usbdev == AR9287_USB))
00894 
00895 #define AR_RADIO_SREV_MAJOR                   0xf0
00896 #define AR_RAD5133_SREV_MAJOR                 0xc0
00897 #define AR_RAD2133_SREV_MAJOR                 0xd0
00898 #define AR_RAD5122_SREV_MAJOR                 0xe0
00899 #define AR_RAD2122_SREV_MAJOR                 0xf0
00900 
00901 #define AR_AHB_MODE                           0x4024
00902 #define AR_AHB_EXACT_WR_EN                    0x00000000
00903 #define AR_AHB_BUF_WR_EN                      0x00000001
00904 #define AR_AHB_EXACT_RD_EN                    0x00000000
00905 #define AR_AHB_CACHELINE_RD_EN                0x00000002
00906 #define AR_AHB_PREFETCH_RD_EN                 0x00000004
00907 #define AR_AHB_PAGE_SIZE_1K                   0x00000000
00908 #define AR_AHB_PAGE_SIZE_2K                   0x00000008
00909 #define AR_AHB_PAGE_SIZE_4K                   0x00000010
00910 #define AR_AHB_CUSTOM_BURST_EN                0x000000C0
00911 #define AR_AHB_CUSTOM_BURST_EN_S              6
00912 #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL    3
00913 
00914 #define AR_INTR_RTC_IRQ                       0x00000001
00915 #define AR_INTR_MAC_IRQ                       0x00000002
00916 #define AR_INTR_EEP_PROT_ACCESS               0x00000004
00917 #define AR_INTR_MAC_AWAKE                     0x00020000
00918 #define AR_INTR_MAC_ASLEEP                    0x00040000
00919 #define AR_INTR_SPURIOUS                      0xFFFFFFFF
00920 
00921 
00922 #define AR_INTR_SYNC_CAUSE                    (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
00923 #define AR_INTR_SYNC_CAUSE_CLR                (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
00924 
00925 
00926 #define AR_INTR_SYNC_ENABLE                   (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
00927 #define AR_INTR_SYNC_ENABLE_GPIO              0xFFFC0000
00928 #define AR_INTR_SYNC_ENABLE_GPIO_S            18
00929 
00930 enum {
00931         AR_INTR_SYNC_RTC_IRQ = 0x00000001,
00932         AR_INTR_SYNC_MAC_IRQ = 0x00000002,
00933         AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004,
00934         AR_INTR_SYNC_APB_TIMEOUT = 0x00000008,
00935         AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010,
00936         AR_INTR_SYNC_HOST1_FATAL = 0x00000020,
00937         AR_INTR_SYNC_HOST1_PERR = 0x00000040,
00938         AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080,
00939         AR_INTR_SYNC_RADM_CPL_EP = 0x00000100,
00940         AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200,
00941         AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400,
00942         AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800,
00943         AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000,
00944         AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000,
00945         AR_INTR_SYNC_PM_ACCESS = 0x00004000,
00946         AR_INTR_SYNC_MAC_AWAKE = 0x00008000,
00947         AR_INTR_SYNC_MAC_ASLEEP = 0x00010000,
00948         AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000,
00949         AR_INTR_SYNC_ALL = 0x0003FFFF,
00950 
00951 
00952         AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL |
00953                                 AR_INTR_SYNC_HOST1_PERR |
00954                                 AR_INTR_SYNC_RADM_CPL_EP |
00955                                 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT |
00956                                 AR_INTR_SYNC_RADM_CPL_TLP_ABORT |
00957                                 AR_INTR_SYNC_RADM_CPL_ECRC_ERR |
00958                                 AR_INTR_SYNC_RADM_CPL_TIMEOUT |
00959                                 AR_INTR_SYNC_LOCAL_TIMEOUT |
00960                                 AR_INTR_SYNC_MAC_SLEEP_ACCESS),
00961 
00962         AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,
00963 
00964 };
00965 
00966 #define AR_INTR_ASYNC_MASK                       (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
00967 #define AR_INTR_ASYNC_MASK_GPIO                  0xFFFC0000
00968 #define AR_INTR_ASYNC_MASK_GPIO_S                18
00969 
00970 #define AR_INTR_SYNC_MASK                        (AR_SREV_9340(ah) ? 0x401c : 0x4034)
00971 #define AR_INTR_SYNC_MASK_GPIO                   0xFFFC0000
00972 #define AR_INTR_SYNC_MASK_GPIO_S                 18
00973 
00974 #define AR_INTR_ASYNC_CAUSE_CLR                  (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
00975 #define AR_INTR_ASYNC_CAUSE                      (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
00976 
00977 #define AR_INTR_ASYNC_ENABLE                     (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
00978 #define AR_INTR_ASYNC_ENABLE_GPIO                0xFFFC0000
00979 #define AR_INTR_ASYNC_ENABLE_GPIO_S              18
00980 
00981 #define AR_PCIE_SERDES                           0x4040
00982 #define AR_PCIE_SERDES2                          0x4044
00983 #define AR_PCIE_PM_CTRL                          (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
00984 #define AR_PCIE_PM_CTRL_ENA                      0x00080000
00985 
00986 #define AR_NUM_GPIO                              14
00987 #define AR928X_NUM_GPIO                          10
00988 #define AR9285_NUM_GPIO                          12
00989 #define AR9287_NUM_GPIO                          11
00990 #define AR9271_NUM_GPIO                          16
00991 #define AR9300_NUM_GPIO                          17
00992 #define AR7010_NUM_GPIO                          16
00993 
00994 #define AR_GPIO_IN_OUT                           (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
00995 #define AR_GPIO_IN_VAL                           0x0FFFC000
00996 #define AR_GPIO_IN_VAL_S                         14
00997 #define AR928X_GPIO_IN_VAL                       0x000FFC00
00998 #define AR928X_GPIO_IN_VAL_S                     10
00999 #define AR9285_GPIO_IN_VAL                       0x00FFF000
01000 #define AR9285_GPIO_IN_VAL_S                     12
01001 #define AR9287_GPIO_IN_VAL                       0x003FF800
01002 #define AR9287_GPIO_IN_VAL_S                     11
01003 #define AR9271_GPIO_IN_VAL                       0xFFFF0000
01004 #define AR9271_GPIO_IN_VAL_S                     16
01005 #define AR7010_GPIO_IN_VAL                       0x0000FFFF
01006 #define AR7010_GPIO_IN_VAL_S                     0
01007 
01008 #define AR_GPIO_IN                               (AR_SREV_9340(ah) ? 0x402c : 0x404c)
01009 #define AR9300_GPIO_IN_VAL                       0x0001FFFF
01010 #define AR9300_GPIO_IN_VAL_S                     0
01011 
01012 #define AR_GPIO_OE_OUT                           (AR_SREV_9340(ah) ? 0x4030 : \
01013                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))
01014 #define AR_GPIO_OE_OUT_DRV                       0x3
01015 #define AR_GPIO_OE_OUT_DRV_NO                    0x0
01016 #define AR_GPIO_OE_OUT_DRV_LOW                   0x1
01017 #define AR_GPIO_OE_OUT_DRV_HI                    0x2
01018 #define AR_GPIO_OE_OUT_DRV_ALL                   0x3
01019 
01020 #define AR7010_GPIO_OE                           0x52000
01021 #define AR7010_GPIO_OE_MASK                      0x1
01022 #define AR7010_GPIO_OE_AS_OUTPUT                 0x0
01023 #define AR7010_GPIO_OE_AS_INPUT                  0x1
01024 #define AR7010_GPIO_IN                           0x52004
01025 #define AR7010_GPIO_OUT                          0x52008
01026 #define AR7010_GPIO_SET                          0x5200C
01027 #define AR7010_GPIO_CLEAR                        0x52010
01028 #define AR7010_GPIO_INT                          0x52014
01029 #define AR7010_GPIO_INT_TYPE                     0x52018
01030 #define AR7010_GPIO_INT_POLARITY                 0x5201C
01031 #define AR7010_GPIO_PENDING                      0x52020
01032 #define AR7010_GPIO_INT_MASK                     0x52024
01033 #define AR7010_GPIO_FUNCTION                     0x52028
01034 
01035 #define AR_GPIO_INTR_POL                         (AR_SREV_9340(ah) ? 0x4038 : \
01036                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))
01037 #define AR_GPIO_INTR_POL_VAL                     0x0001FFFF
01038 #define AR_GPIO_INTR_POL_VAL_S                   0
01039 
01040 #define AR_GPIO_INPUT_EN_VAL                     (AR_SREV_9340(ah) ? 0x403c : \
01041                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))
01042 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF     0x00000004
01043 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S       2
01044 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF    0x00000008
01045 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S      3
01046 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF       0x00000010
01047 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S         4
01048 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF        0x00000080
01049 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S      7
01050 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB      0x00000400
01051 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S    10
01052 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB        0x00001000
01053 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S      12
01054 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB         0x00008000
01055 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S       15
01056 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE        0x00010000
01057 #define AR_GPIO_JTAG_DISABLE                     0x00020000
01058 
01059 #define AR_GPIO_INPUT_MUX1                       (AR_SREV_9340(ah) ? 0x4040 : \
01060                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))
01061 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE             0x000f0000
01062 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S           16
01063 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY           0x00000f00
01064 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S         8
01065 
01066 #define AR_GPIO_INPUT_MUX2                       (AR_SREV_9340(ah) ? 0x4044 : \
01067                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))
01068 #define AR_GPIO_INPUT_MUX2_CLK25                 0x0000000f
01069 #define AR_GPIO_INPUT_MUX2_CLK25_S               0
01070 #define AR_GPIO_INPUT_MUX2_RFSILENT              0x000000f0
01071 #define AR_GPIO_INPUT_MUX2_RFSILENT_S            4
01072 #define AR_GPIO_INPUT_MUX2_RTC_RESET             0x00000f00
01073 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S           8
01074 
01075 #define AR_GPIO_OUTPUT_MUX1                      (AR_SREV_9340(ah) ? 0x4048 : \
01076                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))
01077 #define AR_GPIO_OUTPUT_MUX2                      (AR_SREV_9340(ah) ? 0x404c : \
01078                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))
01079 #define AR_GPIO_OUTPUT_MUX3                      (AR_SREV_9340(ah) ? 0x4050 : \
01080                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))
01081 
01082 #define AR_INPUT_STATE                           (AR_SREV_9340(ah) ? 0x4054 : \
01083                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))
01084 
01085 #define AR_EEPROM_STATUS_DATA                    (AR_SREV_9340(ah) ? 0x40c8 : \
01086                                                   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))
01087 #define AR_EEPROM_STATUS_DATA_VAL                0x0000ffff
01088 #define AR_EEPROM_STATUS_DATA_VAL_S              0
01089 #define AR_EEPROM_STATUS_DATA_BUSY               0x00010000
01090 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS        0x00020000
01091 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS        0x00040000
01092 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS      0x00080000
01093 
01094 #define AR_OBS                  (AR_SREV_9340(ah) ? 0x405c : \
01095                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))
01096 
01097 #define AR_GPIO_PDPU                             (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
01098 
01099 #define AR_PCIE_MSI                             (AR_SREV_9340(ah) ? 0x40d8 : \
01100                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))
01101 #define AR_PCIE_MSI_ENABLE                       0x00000001
01102 
01103 #define AR_INTR_PRIO_SYNC_ENABLE  (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
01104 #define AR_INTR_PRIO_ASYNC_MASK   (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
01105 #define AR_INTR_PRIO_SYNC_MASK    (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
01106 #define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
01107 #define AR_ENT_OTP                0x40d8
01108 #define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
01109 #define AR_ENT_OTP_MPSD         0x00800000
01110 
01111 #define AR_CH0_BB_DPLL1          0x16180
01112 #define AR_CH0_BB_DPLL1_REFDIV   0xF8000000
01113 #define AR_CH0_BB_DPLL1_REFDIV_S 27
01114 #define AR_CH0_BB_DPLL1_NINI     0x07FC0000
01115 #define AR_CH0_BB_DPLL1_NINI_S   18
01116 #define AR_CH0_BB_DPLL1_NFRAC    0x0003FFFF
01117 #define AR_CH0_BB_DPLL1_NFRAC_S  0
01118 
01119 #define AR_CH0_BB_DPLL2              0x16184
01120 #define AR_CH0_BB_DPLL2_LOCAL_PLL       0x40000000
01121 #define AR_CH0_BB_DPLL2_LOCAL_PLL_S     30
01122 #define AR_CH0_DPLL2_KI              0x3C000000
01123 #define AR_CH0_DPLL2_KI_S            26
01124 #define AR_CH0_DPLL2_KD              0x03F80000
01125 #define AR_CH0_DPLL2_KD_S            19
01126 #define AR_CH0_BB_DPLL2_EN_NEGTRIG   0x00040000
01127 #define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18
01128 #define AR_CH0_BB_DPLL2_PLL_PWD      0x00010000
01129 #define AR_CH0_BB_DPLL2_PLL_PWD_S    16
01130 #define AR_CH0_BB_DPLL2_OUTDIV       0x0000E000
01131 #define AR_CH0_BB_DPLL2_OUTDIV_S     13
01132 
01133 #define AR_CH0_BB_DPLL3          0x16188
01134 #define AR_CH0_BB_DPLL3_PHASE_SHIFT     0x3F800000
01135 #define AR_CH0_BB_DPLL3_PHASE_SHIFT_S   23
01136 
01137 #define AR_CH0_DDR_DPLL2         0x16244
01138 #define AR_CH0_DDR_DPLL3         0x16248
01139 #define AR_CH0_DPLL3_PHASE_SHIFT     0x3F800000
01140 #define AR_CH0_DPLL3_PHASE_SHIFT_S   23
01141 #define AR_PHY_CCA_NOM_VAL_2GHZ      -118
01142 
01143 #define AR_RTC_9300_PLL_DIV          0x000003ff
01144 #define AR_RTC_9300_PLL_DIV_S        0
01145 #define AR_RTC_9300_PLL_REFDIV       0x00003C00
01146 #define AR_RTC_9300_PLL_REFDIV_S     10
01147 #define AR_RTC_9300_PLL_CLKSEL       0x0000C000
01148 #define AR_RTC_9300_PLL_CLKSEL_S     14
01149 
01150 #define AR_RTC_9160_PLL_DIV     0x000003ff
01151 #define AR_RTC_9160_PLL_DIV_S   0
01152 #define AR_RTC_9160_PLL_REFDIV  0x00003C00
01153 #define AR_RTC_9160_PLL_REFDIV_S 10
01154 #define AR_RTC_9160_PLL_CLKSEL  0x0000C000
01155 #define AR_RTC_9160_PLL_CLKSEL_S 14
01156 
01157 #define AR_RTC_BASE             0x00020000
01158 #define AR_RTC_RC \
01159         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)
01160 #define AR_RTC_RC_M             0x00000003
01161 #define AR_RTC_RC_MAC_WARM      0x00000001
01162 #define AR_RTC_RC_MAC_COLD      0x00000002
01163 #define AR_RTC_RC_COLD_RESET    0x00000004
01164 #define AR_RTC_RC_WARM_RESET    0x00000008
01165 
01166 /* Crystal Control */
01167 #define AR_RTC_XTAL_CONTROL     0x7004
01168 
01169 /* Reg Control 0 */
01170 #define AR_RTC_REG_CONTROL0     0x7008
01171 
01172 /* Reg Control 1 */
01173 #define AR_RTC_REG_CONTROL1     0x700c
01174 #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM       0x00000001
01175 
01176 #define AR_RTC_PLL_CONTROL \
01177         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
01178 
01179 #define AR_RTC_PLL_CONTROL2     0x703c
01180 
01181 #define AR_RTC_PLL_DIV          0x0000001f
01182 #define AR_RTC_PLL_DIV_S        0
01183 #define AR_RTC_PLL_DIV2         0x00000020
01184 #define AR_RTC_PLL_REFDIV_5     0x000000c0
01185 #define AR_RTC_PLL_CLKSEL       0x00000300
01186 #define AR_RTC_PLL_CLKSEL_S     8
01187 #define AR_RTC_PLL_BYPASS       0x00010000
01188 
01189 #define PLL3 0x16188
01190 #define PLL3_DO_MEAS_MASK 0x40000000
01191 #define PLL4 0x1618c
01192 #define PLL4_MEAS_DONE    0x8
01193 #define SQSUM_DVC_MASK 0x007ffff8
01194 
01195 #define AR_RTC_RESET \
01196         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
01197 #define AR_RTC_RESET_EN         (0x00000001)
01198 
01199 #define AR_RTC_STATUS \
01200         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)
01201 
01202 #define AR_RTC_STATUS_M \
01203         ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)
01204 
01205 #define AR_RTC_PM_STATUS_M      0x0000000f
01206 
01207 #define AR_RTC_STATUS_SHUTDOWN  0x00000001
01208 #define AR_RTC_STATUS_ON        0x00000002
01209 #define AR_RTC_STATUS_SLEEP     0x00000004
01210 #define AR_RTC_STATUS_WAKEUP    0x00000008
01211 
01212 #define AR_RTC_SLEEP_CLK \
01213         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
01214 #define AR_RTC_FORCE_DERIVED_CLK    0x2
01215 #define AR_RTC_FORCE_SWREG_PRD      0x00000004
01216 
01217 #define AR_RTC_FORCE_WAKE \
01218         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
01219 #define AR_RTC_FORCE_WAKE_EN        0x00000001
01220 #define AR_RTC_FORCE_WAKE_ON_INT    0x00000002
01221 
01222 
01223 #define AR_RTC_INTR_CAUSE \
01224         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)
01225 
01226 #define AR_RTC_INTR_ENABLE \
01227         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)
01228 
01229 #define AR_RTC_INTR_MASK \
01230         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)
01231 
01232 /* RTC_DERIVED_* - only for AR9100 */
01233 
01234 #define AR_RTC_DERIVED_CLK \
01235         (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
01236 #define AR_RTC_DERIVED_CLK_PERIOD    0x0000fffe
01237 #define AR_RTC_DERIVED_CLK_PERIOD_S  1
01238 
01239 #define AR_SEQ_MASK     0x8060
01240 
01241 #define AR_AN_RF2G1_CH0         0x7810
01242 #define AR_AN_RF2G1_CH0_OB      0x03800000
01243 #define AR_AN_RF2G1_CH0_OB_S    23
01244 #define AR_AN_RF2G1_CH0_DB      0x1C000000
01245 #define AR_AN_RF2G1_CH0_DB_S    26
01246 
01247 #define AR_AN_RF5G1_CH0         0x7818
01248 #define AR_AN_RF5G1_CH0_OB5     0x00070000
01249 #define AR_AN_RF5G1_CH0_OB5_S   16
01250 #define AR_AN_RF5G1_CH0_DB5     0x00380000
01251 #define AR_AN_RF5G1_CH0_DB5_S   19
01252 
01253 #define AR_AN_RF2G1_CH1         0x7834
01254 #define AR_AN_RF2G1_CH1_OB      0x03800000
01255 #define AR_AN_RF2G1_CH1_OB_S    23
01256 #define AR_AN_RF2G1_CH1_DB      0x1C000000
01257 #define AR_AN_RF2G1_CH1_DB_S    26
01258 
01259 #define AR_AN_RF5G1_CH1         0x783C
01260 #define AR_AN_RF5G1_CH1_OB5     0x00070000
01261 #define AR_AN_RF5G1_CH1_OB5_S   16
01262 #define AR_AN_RF5G1_CH1_DB5     0x00380000
01263 #define AR_AN_RF5G1_CH1_DB5_S   19
01264 
01265 #define AR_AN_TOP1                  0x7890
01266 #define AR_AN_TOP1_DACIPMODE        0x00040000
01267 #define AR_AN_TOP1_DACIPMODE_S      18
01268 
01269 #define AR_AN_TOP2                  0x7894
01270 #define AR_AN_TOP2_XPABIAS_LVL      0xC0000000
01271 #define AR_AN_TOP2_XPABIAS_LVL_S    30
01272 #define AR_AN_TOP2_LOCALBIAS        0x00200000
01273 #define AR_AN_TOP2_LOCALBIAS_S      21
01274 #define AR_AN_TOP2_PWDCLKIND        0x00400000
01275 #define AR_AN_TOP2_PWDCLKIND_S      22
01276 
01277 #define AR_AN_SYNTH9            0x7868
01278 #define AR_AN_SYNTH9_REFDIVA    0xf8000000
01279 #define AR_AN_SYNTH9_REFDIVA_S  27
01280 
01281 #define AR9285_AN_RF2G1              0x7820
01282 #define AR9285_AN_RF2G1_ENPACAL      0x00000800
01283 #define AR9285_AN_RF2G1_ENPACAL_S    11
01284 #define AR9285_AN_RF2G1_PDPADRV1     0x02000000
01285 #define AR9285_AN_RF2G1_PDPADRV1_S   25
01286 #define AR9285_AN_RF2G1_PDPADRV2     0x01000000
01287 #define AR9285_AN_RF2G1_PDPADRV2_S   24
01288 #define AR9285_AN_RF2G1_PDPAOUT      0x00800000
01289 #define AR9285_AN_RF2G1_PDPAOUT_S    23
01290 
01291 
01292 #define AR9285_AN_RF2G2              0x7824
01293 #define AR9285_AN_RF2G2_OFFCAL       0x00001000
01294 #define AR9285_AN_RF2G2_OFFCAL_S     12
01295 
01296 #define AR9285_AN_RF2G3             0x7828
01297 #define AR9285_AN_RF2G3_PDVCCOMP    0x02000000
01298 #define AR9285_AN_RF2G3_PDVCCOMP_S  25
01299 #define AR9285_AN_RF2G3_OB_0    0x00E00000
01300 #define AR9285_AN_RF2G3_OB_0_S    21
01301 #define AR9285_AN_RF2G3_OB_1    0x001C0000
01302 #define AR9285_AN_RF2G3_OB_1_S    18
01303 #define AR9285_AN_RF2G3_OB_2    0x00038000
01304 #define AR9285_AN_RF2G3_OB_2_S    15
01305 #define AR9285_AN_RF2G3_OB_3    0x00007000
01306 #define AR9285_AN_RF2G3_OB_3_S    12
01307 #define AR9285_AN_RF2G3_OB_4    0x00000E00
01308 #define AR9285_AN_RF2G3_OB_4_S    9
01309 
01310 #define AR9285_AN_RF2G3_DB1_0    0x000001C0
01311 #define AR9285_AN_RF2G3_DB1_0_S    6
01312 #define AR9285_AN_RF2G3_DB1_1    0x00000038
01313 #define AR9285_AN_RF2G3_DB1_1_S    3
01314 #define AR9285_AN_RF2G3_DB1_2    0x00000007
01315 #define AR9285_AN_RF2G3_DB1_2_S    0
01316 #define AR9285_AN_RF2G4         0x782C
01317 #define AR9285_AN_RF2G4_DB1_3    0xE0000000
01318 #define AR9285_AN_RF2G4_DB1_3_S    29
01319 #define AR9285_AN_RF2G4_DB1_4    0x1C000000
01320 #define AR9285_AN_RF2G4_DB1_4_S    26
01321 
01322 #define AR9285_AN_RF2G4_DB2_0    0x03800000
01323 #define AR9285_AN_RF2G4_DB2_0_S    23
01324 #define AR9285_AN_RF2G4_DB2_1    0x00700000
01325 #define AR9285_AN_RF2G4_DB2_1_S    20
01326 #define AR9285_AN_RF2G4_DB2_2    0x000E0000
01327 #define AR9285_AN_RF2G4_DB2_2_S    17
01328 #define AR9285_AN_RF2G4_DB2_3    0x0001C000
01329 #define AR9285_AN_RF2G4_DB2_3_S    14
01330 #define AR9285_AN_RF2G4_DB2_4    0x00003800
01331 #define AR9285_AN_RF2G4_DB2_4_S    11
01332 
01333 #define AR9285_RF2G5                    0x7830
01334 #define AR9285_RF2G5_IC50TX             0xfffff8ff
01335 #define AR9285_RF2G5_IC50TX_SET         0x00000400
01336 #define AR9285_RF2G5_IC50TX_XE_SET      0x00000500
01337 #define AR9285_RF2G5_IC50TX_CLEAR       0x00000700
01338 #define AR9285_RF2G5_IC50TX_CLEAR_S     8
01339 
01340 /* AR9271 : 0x7828, 0x782c different setting from AR9285 */
01341 #define AR9271_AN_RF2G3_OB_cck          0x001C0000
01342 #define AR9271_AN_RF2G3_OB_cck_S        18
01343 #define AR9271_AN_RF2G3_OB_psk          0x00038000
01344 #define AR9271_AN_RF2G3_OB_psk_S        15
01345 #define AR9271_AN_RF2G3_OB_qam          0x00007000
01346 #define AR9271_AN_RF2G3_OB_qam_S        12
01347 
01348 #define AR9271_AN_RF2G3_DB_1            0x00E00000
01349 #define AR9271_AN_RF2G3_DB_1_S          21
01350 
01351 #define AR9271_AN_RF2G3_CCOMP           0xFFF
01352 #define AR9271_AN_RF2G3_CCOMP_S         0
01353 
01354 #define AR9271_AN_RF2G4_DB_2            0xE0000000
01355 #define AR9271_AN_RF2G4_DB_2_S          29
01356 
01357 #define AR9285_AN_RF2G6                 0x7834
01358 #define AR9285_AN_RF2G6_CCOMP           0x00007800
01359 #define AR9285_AN_RF2G6_CCOMP_S         11
01360 #define AR9285_AN_RF2G6_OFFS            0x03f00000
01361 #define AR9285_AN_RF2G6_OFFS_S          20
01362 
01363 #define AR9271_AN_RF2G6_OFFS            0x07f00000
01364 #define AR9271_AN_RF2G6_OFFS_S            20
01365 
01366 #define AR9285_AN_RF2G7                 0x7838
01367 #define AR9285_AN_RF2G7_PWDDB           0x00000002
01368 #define AR9285_AN_RF2G7_PWDDB_S         1
01369 #define AR9285_AN_RF2G7_PADRVGN2TAB0    0xE0000000
01370 #define AR9285_AN_RF2G7_PADRVGN2TAB0_S  29
01371 
01372 #define AR9285_AN_RF2G8                  0x783C
01373 #define AR9285_AN_RF2G8_PADRVGN2TAB0     0x0001C000
01374 #define AR9285_AN_RF2G8_PADRVGN2TAB0_S   14
01375 
01376 
01377 #define AR9285_AN_RF2G9          0x7840
01378 #define AR9285_AN_RXTXBB1              0x7854
01379 #define AR9285_AN_RXTXBB1_PDRXTXBB1    0x00000020
01380 #define AR9285_AN_RXTXBB1_PDRXTXBB1_S  5
01381 #define AR9285_AN_RXTXBB1_PDV2I        0x00000080
01382 #define AR9285_AN_RXTXBB1_PDV2I_S      7
01383 #define AR9285_AN_RXTXBB1_PDDACIF      0x00000100
01384 #define AR9285_AN_RXTXBB1_PDDACIF_S    8
01385 #define AR9285_AN_RXTXBB1_SPARE9       0x00000001
01386 #define AR9285_AN_RXTXBB1_SPARE9_S     0
01387 
01388 #define AR9285_AN_TOP2           0x7868
01389 
01390 #define AR9285_AN_TOP3                  0x786c
01391 #define AR9285_AN_TOP3_XPABIAS_LVL      0x0000000C
01392 #define AR9285_AN_TOP3_XPABIAS_LVL_S    2
01393 #define AR9285_AN_TOP3_PWDDAC           0x00800000
01394 #define AR9285_AN_TOP3_PWDDAC_S    23
01395 
01396 #define AR9285_AN_TOP4           0x7870
01397 #define AR9285_AN_TOP4_DEFAULT   0x10142c00
01398 
01399 #define AR9287_AN_RF2G3_CH0             0x7808
01400 #define AR9287_AN_RF2G3_CH1             0x785c
01401 #define AR9287_AN_RF2G3_DB1             0xE0000000
01402 #define AR9287_AN_RF2G3_DB1_S           29
01403 #define AR9287_AN_RF2G3_DB2             0x1C000000
01404 #define AR9287_AN_RF2G3_DB2_S           26
01405 #define AR9287_AN_RF2G3_OB_CCK          0x03800000
01406 #define AR9287_AN_RF2G3_OB_CCK_S        23
01407 #define AR9287_AN_RF2G3_OB_PSK          0x00700000
01408 #define AR9287_AN_RF2G3_OB_PSK_S        20
01409 #define AR9287_AN_RF2G3_OB_QAM          0x000E0000
01410 #define AR9287_AN_RF2G3_OB_QAM_S        17
01411 #define AR9287_AN_RF2G3_OB_PAL_OFF      0x0001C000
01412 #define AR9287_AN_RF2G3_OB_PAL_OFF_S    14
01413 
01414 #define AR9287_AN_TXPC0                 0x7898
01415 #define AR9287_AN_TXPC0_TXPCMODE        0x0000C000
01416 #define AR9287_AN_TXPC0_TXPCMODE_S      14
01417 #define AR9287_AN_TXPC0_TXPCMODE_NORMAL    0
01418 #define AR9287_AN_TXPC0_TXPCMODE_TEST      1
01419 #define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2
01420 #define AR9287_AN_TXPC0_TXPCMODE_ATBTEST   3
01421 
01422 #define AR9287_AN_TOP2                  0x78b4
01423 #define AR9287_AN_TOP2_XPABIAS_LVL      0xC0000000
01424 #define AR9287_AN_TOP2_XPABIAS_LVL_S    30
01425 
01426 /* AR9271 specific stuff */
01427 #define AR9271_RESET_POWER_DOWN_CONTROL         0x50044
01428 #define AR9271_RADIO_RF_RST                     0x20
01429 #define AR9271_GATE_MAC_CTL                     0x4000
01430 
01431 #define AR_STA_ID0                 0x8000
01432 #define AR_STA_ID1                 0x8004
01433 #define AR_STA_ID1_SADH_MASK       0x0000FFFF
01434 #define AR_STA_ID1_STA_AP          0x00010000
01435 #define AR_STA_ID1_ADHOC           0x00020000
01436 #define AR_STA_ID1_PWR_SAV         0x00040000
01437 #define AR_STA_ID1_KSRCHDIS        0x00080000
01438 #define AR_STA_ID1_PCF             0x00100000
01439 #define AR_STA_ID1_USE_DEFANT      0x00200000
01440 #define AR_STA_ID1_DEFANT_UPDATE   0x00400000
01441 #define AR_STA_ID1_AR9100_BA_FIX   0x00400000
01442 #define AR_STA_ID1_RTS_USE_DEF     0x00800000
01443 #define AR_STA_ID1_ACKCTS_6MB      0x01000000
01444 #define AR_STA_ID1_BASE_RATE_11B   0x02000000
01445 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000
01446 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000
01447 #define AR_STA_ID1_KSRCH_MODE      0x10000000
01448 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000
01449 #define AR_STA_ID1_CBCIV_ENDIAN    0x40000000
01450 #define AR_STA_ID1_MCAST_KSRCH     0x80000000
01451 
01452 #define AR_BSS_ID0          0x8008
01453 #define AR_BSS_ID1          0x800C
01454 #define AR_BSS_ID1_U16       0x0000FFFF
01455 #define AR_BSS_ID1_AID       0x07FF0000
01456 #define AR_BSS_ID1_AID_S     16
01457 
01458 #define AR_BCN_RSSI_AVE      0x8010
01459 #define AR_BCN_RSSI_AVE_MASK 0x00000FFF
01460 
01461 #define AR_TIME_OUT         0x8014
01462 #define AR_TIME_OUT_ACK      0x00003FFF
01463 #define AR_TIME_OUT_ACK_S    0
01464 #define AR_TIME_OUT_CTS      0x3FFF0000
01465 #define AR_TIME_OUT_CTS_S    16
01466 #define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR    0x16001D56
01467 
01468 #define AR_RSSI_THR          0x8018
01469 #define AR_RSSI_THR_MASK     0x000000FF
01470 #define AR_RSSI_THR_BM_THR   0x0000FF00
01471 #define AR_RSSI_THR_BM_THR_S 8
01472 #define AR_RSSI_BCN_WEIGHT   0x1F000000
01473 #define AR_RSSI_BCN_WEIGHT_S 24
01474 #define AR_RSSI_BCN_RSSI_RST 0x20000000
01475 
01476 #define AR_USEC              0x801c
01477 #define AR_USEC_USEC         0x0000007F
01478 #define AR_USEC_TX_LAT       0x007FC000
01479 #define AR_USEC_TX_LAT_S     14
01480 #define AR_USEC_RX_LAT       0x1F800000
01481 #define AR_USEC_RX_LAT_S     23
01482 #define AR_USEC_ASYNC_FIFO_DUR    0x12e00074
01483 
01484 #define AR_RESET_TSF        0x8020
01485 #define AR_RESET_TSF_ONCE   0x01000000
01486 
01487 #define AR_MAX_CFP_DUR      0x8038
01488 #define AR_CFP_VAL          0x0000FFFF
01489 
01490 #define AR_RX_FILTER        0x803C
01491 
01492 #define AR_MCAST_FIL0       0x8040
01493 #define AR_MCAST_FIL1       0x8044
01494 
01495 /*
01496  * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes.
01497  *
01498  * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with
01499  * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down
01500  * receive. The force RX abort bit will kill any frame which is currently being
01501  * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS)
01502  * will prevent any new frames from getting started.
01503  */
01504 #define AR_DIAG_SW                  0x8048
01505 #define AR_DIAG_CACHE_ACK           0x00000001
01506 #define AR_DIAG_ACK_DIS             0x00000002
01507 #define AR_DIAG_CTS_DIS             0x00000004
01508 #define AR_DIAG_ENCRYPT_DIS         0x00000008
01509 #define AR_DIAG_DECRYPT_DIS         0x00000010
01510 #define AR_DIAG_RX_DIS              0x00000020 /* RX block */
01511 #define AR_DIAG_LOOP_BACK           0x00000040
01512 #define AR_DIAG_CORR_FCS            0x00000080
01513 #define AR_DIAG_CHAN_INFO           0x00000100
01514 #define AR_DIAG_SCRAM_SEED          0x0001FE00
01515 #define AR_DIAG_SCRAM_SEED_S        8
01516 #define AR_DIAG_FRAME_NV0           0x00020000
01517 #define AR_DIAG_OBS_PT_SEL1         0x000C0000
01518 #define AR_DIAG_OBS_PT_SEL1_S       18
01519 #define AR_DIAG_FORCE_RX_CLEAR      0x00100000 /* force rx_clear high */
01520 #define AR_DIAG_IGNORE_VIRT_CS      0x00200000
01521 #define AR_DIAG_FORCE_CH_IDLE_HIGH  0x00400000
01522 #define AR_DIAG_EIFS_CTRL_ENA       0x00800000
01523 #define AR_DIAG_DUAL_CHAIN_INFO     0x01000000
01524 #define AR_DIAG_RX_ABORT            0x02000000 /* Force RX abort */
01525 #define AR_DIAG_SATURATE_CYCLE_CNT  0x04000000
01526 #define AR_DIAG_OBS_PT_SEL2         0x08000000
01527 #define AR_DIAG_RX_CLEAR_CTL_LOW    0x10000000
01528 #define AR_DIAG_RX_CLEAR_EXT_LOW    0x20000000
01529 
01530 #define AR_TSF_L32          0x804c
01531 #define AR_TSF_U32          0x8050
01532 
01533 #define AR_TST_ADDAC        0x8054
01534 #define AR_DEF_ANTENNA      0x8058
01535 
01536 #define AR_AES_MUTE_MASK0       0x805c
01537 #define AR_AES_MUTE_MASK0_FC    0x0000FFFF
01538 #define AR_AES_MUTE_MASK0_QOS   0xFFFF0000
01539 #define AR_AES_MUTE_MASK0_QOS_S 16
01540 
01541 #define AR_AES_MUTE_MASK1       0x8060
01542 #define AR_AES_MUTE_MASK1_SEQ   0x0000FFFF
01543 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000
01544 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16
01545 
01546 #define AR_GATED_CLKS       0x8064
01547 #define AR_GATED_CLKS_TX    0x00000002
01548 #define AR_GATED_CLKS_RX    0x00000004
01549 #define AR_GATED_CLKS_REG   0x00000008
01550 
01551 #define AR_OBS_BUS_CTRL     0x8068
01552 #define AR_OBS_BUS_SEL_1    0x00040000
01553 #define AR_OBS_BUS_SEL_2    0x00080000
01554 #define AR_OBS_BUS_SEL_3    0x000C0000
01555 #define AR_OBS_BUS_SEL_4    0x08040000
01556 #define AR_OBS_BUS_SEL_5    0x08080000
01557 
01558 #define AR_OBS_BUS_1               0x806c
01559 #define AR_OBS_BUS_1_PCU           0x00000001
01560 #define AR_OBS_BUS_1_RX_END        0x00000002
01561 #define AR_OBS_BUS_1_RX_WEP        0x00000004
01562 #define AR_OBS_BUS_1_RX_BEACON     0x00000008
01563 #define AR_OBS_BUS_1_RX_FILTER     0x00000010
01564 #define AR_OBS_BUS_1_TX_HCF        0x00000020
01565 #define AR_OBS_BUS_1_QUIET_TIME    0x00000040
01566 #define AR_OBS_BUS_1_CHAN_IDLE     0x00000080
01567 #define AR_OBS_BUS_1_TX_HOLD       0x00000100
01568 #define AR_OBS_BUS_1_TX_FRAME      0x00000200
01569 #define AR_OBS_BUS_1_RX_FRAME      0x00000400
01570 #define AR_OBS_BUS_1_RX_CLEAR      0x00000800
01571 #define AR_OBS_BUS_1_WEP_STATE     0x0003F000
01572 #define AR_OBS_BUS_1_WEP_STATE_S   12
01573 #define AR_OBS_BUS_1_RX_STATE      0x01F00000
01574 #define AR_OBS_BUS_1_RX_STATE_S    20
01575 #define AR_OBS_BUS_1_TX_STATE      0x7E000000
01576 #define AR_OBS_BUS_1_TX_STATE_S    25
01577 
01578 #define AR_LAST_TSTP        0x8080
01579 #define AR_NAV              0x8084
01580 #define AR_RTS_OK           0x8088
01581 #define AR_RTS_FAIL         0x808c
01582 #define AR_ACK_FAIL         0x8090
01583 #define AR_FCS_FAIL         0x8094
01584 #define AR_BEACON_CNT       0x8098
01585 
01586 #define AR_SLEEP1               0x80d4
01587 #define AR_SLEEP1_ASSUME_DTIM   0x00080000
01588 #define AR_SLEEP1_CAB_TIMEOUT   0xFFE00000
01589 #define AR_SLEEP1_CAB_TIMEOUT_S 21
01590 
01591 #define AR_SLEEP2                   0x80d8
01592 #define AR_SLEEP2_BEACON_TIMEOUT    0xFFE00000
01593 #define AR_SLEEP2_BEACON_TIMEOUT_S  21
01594 
01595 #define AR_TPC                 0x80e8
01596 #define AR_TPC_ACK             0x0000003f
01597 #define AR_TPC_ACK_S           0x00
01598 #define AR_TPC_CTS             0x00003f00
01599 #define AR_TPC_CTS_S           0x08
01600 #define AR_TPC_CHIRP           0x003f0000
01601 #define AR_TPC_CHIRP_S         0x16
01602 
01603 #define AR_QUIET1          0x80fc
01604 #define AR_QUIET1_NEXT_QUIET_S         0
01605 #define AR_QUIET1_NEXT_QUIET_M         0x0000ffff
01606 #define AR_QUIET1_QUIET_ENABLE         0x00010000
01607 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000
01608 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17
01609 #define AR_QUIET2          0x8100
01610 #define AR_QUIET2_QUIET_PERIOD_S       0
01611 #define AR_QUIET2_QUIET_PERIOD_M       0x0000ffff
01612 #define AR_QUIET2_QUIET_DUR_S     16
01613 #define AR_QUIET2_QUIET_DUR       0xffff0000
01614 
01615 #define AR_TSF_PARM        0x8104
01616 #define AR_TSF_INCREMENT_M     0x000000ff
01617 #define AR_TSF_INCREMENT_S     0x00
01618 
01619 #define AR_QOS_NO_ACK              0x8108
01620 #define AR_QOS_NO_ACK_TWO_BIT      0x0000000f
01621 #define AR_QOS_NO_ACK_TWO_BIT_S    0
01622 #define AR_QOS_NO_ACK_BIT_OFF      0x00000070
01623 #define AR_QOS_NO_ACK_BIT_OFF_S    4
01624 #define AR_QOS_NO_ACK_BYTE_OFF     0x00000180
01625 #define AR_QOS_NO_ACK_BYTE_OFF_S   7
01626 
01627 #define AR_PHY_ERR         0x810c
01628 
01629 #define AR_PHY_ERR_DCHIRP      0x00000008
01630 #define AR_PHY_ERR_RADAR       0x00000020
01631 #define AR_PHY_ERR_OFDM_TIMING 0x00020000
01632 #define AR_PHY_ERR_CCK_TIMING  0x02000000
01633 
01634 #define AR_RXFIFO_CFG          0x8114
01635 
01636 
01637 #define AR_MIC_QOS_CONTROL 0x8118
01638 #define AR_MIC_QOS_SELECT  0x811c
01639 
01640 #define AR_PCU_MISC                0x8120
01641 #define AR_PCU_FORCE_BSSID_MATCH   0x00000001
01642 #define AR_PCU_MIC_NEW_LOC_ENA     0x00000004
01643 #define AR_PCU_TX_ADD_TSF          0x00000008
01644 #define AR_PCU_CCK_SIFS_MODE       0x00000010
01645 #define AR_PCU_RX_ANT_UPDT         0x00000800
01646 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000
01647 #define AR_PCU_MISS_BCN_IN_SLEEP   0x00004000
01648 #define AR_PCU_BUG_12306_FIX_ENA   0x00020000
01649 #define AR_PCU_FORCE_QUIET_COLL    0x00040000
01650 #define AR_PCU_TBTT_PROTECT        0x00200000
01651 #define AR_PCU_CLEAR_VMF           0x01000000
01652 #define AR_PCU_CLEAR_BA_VALID      0x04000000
01653 #define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000
01654 
01655 #define AR_PCU_BT_ANT_PREVENT_RX   0x00100000
01656 #define AR_PCU_BT_ANT_PREVENT_RX_S 20
01657 
01658 #define AR_FILT_OFDM           0x8124
01659 #define AR_FILT_OFDM_COUNT     0x00FFFFFF
01660 
01661 #define AR_FILT_CCK            0x8128
01662 #define AR_FILT_CCK_COUNT      0x00FFFFFF
01663 
01664 #define AR_PHY_ERR_1           0x812c
01665 #define AR_PHY_ERR_1_COUNT     0x00FFFFFF
01666 #define AR_PHY_ERR_MASK_1      0x8130
01667 
01668 #define AR_PHY_ERR_2           0x8134
01669 #define AR_PHY_ERR_2_COUNT     0x00FFFFFF
01670 #define AR_PHY_ERR_MASK_2      0x8138
01671 
01672 #define AR_PHY_COUNTMAX        (3 << 22)
01673 #define AR_MIBCNT_INTRMASK     (3 << 22)
01674 
01675 #define AR_TSFOOR_THRESHOLD       0x813c
01676 #define AR_TSFOOR_THRESHOLD_VAL   0x0000FFFF
01677 
01678 #define AR_PHY_ERR_EIFS_MASK   0x8144
01679 
01680 #define AR_PHY_ERR_3           0x8168
01681 #define AR_PHY_ERR_3_COUNT     0x00FFFFFF
01682 #define AR_PHY_ERR_MASK_3      0x816c
01683 
01684 #define AR_BT_COEX_MODE            0x8170
01685 #define AR_BT_TIME_EXTEND          0x000000ff
01686 #define AR_BT_TIME_EXTEND_S        0
01687 #define AR_BT_TXSTATE_EXTEND       0x00000100
01688 #define AR_BT_TXSTATE_EXTEND_S     8
01689 #define AR_BT_TX_FRAME_EXTEND      0x00000200
01690 #define AR_BT_TX_FRAME_EXTEND_S    9
01691 #define AR_BT_MODE                 0x00000c00
01692 #define AR_BT_MODE_S               10
01693 #define AR_BT_QUIET                0x00001000
01694 #define AR_BT_QUIET_S              12
01695 #define AR_BT_QCU_THRESH           0x0001e000
01696 #define AR_BT_QCU_THRESH_S         13
01697 #define AR_BT_RX_CLEAR_POLARITY    0x00020000
01698 #define AR_BT_RX_CLEAR_POLARITY_S  17
01699 #define AR_BT_PRIORITY_TIME        0x00fc0000
01700 #define AR_BT_PRIORITY_TIME_S      18
01701 #define AR_BT_FIRST_SLOT_TIME      0xff000000
01702 #define AR_BT_FIRST_SLOT_TIME_S    24
01703 
01704 #define AR_BT_COEX_WEIGHT          0x8174
01705 #define AR_BT_COEX_WGHT            0xff55
01706 #define AR_STOMP_ALL_WLAN_WGHT     0xfcfc
01707 #define AR_STOMP_LOW_WLAN_WGHT     0xa8a8
01708 #define AR_STOMP_NONE_WLAN_WGHT    0x0000
01709 #define AR_BTCOEX_BT_WGHT          0x0000ffff
01710 #define AR_BTCOEX_BT_WGHT_S        0
01711 #define AR_BTCOEX_WL_WGHT          0xffff0000
01712 #define AR_BTCOEX_WL_WGHT_S        16
01713 
01714 #define AR_BT_COEX_WL_WEIGHTS0     0x8174
01715 #define AR_BT_COEX_WL_WEIGHTS1     0x81c4
01716 
01717 #define AR_BT_COEX_BT_WEIGHTS0     0x83ac
01718 #define AR_BT_COEX_BT_WEIGHTS1     0x83b0
01719 #define AR_BT_COEX_BT_WEIGHTS2     0x83b4
01720 #define AR_BT_COEX_BT_WEIGHTS3     0x83b8
01721 
01722 #define AR9300_BT_WGHT                     0xcccc4444
01723 #define AR9300_STOMP_ALL_WLAN_WGHT0        0xfffffff0
01724 #define AR9300_STOMP_ALL_WLAN_WGHT1        0xfffffff0
01725 #define AR9300_STOMP_LOW_WLAN_WGHT0        0x88888880
01726 #define AR9300_STOMP_LOW_WLAN_WGHT1        0x88888880
01727 #define AR9300_STOMP_NONE_WLAN_WGHT0       0x00000000
01728 #define AR9300_STOMP_NONE_WLAN_WGHT1       0x00000000
01729 
01730 #define AR_BT_COEX_MODE2           0x817c
01731 #define AR_BT_BCN_MISS_THRESH      0x000000ff
01732 #define AR_BT_BCN_MISS_THRESH_S    0
01733 #define AR_BT_BCN_MISS_CNT         0x0000ff00
01734 #define AR_BT_BCN_MISS_CNT_S       8
01735 #define AR_BT_HOLD_RX_CLEAR        0x00010000
01736 #define AR_BT_HOLD_RX_CLEAR_S      16
01737 #define AR_BT_DISABLE_BT_ANT       0x00100000
01738 #define AR_BT_DISABLE_BT_ANT_S     20
01739 
01740 #define AR_TXSIFS              0x81d0
01741 #define AR_TXSIFS_TIME         0x000000FF
01742 #define AR_TXSIFS_TX_LATENCY   0x00000F00
01743 #define AR_TXSIFS_TX_LATENCY_S 8
01744 #define AR_TXSIFS_ACK_SHIFT    0x00007000
01745 #define AR_TXSIFS_ACK_SHIFT_S  12
01746 
01747 #define AR_TXOP_X          0x81ec
01748 #define AR_TXOP_X_VAL      0x000000FF
01749 
01750 
01751 #define AR_TXOP_0_3    0x81f0
01752 #define AR_TXOP_4_7    0x81f4
01753 #define AR_TXOP_8_11   0x81f8
01754 #define AR_TXOP_12_15  0x81fc
01755 
01756 #define AR_NEXT_NDP2_TIMER                  0x8180
01757 #define AR_FIRST_NDP_TIMER                  7
01758 #define AR_NDP2_PERIOD                      0x81a0
01759 #define AR_NDP2_TIMER_MODE                  0x81c0
01760 
01761 #define AR_GEN_TIMERS(_i)                   (0x8200 + ((_i) << 2))
01762 #define AR_NEXT_TBTT_TIMER                  AR_GEN_TIMERS(0)
01763 #define AR_NEXT_DMA_BEACON_ALERT            AR_GEN_TIMERS(1)
01764 #define AR_NEXT_SWBA                        AR_GEN_TIMERS(2)
01765 #define AR_NEXT_CFP                         AR_GEN_TIMERS(2)
01766 #define AR_NEXT_HCF                         AR_GEN_TIMERS(3)
01767 #define AR_NEXT_TIM                         AR_GEN_TIMERS(4)
01768 #define AR_NEXT_DTIM                        AR_GEN_TIMERS(5)
01769 #define AR_NEXT_QUIET_TIMER                 AR_GEN_TIMERS(6)
01770 #define AR_NEXT_NDP_TIMER                   AR_GEN_TIMERS(7)
01771 
01772 #define AR_BEACON_PERIOD                    AR_GEN_TIMERS(8)
01773 #define AR_DMA_BEACON_PERIOD                AR_GEN_TIMERS(9)
01774 #define AR_SWBA_PERIOD                      AR_GEN_TIMERS(10)
01775 #define AR_HCF_PERIOD                       AR_GEN_TIMERS(11)
01776 #define AR_TIM_PERIOD                       AR_GEN_TIMERS(12)
01777 #define AR_DTIM_PERIOD                      AR_GEN_TIMERS(13)
01778 #define AR_QUIET_PERIOD                     AR_GEN_TIMERS(14)
01779 #define AR_NDP_PERIOD                       AR_GEN_TIMERS(15)
01780 
01781 #define AR_TIMER_MODE                       0x8240
01782 #define AR_TBTT_TIMER_EN                    0x00000001
01783 #define AR_DBA_TIMER_EN                     0x00000002
01784 #define AR_SWBA_TIMER_EN                    0x00000004
01785 #define AR_HCF_TIMER_EN                     0x00000008
01786 #define AR_TIM_TIMER_EN                     0x00000010
01787 #define AR_DTIM_TIMER_EN                    0x00000020
01788 #define AR_QUIET_TIMER_EN                   0x00000040
01789 #define AR_NDP_TIMER_EN                     0x00000080
01790 #define AR_TIMER_OVERFLOW_INDEX             0x00000700
01791 #define AR_TIMER_OVERFLOW_INDEX_S           8
01792 #define AR_TIMER_THRESH                     0xFFFFF000
01793 #define AR_TIMER_THRESH_S                   12
01794 
01795 #define AR_SLP32_MODE                  0x8244
01796 #define AR_SLP32_HALF_CLK_LATENCY      0x000FFFFF
01797 #define AR_SLP32_ENA                   0x00100000
01798 #define AR_SLP32_TSF_WRITE_STATUS      0x00200000
01799 
01800 #define AR_SLP32_WAKE              0x8248
01801 #define AR_SLP32_WAKE_XTL_TIME     0x0000FFFF
01802 
01803 #define AR_SLP32_INC               0x824c
01804 #define AR_SLP32_TST_INC           0x000FFFFF
01805 
01806 #define AR_SLP_CNT         0x8250
01807 #define AR_SLP_CYCLE_CNT   0x8254
01808 
01809 #define AR_SLP_MIB_CTRL    0x8258
01810 #define AR_SLP_MIB_CLEAR   0x00000001
01811 #define AR_SLP_MIB_PENDING 0x00000002
01812 
01813 #define AR_MAC_PCU_LOGIC_ANALYZER               0x8264
01814 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768   0x20000000
01815 
01816 
01817 #define AR_2040_MODE                0x8318
01818 #define AR_2040_JOINED_RX_CLEAR 0x00000001
01819 
01820 
01821 #define AR_EXTRCCNT         0x8328
01822 
01823 #define AR_SELFGEN_MASK         0x832c
01824 
01825 #define AR_PCU_TXBUF_CTRL               0x8340
01826 #define AR_PCU_TXBUF_CTRL_SIZE_MASK     0x7FF
01827 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE   0x700
01828 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE   0x380
01829 
01830 #define AR_PCU_MISC_MODE2               0x8344
01831 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE           0x00000002
01832 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT   0x00000004
01833 
01834 #define AR_PCU_MISC_MODE2_RESERVED                     0x00000038
01835 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE     0x00000040
01836 #define AR_PCU_MISC_MODE2_CFP_IGNORE                   0x00000080
01837 #define AR_PCU_MISC_MODE2_MGMT_QOS                     0x0000FF00
01838 #define AR_PCU_MISC_MODE2_MGMT_QOS_S                   8
01839 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000
01840 #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP                0x00020000
01841 #define AR_PCU_MISC_MODE2_HWWAR1                       0x00100000
01842 #define AR_PCU_MISC_MODE2_HWWAR2                       0x02000000
01843 #define AR_PCU_MISC_MODE2_RESERVED2                    0xFFFE0000
01844 
01845 #define AR_MAC_PCU_ASYNC_FIFO_REG3                     0x8358
01846 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL        0x00000400
01847 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET          0x80000000
01848 
01849 
01850 #define AR_AES_MUTE_MASK0       0x805c
01851 #define AR_AES_MUTE_MASK0_FC    0x0000FFFF
01852 #define AR_AES_MUTE_MASK0_QOS   0xFFFF0000
01853 #define AR_AES_MUTE_MASK0_QOS_S 16
01854 
01855 #define AR_AES_MUTE_MASK1              0x8060
01856 #define AR_AES_MUTE_MASK1_SEQ          0x0000FFFF
01857 #define AR_AES_MUTE_MASK1_SEQ_S        0
01858 #define AR_AES_MUTE_MASK1_FC_MGMT      0xFFFF0000
01859 #define AR_AES_MUTE_MASK1_FC_MGMT_S    16
01860 
01861 #define AR_RATE_DURATION_0      0x8700
01862 #define AR_RATE_DURATION_31     0x87CC
01863 #define AR_RATE_DURATION_32     0x8780
01864 #define AR_RATE_DURATION(_n)    (AR_RATE_DURATION_0 + ((_n)<<2))
01865 
01866 
01867 #define AR_KEYTABLE_0           0x8800
01868 #define AR_KEYTABLE(_n)         (AR_KEYTABLE_0 + ((_n)*32))
01869 #define AR_KEY_CACHE_SIZE       128
01870 #define AR_RSVD_KEYTABLE_ENTRIES 4
01871 #define AR_KEY_TYPE             0x00000007
01872 #define AR_KEYTABLE_TYPE_40     0x00000000
01873 #define AR_KEYTABLE_TYPE_104    0x00000001
01874 #define AR_KEYTABLE_TYPE_128    0x00000003
01875 #define AR_KEYTABLE_TYPE_TKIP   0x00000004
01876 #define AR_KEYTABLE_TYPE_AES    0x00000005
01877 #define AR_KEYTABLE_TYPE_CCM    0x00000006
01878 #define AR_KEYTABLE_TYPE_CLR    0x00000007
01879 #define AR_KEYTABLE_ANT         0x00000008
01880 #define AR_KEYTABLE_VALID       0x00008000
01881 #define AR_KEYTABLE_KEY0(_n)    (AR_KEYTABLE(_n) + 0)
01882 #define AR_KEYTABLE_KEY1(_n)    (AR_KEYTABLE(_n) + 4)
01883 #define AR_KEYTABLE_KEY2(_n)    (AR_KEYTABLE(_n) + 8)
01884 #define AR_KEYTABLE_KEY3(_n)    (AR_KEYTABLE(_n) + 12)
01885 #define AR_KEYTABLE_KEY4(_n)    (AR_KEYTABLE(_n) + 16)
01886 #define AR_KEYTABLE_TYPE(_n)    (AR_KEYTABLE(_n) + 20)
01887 #define AR_KEYTABLE_MAC0(_n)    (AR_KEYTABLE(_n) + 24)
01888 #define AR_KEYTABLE_MAC1(_n)    (AR_KEYTABLE(_n) + 28)
01889 
01890 #define AR9271_CORE_CLOCK       117   /* clock to 117Mhz */
01891 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
01892 
01893 #define AR_AGG_WEP_ENABLE_FIX           0x00000008  /* This allows the use of AR_AGG_WEP_ENABLE */
01894 #define AR_ADHOC_MCAST_KEYID_ENABLE     0x00000040  /* This bit enables the Multicast search
01895                                                      * based on both MAC Address and Key ID.
01896                                                      * If bit is 0, then Multicast search is
01897                                                      * based on MAC address only.
01898                                                      * For Merlin and above only.
01899                                                      */
01900 #define AR_AGG_WEP_ENABLE               0x00020000  /* This field enables AGG_WEP feature,
01901                                                      * when it is enable, AGG_WEP would takes
01902                                                      * charge of the encryption interface of
01903                                                      * pcu_txsm.
01904                                                      */
01905 
01906 #define AR9300_SM_BASE                          0xa200
01907 #define AR9002_PHY_AGC_CONTROL                  0x9860
01908 #define AR9003_PHY_AGC_CONTROL                  AR9300_SM_BASE + 0xc4
01909 #define AR_PHY_AGC_CONTROL                      (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
01910 #define AR_PHY_AGC_CONTROL_CAL                  0x00000001  /* do internal calibration */
01911 #define AR_PHY_AGC_CONTROL_NF                   0x00000002  /* do noise-floor calibration */
01912 #define AR_PHY_AGC_CONTROL_OFFSET_CAL           0x00000800  /* allow offset calibration */
01913 #define AR_PHY_AGC_CONTROL_ENABLE_NF            0x00008000  /* enable noise floor calibration to happen */
01914 #define AR_PHY_AGC_CONTROL_FLTR_CAL             0x00010000  /* allow tx filter calibration */
01915 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF         0x00020000  /* don't update noise floor automatically */
01916 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS      0x00040000  /* extend noise floor power measurement */
01917 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS          0x00080000  /* carrier leak calibration done */
01918 #define AR_PHY_AGC_CONTROL_YCOK_MAX             0x000003c0
01919 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S           6
01920 
01921 #endif