iPXE
desc.h
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00001 /*
00002  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
00003  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
00004  *
00005  * Permission to use, copy, modify, and distribute this software for any
00006  * purpose with or without fee is hereby granted, provided that the above
00007  * copyright notice and this permission notice appear in all copies.
00008  *
00009  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00010  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00011  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00012  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00013  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00014  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00015  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00016  *
00017  */
00018 
00019 /*
00020  * Internal RX/TX descriptor structures
00021  * (rX: reserved fields possibily used by future versions of the ar5k chipset)
00022  */
00023 
00024 /*
00025  * common hardware RX control descriptor
00026  */
00027 struct ath5k_hw_rx_ctl {
00028         u32     rx_control_0; /* RX control word 0 */
00029         u32     rx_control_1; /* RX control word 1 */
00030 } __attribute__ ((packed));
00031 
00032 /* RX control word 0 field/sflags */
00033 #define AR5K_DESC_RX_CTL0                       0x00000000
00034 
00035 /* RX control word 1 fields/flags */
00036 #define AR5K_DESC_RX_CTL1_BUF_LEN               0x00000fff
00037 #define AR5K_DESC_RX_CTL1_INTREQ                0x00002000
00038 
00039 /*
00040  * common hardware RX status descriptor
00041  * 5210/11 and 5212 differ only in the flags defined below
00042  */
00043 struct ath5k_hw_rx_status {
00044         u32     rx_status_0; /* RX status word 0 */
00045         u32     rx_status_1; /* RX status word 1 */
00046 } __attribute__ ((packed));
00047 
00048 /* 5210/5211 */
00049 /* RX status word 0 fields/flags */
00050 #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN              0x00000fff
00051 #define AR5K_5210_RX_DESC_STATUS0_MORE                  0x00001000
00052 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE          0x00078000
00053 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S        15
00054 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL        0x07f80000
00055 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S      19
00056 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA       0x38000000
00057 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S     27
00058 
00059 /* RX status word 1 fields/flags */
00060 #define AR5K_5210_RX_DESC_STATUS1_DONE                  0x00000001
00061 #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK      0x00000002
00062 #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR             0x00000004
00063 #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN          0x00000008
00064 #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR     0x00000010
00065 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR             0x000000e0
00066 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S           5
00067 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID       0x00000100
00068 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX             0x00007e00
00069 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S           9
00070 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP     0x0fff8000
00071 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S   15
00072 #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS        0x10000000
00073 
00074 /* 5212 */
00075 /* RX status word 0 fields/flags */
00076 #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN              0x00000fff
00077 #define AR5K_5212_RX_DESC_STATUS0_MORE                  0x00001000
00078 #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR      0x00002000
00079 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE          0x000f8000
00080 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S        15
00081 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL        0x0ff00000
00082 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S      20
00083 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA       0xf0000000
00084 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S     28
00085 
00086 /* RX status word 1 fields/flags */
00087 #define AR5K_5212_RX_DESC_STATUS1_DONE                  0x00000001
00088 #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK      0x00000002
00089 #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR             0x00000004
00090 #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR     0x00000008
00091 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR             0x00000010
00092 #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR             0x00000020
00093 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID       0x00000100
00094 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX             0x0000fe00
00095 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S           9
00096 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP     0x7fff0000
00097 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S   16
00098 #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS        0x80000000
00099 
00100 /*
00101  * common hardware RX error descriptor
00102  */
00103 struct ath5k_hw_rx_error {
00104         u32     rx_error_0; /* RX status word 0 */
00105         u32     rx_error_1; /* RX status word 1 */
00106 } __attribute__ ((packed));
00107 
00108 /* RX error word 0 fields/flags */
00109 #define AR5K_RX_DESC_ERROR0                     0x00000000
00110 
00111 /* RX error word 1 fields/flags */
00112 #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE      0x0000ff00
00113 #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S    8
00114 
00115 /* PHY Error codes */
00116 #define AR5K_DESC_RX_PHY_ERROR_NONE             0x00
00117 #define AR5K_DESC_RX_PHY_ERROR_TIMING           0x20
00118 #define AR5K_DESC_RX_PHY_ERROR_PARITY           0x40
00119 #define AR5K_DESC_RX_PHY_ERROR_RATE             0x60
00120 #define AR5K_DESC_RX_PHY_ERROR_LENGTH           0x80
00121 #define AR5K_DESC_RX_PHY_ERROR_64QAM            0xa0
00122 #define AR5K_DESC_RX_PHY_ERROR_SERVICE          0xc0
00123 #define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR      0xe0
00124 
00125 /*
00126  * 5210/5211 hardware 2-word TX control descriptor
00127  */
00128 struct ath5k_hw_2w_tx_ctl {
00129         u32     tx_control_0; /* TX control word 0 */
00130         u32     tx_control_1; /* TX control word 1 */
00131 } __attribute__ ((packed));
00132 
00133 /* TX control word 0 fields/flags */
00134 #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN          0x00000fff
00135 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN         0x0003f000 /*[5210 ?]*/
00136 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S       12
00137 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE          0x003c0000
00138 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S        18
00139 #define AR5K_2W_TX_DESC_CTL0_RTSENA             0x00400000
00140 #define AR5K_2W_TX_DESC_CTL0_CLRDMASK           0x01000000
00141 #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET        0x00800000 /*[5210]*/
00142 #define AR5K_2W_TX_DESC_CTL0_VEOL               0x00800000 /*[5211]*/
00143 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE         0x1c000000 /*[5210]*/
00144 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S       26
00145 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000
00146 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000
00147 
00148 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT                      \
00149                 (ah->ah_version == AR5K_AR5210 ?                \
00150                 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 :       \
00151                 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
00152 
00153 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S    25
00154 #define AR5K_2W_TX_DESC_CTL0_INTREQ             0x20000000
00155 #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID  0x40000000
00156 
00157 /* TX control word 1 fields/flags */
00158 #define AR5K_2W_TX_DESC_CTL1_BUF_LEN            0x00000fff
00159 #define AR5K_2W_TX_DESC_CTL1_MORE               0x00001000
00160 #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210     0x0007e000
00161 #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211     0x000fe000
00162 
00163 #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX                          \
00164                         (ah->ah_version == AR5K_AR5210 ?                \
00165                         AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 :   \
00166                         AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211)
00167 
00168 #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S        13
00169 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE         0x00700000 /*[5211]*/
00170 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S       20
00171 #define AR5K_2W_TX_DESC_CTL1_NOACK              0x00800000 /*[5211]*/
00172 #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION       0xfff80000 /*[5210 ?]*/
00173 
00174 /* Frame types */
00175 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL   0x00
00176 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM     0x04
00177 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL   0x08
00178 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c
00179 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS     0x10
00180 
00181 /*
00182  * 5212 hardware 4-word TX control descriptor
00183  */
00184 struct ath5k_hw_4w_tx_ctl {
00185         u32     tx_control_0; /* TX control word 0 */
00186 
00187 #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN          0x00000fff
00188 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER         0x003f0000
00189 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S       16
00190 #define AR5K_4W_TX_DESC_CTL0_RTSENA             0x00400000
00191 #define AR5K_4W_TX_DESC_CTL0_VEOL               0x00800000
00192 #define AR5K_4W_TX_DESC_CTL0_CLRDMASK           0x01000000
00193 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT      0x1e000000
00194 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S    25
00195 #define AR5K_4W_TX_DESC_CTL0_INTREQ             0x20000000
00196 #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID  0x40000000
00197 #define AR5K_4W_TX_DESC_CTL0_CTSENA             0x80000000
00198 
00199         u32     tx_control_1; /* TX control word 1 */
00200 
00201 #define AR5K_4W_TX_DESC_CTL1_BUF_LEN            0x00000fff
00202 #define AR5K_4W_TX_DESC_CTL1_MORE               0x00001000
00203 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX  0x000fe000
00204 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S        13
00205 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE         0x00f00000
00206 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S       20
00207 #define AR5K_4W_TX_DESC_CTL1_NOACK              0x01000000
00208 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC          0x06000000
00209 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S        25
00210 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN        0x18000000
00211 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S      27
00212 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN       0x60000000
00213 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S     29
00214 
00215         u32     tx_control_2; /* TX control word 2 */
00216 
00217 #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION               0x00007fff
00218 #define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE     0x00008000
00219 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0                0x000f0000
00220 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S              16
00221 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1                0x00f00000
00222 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S              20
00223 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2                0x0f000000
00224 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S              24
00225 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3                0xf0000000
00226 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S              28
00227 
00228         u32     tx_control_3; /* TX control word 3 */
00229 
00230 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0         0x0000001f
00231 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1         0x000003e0
00232 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S       5
00233 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2         0x00007c00
00234 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S       10
00235 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3         0x000f8000
00236 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S       15
00237 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE       0x01f00000
00238 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S     20
00239 } __attribute__ ((packed));
00240 
00241 /*
00242  * Common TX status descriptor
00243  */
00244 struct ath5k_hw_tx_status {
00245         u32     tx_status_0; /* TX status word 0 */
00246         u32     tx_status_1; /* TX status word 1 */
00247 } __attribute__ ((packed));
00248 
00249 /* TX status word 0 fields/flags */
00250 #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK      0x00000001
00251 #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES  0x00000002
00252 #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN      0x00000004
00253 #define AR5K_DESC_TX_STATUS0_FILTERED           0x00000008
00254 /*???
00255 #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT     0x000000f0
00256 #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S   4
00257 */
00258 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT  0x000000f0
00259 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S        4
00260 /*???
00261 #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT    0x00000f00
00262 #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S  8
00263 */
00264 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT   0x00000f00
00265 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8
00266 #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT    0x0000f000
00267 #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S  12
00268 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP     0xffff0000
00269 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S   16
00270 
00271 /* TX status word 1 fields/flags */
00272 #define AR5K_DESC_TX_STATUS1_DONE               0x00000001
00273 #define AR5K_DESC_TX_STATUS1_SEQ_NUM            0x00001ffe
00274 #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S          1
00275 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH   0x001fe000
00276 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
00277 #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX     0x00600000
00278 #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S   21
00279 #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS       0x00800000
00280 #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA       0x01000000
00281 
00282 /*
00283  * 5210/5211 hardware TX descriptor
00284  */
00285 struct ath5k_hw_5210_tx_desc {
00286         struct ath5k_hw_2w_tx_ctl       tx_ctl;
00287         struct ath5k_hw_tx_status       tx_stat;
00288 } __attribute__ ((packed));
00289 
00290 /*
00291  * 5212 hardware TX descriptor
00292  */
00293 struct ath5k_hw_5212_tx_desc {
00294         struct ath5k_hw_4w_tx_ctl       tx_ctl;
00295         struct ath5k_hw_tx_status       tx_stat;
00296 } __attribute__ ((packed));
00297 
00298 /*
00299  * common hardware RX descriptor
00300  */
00301 struct ath5k_hw_all_rx_desc {
00302         struct ath5k_hw_rx_ctl                  rx_ctl;
00303         union {
00304                 struct ath5k_hw_rx_status       rx_stat;
00305                 struct ath5k_hw_rx_error        rx_err;
00306         } u;
00307 } __attribute__ ((packed));
00308 
00309 /*
00310  * Atheros hardware descriptor
00311  * This is read and written to by the hardware
00312  */
00313 struct ath5k_desc {
00314         u32     ds_link;        /* physical address of the next descriptor */
00315         u32     ds_data;        /* physical address of data buffer (skb) */
00316 
00317         union {
00318                 struct ath5k_hw_5210_tx_desc    ds_tx5210;
00319                 struct ath5k_hw_5212_tx_desc    ds_tx5212;
00320                 struct ath5k_hw_all_rx_desc     ds_rx;
00321         } ud;
00322 } __attribute__ ((packed));
00323 
00324 #define AR5K_RXDESC_INTREQ      0x0020
00325 
00326 #define AR5K_TXDESC_CLRDMASK    0x0001
00327 #define AR5K_TXDESC_NOACK       0x0002  /*[5211+]*/
00328 #define AR5K_TXDESC_RTSENA      0x0004
00329 #define AR5K_TXDESC_CTSENA      0x0008
00330 #define AR5K_TXDESC_INTREQ      0x0010
00331 #define AR5K_TXDESC_VEOL        0x0020  /*[5211+]*/
00332