iPXE
intelx.h
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00001 #ifndef _INTELX_H
00002 #define _INTELX_H
00003 
00004 /** @file
00005  *
00006  * Intel 10 Gigabit Ethernet network card driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/if_ether.h>
00014 #include "intel.h"
00015 
00016 /** Device Control Register */
00017 #define INTELX_CTRL 0x00000UL
00018 #define INTELX_CTRL_LRST        0x00000008UL    /**< Link reset */
00019 #define INTELX_CTRL_RST         0x04000000UL    /**< Device reset */
00020 
00021 /** Time to delay for device reset, in milliseconds */
00022 #define INTELX_RESET_DELAY_MS 20
00023 
00024 /** Extended Interrupt Cause Read Register */
00025 #define INTELX_EICR 0x00800UL
00026 #define INTELX_EIRQ_RX0         0x00000001UL    /**< RX0 (via IVAR) */
00027 #define INTELX_EIRQ_TX0         0x00000002UL    /**< RX0 (via IVAR) */
00028 #define INTELX_EIRQ_RXO         0x00020000UL    /**< Receive overrun */
00029 #define INTELX_EIRQ_LSC         0x00100000UL    /**< Link status change */
00030 
00031 /** Interrupt Mask Set/Read Register */
00032 #define INTELX_EIMS 0x00880UL
00033 
00034 /** Interrupt Mask Clear Register */
00035 #define INTELX_EIMC 0x00888UL
00036 
00037 /** Interrupt Vector Allocation Register */
00038 #define INTELX_IVAR 0x00900UL
00039 #define INTELX_IVAR_RX0(bit)    ( (bit) << 0 )  /**< RX queue 0 allocation */
00040 #define INTELX_IVAR_RX0_DEFAULT INTELX_IVAR_RX0 ( 0x00 )
00041 #define INTELX_IVAR_RX0_MASK    INTELX_IVAR_RX0 ( 0x3f )
00042 #define INTELX_IVAR_RX0_VALID   0x00000080UL    /**< RX queue 0 valid */
00043 #define INTELX_IVAR_TX0(bit)    ( (bit) << 8 )  /**< TX queue 0 allocation */
00044 #define INTELX_IVAR_TX0_DEFAULT INTELX_IVAR_TX0 ( 0x01 )
00045 #define INTELX_IVAR_TX0_MASK    INTELX_IVAR_TX0 ( 0x3f )
00046 #define INTELX_IVAR_TX0_VALID   0x00008000UL    /**< TX queue 0 valid */
00047 
00048 /** Receive Filter Control Register */
00049 #define INTELX_FCTRL 0x05080UL
00050 #define INTELX_FCTRL_MPE        0x00000100UL    /**< Multicast promiscuous */
00051 #define INTELX_FCTRL_UPE        0x00000200UL    /**< Unicast promiscuous mode */
00052 #define INTELX_FCTRL_BAM        0x00000400UL    /**< Broadcast accept mode */
00053 
00054 /** Receive Address Low
00055  *
00056  * The MAC address registers RAL0/RAH0 exist at address 0x05400 for
00057  * the 82598 and 0x0a200 for the 82599, according to the datasheet.
00058  * In practice, the 82599 seems to also provide a copy of these
00059  * registers at 0x05400.  To aim for maximum compatibility, we try
00060  * both addresses when reading the initial MAC address, and set both
00061  * addresses when setting the MAC address.
00062  */
00063 #define INTELX_RAL0 0x05400UL
00064 #define INTELX_RAL0_ALT 0x0a200UL
00065 
00066 /** Receive Address High */
00067 #define INTELX_RAH0 0x05404UL
00068 #define INTELX_RAH0_ALT 0x0a204UL
00069 #define INTELX_RAH0_AV          0x80000000UL    /**< Address valid */
00070 
00071 /** Receive Descriptor register block */
00072 #define INTELX_RD 0x01000UL
00073 
00074 /** Receive Descriptor Control Register */
00075 #define INTELX_RXDCTL_VME       0x40000000UL    /**< Strip VLAN tag */
00076 
00077 /** Split Receive Control Register */
00078 #define INTELX_SRRCTL 0x02100UL
00079 #define INTELX_SRRCTL_BSIZE(kb) ( (kb) << 0 )   /**< Receive buffer size */
00080 #define INTELX_SRRCTL_BSIZE_DEFAULT INTELX_SRRCTL_BSIZE ( 0x02 )
00081 #define INTELX_SRRCTL_BSIZE_MASK INTELX_SRRCTL_BSIZE ( 0x1f )
00082 
00083 /** Receive DMA Control Register */
00084 #define INTELX_RDRXCTL 0x02f00UL
00085 #define INTELX_RDRXCTL_SECRC    0x00000001UL    /**< Strip CRC */
00086 
00087 /** Receive Control Register */
00088 #define INTELX_RXCTRL 0x03000UL
00089 #define INTELX_RXCTRL_RXEN      0x00000001UL    /**< Receive enable */
00090 
00091 /** Transmit DMA Control Register */
00092 #define INTELX_DMATXCTL 0x04a80UL
00093 #define INTELX_DMATXCTL_TE      0x00000001UL    /**< Transmit enable */
00094 
00095 /** Transmit Descriptor register block */
00096 #define INTELX_TD 0x06000UL
00097 
00098 /** RX DCA Control Register */
00099 #define INTELX_DCA_RXCTRL 0x02200UL
00100 #define INTELX_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL /**< Must be zero */
00101 
00102 /** MAC Core Control 0 Register */
00103 #define INTELX_HLREG0 0x04240UL
00104 #define INTELX_HLREG0_JUMBOEN   0x00000004UL    /**< Jumbo frame enable */
00105 
00106 /** Maximum Frame Size Register */
00107 #define INTELX_MAXFRS 0x04268UL
00108 #define INTELX_MAXFRS_MFS(len)  ( (len) << 16 ) /**< Maximum frame size */
00109 #define INTELX_MAXFRS_MFS_DEFAULT \
00110         INTELX_MAXFRS_MFS ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
00111 #define INTELX_MAXFRS_MFS_MASK  INTELX_MAXFRS_MFS ( 0xffff )
00112 
00113 /** Link Status Register */
00114 #define INTELX_LINKS 0x042a4UL
00115 #define INTELX_LINKS_UP         0x40000000UL    /**< Link up */
00116 
00117 #endif /* _INTELX_H */