iPXE
lan78xx.h
Go to the documentation of this file.
00001 #ifndef _LAN78XX_H
00002 #define _LAN78XX_H
00003 
00004 /** @file
00005  *
00006  * Microchip LAN78xx USB Ethernet driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include "smscusb.h"
00013 #include "smsc75xx.h"
00014 
00015 /** Hardware configuration register */
00016 #define LAN78XX_HW_CFG 0x0010
00017 #define LAN78XX_HW_CFG_LED1_EN          0x00200000UL    /**< LED1 enable */
00018 #define LAN78XX_HW_CFG_LED0_EN          0x00100000UL    /**< LED1 enable */
00019 #define LAN78XX_HW_CFG_LRST             0x00000002UL    /**< Soft lite reset */
00020 
00021 /** Interrupt endpoint control register */
00022 #define LAN78XX_INT_EP_CTL 0x0098
00023 #define LAN78XX_INT_EP_CTL_RDFO_EN      0x00400000UL    /**< RX FIFO overflow */
00024 #define LAN78XX_INT_EP_CTL_PHY_EN       0x00020000UL    /**< PHY interrupt */
00025 
00026 /** Bulk IN delay register */
00027 #define LAN78XX_BULK_IN_DLY 0x0094
00028 #define LAN78XX_BULK_IN_DLY_SET(ticks)  ( (ticks) << 0 ) /**< Delay / 16.7ns */
00029 
00030 /** EEPROM register base */
00031 #define LAN78XX_E2P_BASE 0x0040
00032 
00033 /** USB configuration register 0 */
00034 #define LAN78XX_USB_CFG0 0x0080
00035 #define LAN78XX_USB_CFG0_BIR            0x00000040UL    /**< Bulk IN use NAK */
00036 
00037 /** Receive filtering engine control register */
00038 #define LAN78XX_RFE_CTL 0x00b0
00039 #define LAN78XX_RFE_CTL_AB              0x00000400UL    /**< Accept broadcast */
00040 #define LAN78XX_RFE_CTL_AM              0x00000200UL    /**< Accept multicast */
00041 #define LAN78XX_RFE_CTL_AU              0x00000100UL    /**< Accept unicast */
00042 
00043 /** FIFO controller RX FIFO control register */
00044 #define LAN78XX_FCT_RX_CTL 0x00c0
00045 #define LAN78XX_FCT_RX_CTL_EN           0x80000000UL    /**< FCT RX enable */
00046 #define LAN78XX_FCT_RX_CTL_BAD          0x02000000UL    /**< Store bad frames */
00047 
00048 /** FIFO controller TX FIFO control register */
00049 #define LAN78XX_FCT_TX_CTL 0x00c4
00050 #define LAN78XX_FCT_TX_CTL_EN           0x80000000UL    /**< FCT TX enable */
00051 
00052 /** MAC receive register */
00053 #define LAN78XX_MAC_RX 0x0104
00054 #define LAN78XX_MAC_RX_MAX_SIZE(mtu)    ( (mtu) << 16 ) /**< Max frame size */
00055 #define LAN78XX_MAC_RX_MAX_SIZE_DEFAULT \
00056         LAN78XX_MAC_RX_MAX_SIZE ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
00057 #define LAN78XX_MAC_RX_FCS              0x00000010UL    /**< FCS stripping */
00058 #define LAN78XX_MAC_RX_EN               0x00000001UL    /**< RX enable */
00059 
00060 /** MAC transmit register */
00061 #define LAN78XX_MAC_TX 0x0108
00062 #define LAN78XX_MAC_TX_EN               0x00000001UL    /**< TX enable */
00063 
00064 /** MAC receive address register base */
00065 #define LAN78XX_RX_ADDR_BASE 0x0118
00066 
00067 /** MII register base */
00068 #define LAN78XX_MII_BASE 0x0120
00069 
00070 /** PHY interrupt mask MII register */
00071 #define LAN78XX_MII_PHY_INTR_MASK 25
00072 
00073 /** PHY interrupt source MII register */
00074 #define LAN78XX_MII_PHY_INTR_SOURCE 26
00075 
00076 /** PHY interrupt: global enable */
00077 #define LAN78XX_PHY_INTR_ENABLE 0x8000
00078 
00079 /** PHY interrupt: link state change */
00080 #define LAN78XX_PHY_INTR_LINK 0x2000
00081 
00082 /** PHY interrupt: auto-negotiation failure */
00083 #define LAN78XX_PHY_INTR_ANEG_ERR 0x0800
00084 
00085 /** PHY interrupt: auto-negotiation complete */
00086 #define LAN78XX_PHY_INTR_ANEG_DONE 0x0400
00087 
00088 /** MAC address perfect filter register base */
00089 #define LAN78XX_ADDR_FILT_BASE 0x0400
00090 
00091 /** OTP register base */
00092 #define LAN78XX_OTP_BASE 0x1000
00093 
00094 /** Maximum time to wait for reset (in milliseconds) */
00095 #define LAN78XX_RESET_MAX_WAIT_MS 100
00096 
00097 #endif /* _LAN78XX_H */