iPXE
myson.h
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00001 #ifndef _MYSON_H
00002 #define _MYSON_H
00003 
00004 /** @file
00005  *
00006  * Myson Technology network card driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/if_ether.h>
00014 
00015 /** BAR size */
00016 #define MYSON_BAR_SIZE 256
00017 
00018 /** A packet descriptor */
00019 struct myson_descriptor {
00020         /** Status */
00021         uint32_t status;
00022         /** Control */
00023         uint32_t control;
00024         /** Buffer start address */
00025         uint32_t address;
00026         /** Next descriptor address */
00027         uint32_t next;
00028 } __attribute__ (( packed ));
00029 
00030 /* Transmit status */
00031 #define MYSON_TX_STAT_OWN       0x80000000UL    /**< Owner */
00032 #define MYSON_TX_STAT_ABORT     0x00002000UL    /**< Abort */
00033 #define MYSON_TX_STAT_CSL       0x00001000UL    /**< Carrier sense lost */
00034 
00035 /* Transmit control */
00036 #define MYSON_TX_CTRL_IC        0x80000000UL    /**< Interrupt control */
00037 #define MYSON_TX_CTRL_LD        0x20000000UL    /**< Last descriptor */
00038 #define MYSON_TX_CTRL_FD        0x10000000UL    /**< First descriptor */
00039 #define MYSON_TX_CTRL_CRC       0x08000000UL    /**< CRC append */
00040 #define MYSON_TX_CTRL_PAD       0x04000000UL    /**< Pad control */
00041 #define MYSON_TX_CTRL_RTLC      0x02000000UL    /**< Retry late collision */
00042 #define MYSON_TX_CTRL_PKTS(x)   ( (x) << 11 )   /**< Packet size */
00043 #define MYSON_TX_CTRL_TBS(x)    ( (x) << 0 )    /**< Transmit buffer size */
00044 
00045 /* Receive status */
00046 #define MYSON_RX_STAT_OWN       0x80000000UL    /**< Owner */
00047 #define MYSON_RX_STAT_FLNG(status) ( ( (status) >> 16 ) & 0xfff )
00048 #define MYSON_RX_STAT_ES        0x00000080UL    /**< Error summary */
00049 
00050 /* Receive control */
00051 #define MYSON_RX_CTRL_RBS(x)    ( (x) << 0 )    /**< Receive buffer size */
00052 
00053 /** Descriptor ring alignment */
00054 #define MYSON_RING_ALIGN 4
00055 
00056 /** Physical Address Register 0 */
00057 #define MYSON_PAR0 0x00
00058 
00059 /** Physical Address Register 4 */
00060 #define MYSON_PAR4 0x04
00061 
00062 /** Physical address */
00063 union myson_physical_address {
00064         struct {
00065                 uint32_t low;
00066                 uint32_t high;
00067         } __attribute__ (( packed )) reg;
00068         uint8_t raw[ETH_ALEN];
00069 };
00070 
00071 /** Transmit and Receive Configuration Register */
00072 #define MYSON_TCR_RCR 0x18
00073 #define MYSON_TCR_TXS           0x80000000UL    /**< Transmit status */
00074 #define MYSON_TCR_TE            0x00040000UL    /**< Transmit enable */
00075 #define MYSON_RCR_RXS           0x00008000UL    /**< Receive status */
00076 #define MYSON_RCR_PROM          0x00000080UL    /**< Promiscuous mode */
00077 #define MYSON_RCR_AB            0x00000040UL    /**< Accept broadcast */
00078 #define MYSON_RCR_AM            0x00000020UL    /**< Accept multicast */
00079 #define MYSON_RCR_ARP           0x00000008UL    /**< Accept runt packet */
00080 #define MYSON_RCR_ALP           0x00000004UL    /**< Accept long packet */
00081 #define MYSON_RCR_RE            0x00000001UL    /**< Receive enable */
00082 
00083 /** Maximum time to wait for transmit and receive to be idle, in milliseconds */
00084 #define MYSON_IDLE_MAX_WAIT_MS 100
00085 
00086 /** Bus Command Register */
00087 #define MYSON_BCR 0x1c
00088 #define MYSON_BCR_RLE           0x00000100UL    /**< Read line enable */
00089 #define MYSON_BCR_RME           0x00000080UL    /**< Read multiple enable */
00090 #define MYSON_BCR_WIE           0x00000040UL    /**< Write and invalidate */
00091 #define MYSON_BCR_PBL(x)        ( (x) << 3 )    /**< Burst length */
00092 #define MYSON_BCR_PBL_MASK      MYSON_BCR_PBL ( 0x7 )
00093 #define MYSON_BCR_PBL_DEFAULT   MYSON_BCR_PBL ( 0x6 )
00094 #define MYSON_BCR_SWR           0x00000001UL    /**< Software reset */
00095 
00096 /** Maximum time to wait for a reset, in milliseconds */
00097 #define MYSON_RESET_MAX_WAIT_MS 100
00098 
00099 /** Transmit Poll Demand Register */
00100 #define MYSON_TXPDR 0x20
00101 
00102 /** Receive Poll Demand Register */
00103 #define MYSON_RXPDR 0x24
00104 
00105 /** Transmit List Base Address */
00106 #define MYSON_TXLBA 0x2c
00107 
00108 /** Number of transmit descriptors */
00109 #define MYSON_NUM_TX_DESC 4
00110 
00111 /** Receive List Base Address */
00112 #define MYSON_RXLBA 0x30
00113 
00114 /** Number of receive descriptors */
00115 #define MYSON_NUM_RX_DESC 4
00116 
00117 /** Receive buffer length */
00118 #define MYSON_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
00119 
00120 /** Interrupt Status Register */
00121 #define MYSON_ISR 0x34
00122 #define MYSON_IRQ_TI            0x00000008UL    /**< Transmit interrupt */
00123 #define MYSON_IRQ_RI            0x00000004UL    /**< Receive interrupt */
00124 
00125 /** Number of I/O delays between ISR reads */
00126 #define MYSON_ISR_IODELAY_COUNT 4
00127 
00128 /** Interrupt Mask Register */
00129 #define MYSON_IMR 0x38
00130 
00131 /** Boot ROM / EEPROM / MII Management Register */
00132 #define MYSON_ROM_MII 0x40
00133 #define MYSON_ROM_AUTOLD        0x00100000UL    /**< Auto load */
00134 
00135 /** Maximum time to wait for a configuration reload, in milliseconds */
00136 #define MYSON_AUTOLD_MAX_WAIT_MS 100
00137 
00138 /** A Myson descriptor ring */
00139 struct myson_ring {
00140         /** Descriptors */
00141         struct myson_descriptor *desc;
00142         /** Producer index */
00143         unsigned int prod;
00144         /** Consumer index */
00145         unsigned int cons;
00146 
00147         /** Number of descriptors */
00148         unsigned int count;
00149         /** Descriptor start address register */
00150         unsigned int reg;
00151 };
00152 
00153 /**
00154  * Initialise descriptor ring
00155  *
00156  * @v ring              Descriptor ring
00157  * @v count             Number of descriptors
00158  * @v reg               Descriptor base address register
00159  */
00160 static inline __attribute__ (( always_inline)) void
00161 myson_init_ring ( struct myson_ring *ring, unsigned int count,
00162                   unsigned int reg ) {
00163         ring->count = count;
00164         ring->reg = reg;
00165 }
00166 
00167 /** A myson network card */
00168 struct myson_nic {
00169         /** Registers */
00170         void *regs;
00171 
00172         /** Transmit descriptor ring */
00173         struct myson_ring tx;
00174         /** Receive descriptor ring */
00175         struct myson_ring rx;
00176         /** Receive I/O buffers */
00177         struct io_buffer *rx_iobuf[MYSON_NUM_RX_DESC];
00178 };
00179 
00180 /**
00181  * Check if card can access physical address
00182  *
00183  * @v address           Physical address
00184  * @v address_ok        Card can access physical address
00185  */
00186 static inline __attribute__ (( always_inline )) int
00187 myson_address_ok ( physaddr_t address ) {
00188 
00189         /* In a 32-bit build, all addresses can be accessed */
00190         if ( sizeof ( physaddr_t ) <= sizeof ( uint32_t ) )
00191                 return 1;
00192 
00193         /* Card can access all addresses below 4GB */
00194         if ( ( address & ~0xffffffffULL ) == 0 )
00195                 return 1;
00196 
00197         return 0;
00198 }
00199 
00200 #endif /* _MYSON_H */