iPXE
phantom.h
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00001 #ifndef _PHANTOM_H
00002 #define _PHANTOM_H
00003 
00004 /*
00005  * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
00006  * Copyright (C) 2008 NetXen, Inc.
00007  *
00008  * This program is free software; you can redistribute it and/or
00009  * modify it under the terms of the GNU General Public License as
00010  * published by the Free Software Foundation; either version 2 of the
00011  * License, or any later version.
00012  *
00013  * This program is distributed in the hope that it will be useful, but
00014  * WITHOUT ANY WARRANTY; without even the implied warranty of
00015  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00016  * General Public License for more details.
00017  *
00018  * You should have received a copy of the GNU General Public License
00019  * along with this program; if not, write to the Free Software
00020  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00021  * 02110-1301, USA.
00022  *
00023  * You can also choose to distribute this program under the terms of
00024  * the Unmodified Binary Distribution Licence (as given in the file
00025  * COPYING.UBDL), provided that you have satisfied its requirements.
00026  */
00027 
00028 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00029 
00030 /**
00031  * @file
00032  *
00033  * NetXen Phantom NICs
00034  *
00035  */
00036 
00037 #include <stdint.h>
00038 
00039 /* Drag in hardware definitions */
00040 #include "nx_bitops.h"
00041 #include "phantom_hw.h"
00042 struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
00043 struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
00044 union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
00045 
00046 /* Drag in firmware interface definitions */
00047 typedef uint8_t U8;
00048 typedef uint16_t U16;
00049 typedef uint32_t U32;
00050 typedef uint64_t U64;
00051 typedef uint32_t nx_rcode_t;
00052 #define NXHAL_VERSION 1
00053 #include "nxhal_nic_interface.h"
00054 
00055 /** DMA buffer alignment */
00056 #define UNM_DMA_BUFFER_ALIGN 16
00057 
00058 /** Mark structure as DMA-aligned */
00059 #define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
00060 
00061 /******************************************************************************
00062  *
00063  * Register definitions
00064  *
00065  */
00066 
00067 #define UNM_128M_CRB_WINDOW             0x6110210UL
00068 #define UNM_32M_CRB_WINDOW              0x0110210UL
00069 #define UNM_2M_CRB_WINDOW               0x0130060UL
00070 
00071 /**
00072  * Phantom register blocks
00073  *
00074  * The upper address bits vary between cards.  We define an abstract
00075  * address space in which the upper 8 bits of the 32-bit register
00076  * address encode the register block.  This gets translated to a bus
00077  * address by the phantom_crb_access_xxx() methods.
00078  */
00079 enum unm_reg_blocks {
00080         UNM_CRB_BLK_PCIE        = 0x01,
00081         UNM_CRB_BLK_CAM         = 0x22,
00082         UNM_CRB_BLK_ROMUSB      = 0x33,
00083         UNM_CRB_BLK_TEST        = 0x02,
00084         UNM_CRB_BLK_PEG_0       = 0x11,
00085         UNM_CRB_BLK_PEG_1       = 0x12,
00086         UNM_CRB_BLK_PEG_2       = 0x13,
00087         UNM_CRB_BLK_PEG_3       = 0x14,
00088         UNM_CRB_BLK_PEG_4       = 0x0f,
00089 };
00090 #define UNM_CRB_BASE(blk)               ( (blk) << 20 )
00091 #define UNM_CRB_BLK(reg)                ( (reg) >> 20 )
00092 #define UNM_CRB_OFFSET(reg)             ( (reg) & 0x000fffff )
00093 
00094 #define UNM_CRB_PCIE                    UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
00095 #define UNM_PCIE_SEM2_LOCK              ( UNM_CRB_PCIE + 0x1c010 )
00096 #define UNM_PCIE_SEM2_UNLOCK            ( UNM_CRB_PCIE + 0x1c014 )
00097 #define UNM_PCIE_IRQ_VECTOR             ( UNM_CRB_PCIE + 0x10100 )
00098 #define UNM_PCIE_IRQ_VECTOR_BIT(n)              ( 1 << ( (n) + 7 ) )
00099 #define UNM_PCIE_IRQ_STATE              ( UNM_CRB_PCIE + 0x1206c )
00100 #define UNM_PCIE_IRQ_STATE_TRIGGERED(state)     (( (state) & 0x300 ) == 0x200 )
00101 #define UNM_PCIE_IRQ_MASK_F0            ( UNM_CRB_PCIE + 0x10128 )
00102 #define UNM_PCIE_IRQ_MASK_F1            ( UNM_CRB_PCIE + 0x10170 )
00103 #define UNM_PCIE_IRQ_MASK_F2            ( UNM_CRB_PCIE + 0x10174 )
00104 #define UNM_PCIE_IRQ_MASK_F3            ( UNM_CRB_PCIE + 0x10178 )
00105 #define UNM_PCIE_IRQ_MASK_F4            ( UNM_CRB_PCIE + 0x10370 )
00106 #define UNM_PCIE_IRQ_MASK_F5            ( UNM_CRB_PCIE + 0x10374 )
00107 #define UNM_PCIE_IRQ_MASK_F6            ( UNM_CRB_PCIE + 0x10378 )
00108 #define UNM_PCIE_IRQ_MASK_F7            ( UNM_CRB_PCIE + 0x1037c )
00109 #define UNM_PCIE_IRQ_MASK_MAGIC                 0x0000fbffUL
00110 #define UNM_PCIE_IRQ_STATUS_F0          ( UNM_CRB_PCIE + 0x10118 )
00111 #define UNM_PCIE_IRQ_STATUS_F1          ( UNM_CRB_PCIE + 0x10160 )
00112 #define UNM_PCIE_IRQ_STATUS_F2          ( UNM_CRB_PCIE + 0x10164 )
00113 #define UNM_PCIE_IRQ_STATUS_F3          ( UNM_CRB_PCIE + 0x10168 )
00114 #define UNM_PCIE_IRQ_STATUS_F4          ( UNM_CRB_PCIE + 0x10360 )
00115 #define UNM_PCIE_IRQ_STATUS_F5          ( UNM_CRB_PCIE + 0x10364 )
00116 #define UNM_PCIE_IRQ_STATUS_F6          ( UNM_CRB_PCIE + 0x10368 )
00117 #define UNM_PCIE_IRQ_STATUS_F7          ( UNM_CRB_PCIE + 0x1036c )
00118 #define UNM_PCIE_IRQ_STATUS_MAGIC               0xffffffffUL
00119 
00120 #define UNM_CRB_CAM                     UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
00121 
00122 #define UNM_CAM_RAM                     ( UNM_CRB_CAM + 0x02000 )
00123 #define UNM_CAM_RAM_PORT_MODE           ( UNM_CAM_RAM + 0x00024 )
00124 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG          4
00125 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G       5
00126 #define UNM_CAM_RAM_DMESG_HEAD(n)       ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
00127 #define UNM_CAM_RAM_DMESG_LEN(n)        ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
00128 #define UNM_CAM_RAM_DMESG_TAIL(n)       ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
00129 #define UNM_CAM_RAM_DMESG_SIG(n)        ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
00130 #define UNM_CAM_RAM_DMESG_SIG_MAGIC             0xcafebabeUL
00131 #define UNM_CAM_RAM_NUM_DMESG_BUFFERS           5
00132 #define UNM_CAM_RAM_CLP_COMMAND         ( UNM_CAM_RAM + 0x000c0 )
00133 #define UNM_CAM_RAM_CLP_COMMAND_LAST            0x00000080UL
00134 #define UNM_CAM_RAM_CLP_DATA_LO         ( UNM_CAM_RAM + 0x000c4 )
00135 #define UNM_CAM_RAM_CLP_DATA_HI         ( UNM_CAM_RAM + 0x000c8 )
00136 #define UNM_CAM_RAM_CLP_STATUS          ( UNM_CAM_RAM + 0x000cc )
00137 #define UNM_CAM_RAM_CLP_STATUS_START            0x00000001UL
00138 #define UNM_CAM_RAM_CLP_STATUS_DONE             0x00000002UL
00139 #define UNM_CAM_RAM_CLP_STATUS_ERROR            0x0000ff00UL
00140 #define UNM_CAM_RAM_CLP_STATUS_UNINITIALISED    0xffffffffUL
00141 #define UNM_CAM_RAM_BOOT_ENABLE         ( UNM_CAM_RAM + 0x000fc )
00142 #define UNM_CAM_RAM_WOL_PORT_MODE       ( UNM_CAM_RAM + 0x00198 )
00143 #define UNM_CAM_RAM_MAC_ADDRS           ( UNM_CAM_RAM + 0x001c0 )
00144 #define UNM_CAM_RAM_COLD_BOOT           ( UNM_CAM_RAM + 0x001fc )
00145 #define UNM_CAM_RAM_COLD_BOOT_MAGIC             0x55555555UL
00146 
00147 #define UNM_NIC_REG                     ( UNM_CRB_CAM + 0x02200 )
00148 #define UNM_NIC_REG_NX_CDRP             ( UNM_NIC_REG + 0x00018 )
00149 #define UNM_NIC_REG_NX_ARG1             ( UNM_NIC_REG + 0x0001c )
00150 #define UNM_NIC_REG_NX_ARG2             ( UNM_NIC_REG + 0x00020 )
00151 #define UNM_NIC_REG_NX_ARG3             ( UNM_NIC_REG + 0x00024 )
00152 #define UNM_NIC_REG_NX_SIGN             ( UNM_NIC_REG + 0x00028 )
00153 #define UNM_NIC_REG_DUMMY_BUF_ADDR_HI   ( UNM_NIC_REG + 0x0003c )
00154 #define UNM_NIC_REG_DUMMY_BUF_ADDR_LO   ( UNM_NIC_REG + 0x00040 )
00155 #define UNM_NIC_REG_CMDPEG_STATE        ( UNM_NIC_REG + 0x00050 )
00156 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED    0xff01
00157 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
00158 #define UNM_NIC_REG_DUMMY_BUF           ( UNM_NIC_REG + 0x000fc )
00159 #define UNM_NIC_REG_DUMMY_BUF_INIT              0
00160 #define UNM_NIC_REG_XG_STATE_P3         ( UNM_NIC_REG + 0x00098 )
00161 #define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
00162         ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
00163 #define UNM_NIC_REG_XG_STATE_P3_LINK_UP         0x01
00164 #define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN       0x02
00165 #define UNM_NIC_REG_RCVPEG_STATE        ( UNM_NIC_REG + 0x0013c )
00166 #define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED    0xff01
00167 
00168 #define UNM_CRB_ROMUSB                  UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
00169 
00170 #define UNM_ROMUSB_GLB                  ( UNM_CRB_ROMUSB + 0x00000 )
00171 #define UNM_ROMUSB_GLB_STATUS           ( UNM_ROMUSB_GLB + 0x00004 )
00172 #define UNM_ROMUSB_GLB_STATUS_ROM_DONE          ( 1 << 1 )
00173 #define UNM_ROMUSB_GLB_SW_RESET         ( UNM_ROMUSB_GLB + 0x00008 )
00174 #define UNM_ROMUSB_GLB_SW_RESET_MAGIC           0x0080000fUL
00175 #define UNM_ROMUSB_GLB_PEGTUNE_DONE     ( UNM_ROMUSB_GLB + 0x0005c )
00176 #define UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC       0x31
00177 
00178 #define UNM_ROMUSB_ROM                  ( UNM_CRB_ROMUSB + 0x10000 )
00179 #define UNM_ROMUSB_ROM_INSTR_OPCODE     ( UNM_ROMUSB_ROM + 0x00004 )
00180 #define UNM_ROMUSB_ROM_ADDRESS          ( UNM_ROMUSB_ROM + 0x00008 )
00181 #define UNM_ROMUSB_ROM_WDATA            ( UNM_ROMUSB_ROM + 0x0000c )
00182 #define UNM_ROMUSB_ROM_ABYTE_CNT        ( UNM_ROMUSB_ROM + 0x00010 )
00183 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT   ( UNM_ROMUSB_ROM + 0x00014 )
00184 #define UNM_ROMUSB_ROM_RDATA            ( UNM_ROMUSB_ROM + 0x00018 )
00185 
00186 #define UNM_CRB_TEST                    UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
00187 
00188 #define UNM_TEST_CONTROL                ( UNM_CRB_TEST + 0x00090 )
00189 #define UNM_TEST_CONTROL_START                  0x01
00190 #define UNM_TEST_CONTROL_ENABLE                 0x02
00191 #define UNM_TEST_CONTROL_BUSY                   0x08
00192 #define UNM_TEST_ADDR_LO                ( UNM_CRB_TEST + 0x00094 )
00193 #define UNM_TEST_ADDR_HI                ( UNM_CRB_TEST + 0x00098 )
00194 #define UNM_TEST_RDDATA_LO              ( UNM_CRB_TEST + 0x000a8 )
00195 #define UNM_TEST_RDDATA_HI              ( UNM_CRB_TEST + 0x000ac )
00196 
00197 #define UNM_CRB_PEG_0                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 )
00198 #define UNM_PEG_0_HALT_STATUS           ( UNM_CRB_PEG_0 + 0x00030 )
00199 #define UNM_PEG_0_HALT                  ( UNM_CRB_PEG_0 + 0x0003c )
00200 
00201 #define UNM_CRB_PEG_1                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 )
00202 #define UNM_PEG_1_HALT_STATUS           ( UNM_CRB_PEG_1 + 0x00030 )
00203 #define UNM_PEG_1_HALT                  ( UNM_CRB_PEG_1 + 0x0003c )
00204 
00205 #define UNM_CRB_PEG_2                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 )
00206 #define UNM_PEG_2_HALT_STATUS           ( UNM_CRB_PEG_2 + 0x00030 )
00207 #define UNM_PEG_2_HALT                  ( UNM_CRB_PEG_2 + 0x0003c )
00208 
00209 #define UNM_CRB_PEG_3                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 )
00210 #define UNM_PEG_3_HALT_STATUS           ( UNM_CRB_PEG_3 + 0x00030 )
00211 #define UNM_PEG_3_HALT                  ( UNM_CRB_PEG_3 + 0x0003c )
00212 
00213 #define UNM_CRB_PEG_4                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 )
00214 #define UNM_PEG_4_HALT_STATUS           ( UNM_CRB_PEG_4 + 0x00030 )
00215 #define UNM_PEG_4_HALT                  ( UNM_CRB_PEG_4 + 0x0003c )
00216 
00217 #endif /* _PHANTOM_H */