iPXE
qib7322.h
Go to the documentation of this file.
00001 #ifndef _QIB7322_H
00002 #define _QIB7322_H
00003 
00004 /*
00005  * Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
00006  *
00007  * This program is free software; you can redistribute it and/or
00008  * modify it under the terms of the GNU General Public License as
00009  * published by the Free Software Foundation; either version 2 of the
00010  * License, or any later version.
00011  *
00012  * This program is distributed in the hope that it will be useful, but
00013  * WITHOUT ANY WARRANTY; without even the implied warranty of
00014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00015  * General Public License for more details.
00016  *
00017  * You should have received a copy of the GNU General Public License
00018  * along with this program; if not, write to the Free Software
00019  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00020  * 02110-1301, USA.
00021  *
00022  * You can also choose to distribute this program under the terms of
00023  * the Unmodified Binary Distribution Licence (as given in the file
00024  * COPYING.UBDL), provided that you have satisfied its requirements.
00025  */
00026 
00027 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00028 
00029 /**
00030  * @file
00031  *
00032  * QLogic QIB7322 Infiniband HCA
00033  *
00034  */
00035 
00036 #define PSEUDOBIT_LITTLE_ENDIAN
00037 #include <ipxe/pseudobit.h>
00038 #include "qib_7322_regs.h"
00039 
00040 /** A QIB7322 GPIO register */
00041 struct QIB_7322_GPIO_pb {
00042         pseudo_bit_t GPIO[16];
00043         pseudo_bit_t Reserved[48];
00044 };
00045 struct QIB_7322_GPIO {
00046         PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIO_pb );
00047 };
00048 
00049 /** A QIB7322 general scalar register */
00050 struct QIB_7322_scalar_pb {
00051         pseudo_bit_t Value[64];
00052 };
00053 struct QIB_7322_scalar {
00054         PSEUDO_BIT_STRUCT ( struct QIB_7322_scalar_pb );
00055 };
00056 
00057 /** QIB7322 feature mask */
00058 struct QIB_7322_feature_mask_pb {
00059         pseudo_bit_t Port0_Link_Speed_Supported[3];
00060         pseudo_bit_t Port1_Link_Speed_Supported[3];
00061         pseudo_bit_t _unused_0[58];
00062 };
00063 struct QIB_7322_feature_mask {
00064         PSEUDO_BIT_STRUCT ( struct QIB_7322_feature_mask_pb );
00065 };
00066 
00067 /** QIB7322 send per-buffer control word */
00068 struct QIB_7322_SendPbc_pb {
00069         pseudo_bit_t LengthP1_toibc[11];
00070         pseudo_bit_t Reserved1[4];
00071         pseudo_bit_t LengthP1_trigger[11];
00072         pseudo_bit_t Reserved2[3];
00073         pseudo_bit_t TestEbp[1];
00074         pseudo_bit_t Test[1];
00075         pseudo_bit_t Intr[1];
00076         pseudo_bit_t StaticRateControlCnt[14];
00077         pseudo_bit_t Reserved3[12];
00078         pseudo_bit_t Port[1];
00079         pseudo_bit_t VLane[3];
00080         pseudo_bit_t Reserved4[1];
00081         pseudo_bit_t VL15[1];
00082 };
00083 struct QIB_7322_SendPbc {
00084         PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbc_pb );
00085 };
00086 
00087 /** QIB7322 send buffer availability */
00088 struct QIB_7322_SendBufAvail_pb {
00089         pseudo_bit_t InUseCheck[162][2];
00090         pseudo_bit_t Reserved[60];
00091 };
00092 struct QIB_7322_SendBufAvail {
00093         PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvail_pb );
00094 };
00095 
00096 /** DMA alignment for send buffer availability */
00097 #define QIB7322_SENDBUFAVAIL_ALIGN 64
00098 
00099 /** QIB7322 port-specific receive control */
00100 struct QIB_7322_RcvCtrl_P_pb {
00101         pseudo_bit_t ContextEnable[18];
00102         pseudo_bit_t _unused_1[21];
00103         pseudo_bit_t RcvIBPortEnable[1];
00104         pseudo_bit_t RcvQPMapEnable[1];
00105         pseudo_bit_t RcvPartitionKeyDisable[1];
00106         pseudo_bit_t RcvResetCredit[1];
00107         pseudo_bit_t _unused_2[21];
00108 };
00109 struct QIB_7322_RcvCtrl_P {
00110         PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_P_pb );
00111 };
00112 
00113 /** A QIB7322 eager receive descriptor */
00114 struct QIB_7322_RcvEgr_pb {
00115         pseudo_bit_t Addr[37];
00116         pseudo_bit_t BufSize[3];
00117         pseudo_bit_t Reserved[24];
00118 };
00119 struct QIB_7322_RcvEgr {
00120         PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvEgr_pb );
00121 };
00122 
00123 /** QIB7322 receive header flags */
00124 struct QIB_7322_RcvHdrFlags_pb {
00125         pseudo_bit_t PktLen[11];
00126         pseudo_bit_t RcvType[3];
00127         pseudo_bit_t SoftB[1];
00128         pseudo_bit_t SoftA[1];
00129         pseudo_bit_t EgrIndex[12];
00130         pseudo_bit_t Reserved1[3];
00131         pseudo_bit_t UseEgrBfr[1];
00132         pseudo_bit_t RcvSeq[4];
00133         pseudo_bit_t HdrqOffset[11];
00134         pseudo_bit_t Reserved2[8];
00135         pseudo_bit_t IBErr[1];
00136         pseudo_bit_t MKErr[1];
00137         pseudo_bit_t TIDErr[1];
00138         pseudo_bit_t KHdrErr[1];
00139         pseudo_bit_t MTUErr[1];
00140         pseudo_bit_t LenErr[1];
00141         pseudo_bit_t ParityErr[1];
00142         pseudo_bit_t VCRCErr[1];
00143         pseudo_bit_t ICRCErr[1];
00144 };
00145 struct QIB_7322_RcvHdrFlags {
00146         PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrFlags_pb );
00147 };
00148 
00149 /** QIB7322 DDS tuning parameters */
00150 struct QIB_7322_IBSD_DDS_MAP_TABLE_pb {
00151         pseudo_bit_t Pre[3];
00152         pseudo_bit_t PreXtra[2];
00153         pseudo_bit_t Post[4];
00154         pseudo_bit_t Main[5];
00155         pseudo_bit_t Amp[4];
00156         pseudo_bit_t _unused_0[46];
00157 };
00158 struct QIB_7322_IBSD_DDS_MAP_TABLE {
00159         PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_DDS_MAP_TABLE_pb );
00160 };
00161 
00162 /** QIB7322 memory BAR size */
00163 #define QIB7322_BAR0_SIZE 0x400000
00164 
00165 /** QIB7322 base port number */
00166 #define QIB7322_PORT_BASE 1
00167 
00168 /** QIB7322 maximum number of ports */
00169 #define QIB7322_MAX_PORTS 2
00170 
00171 /** QIB7322 maximum width */
00172 #define QIB7322_MAX_WIDTH 4
00173 
00174 /** QIB7322 board identifiers */
00175 enum qib7322_board_id {
00176         QIB7322_BOARD_QLE7342_EMULATION = 0,
00177         QIB7322_BOARD_QLE7340 = 1,
00178         QIB7322_BOARD_QLE7342 = 2,
00179         QIB7322_BOARD_QMI7342 = 3,
00180         QIB7322_BOARD_QMH7342_UNSUPPORTED = 4,
00181         QIB7322_BOARD_QME7342 = 5,
00182         QIB7322_BOARD_QMH7342 = 6,
00183         QIB7322_BOARD_QLE7342_TEST = 15,
00184 };
00185 
00186 /** QIB7322 I2C SCL line GPIO number */
00187 #define QIB7322_GPIO_SCL 0
00188 
00189 /** QIB7322 I2C SDA line GPIO number */
00190 #define QIB7322_GPIO_SDA 1
00191 
00192 /** GUID offset within EEPROM */
00193 #define QIB7322_EEPROM_GUID_OFFSET 3
00194 
00195 /** GUID size within EEPROM */
00196 #define QIB7322_EEPROM_GUID_SIZE 8
00197 
00198 /** Board serial number offset within EEPROM */
00199 #define QIB7322_EEPROM_SERIAL_OFFSET 12
00200 
00201 /** Board serial number size within EEPROM */
00202 #define QIB7322_EEPROM_SERIAL_SIZE 12
00203 
00204 /** QIB7322 small send buffer size */
00205 #define QIB7322_SMALL_SEND_BUF_SIZE 4096
00206 
00207 /** QIB7322 small send buffer starting index */
00208 #define QIB7322_SMALL_SEND_BUF_START 0
00209 
00210 /** QIB7322 small send buffer count */
00211 #define QIB7322_SMALL_SEND_BUF_COUNT 128
00212 
00213 /** QIB7322 large send buffer size */
00214 #define QIB7322_LARGE_SEND_BUF_SIZE 8192
00215 
00216 /** QIB7322 large send buffer starting index */
00217 #define QIB7322_LARGE_SEND_BUF_START 128
00218 
00219 /** QIB7322 large send buffer count */
00220 #define QIB7322_LARGE_SEND_BUF_COUNT 32
00221 
00222 /** QIB7322 VL15 port 0 send buffer starting index */
00223 #define QIB7322_VL15_PORT0_SEND_BUF_START 160
00224 
00225 /** QIB7322 VL15 port 0 send buffer count */
00226 #define QIB7322_VL15_PORT0_SEND_BUF_COUNT 1
00227 
00228 /** QIB7322 VL15 port 0 send buffer size */
00229 #define QIB7322_VL15_PORT0_SEND_BUF_SIZE 8192
00230 
00231 /** QIB7322 VL15 port 0 send buffer starting index */
00232 #define QIB7322_VL15_PORT1_SEND_BUF_START 161
00233 
00234 /** QIB7322 VL15 port 0 send buffer count */
00235 #define QIB7322_VL15_PORT1_SEND_BUF_COUNT 1
00236 
00237 /** QIB7322 VL15 port 0 send buffer size */
00238 #define QIB7322_VL15_PORT1_SEND_BUF_SIZE 8192
00239 
00240 /** Number of small send buffers used
00241  *
00242  * This is a policy decision.  Must be less than or equal to the total
00243  * number of small send buffers supported by the hardware
00244  * (QIB7322_SMALL_SEND_BUF_COUNT).
00245  */
00246 #define QIB7322_SMALL_SEND_BUF_USED 32
00247 
00248 /** Number of contexts (including kernel context)
00249  *
00250  * This is a policy decision.  Must be 6, 10 or 18.
00251  */
00252 #define QIB7322_NUM_CONTEXTS 6
00253 
00254 /** ContextCfg values for different numbers of contexts */
00255 enum qib7322_contextcfg {
00256         QIB7322_CONTEXTCFG_6CTX = 0,
00257         QIB7322_CONTEXTCFG_10CTX = 1,
00258         QIB7322_CONTEXTCFG_18CTX = 2,
00259 };
00260 
00261 /** ContextCfg values for different numbers of contexts */
00262 #define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL 1024
00263 #define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER 4096
00264 #define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL 1024
00265 #define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER 2048
00266 #define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL 1024
00267 #define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER 1024
00268 
00269 /** Eager buffer required alignment */
00270 #define QIB7322_EAGER_BUFFER_ALIGN 2048
00271 
00272 /** Eager buffer size encodings */
00273 enum qib7322_eager_buffer_size {
00274         QIB7322_EAGER_BUFFER_NONE = 0,
00275         QIB7322_EAGER_BUFFER_2K = 1,
00276         QIB7322_EAGER_BUFFER_4K = 2,
00277         QIB7322_EAGER_BUFFER_8K = 3,
00278         QIB7322_EAGER_BUFFER_16K = 4,
00279         QIB7322_EAGER_BUFFER_32K = 5,
00280         QIB7322_EAGER_BUFFER_64K = 6,
00281 };
00282 
00283 /** Number of RX headers per context
00284  *
00285  * This is a policy decision.
00286  */
00287 #define QIB7322_RECV_HEADER_COUNT 8
00288 
00289 /** Maximum size of each RX header
00290  *
00291  * This is a policy decision.  Must be divisible by 4.
00292  */
00293 #define QIB7322_RECV_HEADER_SIZE 96
00294 
00295 /** Total size of an RX header ring */
00296 #define QIB7322_RECV_HEADERS_SIZE \
00297         ( QIB7322_RECV_HEADER_SIZE * QIB7322_RECV_HEADER_COUNT )
00298 
00299 /** RX header alignment */
00300 #define QIB7322_RECV_HEADERS_ALIGN 64
00301 
00302 /** RX payload size
00303  *
00304  * This is a policy decision.  Must be a valid eager buffer size.
00305  */
00306 #define QIB7322_RECV_PAYLOAD_SIZE 2048
00307 
00308 /** Maximum number of credits per port
00309  *
00310  * 64kB of internal RX buffer space, in units of 64 bytes, split
00311  * between two ports.
00312  */
00313 #define QIB7322_MAX_CREDITS ( ( 65536 / 64 ) / QIB7322_MAX_PORTS )
00314 
00315 /** Number of credits to advertise for VL15
00316  *
00317  * This is a policy decision.  Using 9 credits allows for 9*64=576
00318  * bytes, which is enough for two MADs.
00319  */
00320 #define QIB7322_MAX_CREDITS_VL15 9
00321 
00322 /** Number of credits to advertise for VL0
00323  *
00324  * This is a policy decision.
00325  */
00326 #define QIB7322_MAX_CREDITS_VL0 \
00327         ( QIB7322_MAX_CREDITS - QIB7322_MAX_CREDITS_VL15 )
00328 
00329 /** QPN used for Infinipath Packets
00330  *
00331  * This is a policy decision.  Must have bit 0 clear.  Must not be a
00332  * QPN that we will use.
00333  */
00334 #define QIB7322_QP_IDETH 0xdead0
00335 
00336 /** Maximum time for wait for AHB, in us */
00337 #define QIB7322_AHB_MAX_WAIT_US 500
00338 
00339 /** QIB7322 AHB locations */
00340 #define QIB7322_AHB_LOC_ADDRESS( _location ) ( (_location) & 0xffff )
00341 #define QIB7322_AHB_LOC_TARGET( _location ) ( (_location) >> 16 )
00342 #define QIB7322_AHB_CHAN_0 0
00343 #define QIB7322_AHB_CHAN_1 1
00344 #define QIB7322_AHB_PLL 2
00345 #define QIB7322_AHB_CHAN_2 3
00346 #define QIB7322_AHB_CHAN_3 4
00347 #define QIB7322_AHB_SUBSYS 5
00348 #define QIB7322_AHB_CHAN( _channel ) ( (_channel) + ( (_channel) >> 1 ) )
00349 #define QIB7322_AHB_TARGET_0 2
00350 #define QIB7322_AHB_TARGET_1 3
00351 #define QIB7322_AHB_TARGET( _port ) ( (_port) + 2 )
00352 #define QIB7322_AHB_LOCATION( _port, _channel, _register )      \
00353         ( ( QIB7322_AHB_TARGET(_port) << 16 ) |                 \
00354           ( QIB7322_AHB_CHAN(_channel) << 7 ) |                 \
00355           ( (_register) << 1 ) )
00356 
00357 /** QIB7322 link states */
00358 enum qib7322_link_state {
00359         QIB7322_LINK_STATE_DOWN = 0,
00360         QIB7322_LINK_STATE_INIT = 1,
00361         QIB7322_LINK_STATE_ARM = 2,
00362         QIB7322_LINK_STATE_ACTIVE = 3,
00363         QIB7322_LINK_STATE_ACT_DEFER = 4,
00364 };
00365 
00366 /** Maximum time to wait for link state changes, in us */
00367 #define QIB7322_LINK_STATE_MAX_WAIT_US 20
00368 
00369 #endif /* _QIB7322_H */