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iPXE
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00001 /* 00002 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. 00003 * 00004 * This software is available to you under a choice of one of two 00005 * licenses. You may choose to be licensed under the terms of the GNU 00006 * General Public License (GPL) Version 2, available from the file 00007 * COPYING in the main directory of this source tree, or the 00008 * OpenIB.org BSD license below: 00009 * 00010 * Redistribution and use in source and binary forms, with or 00011 * without modification, are permitted provided that the following 00012 * conditions are met: 00013 * 00014 * - Redistributions of source code must retain the above 00015 * copyright notice, this list of conditions and the following 00016 * disclaimer. 00017 * 00018 * - Redistributions in binary form must reproduce the above 00019 * copyright notice, this list of conditions and the following 00020 * disclaimer in the documentation and/or other materials 00021 * provided with the distribution. 00022 * 00023 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 00024 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00025 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 00026 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 00027 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 00028 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 00029 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 00030 * SOFTWARE. 00031 */ 00032 /* This file is mechanically generated from RTL. Any hand-edits will be lost! */ 00033 00034 /* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */ 00035 00036 FILE_LICENCE ( GPL2_ONLY ); 00037 00038 #define QIB_7322_Revision_offset 0x00000000UL 00039 struct QIB_7322_Revision_pb { 00040 pseudo_bit_t R_ChipRevMinor[8]; 00041 pseudo_bit_t R_ChipRevMajor[8]; 00042 pseudo_bit_t R_Arch[8]; 00043 pseudo_bit_t R_SW[8]; 00044 pseudo_bit_t BoardID[8]; 00045 pseudo_bit_t R_Emulation_Revcode[22]; 00046 pseudo_bit_t R_Emulation[1]; 00047 pseudo_bit_t R_Simulator[1]; 00048 }; 00049 struct QIB_7322_Revision { 00050 PSEUDO_BIT_STRUCT ( struct QIB_7322_Revision_pb ); 00051 }; 00052 /* Default value: 0x0000000002010601 */ 00053 00054 #define QIB_7322_Control_offset 0x00000008UL 00055 struct QIB_7322_Control_pb { 00056 pseudo_bit_t SyncReset[1]; 00057 pseudo_bit_t FreezeMode[1]; 00058 pseudo_bit_t _unused_0[1]; 00059 pseudo_bit_t PCIERetryBufDiagEn[1]; 00060 pseudo_bit_t SDmaDescFetchPriorityEn[1]; 00061 pseudo_bit_t PCIEPostQDiagEn[1]; 00062 pseudo_bit_t PCIECplQDiagEn[1]; 00063 pseudo_bit_t _unused_1[57]; 00064 }; 00065 struct QIB_7322_Control { 00066 PSEUDO_BIT_STRUCT ( struct QIB_7322_Control_pb ); 00067 }; 00068 /* Default value: 0x0000000000000000 */ 00069 00070 #define QIB_7322_PageAlign_offset 0x00000010UL 00071 /* Default value: 0x0000000000001000 */ 00072 00073 #define QIB_7322_ContextCnt_offset 0x00000018UL 00074 /* Default value: 0x0000000000000012 */ 00075 00076 #define QIB_7322_Scratch_offset 0x00000020UL 00077 /* Default value: 0x0000000000000000 */ 00078 00079 #define QIB_7322_CntrRegBase_offset 0x00000028UL 00080 /* Default value: 0x0000000000011000 */ 00081 00082 #define QIB_7322_SendRegBase_offset 0x00000030UL 00083 /* Default value: 0x0000000000003000 */ 00084 00085 #define QIB_7322_UserRegBase_offset 0x00000038UL 00086 /* Default value: 0x0000000000200000 */ 00087 00088 #define QIB_7322_DebugPortSel_offset 0x00000040UL 00089 struct QIB_7322_DebugPortSel_pb { 00090 pseudo_bit_t DebugOutMuxSel[2]; 00091 pseudo_bit_t _unused_0[28]; 00092 pseudo_bit_t SrcMuxSel0[8]; 00093 pseudo_bit_t SrcMuxSel1[8]; 00094 pseudo_bit_t DbgClkPortSel[5]; 00095 pseudo_bit_t EnDbgPort[1]; 00096 pseudo_bit_t EnEnhancedDebugMode[1]; 00097 pseudo_bit_t EnhMode_SrcMuxSelIndex[10]; 00098 pseudo_bit_t EnhMode_SrcMuxSelWrEn[1]; 00099 }; 00100 struct QIB_7322_DebugPortSel { 00101 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugPortSel_pb ); 00102 }; 00103 /* Default value: 0x0000000000000000 */ 00104 00105 #define QIB_7322_DebugPortNibbleSel_offset 0x00000048UL 00106 struct QIB_7322_DebugPortNibbleSel_pb { 00107 pseudo_bit_t NibbleSel0[4]; 00108 pseudo_bit_t NibbleSel1[4]; 00109 pseudo_bit_t NibbleSel2[4]; 00110 pseudo_bit_t NibbleSel3[4]; 00111 pseudo_bit_t NibbleSel4[4]; 00112 pseudo_bit_t NibbleSel5[4]; 00113 pseudo_bit_t NibbleSel6[4]; 00114 pseudo_bit_t NibbleSel7[4]; 00115 pseudo_bit_t NibbleSel8[4]; 00116 pseudo_bit_t NibbleSel9[4]; 00117 pseudo_bit_t NibbleSel10[4]; 00118 pseudo_bit_t NibbleSel11[4]; 00119 pseudo_bit_t NibbleSel12[4]; 00120 pseudo_bit_t NibbleSel13[4]; 00121 pseudo_bit_t NibbleSel14[4]; 00122 pseudo_bit_t NibbleSel15[4]; 00123 }; 00124 struct QIB_7322_DebugPortNibbleSel { 00125 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugPortNibbleSel_pb ); 00126 }; 00127 /* Default value: 0xFEDCBA9876543210 */ 00128 00129 #define QIB_7322_DebugSigsIntSel_offset 0x00000050UL 00130 struct QIB_7322_DebugSigsIntSel_pb { 00131 pseudo_bit_t debug_port_sel_pcs_pipe_lane07[3]; 00132 pseudo_bit_t debug_port_sel_pcs_pipe_lane815[3]; 00133 pseudo_bit_t debug_port_sel_pcs_sdout[1]; 00134 pseudo_bit_t debug_port_sel_pcs_symlock_elfifo_lane[4]; 00135 pseudo_bit_t debug_port_sel_pcs_rxdet_encdec_lane[3]; 00136 pseudo_bit_t EnableSDma_SelfDrain[1]; 00137 pseudo_bit_t debug_port_sel_pcie_rx_tx[1]; 00138 pseudo_bit_t _unused_0[1]; 00139 pseudo_bit_t debug_port_sel_tx_ibport[1]; 00140 pseudo_bit_t debug_port_sel_tx_sdma[1]; 00141 pseudo_bit_t debug_port_sel_rx_ibport[1]; 00142 pseudo_bit_t _unused_1[12]; 00143 pseudo_bit_t debug_port_sel_xgxs_0[4]; 00144 pseudo_bit_t debug_port_sel_credit_a_0[3]; 00145 pseudo_bit_t debug_port_sel_credit_b_0[3]; 00146 pseudo_bit_t debug_port_sel_xgxs_1[4]; 00147 pseudo_bit_t debug_port_sel_credit_a_1[3]; 00148 pseudo_bit_t debug_port_sel_credit_b_1[3]; 00149 pseudo_bit_t _unused_2[12]; 00150 }; 00151 struct QIB_7322_DebugSigsIntSel { 00152 PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugSigsIntSel_pb ); 00153 }; 00154 /* Default value: 0x0000000000000000 */ 00155 00156 #define QIB_7322_DebugPortValueReg_offset 0x00000058UL 00157 00158 #define QIB_7322_IntBlocked_offset 0x00000060UL 00159 struct QIB_7322_IntBlocked_pb { 00160 pseudo_bit_t RcvAvail0IntBlocked[1]; 00161 pseudo_bit_t RcvAvail1IntBlocked[1]; 00162 pseudo_bit_t RcvAvail2IntBlocked[1]; 00163 pseudo_bit_t RcvAvail3IntBlocked[1]; 00164 pseudo_bit_t RcvAvail4IntBlocked[1]; 00165 pseudo_bit_t RcvAvail5IntBlocked[1]; 00166 pseudo_bit_t RcvAvail6IntBlocked[1]; 00167 pseudo_bit_t RcvAvail7IntBlocked[1]; 00168 pseudo_bit_t RcvAvail8IntBlocked[1]; 00169 pseudo_bit_t RcvAvail9IntBlocked[1]; 00170 pseudo_bit_t RcvAvail10IntBlocked[1]; 00171 pseudo_bit_t RcvAvail11IntBlocked[1]; 00172 pseudo_bit_t RcvAvail12IntBlocked[1]; 00173 pseudo_bit_t RcvAvail13IntBlocked[1]; 00174 pseudo_bit_t RcvAvail14IntBlocked[1]; 00175 pseudo_bit_t RcvAvail15IntBlocked[1]; 00176 pseudo_bit_t RcvAvail16IntBlocked[1]; 00177 pseudo_bit_t RcvAvail17IntBlocked[1]; 00178 pseudo_bit_t _unused_0[5]; 00179 pseudo_bit_t SendBufAvailIntBlocked[1]; 00180 pseudo_bit_t SendDoneIntBlocked_0[1]; 00181 pseudo_bit_t SendDoneIntBlocked_1[1]; 00182 pseudo_bit_t _unused_1[2]; 00183 pseudo_bit_t AssertGPIOIntBlocked[1]; 00184 pseudo_bit_t ErrIntBlocked[1]; 00185 pseudo_bit_t ErrIntBlocked_0[1]; 00186 pseudo_bit_t ErrIntBlocked_1[1]; 00187 pseudo_bit_t RcvUrg0IntBlocked[1]; 00188 pseudo_bit_t RcvUrg1IntBlocked[1]; 00189 pseudo_bit_t RcvUrg2IntBlocked[1]; 00190 pseudo_bit_t RcvUrg3IntBlocked[1]; 00191 pseudo_bit_t RcvUrg4IntBlocked[1]; 00192 pseudo_bit_t RcvUrg5IntBlocked[1]; 00193 pseudo_bit_t RcvUrg6IntBlocked[1]; 00194 pseudo_bit_t RcvUrg7IntBlocked[1]; 00195 pseudo_bit_t RcvUrg8IntBlocked[1]; 00196 pseudo_bit_t RcvUrg9IntBlocked[1]; 00197 pseudo_bit_t RcvUrg10IntBlocked[1]; 00198 pseudo_bit_t RcvUrg11IntBlocked[1]; 00199 pseudo_bit_t RcvUrg12IntBlocked[1]; 00200 pseudo_bit_t RcvUrg13IntBlocked[1]; 00201 pseudo_bit_t RcvUrg14IntBlocked[1]; 00202 pseudo_bit_t RcvUrg15IntBlocked[1]; 00203 pseudo_bit_t RcvUrg16IntBlocked[1]; 00204 pseudo_bit_t RcvUrg17IntBlocked[1]; 00205 pseudo_bit_t _unused_2[6]; 00206 pseudo_bit_t SDmaCleanupDoneBlocked_0[1]; 00207 pseudo_bit_t SDmaCleanupDoneBlocked_1[1]; 00208 pseudo_bit_t SDmaIdleIntBlocked_0[1]; 00209 pseudo_bit_t SDmaIdleIntBlocked_1[1]; 00210 pseudo_bit_t SDmaProgressIntBlocked_0[1]; 00211 pseudo_bit_t SDmaProgressIntBlocked_1[1]; 00212 pseudo_bit_t SDmaIntBlocked_0[1]; 00213 pseudo_bit_t SDmaIntBlocked_1[1]; 00214 }; 00215 struct QIB_7322_IntBlocked { 00216 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntBlocked_pb ); 00217 }; 00218 /* Default value: 0x0000000000000000 */ 00219 00220 #define QIB_7322_IntMask_offset 0x00000068UL 00221 struct QIB_7322_IntMask_pb { 00222 pseudo_bit_t RcvAvail0IntMask[1]; 00223 pseudo_bit_t RcvAvail1IntMask[1]; 00224 pseudo_bit_t RcvAvail2IntMask[1]; 00225 pseudo_bit_t RcvAvail3IntMask[1]; 00226 pseudo_bit_t RcvAvail4IntMask[1]; 00227 pseudo_bit_t RcvAvail5IntMask[1]; 00228 pseudo_bit_t RcvAvail6IntMask[1]; 00229 pseudo_bit_t RcvAvail7IntMask[1]; 00230 pseudo_bit_t RcvAvail8IntMask[1]; 00231 pseudo_bit_t RcvAvail9IntMask[1]; 00232 pseudo_bit_t RcvAvail10IntMask[1]; 00233 pseudo_bit_t RcvAvail11IntMask[1]; 00234 pseudo_bit_t RcvAvail12IntMask[1]; 00235 pseudo_bit_t RcvAvail13IntMask[1]; 00236 pseudo_bit_t RcvAvail14IntMask[1]; 00237 pseudo_bit_t RcvAvail15IntMask[1]; 00238 pseudo_bit_t RcvAvail16IntMask[1]; 00239 pseudo_bit_t RcvAvail17IntMask[1]; 00240 pseudo_bit_t _unused_0[5]; 00241 pseudo_bit_t SendBufAvailIntMask[1]; 00242 pseudo_bit_t SendDoneIntMask_0[1]; 00243 pseudo_bit_t SendDoneIntMask_1[1]; 00244 pseudo_bit_t _unused_1[2]; 00245 pseudo_bit_t AssertGPIOIntMask[1]; 00246 pseudo_bit_t ErrIntMask[1]; 00247 pseudo_bit_t ErrIntMask_0[1]; 00248 pseudo_bit_t ErrIntMask_1[1]; 00249 pseudo_bit_t RcvUrg0IntMask[1]; 00250 pseudo_bit_t RcvUrg1IntMask[1]; 00251 pseudo_bit_t RcvUrg2IntMask[1]; 00252 pseudo_bit_t RcvUrg3IntMask[1]; 00253 pseudo_bit_t RcvUrg4IntMask[1]; 00254 pseudo_bit_t RcvUrg5IntMask[1]; 00255 pseudo_bit_t RcvUrg6IntMask[1]; 00256 pseudo_bit_t RcvUrg7IntMask[1]; 00257 pseudo_bit_t RcvUrg8IntMask[1]; 00258 pseudo_bit_t RcvUrg9IntMask[1]; 00259 pseudo_bit_t RcvUrg10IntMask[1]; 00260 pseudo_bit_t RcvUrg11IntMask[1]; 00261 pseudo_bit_t RcvUrg12IntMask[1]; 00262 pseudo_bit_t RcvUrg13IntMask[1]; 00263 pseudo_bit_t RcvUrg14IntMask[1]; 00264 pseudo_bit_t RcvUrg15IntMask[1]; 00265 pseudo_bit_t RcvUrg16IntMask[1]; 00266 pseudo_bit_t RcvUrg17IntMask[1]; 00267 pseudo_bit_t _unused_2[6]; 00268 pseudo_bit_t SDmaCleanupDoneMask_0[1]; 00269 pseudo_bit_t SDmaCleanupDoneMask_1[1]; 00270 pseudo_bit_t SDmaIdleIntMask_0[1]; 00271 pseudo_bit_t SDmaIdleIntMask_1[1]; 00272 pseudo_bit_t SDmaProgressIntMask_0[1]; 00273 pseudo_bit_t SDmaProgressIntMask_1[1]; 00274 pseudo_bit_t SDmaIntMask_0[1]; 00275 pseudo_bit_t SDmaIntMask_1[1]; 00276 }; 00277 struct QIB_7322_IntMask { 00278 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntMask_pb ); 00279 }; 00280 /* Default value: 0x0000000000000000 */ 00281 00282 #define QIB_7322_IntStatus_offset 0x00000070UL 00283 struct QIB_7322_IntStatus_pb { 00284 pseudo_bit_t RcvAvail0[1]; 00285 pseudo_bit_t RcvAvail1[1]; 00286 pseudo_bit_t RcvAvail2[1]; 00287 pseudo_bit_t RcvAvail3[1]; 00288 pseudo_bit_t RcvAvail4[1]; 00289 pseudo_bit_t RcvAvail5[1]; 00290 pseudo_bit_t RcvAvail6[1]; 00291 pseudo_bit_t RcvAvail7[1]; 00292 pseudo_bit_t RcvAvail8[1]; 00293 pseudo_bit_t RcvAvail9[1]; 00294 pseudo_bit_t RcvAvail10[1]; 00295 pseudo_bit_t RcvAvail11[1]; 00296 pseudo_bit_t RcvAvail12[1]; 00297 pseudo_bit_t RcvAvail13[1]; 00298 pseudo_bit_t RcvAvail14[1]; 00299 pseudo_bit_t RcvAvail15[1]; 00300 pseudo_bit_t RcvAvail16[1]; 00301 pseudo_bit_t RcvAvail17[1]; 00302 pseudo_bit_t _unused_0[5]; 00303 pseudo_bit_t SendBufAvail[1]; 00304 pseudo_bit_t SendDone_0[1]; 00305 pseudo_bit_t SendDone_1[1]; 00306 pseudo_bit_t _unused_1[2]; 00307 pseudo_bit_t AssertGPIO[1]; 00308 pseudo_bit_t Err[1]; 00309 pseudo_bit_t Err_0[1]; 00310 pseudo_bit_t Err_1[1]; 00311 pseudo_bit_t RcvUrg0[1]; 00312 pseudo_bit_t RcvUrg1[1]; 00313 pseudo_bit_t RcvUrg2[1]; 00314 pseudo_bit_t RcvUrg3[1]; 00315 pseudo_bit_t RcvUrg4[1]; 00316 pseudo_bit_t RcvUrg5[1]; 00317 pseudo_bit_t RcvUrg6[1]; 00318 pseudo_bit_t RcvUrg7[1]; 00319 pseudo_bit_t RcvUrg8[1]; 00320 pseudo_bit_t RcvUrg9[1]; 00321 pseudo_bit_t RcvUrg10[1]; 00322 pseudo_bit_t RcvUrg11[1]; 00323 pseudo_bit_t RcvUrg12[1]; 00324 pseudo_bit_t RcvUrg13[1]; 00325 pseudo_bit_t RcvUrg14[1]; 00326 pseudo_bit_t RcvUrg15[1]; 00327 pseudo_bit_t RcvUrg16[1]; 00328 pseudo_bit_t RcvUrg17[1]; 00329 pseudo_bit_t _unused_2[6]; 00330 pseudo_bit_t SDmaCleanupDone_0[1]; 00331 pseudo_bit_t SDmaCleanupDone_1[1]; 00332 pseudo_bit_t SDmaIdleInt_0[1]; 00333 pseudo_bit_t SDmaIdleInt_1[1]; 00334 pseudo_bit_t SDmaProgressInt_0[1]; 00335 pseudo_bit_t SDmaProgressInt_1[1]; 00336 pseudo_bit_t SDmaInt_0[1]; 00337 pseudo_bit_t SDmaInt_1[1]; 00338 }; 00339 struct QIB_7322_IntStatus { 00340 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntStatus_pb ); 00341 }; 00342 /* Default value: 0x0000000000000000 */ 00343 00344 #define QIB_7322_IntClear_offset 0x00000078UL 00345 struct QIB_7322_IntClear_pb { 00346 pseudo_bit_t RcvAvail0IntClear[1]; 00347 pseudo_bit_t RcvAvail1IntClear[1]; 00348 pseudo_bit_t RcvAvail2IntClear[1]; 00349 pseudo_bit_t RcvAvail3IntClear[1]; 00350 pseudo_bit_t RcvAvail4IntClear[1]; 00351 pseudo_bit_t RcvAvail5IntClear[1]; 00352 pseudo_bit_t RcvAvail6IntClear[1]; 00353 pseudo_bit_t RcvAvail7IntClear[1]; 00354 pseudo_bit_t RcvAvail8IntClear[1]; 00355 pseudo_bit_t RcvAvail9IntClear[1]; 00356 pseudo_bit_t RcvAvail10IntClear[1]; 00357 pseudo_bit_t RcvAvail11IntClear[1]; 00358 pseudo_bit_t RcvAvail12IntClear[1]; 00359 pseudo_bit_t RcvAvail13IntClear[1]; 00360 pseudo_bit_t RcvAvail14IntClear[1]; 00361 pseudo_bit_t RcvAvail15IntClear[1]; 00362 pseudo_bit_t RcvAvail16IntClear[1]; 00363 pseudo_bit_t RcvAvail17IntClear[1]; 00364 pseudo_bit_t _unused_0[5]; 00365 pseudo_bit_t SendBufAvailIntClear[1]; 00366 pseudo_bit_t SendDoneIntClear_0[1]; 00367 pseudo_bit_t SendDoneIntClear_1[1]; 00368 pseudo_bit_t _unused_1[2]; 00369 pseudo_bit_t AssertGPIOIntClear[1]; 00370 pseudo_bit_t ErrIntClear[1]; 00371 pseudo_bit_t ErrIntClear_0[1]; 00372 pseudo_bit_t ErrIntClear_1[1]; 00373 pseudo_bit_t RcvUrg0IntClear[1]; 00374 pseudo_bit_t RcvUrg1IntClear[1]; 00375 pseudo_bit_t RcvUrg2IntClear[1]; 00376 pseudo_bit_t RcvUrg3IntClear[1]; 00377 pseudo_bit_t RcvUrg4IntClear[1]; 00378 pseudo_bit_t RcvUrg5IntClear[1]; 00379 pseudo_bit_t RcvUrg6IntClear[1]; 00380 pseudo_bit_t RcvUrg7IntClear[1]; 00381 pseudo_bit_t RcvUrg8IntClear[1]; 00382 pseudo_bit_t RcvUrg9IntClear[1]; 00383 pseudo_bit_t RcvUrg10IntClear[1]; 00384 pseudo_bit_t RcvUrg11IntClear[1]; 00385 pseudo_bit_t RcvUrg12IntClear[1]; 00386 pseudo_bit_t RcvUrg13IntClear[1]; 00387 pseudo_bit_t RcvUrg14IntClear[1]; 00388 pseudo_bit_t RcvUrg15IntClear[1]; 00389 pseudo_bit_t RcvUrg16IntClear[1]; 00390 pseudo_bit_t RcvUrg17IntClear[1]; 00391 pseudo_bit_t _unused_2[6]; 00392 pseudo_bit_t SDmaCleanupDoneClear_0[1]; 00393 pseudo_bit_t SDmaCleanupDoneClear_1[1]; 00394 pseudo_bit_t SDmaIdleIntClear_0[1]; 00395 pseudo_bit_t SDmaIdleIntClear_1[1]; 00396 pseudo_bit_t SDmaProgressIntClear_0[1]; 00397 pseudo_bit_t SDmaProgressIntClear_1[1]; 00398 pseudo_bit_t SDmaIntClear_0[1]; 00399 pseudo_bit_t SDmaIntClear_1[1]; 00400 }; 00401 struct QIB_7322_IntClear { 00402 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntClear_pb ); 00403 }; 00404 /* Default value: 0x0000000000000000 */ 00405 00406 #define QIB_7322_ErrMask_offset 0x00000080UL 00407 struct QIB_7322_ErrMask_pb { 00408 pseudo_bit_t _unused_0[12]; 00409 pseudo_bit_t RcvEgrFullErrMask[1]; 00410 pseudo_bit_t RcvHdrFullErrMask[1]; 00411 pseudo_bit_t _unused_1[11]; 00412 pseudo_bit_t SDmaBufMaskDuplicateErrMask[1]; 00413 pseudo_bit_t SDmaWrongPortErrMask[1]; 00414 pseudo_bit_t SendSpecialTriggerErrMask[1]; 00415 pseudo_bit_t _unused_2[7]; 00416 pseudo_bit_t SendArmLaunchErrMask[1]; 00417 pseudo_bit_t SendVLMismatchErrMask[1]; 00418 pseudo_bit_t _unused_3[15]; 00419 pseudo_bit_t RcvContextShareErrMask[1]; 00420 pseudo_bit_t InvalidEEPCmdMask[1]; 00421 pseudo_bit_t _unused_4[1]; 00422 pseudo_bit_t SBufVL15MisUseErrMask[1]; 00423 pseudo_bit_t SDmaVL15ErrMask[1]; 00424 pseudo_bit_t _unused_5[4]; 00425 pseudo_bit_t InvalidAddrErrMask[1]; 00426 pseudo_bit_t HardwareErrMask[1]; 00427 pseudo_bit_t ResetNegatedMask[1]; 00428 }; 00429 struct QIB_7322_ErrMask { 00430 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_pb ); 00431 }; 00432 /* Default value: 0x0000000000000000 */ 00433 00434 #define QIB_7322_ErrStatus_offset 0x00000088UL 00435 struct QIB_7322_ErrStatus_pb { 00436 pseudo_bit_t _unused_0[12]; 00437 pseudo_bit_t RcvEgrFullErr[1]; 00438 pseudo_bit_t RcvHdrFullErr[1]; 00439 pseudo_bit_t _unused_1[11]; 00440 pseudo_bit_t SDmaBufMaskDuplicateErr[1]; 00441 pseudo_bit_t SDmaWrongPortErr[1]; 00442 pseudo_bit_t SendSpecialTriggerErr[1]; 00443 pseudo_bit_t _unused_2[7]; 00444 pseudo_bit_t SendArmLaunchErr[1]; 00445 pseudo_bit_t SendVLMismatchErr[1]; 00446 pseudo_bit_t _unused_3[15]; 00447 pseudo_bit_t RcvContextShareErr[1]; 00448 pseudo_bit_t InvalidEEPCmdErr[1]; 00449 pseudo_bit_t _unused_4[1]; 00450 pseudo_bit_t SBufVL15MisUseErr[1]; 00451 pseudo_bit_t SDmaVL15Err[1]; 00452 pseudo_bit_t _unused_5[4]; 00453 pseudo_bit_t InvalidAddrErr[1]; 00454 pseudo_bit_t HardwareErr[1]; 00455 pseudo_bit_t ResetNegated[1]; 00456 }; 00457 struct QIB_7322_ErrStatus { 00458 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_pb ); 00459 }; 00460 /* Default value: 0x0000000000000000 */ 00461 00462 #define QIB_7322_ErrClear_offset 0x00000090UL 00463 struct QIB_7322_ErrClear_pb { 00464 pseudo_bit_t _unused_0[12]; 00465 pseudo_bit_t RcvEgrFullErrClear[1]; 00466 pseudo_bit_t RcvHdrFullErrClear[1]; 00467 pseudo_bit_t _unused_1[11]; 00468 pseudo_bit_t SDmaBufMaskDuplicateErrClear[1]; 00469 pseudo_bit_t SDmaWrongPortErrClear[1]; 00470 pseudo_bit_t SendSpecialTriggerErrClear[1]; 00471 pseudo_bit_t _unused_2[7]; 00472 pseudo_bit_t SendArmLaunchErrClear[1]; 00473 pseudo_bit_t SendVLMismatchErrMask[1]; 00474 pseudo_bit_t _unused_3[15]; 00475 pseudo_bit_t RcvContextShareErrClear[1]; 00476 pseudo_bit_t InvalidEEPCmdErrClear[1]; 00477 pseudo_bit_t _unused_4[1]; 00478 pseudo_bit_t SBufVL15MisUseErrClear[1]; 00479 pseudo_bit_t SDmaVL15ErrClear[1]; 00480 pseudo_bit_t _unused_5[4]; 00481 pseudo_bit_t InvalidAddrErrClear[1]; 00482 pseudo_bit_t HardwareErrClear[1]; 00483 pseudo_bit_t ResetNegatedClear[1]; 00484 }; 00485 struct QIB_7322_ErrClear { 00486 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_pb ); 00487 }; 00488 /* Default value: 0x0000000000000000 */ 00489 00490 #define QIB_7322_HwErrMask_offset 0x00000098UL 00491 struct QIB_7322_HwErrMask_pb { 00492 pseudo_bit_t _unused_0[11]; 00493 pseudo_bit_t LATriggeredMask[1]; 00494 pseudo_bit_t statusValidNoEopMask_0[1]; 00495 pseudo_bit_t IBCBusFromSPCParityErrMask_0[1]; 00496 pseudo_bit_t statusValidNoEopMask_1[1]; 00497 pseudo_bit_t IBCBusFromSPCParityErrMask_1[1]; 00498 pseudo_bit_t _unused_1[11]; 00499 pseudo_bit_t SDmaMemReadErrMask_0[1]; 00500 pseudo_bit_t SDmaMemReadErrMask_1[1]; 00501 pseudo_bit_t PciePoisonedTLPMask[1]; 00502 pseudo_bit_t PcieCplTimeoutMask[1]; 00503 pseudo_bit_t PCIeBusParityErrMask[3]; 00504 pseudo_bit_t pcie_phy_txParityErr[1]; 00505 pseudo_bit_t _unused_2[13]; 00506 pseudo_bit_t MemoryErrMask[1]; 00507 pseudo_bit_t _unused_3[4]; 00508 pseudo_bit_t TempsenseTholdReachedMask[1]; 00509 pseudo_bit_t PowerOnBISTFailedMask[1]; 00510 pseudo_bit_t PCIESerdesPClkNotDetectMask[1]; 00511 pseudo_bit_t _unused_4[6]; 00512 pseudo_bit_t IBSerdesPClkNotDetectMask_0[1]; 00513 pseudo_bit_t IBSerdesPClkNotDetectMask_1[1]; 00514 }; 00515 struct QIB_7322_HwErrMask { 00516 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrMask_pb ); 00517 }; 00518 /* Default value: 0x0000000000000000 */ 00519 00520 #define QIB_7322_HwErrStatus_offset 0x000000a0UL 00521 struct QIB_7322_HwErrStatus_pb { 00522 pseudo_bit_t _unused_0[11]; 00523 pseudo_bit_t LATriggered[1]; 00524 pseudo_bit_t statusValidNoEop_0[1]; 00525 pseudo_bit_t IBCBusFromSPCParityErr_0[1]; 00526 pseudo_bit_t statusValidNoEop_1[1]; 00527 pseudo_bit_t IBCBusFromSPCParityErr_1[1]; 00528 pseudo_bit_t _unused_1[11]; 00529 pseudo_bit_t SDmaMemReadErr_0[1]; 00530 pseudo_bit_t SDmaMemReadErr_1[1]; 00531 pseudo_bit_t PciePoisonedTLP[1]; 00532 pseudo_bit_t PcieCplTimeout[1]; 00533 pseudo_bit_t PCIeBusParity[3]; 00534 pseudo_bit_t pcie_phy_txParityErr[1]; 00535 pseudo_bit_t _unused_2[13]; 00536 pseudo_bit_t MemoryErr[1]; 00537 pseudo_bit_t _unused_3[4]; 00538 pseudo_bit_t TempsenseTholdReached[1]; 00539 pseudo_bit_t PowerOnBISTFailed[1]; 00540 pseudo_bit_t PCIESerdesPClkNotDetect[1]; 00541 pseudo_bit_t _unused_4[6]; 00542 pseudo_bit_t IBSerdesPClkNotDetect_0[1]; 00543 pseudo_bit_t IBSerdesPClkNotDetect_1[1]; 00544 }; 00545 struct QIB_7322_HwErrStatus { 00546 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrStatus_pb ); 00547 }; 00548 /* Default value: 0x0000000000000000 */ 00549 00550 #define QIB_7322_HwErrClear_offset 0x000000a8UL 00551 struct QIB_7322_HwErrClear_pb { 00552 pseudo_bit_t _unused_0[11]; 00553 pseudo_bit_t LATriggeredClear[1]; 00554 pseudo_bit_t IBCBusToSPCparityErrClear_0[1]; 00555 pseudo_bit_t IBCBusFromSPCParityErrClear_0[1]; 00556 pseudo_bit_t IBCBusToSPCparityErrClear_1[1]; 00557 pseudo_bit_t IBCBusFromSPCParityErrClear_1[1]; 00558 pseudo_bit_t _unused_1[11]; 00559 pseudo_bit_t SDmaMemReadErrClear_0[1]; 00560 pseudo_bit_t SDmaMemReadErrClear_1[1]; 00561 pseudo_bit_t PciePoisonedTLPClear[1]; 00562 pseudo_bit_t PcieCplTimeoutClear[1]; 00563 pseudo_bit_t PCIeBusParityClear[3]; 00564 pseudo_bit_t pcie_phy_txParityErr[1]; 00565 pseudo_bit_t _unused_2[13]; 00566 pseudo_bit_t MemoryErrClear[1]; 00567 pseudo_bit_t _unused_3[4]; 00568 pseudo_bit_t TempsenseTholdReachedClear[1]; 00569 pseudo_bit_t PowerOnBISTFailedClear[1]; 00570 pseudo_bit_t PCIESerdesPClkNotDetectClear[1]; 00571 pseudo_bit_t _unused_4[6]; 00572 pseudo_bit_t IBSerdesPClkNotDetectClear_0[1]; 00573 pseudo_bit_t IBSerdesPClkNotDetectClear_1[1]; 00574 }; 00575 struct QIB_7322_HwErrClear { 00576 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrClear_pb ); 00577 }; 00578 /* Default value: 0x0000000000000000 */ 00579 00580 #define QIB_7322_HwDiagCtrl_offset 0x000000b0UL 00581 struct QIB_7322_HwDiagCtrl_pb { 00582 pseudo_bit_t _unused_0[12]; 00583 pseudo_bit_t ForcestatusValidNoEop_0[1]; 00584 pseudo_bit_t ForceIBCBusFromSPCParityErr_0[1]; 00585 pseudo_bit_t ForcestatusValidNoEop_1[1]; 00586 pseudo_bit_t ForceIBCBusFromSPCParityErr_1[1]; 00587 pseudo_bit_t _unused_1[15]; 00588 pseudo_bit_t forcePCIeBusParity[4]; 00589 pseudo_bit_t _unused_2[25]; 00590 pseudo_bit_t CounterDisable[1]; 00591 pseudo_bit_t CounterWrEnable[1]; 00592 pseudo_bit_t _unused_3[1]; 00593 pseudo_bit_t Diagnostic[1]; 00594 }; 00595 struct QIB_7322_HwDiagCtrl { 00596 PSEUDO_BIT_STRUCT ( struct QIB_7322_HwDiagCtrl_pb ); 00597 }; 00598 /* Default value: 0x0000000000000000 */ 00599 00600 #define QIB_7322_EXTStatus_offset 0x000000c0UL 00601 struct QIB_7322_EXTStatus_pb { 00602 pseudo_bit_t _unused_0[14]; 00603 pseudo_bit_t MemBISTEndTest[1]; 00604 pseudo_bit_t MemBISTDisabled[1]; 00605 pseudo_bit_t _unused_1[32]; 00606 pseudo_bit_t GPIOIn[16]; 00607 }; 00608 struct QIB_7322_EXTStatus { 00609 PSEUDO_BIT_STRUCT ( struct QIB_7322_EXTStatus_pb ); 00610 }; 00611 /* Default value: 0x000000000000X000 */ 00612 00613 #define QIB_7322_EXTCtrl_offset 0x000000c8UL 00614 struct QIB_7322_EXTCtrl_pb { 00615 pseudo_bit_t LEDPort0YellowOn[1]; 00616 pseudo_bit_t LEDPort0GreenOn[1]; 00617 pseudo_bit_t LEDPort1YellowOn[1]; 00618 pseudo_bit_t LEDPort1GreenOn[1]; 00619 pseudo_bit_t _unused_0[28]; 00620 pseudo_bit_t GPIOInvert[16]; 00621 pseudo_bit_t GPIOOe[16]; 00622 }; 00623 struct QIB_7322_EXTCtrl { 00624 PSEUDO_BIT_STRUCT ( struct QIB_7322_EXTCtrl_pb ); 00625 }; 00626 /* Default value: 0x0000000000000000 */ 00627 00628 #define QIB_7322_GPIODebugSelReg_offset 0x000000d8UL 00629 struct QIB_7322_GPIODebugSelReg_pb { 00630 pseudo_bit_t GPIOSourceSelDebug[16]; 00631 pseudo_bit_t SelPulse[16]; 00632 pseudo_bit_t _unused_0[32]; 00633 }; 00634 struct QIB_7322_GPIODebugSelReg { 00635 PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIODebugSelReg_pb ); 00636 }; 00637 /* Default value: 0x0000000000000000 */ 00638 00639 #define QIB_7322_GPIOOut_offset 0x000000e0UL 00640 /* Default value: 0x0000000000000000 */ 00641 00642 #define QIB_7322_GPIOMask_offset 0x000000e8UL 00643 /* Default value: 0x0000000000000000 */ 00644 00645 #define QIB_7322_GPIOStatus_offset 0x000000f0UL 00646 /* Default value: 0x0000000000000000 */ 00647 00648 #define QIB_7322_GPIOClear_offset 0x000000f8UL 00649 /* Default value: 0x0000000000000000 */ 00650 00651 #define QIB_7322_RcvCtrl_offset 0x00000100UL 00652 struct QIB_7322_RcvCtrl_pb { 00653 pseudo_bit_t dontDropRHQFull[18]; 00654 pseudo_bit_t _unused_0[2]; 00655 pseudo_bit_t IntrAvail[18]; 00656 pseudo_bit_t _unused_1[3]; 00657 pseudo_bit_t ContextCfg[2]; 00658 pseudo_bit_t TidFlowEnable[1]; 00659 pseudo_bit_t XrcTypeCode[3]; 00660 pseudo_bit_t TailUpd[1]; 00661 pseudo_bit_t TidReDirect[16]; 00662 }; 00663 struct QIB_7322_RcvCtrl { 00664 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_pb ); 00665 }; 00666 /* Default value: 0x0000000000000000 */ 00667 00668 #define QIB_7322_RcvHdrSize_offset 0x00000110UL 00669 /* Default value: 0x0000000000000000 */ 00670 00671 #define QIB_7322_RcvHdrCnt_offset 0x00000118UL 00672 /* Default value: 0x0000000000000000 */ 00673 00674 #define QIB_7322_RcvHdrEntSize_offset 0x00000120UL 00675 /* Default value: 0x0000000000000000 */ 00676 00677 #define QIB_7322_RcvTIDBase_offset 0x00000128UL 00678 /* Default value: 0x0000000000050000 */ 00679 00680 #define QIB_7322_RcvTIDCnt_offset 0x00000130UL 00681 /* Default value: 0x0000000000000200 */ 00682 00683 #define QIB_7322_RcvEgrBase_offset 0x00000138UL 00684 /* Default value: 0x0000000000014000 */ 00685 00686 #define QIB_7322_RcvEgrCnt_offset 0x00000140UL 00687 /* Default value: 0x0000000000001000 */ 00688 00689 #define QIB_7322_RcvBufBase_offset 0x00000148UL 00690 /* Default value: 0x0000000000080000 */ 00691 00692 #define QIB_7322_RcvBufSize_offset 0x00000150UL 00693 /* Default value: 0x0000000000005000 */ 00694 00695 #define QIB_7322_RxIntMemBase_offset 0x00000158UL 00696 /* Default value: 0x0000000000077000 */ 00697 00698 #define QIB_7322_RxIntMemSize_offset 0x00000160UL 00699 /* Default value: 0x0000000000007000 */ 00700 00701 #define QIB_7322_encryption_key_low_offset 0x00000180UL 00702 /* Default value: 0x0000000000000000 */ 00703 00704 #define QIB_7322_encryption_key_high_offset 0x00000188UL 00705 /* Default value: 0x0000000000000000 */ 00706 00707 #define QIB_7322_feature_mask_offset 0x00000190UL 00708 /* Default value: 0x00000000000000XX */ 00709 00710 #define QIB_7322_active_feature_mask_offset 0x00000198UL 00711 struct QIB_7322_active_feature_mask_pb { 00712 pseudo_bit_t Port0_SDR_Enabled[1]; 00713 pseudo_bit_t Port0_DDR_Enabled[1]; 00714 pseudo_bit_t Port0_QDR_Enabled[1]; 00715 pseudo_bit_t Port1_SDR_Enabled[1]; 00716 pseudo_bit_t Port1_DDR_Enabled[1]; 00717 pseudo_bit_t Port1_QDR_Enabled[1]; 00718 pseudo_bit_t _unused_0[58]; 00719 }; 00720 struct QIB_7322_active_feature_mask { 00721 PSEUDO_BIT_STRUCT ( struct QIB_7322_active_feature_mask_pb ); 00722 }; 00723 /* Default value: 0x00000000000000XX */ 00724 00725 #define QIB_7322_SendCtrl_offset 0x000001c0UL 00726 struct QIB_7322_SendCtrl_pb { 00727 pseudo_bit_t _unused_0[1]; 00728 pseudo_bit_t SendIntBufAvail[1]; 00729 pseudo_bit_t SendBufAvailUpd[1]; 00730 pseudo_bit_t _unused_1[1]; 00731 pseudo_bit_t SpecialTriggerEn[1]; 00732 pseudo_bit_t _unused_2[11]; 00733 pseudo_bit_t DisarmSendBuf[8]; 00734 pseudo_bit_t AvailUpdThld[5]; 00735 pseudo_bit_t SendBufAvailPad64Byte[1]; 00736 pseudo_bit_t _unused_3[1]; 00737 pseudo_bit_t Disarm[1]; 00738 pseudo_bit_t _unused_4[32]; 00739 }; 00740 struct QIB_7322_SendCtrl { 00741 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_pb ); 00742 }; 00743 /* Default value: 0x0000000000000000 */ 00744 00745 #define QIB_7322_SendBufBase_offset 0x000001c8UL 00746 struct QIB_7322_SendBufBase_pb { 00747 pseudo_bit_t BaseAddr_SmallPIO[21]; 00748 pseudo_bit_t _unused_0[11]; 00749 pseudo_bit_t BaseAddr_LargePIO[21]; 00750 pseudo_bit_t _unused_1[11]; 00751 }; 00752 struct QIB_7322_SendBufBase { 00753 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufBase_pb ); 00754 }; 00755 /* Default value: 0x0018000000100000 */ 00756 00757 #define QIB_7322_SendBufSize_offset 0x000001d0UL 00758 struct QIB_7322_SendBufSize_pb { 00759 pseudo_bit_t Size_SmallPIO[12]; 00760 pseudo_bit_t _unused_0[20]; 00761 pseudo_bit_t Size_LargePIO[13]; 00762 pseudo_bit_t _unused_1[19]; 00763 }; 00764 struct QIB_7322_SendBufSize { 00765 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufSize_pb ); 00766 }; 00767 /* Default value: 0x0000108000000880 */ 00768 00769 #define QIB_7322_SendBufCnt_offset 0x000001d8UL 00770 struct QIB_7322_SendBufCnt_pb { 00771 pseudo_bit_t Num_SmallBuffers[9]; 00772 pseudo_bit_t _unused_0[23]; 00773 pseudo_bit_t Num_LargeBuffers[6]; 00774 pseudo_bit_t _unused_1[26]; 00775 }; 00776 struct QIB_7322_SendBufCnt { 00777 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufCnt_pb ); 00778 }; 00779 /* Default value: 0x0000002000000080 */ 00780 00781 #define QIB_7322_SendBufAvailAddr_offset 0x000001e0UL 00782 struct QIB_7322_SendBufAvailAddr_pb { 00783 pseudo_bit_t _unused_0[6]; 00784 pseudo_bit_t SendBufAvailAddr[34]; 00785 pseudo_bit_t _unused_1[24]; 00786 }; 00787 struct QIB_7322_SendBufAvailAddr { 00788 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvailAddr_pb ); 00789 }; 00790 /* Default value: 0x0000000000000000 */ 00791 00792 #define QIB_7322_TxIntMemBase_offset 0x000001e8UL 00793 /* Default value: 0x0000000000064000 */ 00794 00795 #define QIB_7322_TxIntMemSize_offset 0x000001f0UL 00796 /* Default value: 0x000000000000C000 */ 00797 00798 #define QIB_7322_SendBufErr0_offset 0x00000240UL 00799 struct QIB_7322_SendBufErr0_pb { 00800 pseudo_bit_t SendBufErr_63_0[64]; 00801 }; 00802 struct QIB_7322_SendBufErr0 { 00803 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufErr0_pb ); 00804 }; 00805 /* Default value: 0x0000000000000000 */ 00806 00807 #define QIB_7322_AvailUpdCount_offset 0x00000268UL 00808 struct QIB_7322_AvailUpdCount_pb { 00809 pseudo_bit_t AvailUpdCount[5]; 00810 pseudo_bit_t _unused_0[59]; 00811 }; 00812 struct QIB_7322_AvailUpdCount { 00813 PSEUDO_BIT_STRUCT ( struct QIB_7322_AvailUpdCount_pb ); 00814 }; 00815 /* Default value: 0x0000000000000000 */ 00816 00817 #define QIB_7322_RcvHdrAddr0_offset 0x00000280UL 00818 struct QIB_7322_RcvHdrAddr0_pb { 00819 pseudo_bit_t _unused_0[2]; 00820 pseudo_bit_t RcvHdrAddr[38]; 00821 pseudo_bit_t _unused_1[24]; 00822 }; 00823 struct QIB_7322_RcvHdrAddr0 { 00824 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrAddr0_pb ); 00825 }; 00826 /* Default value: 0x0000000000000000 */ 00827 00828 #define QIB_7322_RcvHdrTailAddr0_offset 0x00000340UL 00829 struct QIB_7322_RcvHdrTailAddr0_pb { 00830 pseudo_bit_t _unused_0[2]; 00831 pseudo_bit_t RcvHdrTailAddr[38]; 00832 pseudo_bit_t _unused_1[24]; 00833 }; 00834 struct QIB_7322_RcvHdrTailAddr0 { 00835 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrTailAddr0_pb ); 00836 }; 00837 /* Default value: 0x0000000000000000 */ 00838 00839 #define QIB_7322_EEPCtlStat_offset 0x000003e8UL 00840 struct QIB_7322_EEPCtlStat_pb { 00841 pseudo_bit_t EPAccEn[2]; 00842 pseudo_bit_t EPReset[1]; 00843 pseudo_bit_t ByteProg[1]; 00844 pseudo_bit_t PageMode[1]; 00845 pseudo_bit_t LstDatWr[1]; 00846 pseudo_bit_t CmdWrErr[1]; 00847 pseudo_bit_t _unused_0[24]; 00848 pseudo_bit_t CtlrStat[1]; 00849 pseudo_bit_t _unused_1[32]; 00850 }; 00851 struct QIB_7322_EEPCtlStat { 00852 PSEUDO_BIT_STRUCT ( struct QIB_7322_EEPCtlStat_pb ); 00853 }; 00854 /* Default value: 0x0000000000000002 */ 00855 00856 #define QIB_7322_EEPAddrCmd_offset 0x000003f0UL 00857 struct QIB_7322_EEPAddrCmd_pb { 00858 pseudo_bit_t EPAddr[24]; 00859 pseudo_bit_t EPCmd[8]; 00860 pseudo_bit_t _unused_0[32]; 00861 }; 00862 struct QIB_7322_EEPAddrCmd { 00863 PSEUDO_BIT_STRUCT ( struct QIB_7322_EEPAddrCmd_pb ); 00864 }; 00865 /* Default value: 0x0000000000000000 */ 00866 00867 #define QIB_7322_EEPData_offset 0x000003f8UL 00868 /* Default value: 0x0000000000000000 */ 00869 00870 #define QIB_7322_efuse_control_reg_offset 0x00000410UL 00871 struct QIB_7322_efuse_control_reg_pb { 00872 pseudo_bit_t address[11]; 00873 pseudo_bit_t last_program_address[11]; 00874 pseudo_bit_t operation[2]; 00875 pseudo_bit_t start_operation[1]; 00876 pseudo_bit_t _unused_0[4]; 00877 pseudo_bit_t req_err[1]; 00878 pseudo_bit_t read_data_valid[1]; 00879 pseudo_bit_t rdy[1]; 00880 pseudo_bit_t _unused_1[32]; 00881 }; 00882 struct QIB_7322_efuse_control_reg { 00883 PSEUDO_BIT_STRUCT ( struct QIB_7322_efuse_control_reg_pb ); 00884 }; 00885 /* Default value: 0x0000000080000000 */ 00886 00887 #define QIB_7322_efuse_data_reg_offset 0x00000418UL 00888 /* Default value: 0x0000000000000000 */ 00889 00890 #define QIB_7322_voltage_margin_reg_offset 0x00000428UL 00891 struct QIB_7322_voltage_margin_reg_pb { 00892 pseudo_bit_t voltage_margin_settings_enable[1]; 00893 pseudo_bit_t voltage_margin_settings[2]; 00894 pseudo_bit_t _unused_0[61]; 00895 }; 00896 struct QIB_7322_voltage_margin_reg { 00897 PSEUDO_BIT_STRUCT ( struct QIB_7322_voltage_margin_reg_pb ); 00898 }; 00899 /* Default value: 0x0000000000000000 */ 00900 00901 #define QIB_7322_VTSense_reg_offset 0x00000430UL 00902 struct QIB_7322_VTSense_reg_pb { 00903 pseudo_bit_t temp_sense_select[3]; 00904 pseudo_bit_t adc_mode[1]; 00905 pseudo_bit_t start_busy[1]; 00906 pseudo_bit_t power_down[1]; 00907 pseudo_bit_t threshold[10]; 00908 pseudo_bit_t sensor_output_data[10]; 00909 pseudo_bit_t _unused_0[1]; 00910 pseudo_bit_t threshold_limbit[1]; 00911 pseudo_bit_t _unused_1[3]; 00912 pseudo_bit_t output_valid[1]; 00913 pseudo_bit_t _unused_2[32]; 00914 }; 00915 struct QIB_7322_VTSense_reg { 00916 PSEUDO_BIT_STRUCT ( struct QIB_7322_VTSense_reg_pb ); 00917 }; 00918 /* Default value: 0x0000000000000020 */ 00919 00920 #define QIB_7322_procmon_reg_offset 0x00000438UL 00921 struct QIB_7322_procmon_reg_pb { 00922 pseudo_bit_t ring_osc_select[3]; 00923 pseudo_bit_t _unused_0[12]; 00924 pseudo_bit_t start_counter[1]; 00925 pseudo_bit_t procmon_count[12]; 00926 pseudo_bit_t _unused_1[3]; 00927 pseudo_bit_t procmon_count_valid[1]; 00928 pseudo_bit_t _unused_2[32]; 00929 }; 00930 struct QIB_7322_procmon_reg { 00931 PSEUDO_BIT_STRUCT ( struct QIB_7322_procmon_reg_pb ); 00932 }; 00933 /* Default value: 0x0000000000000000 */ 00934 00935 #define QIB_7322_PcieRbufTestReg0_offset 0x00000440UL 00936 /* Default value: 0x0000000000000000 */ 00937 00938 #define QIB_7322_ahb_access_ctrl_offset 0x00000460UL 00939 struct QIB_7322_ahb_access_ctrl_pb { 00940 pseudo_bit_t sw_ahb_sel[1]; 00941 pseudo_bit_t sw_sel_ahb_trgt[2]; 00942 pseudo_bit_t _unused_0[61]; 00943 }; 00944 struct QIB_7322_ahb_access_ctrl { 00945 PSEUDO_BIT_STRUCT ( struct QIB_7322_ahb_access_ctrl_pb ); 00946 }; 00947 /* Default value: 0x0000000000000000 */ 00948 00949 #define QIB_7322_ahb_transaction_reg_offset 0x00000468UL 00950 struct QIB_7322_ahb_transaction_reg_pb { 00951 pseudo_bit_t _unused_0[16]; 00952 pseudo_bit_t ahb_address[11]; 00953 pseudo_bit_t write_not_read[1]; 00954 pseudo_bit_t _unused_1[2]; 00955 pseudo_bit_t ahb_req_err[1]; 00956 pseudo_bit_t ahb_rdy[1]; 00957 pseudo_bit_t ahb_data[32]; 00958 }; 00959 struct QIB_7322_ahb_transaction_reg { 00960 PSEUDO_BIT_STRUCT ( struct QIB_7322_ahb_transaction_reg_pb ); 00961 }; 00962 /* Default value: 0x0000000080000000 */ 00963 00964 #define QIB_7322_SPC_JTAG_ACCESS_REG_offset 0x00000470UL 00965 struct QIB_7322_SPC_JTAG_ACCESS_REG_pb { 00966 pseudo_bit_t rdy[1]; 00967 pseudo_bit_t tdo[1]; 00968 pseudo_bit_t tdi[1]; 00969 pseudo_bit_t opcode[2]; 00970 pseudo_bit_t bist_en[5]; 00971 pseudo_bit_t SPC_JTAG_ACCESS_EN[1]; 00972 pseudo_bit_t _unused_0[53]; 00973 }; 00974 struct QIB_7322_SPC_JTAG_ACCESS_REG { 00975 PSEUDO_BIT_STRUCT ( struct QIB_7322_SPC_JTAG_ACCESS_REG_pb ); 00976 }; 00977 /* Default value: 0x0000000000000001 */ 00978 00979 #define QIB_7322_LAControlReg_offset 0x00000478UL 00980 struct QIB_7322_LAControlReg_pb { 00981 pseudo_bit_t Finished[1]; 00982 pseudo_bit_t Address[9]; 00983 pseudo_bit_t Mode[2]; 00984 pseudo_bit_t Delay[20]; 00985 pseudo_bit_t Finished_sc[1]; 00986 pseudo_bit_t Address_sc[9]; 00987 pseudo_bit_t Mode_sc[2]; 00988 pseudo_bit_t Delay_sc[20]; 00989 }; 00990 struct QIB_7322_LAControlReg { 00991 PSEUDO_BIT_STRUCT ( struct QIB_7322_LAControlReg_pb ); 00992 }; 00993 /* Default value: 0x0000000100000001 */ 00994 00995 #define QIB_7322_PcieRhdrTestReg0_offset 0x00000480UL 00996 /* Default value: 0x0000000000000000 */ 00997 00998 #define QIB_7322_SendCheckMask0_offset 0x000004c0UL 00999 struct QIB_7322_SendCheckMask0_pb { 01000 pseudo_bit_t SendCheckMask_63_32[64]; 01001 }; 01002 struct QIB_7322_SendCheckMask0 { 01003 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckMask0_pb ); 01004 }; 01005 /* Default value: 0x0000000000000000 */ 01006 01007 #define QIB_7322_SendGRHCheckMask0_offset 0x000004e0UL 01008 struct QIB_7322_SendGRHCheckMask0_pb { 01009 pseudo_bit_t SendGRHCheckMask_63_32[64]; 01010 }; 01011 struct QIB_7322_SendGRHCheckMask0 { 01012 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendGRHCheckMask0_pb ); 01013 }; 01014 /* Default value: 0x0000000000000000 */ 01015 01016 #define QIB_7322_SendIBPacketMask0_offset 0x00000500UL 01017 struct QIB_7322_SendIBPacketMask0_pb { 01018 pseudo_bit_t SendIBPacketMask_63_32[64]; 01019 }; 01020 struct QIB_7322_SendIBPacketMask0 { 01021 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBPacketMask0_pb ); 01022 }; 01023 /* Default value: 0x0000000000000000 */ 01024 01025 #define QIB_7322_IntRedirect0_offset 0x00000540UL 01026 struct QIB_7322_IntRedirect0_pb { 01027 pseudo_bit_t vec0[5]; 01028 pseudo_bit_t vec1[5]; 01029 pseudo_bit_t vec2[5]; 01030 pseudo_bit_t vec3[5]; 01031 pseudo_bit_t vec4[5]; 01032 pseudo_bit_t vec5[5]; 01033 pseudo_bit_t vec6[5]; 01034 pseudo_bit_t vec7[5]; 01035 pseudo_bit_t vec8[5]; 01036 pseudo_bit_t vec9[5]; 01037 pseudo_bit_t vec10[5]; 01038 pseudo_bit_t vec11[5]; 01039 pseudo_bit_t _unused_0[4]; 01040 }; 01041 struct QIB_7322_IntRedirect0 { 01042 PSEUDO_BIT_STRUCT ( struct QIB_7322_IntRedirect0_pb ); 01043 }; 01044 /* Default value: 0x0000000000000000 */ 01045 01046 #define QIB_7322_Int_Granted_offset 0x00000570UL 01047 /* Default value: 0x0000000000000000 */ 01048 01049 #define QIB_7322_vec_clr_without_int_offset 0x00000578UL 01050 /* Default value: 0x0000000000000000 */ 01051 01052 #define QIB_7322_DCACtrlA_offset 0x00000580UL 01053 struct QIB_7322_DCACtrlA_pb { 01054 pseudo_bit_t RcvHdrqDCAEnable[1]; 01055 pseudo_bit_t EagerDCAEnable[1]; 01056 pseudo_bit_t RcvTailUpdDCAEnable[1]; 01057 pseudo_bit_t SendDMAHead0DCAEnable[1]; 01058 pseudo_bit_t SendDMAHead1DCAEnable[1]; 01059 pseudo_bit_t _unused_0[59]; 01060 }; 01061 struct QIB_7322_DCACtrlA { 01062 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlA_pb ); 01063 }; 01064 /* Default value: 0x0000000000000000 */ 01065 01066 #define QIB_7322_DCACtrlB_offset 0x00000588UL 01067 struct QIB_7322_DCACtrlB_pb { 01068 pseudo_bit_t RcvHdrq0DCAOPH[8]; 01069 pseudo_bit_t RcvHdrq0DCAXfrCnt[6]; 01070 pseudo_bit_t RcvHdrq1DCAOPH[8]; 01071 pseudo_bit_t RcvHdrq1DCAXfrCnt[6]; 01072 pseudo_bit_t _unused_0[4]; 01073 pseudo_bit_t RcvHdrq2DCAOPH[8]; 01074 pseudo_bit_t RcvHdrq2DCAXfrCnt[6]; 01075 pseudo_bit_t RcvHdrq3DCAOPH[8]; 01076 pseudo_bit_t RcvHdrq3DCAXfrCnt[6]; 01077 pseudo_bit_t _unused_1[4]; 01078 }; 01079 struct QIB_7322_DCACtrlB { 01080 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlB_pb ); 01081 }; 01082 /* Default value: 0x0000000000000000 */ 01083 01084 #define QIB_7322_DCACtrlC_offset 0x00000590UL 01085 struct QIB_7322_DCACtrlC_pb { 01086 pseudo_bit_t RcvHdrq4DCAOPH[8]; 01087 pseudo_bit_t RcvHdrq4DCAXfrCnt[6]; 01088 pseudo_bit_t RcvHdrq5DCAOPH[8]; 01089 pseudo_bit_t RcvHdrq5DCAXfrCnt[6]; 01090 pseudo_bit_t _unused_0[4]; 01091 pseudo_bit_t RcvHdrq6DCAOPH[8]; 01092 pseudo_bit_t RcvHdrq6DCAXfrCnt[6]; 01093 pseudo_bit_t RcvHdrq7DCAOPH[8]; 01094 pseudo_bit_t RcvHdrq7DCAXfrCnt[6]; 01095 pseudo_bit_t _unused_1[4]; 01096 }; 01097 struct QIB_7322_DCACtrlC { 01098 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlC_pb ); 01099 }; 01100 /* Default value: 0x0000000000000000 */ 01101 01102 #define QIB_7322_DCACtrlD_offset 0x00000598UL 01103 struct QIB_7322_DCACtrlD_pb { 01104 pseudo_bit_t RcvHdrq8DCAOPH[8]; 01105 pseudo_bit_t RcvHdrq8DCAXfrCnt[6]; 01106 pseudo_bit_t RcvHdrq9DCAOPH[8]; 01107 pseudo_bit_t RcvHdrq9DCAXfrCnt[6]; 01108 pseudo_bit_t _unused_0[4]; 01109 pseudo_bit_t RcvHdrq10DCAOPH[8]; 01110 pseudo_bit_t RcvHdrq10DCAXfrCnt[6]; 01111 pseudo_bit_t RcvHdrq11DCAOPH[8]; 01112 pseudo_bit_t RcvHdrq11DCAXfrCnt[6]; 01113 pseudo_bit_t _unused_1[4]; 01114 }; 01115 struct QIB_7322_DCACtrlD { 01116 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlD_pb ); 01117 }; 01118 /* Default value: 0x0000000000000000 */ 01119 01120 #define QIB_7322_DCACtrlE_offset 0x000005a0UL 01121 struct QIB_7322_DCACtrlE_pb { 01122 pseudo_bit_t RcvHdrq12DCAOPH[8]; 01123 pseudo_bit_t RcvHdrq12DCAXfrCnt[6]; 01124 pseudo_bit_t RcvHdrq13DCAOPH[8]; 01125 pseudo_bit_t RcvHdrq13DCAXfrCnt[6]; 01126 pseudo_bit_t _unused_0[4]; 01127 pseudo_bit_t RcvHdrq14DCAOPH[8]; 01128 pseudo_bit_t RcvHdrq14DCAXfrCnt[6]; 01129 pseudo_bit_t RcvHdrq15DCAOPH[8]; 01130 pseudo_bit_t RcvHdrq15DCAXfrCnt[6]; 01131 pseudo_bit_t _unused_1[4]; 01132 }; 01133 struct QIB_7322_DCACtrlE { 01134 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlE_pb ); 01135 }; 01136 /* Default value: 0x0000000000000000 */ 01137 01138 #define QIB_7322_DCACtrlF_offset 0x000005a8UL 01139 struct QIB_7322_DCACtrlF_pb { 01140 pseudo_bit_t RcvHdrq16DCAOPH[8]; 01141 pseudo_bit_t RcvHdrq16DCAXfrCnt[6]; 01142 pseudo_bit_t RcvHdrq17DCAOPH[8]; 01143 pseudo_bit_t RcvHdrq17DCAXfrCnt[6]; 01144 pseudo_bit_t _unused_0[4]; 01145 pseudo_bit_t SendDma0DCAOPH[8]; 01146 pseudo_bit_t SendDma1DCAOPH[8]; 01147 pseudo_bit_t _unused_1[16]; 01148 }; 01149 struct QIB_7322_DCACtrlF { 01150 PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlF_pb ); 01151 }; 01152 /* Default value: 0x0000000000000000 */ 01153 01154 #define QIB_7322_MemErrCtrlA_offset 0x00000600UL 01155 struct QIB_7322_MemErrCtrlA_pb { 01156 pseudo_bit_t FSSUncErrRcvBuf_0[1]; 01157 pseudo_bit_t FSSUncErrRcvFlags_0[1]; 01158 pseudo_bit_t FSSUncErrLookupiqBuf_0[1]; 01159 pseudo_bit_t FSSUncErrRcvDMAHdrBuf_0[1]; 01160 pseudo_bit_t FSSUncErrRcvDMADataBuf_0[1]; 01161 pseudo_bit_t FSSUncErrRcvBuf_1[1]; 01162 pseudo_bit_t FSSUncErrRcvFlags_1[1]; 01163 pseudo_bit_t FSSUncErrLookupiqBuf_1[1]; 01164 pseudo_bit_t FSSUncErrRcvDMAHdrBuf_1[1]; 01165 pseudo_bit_t FSSUncErrRcvDMADataBuf_1[1]; 01166 pseudo_bit_t FSSUncErrRcvTIDArray[1]; 01167 pseudo_bit_t FSSUncErrRcvEgrArray[1]; 01168 pseudo_bit_t _unused_0[3]; 01169 pseudo_bit_t FSSUncErrSendBufVL15[1]; 01170 pseudo_bit_t FSSUncErrSendBufMain[1]; 01171 pseudo_bit_t FSSUncErrSendBufExtra[1]; 01172 pseudo_bit_t FSSUncErrSendPbcArray[1]; 01173 pseudo_bit_t FSSUncErrSendLaFIFO0_0[1]; 01174 pseudo_bit_t FSSUncErrSendLaFIFO1_0[1]; 01175 pseudo_bit_t FSSUncErrSendLaFIFO2_0[1]; 01176 pseudo_bit_t FSSUncErrSendLaFIFO3_0[1]; 01177 pseudo_bit_t FSSUncErrSendLaFIFO4_0[1]; 01178 pseudo_bit_t FSSUncErrSendLaFIFO5_0[1]; 01179 pseudo_bit_t FSSUncErrSendLaFIFO6_0[1]; 01180 pseudo_bit_t FSSUncErrSendLaFIFO7_0[1]; 01181 pseudo_bit_t FSSUncErrSendLaFIFO0_1[1]; 01182 pseudo_bit_t FSSUncErrSendLaFIFO1_1[1]; 01183 pseudo_bit_t FSSUncErrSendLaFIFO2_1[1]; 01184 pseudo_bit_t FSSUncErrSendLaFIFO3_1[1]; 01185 pseudo_bit_t FSSUncErrSendLaFIFO4_1[1]; 01186 pseudo_bit_t FSSUncErrSendLaFIFO5_1[1]; 01187 pseudo_bit_t FSSUncErrSendLaFIFO6_1[1]; 01188 pseudo_bit_t FSSUncErrSendLaFIFO7_1[1]; 01189 pseudo_bit_t FSSUncErrSendRmFIFO_0[1]; 01190 pseudo_bit_t FSSUncErrSendRmFIFO_1[1]; 01191 pseudo_bit_t _unused_1[11]; 01192 pseudo_bit_t FSSUncErrPCIeRetryBuf[1]; 01193 pseudo_bit_t FSSUncErrPCIePostHdrBuf[1]; 01194 pseudo_bit_t FSSUncErrPCIePostDataBuf[1]; 01195 pseudo_bit_t FSSUncErrPCIeCompHdrBuf[1]; 01196 pseudo_bit_t FSSUncErrPCIeCompDataBuf[1]; 01197 pseudo_bit_t FSSUncErrMsixTable0[1]; 01198 pseudo_bit_t FSSUncErrMsixTable1[1]; 01199 pseudo_bit_t FSSUncErrMsixTable2[1]; 01200 pseudo_bit_t _unused_2[4]; 01201 pseudo_bit_t SwapEccDataMsixBits[1]; 01202 pseudo_bit_t SwapEccDataExtraBits[1]; 01203 pseudo_bit_t DisableEccCorrection[1]; 01204 pseudo_bit_t SwapEccDataBits[1]; 01205 }; 01206 struct QIB_7322_MemErrCtrlA { 01207 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemErrCtrlA_pb ); 01208 }; 01209 /* Default value: 0x0000000000000000 */ 01210 01211 #define QIB_7322_MemErrCtrlB_offset 0x00000608UL 01212 struct QIB_7322_MemErrCtrlB_pb { 01213 pseudo_bit_t FSSCorErrRcvBuf_0[1]; 01214 pseudo_bit_t FSSCorErrRcvFlags_0[1]; 01215 pseudo_bit_t FSSCorErrLookupiqBuf_0[1]; 01216 pseudo_bit_t FSSCorErrRcvDMAHdrBuf_0[1]; 01217 pseudo_bit_t FSSCorErrRcvDMADataBuf_0[1]; 01218 pseudo_bit_t FSSCorErrRcvBuf_1[1]; 01219 pseudo_bit_t FSSCorErrRcvFlags_1[1]; 01220 pseudo_bit_t FSSCorErrLookupiqBuf_1[1]; 01221 pseudo_bit_t FSSCorErrRcvDMAHdrBuf_1[1]; 01222 pseudo_bit_t FSSCorErrRcvDMADataBuf_1[1]; 01223 pseudo_bit_t FSSCorErrRcvTIDArray[1]; 01224 pseudo_bit_t FSSCorErrRcvEgrArray[1]; 01225 pseudo_bit_t _unused_0[3]; 01226 pseudo_bit_t FSSCorErrSendBufVL15[1]; 01227 pseudo_bit_t FSSCorErrSendBufMain[1]; 01228 pseudo_bit_t FSSCorErrSendBufExtra[1]; 01229 pseudo_bit_t FSSCorErrSendPbcArray[1]; 01230 pseudo_bit_t FSSCorErrSendLaFIFO0_0[1]; 01231 pseudo_bit_t FSSCorErrSendLaFIFO1_0[1]; 01232 pseudo_bit_t FSSCorErrSendLaFIFO2_0[1]; 01233 pseudo_bit_t FSSCorErrSendLaFIFO3_0[1]; 01234 pseudo_bit_t FSSCorErrSendLaFIFO4_0[1]; 01235 pseudo_bit_t FSSCorErrSendLaFIFO5_0[1]; 01236 pseudo_bit_t FSSCorErrSendLaFIFO6_0[1]; 01237 pseudo_bit_t FSSCorErrSendLaFIFO7_0[1]; 01238 pseudo_bit_t FSSCorErrSendLaFIFO0_1[1]; 01239 pseudo_bit_t FSSCorErrSendLaFIFO1_1[1]; 01240 pseudo_bit_t FSSCorErrSendLaFIFO2_1[1]; 01241 pseudo_bit_t FSSCorErrSendLaFIFO3_1[1]; 01242 pseudo_bit_t FSSCorErrSendLaFIFO4_1[1]; 01243 pseudo_bit_t FSSCorErrSendLaFIFO5_1[1]; 01244 pseudo_bit_t FSSCorErrSendLaFIFO6_1[1]; 01245 pseudo_bit_t FSSCorErrSendLaFIFO7_1[1]; 01246 pseudo_bit_t FSSCorErrSendRmFIFO_0[1]; 01247 pseudo_bit_t FSSCorErrSendRmFIFO_1[1]; 01248 pseudo_bit_t _unused_1[11]; 01249 pseudo_bit_t FSSCorErrPCIeRetryBuf[1]; 01250 pseudo_bit_t FSSCorErrPCIePostHdrBuf[1]; 01251 pseudo_bit_t FSSCorErrPCIePostDataBuf[1]; 01252 pseudo_bit_t FSSCorErrPCIeCompHdrBuf[1]; 01253 pseudo_bit_t FSSCorErrPCIeCompDataBuf[1]; 01254 pseudo_bit_t FSSCorErrMsixTable0[1]; 01255 pseudo_bit_t FSSCorErrMsixTable1[1]; 01256 pseudo_bit_t FSSCorErrMsixTable2[1]; 01257 pseudo_bit_t _unused_2[8]; 01258 }; 01259 struct QIB_7322_MemErrCtrlB { 01260 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemErrCtrlB_pb ); 01261 }; 01262 /* Default value: 0x0000000000000000 */ 01263 01264 #define QIB_7322_MemMultiUnCorErrMask_offset 0x00000610UL 01265 struct QIB_7322_MemMultiUnCorErrMask_pb { 01266 pseudo_bit_t MulUncErrMskRcvBuf_0[1]; 01267 pseudo_bit_t MulUncErrMskRcvFlags_0[1]; 01268 pseudo_bit_t MulUncErrMskLookupiqBuf_0[1]; 01269 pseudo_bit_t MulUncErrMskRcvDMAHdrBuf_0[1]; 01270 pseudo_bit_t MulUncErrMskRcvDMADataBuf_0[1]; 01271 pseudo_bit_t MulUncErrMskRcvBuf_1[1]; 01272 pseudo_bit_t MulUncErrMskRcvFlags_1[1]; 01273 pseudo_bit_t MulUncErrMskLookupiqBuf_1[1]; 01274 pseudo_bit_t MulUncErrMskRcvDMAHdrBuf_1[1]; 01275 pseudo_bit_t MulUncErrMskRcvDMADataBuf_1[1]; 01276 pseudo_bit_t MulUncErrMskRcvTIDArray[1]; 01277 pseudo_bit_t MulUncErrMskRcvEgrArray[1]; 01278 pseudo_bit_t _unused_0[3]; 01279 pseudo_bit_t MulUncErrMskSendBufVL15[1]; 01280 pseudo_bit_t MulUncErrMskSendBufMain[1]; 01281 pseudo_bit_t MulUncErrMskSendBufExtra[1]; 01282 pseudo_bit_t MulUncErrMskSendPbcArray[1]; 01283 pseudo_bit_t MulUncErrMskSendLaFIFO0_0[1]; 01284 pseudo_bit_t MulUncErrMskSendLaFIFO1_0[1]; 01285 pseudo_bit_t MulUncErrMskSendLaFIFO2_0[1]; 01286 pseudo_bit_t MulUncErrMskSendLaFIFO3_0[1]; 01287 pseudo_bit_t MulUncErrMskSendLaFIFO4_0[1]; 01288 pseudo_bit_t MulUncErrMskSendLaFIFO5_0[1]; 01289 pseudo_bit_t MulUncErrMskSendLaFIFO6_0[1]; 01290 pseudo_bit_t MulUncErrMskSendLaFIFO7_0[1]; 01291 pseudo_bit_t MulUncErrMskSendLaFIFO0_1[1]; 01292 pseudo_bit_t MulUncErrMskSendLaFIFO1_1[1]; 01293 pseudo_bit_t MulUncErrMskSendLaFIFO2_1[1]; 01294 pseudo_bit_t MulUncErrMskSendLaFIFO3_1[1]; 01295 pseudo_bit_t MulUncErrMskSendLaFIFO4_1[1]; 01296 pseudo_bit_t MulUncErrMskSendLaFIFO5_1[1]; 01297 pseudo_bit_t MulUncErrMskSendLaFIFO6_1[1]; 01298 pseudo_bit_t MulUncErrMskSendLaFIFO7_1[1]; 01299 pseudo_bit_t MulUncErrMskSendRmFIFO_0[1]; 01300 pseudo_bit_t MulUncErrMskSendRmFIFO_1[1]; 01301 pseudo_bit_t _unused_1[11]; 01302 pseudo_bit_t MulUncErrMskPCIeRetryBuf[1]; 01303 pseudo_bit_t MulUncErrMskPCIePostHdrBuf[1]; 01304 pseudo_bit_t MulUncErrMskPCIePostDataBuf[1]; 01305 pseudo_bit_t MulUncErrMskPCIeCompHdrBuf[1]; 01306 pseudo_bit_t MulUncErrMskPCIeCompDataBuf[1]; 01307 pseudo_bit_t MulUncErrMskMsixTable0[1]; 01308 pseudo_bit_t MulUncErrMskMsixTable1[1]; 01309 pseudo_bit_t MulUncErrMskMsixTable2[1]; 01310 pseudo_bit_t _unused_2[8]; 01311 }; 01312 struct QIB_7322_MemMultiUnCorErrMask { 01313 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrMask_pb ); 01314 }; 01315 /* Default value: 0x0000000000000000 */ 01316 01317 #define QIB_7322_MemMultiUnCorErrStatus_offset 0x00000618UL 01318 struct QIB_7322_MemMultiUnCorErrStatus_pb { 01319 pseudo_bit_t MulUncErrStatusRcvBuf_0[1]; 01320 pseudo_bit_t MulUncErrStatusRcvFlags_0[1]; 01321 pseudo_bit_t MulUncErrStatusLookupiqBuf_0[1]; 01322 pseudo_bit_t MulUncErrStatusRcvDMAHdrBuf_0[1]; 01323 pseudo_bit_t MulUncErrStatusRcvDMADataBuf_0[1]; 01324 pseudo_bit_t MulUncErrStatusRcvBuf_1[1]; 01325 pseudo_bit_t MulUncErrStatusRcvFlags_1[1]; 01326 pseudo_bit_t MulUncErrStatusLookupiqBuf_1[1]; 01327 pseudo_bit_t MulUncErrStatusRcvDMAHdrBuf_1[1]; 01328 pseudo_bit_t MulUncErrStatusRcvDMADataBuf_1[1]; 01329 pseudo_bit_t MulUncErrStatusRcvTIDArray[1]; 01330 pseudo_bit_t MulUncErrStatusRcvEgrArray[1]; 01331 pseudo_bit_t _unused_0[3]; 01332 pseudo_bit_t MulUncErrStatusSendBufVL15[1]; 01333 pseudo_bit_t MulUncErrStatusSendBufMain[1]; 01334 pseudo_bit_t MulUncErrStatusSendBufExtra[1]; 01335 pseudo_bit_t MulUncErrStatusSendPbcArray[1]; 01336 pseudo_bit_t MulUncErrStatusSendLaFIFO0_0[1]; 01337 pseudo_bit_t MulUncErrStatusSendLaFIFO1_0[1]; 01338 pseudo_bit_t MulUncErrStatusSendLaFIFO2_0[1]; 01339 pseudo_bit_t MulUncErrStatusSendLaFIFO3_0[1]; 01340 pseudo_bit_t MulUncErrStatusSendLaFIFO4_0[1]; 01341 pseudo_bit_t MulUncErrStatusSendLaFIFO5_0[1]; 01342 pseudo_bit_t MulUncErrStatusSendLaFIFO6_0[1]; 01343 pseudo_bit_t MulUncErrStatusSendLaFIFO7_0[1]; 01344 pseudo_bit_t MulUncErrStatusSendLaFIFO0_1[1]; 01345 pseudo_bit_t MulUncErrStatusSendLaFIFO1_1[1]; 01346 pseudo_bit_t MulUncErrStatusSendLaFIFO2_1[1]; 01347 pseudo_bit_t MulUncErrStatusSendLaFIFO3_1[1]; 01348 pseudo_bit_t MulUncErrStatusSendLaFIFO4_1[1]; 01349 pseudo_bit_t MulUncErrStatusSendLaFIFO5_1[1]; 01350 pseudo_bit_t MulUncErrStatusSendLaFIFO6_1[1]; 01351 pseudo_bit_t MulUncErrStatusSendLaFIFO7_1[1]; 01352 pseudo_bit_t MulUncErrStatusSendRmFIFO_0[1]; 01353 pseudo_bit_t MulUncErrStatusSendRmFIFO_1[1]; 01354 pseudo_bit_t _unused_1[11]; 01355 pseudo_bit_t MulUncErrStatusPCIeRetryBuf[1]; 01356 pseudo_bit_t MulUncErrStatusPCIePostHdrBuf[1]; 01357 pseudo_bit_t MulUncErrStatusPCIePostDataBuf[1]; 01358 pseudo_bit_t MulUncErrStatusPCIeCompHdrBuf[1]; 01359 pseudo_bit_t MulUncErrStatusPCIeCompDataBuf[1]; 01360 pseudo_bit_t MulUncErrStatusMsixTable0[1]; 01361 pseudo_bit_t MulUncErrStatusMsixTable1[1]; 01362 pseudo_bit_t MulUncErrStatusMsixTable2[1]; 01363 pseudo_bit_t _unused_2[8]; 01364 }; 01365 struct QIB_7322_MemMultiUnCorErrStatus { 01366 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrStatus_pb ); 01367 }; 01368 /* Default value: 0x0000000000000000 */ 01369 01370 #define QIB_7322_MemMultiUnCorErrClear_offset 0x00000620UL 01371 struct QIB_7322_MemMultiUnCorErrClear_pb { 01372 pseudo_bit_t MulUncErrClearRcvBuf_0[1]; 01373 pseudo_bit_t MulUncErrClearRcvFlags_0[1]; 01374 pseudo_bit_t MulUncErrClearLookupiqBuf_0[1]; 01375 pseudo_bit_t MulUncErrClearRcvDMAHdrBuf_0[1]; 01376 pseudo_bit_t MulUncErrClearRcvDMADataBuf_0[1]; 01377 pseudo_bit_t MulUncErrClearRcvBuf_1[1]; 01378 pseudo_bit_t MulUncErrClearRcvFlags_1[1]; 01379 pseudo_bit_t MulUncErrClearLookupiqBuf_1[1]; 01380 pseudo_bit_t MulUncErrClearRcvDMAHdrBuf_1[1]; 01381 pseudo_bit_t MulUncErrClearRcvDMADataBuf_1[1]; 01382 pseudo_bit_t MulUncErrClearRcvTIDArray[1]; 01383 pseudo_bit_t MulUncErrClearRcvEgrArray[1]; 01384 pseudo_bit_t _unused_0[3]; 01385 pseudo_bit_t MulUncErrClearSendBufVL15[1]; 01386 pseudo_bit_t MulUncErrClearSendBufMain[1]; 01387 pseudo_bit_t MulUncErrClearSendBufExtra[1]; 01388 pseudo_bit_t MulUncErrClearSendPbcArray[1]; 01389 pseudo_bit_t MulUncErrClearSendLaFIFO0_0[1]; 01390 pseudo_bit_t MulUncErrClearSendLaFIFO1_0[1]; 01391 pseudo_bit_t MulUncErrClearSendLaFIFO2_0[1]; 01392 pseudo_bit_t MulUncErrClearSendLaFIFO3_0[1]; 01393 pseudo_bit_t MulUncErrClearSendLaFIFO4_0[1]; 01394 pseudo_bit_t MulUncErrClearSendLaFIFO5_0[1]; 01395 pseudo_bit_t MulUncErrClearSendLaFIFO6_0[1]; 01396 pseudo_bit_t MulUncErrClearSendLaFIFO7_0[1]; 01397 pseudo_bit_t MulUncErrClearSendLaFIFO0_1[1]; 01398 pseudo_bit_t MulUncErrClearSendLaFIFO1_1[1]; 01399 pseudo_bit_t MulUncErrClearSendLaFIFO2_1[1]; 01400 pseudo_bit_t MulUncErrClearSendLaFIFO3_1[1]; 01401 pseudo_bit_t MulUncErrClearSendLaFIFO4_1[1]; 01402 pseudo_bit_t MulUncErrClearSendLaFIFO5_1[1]; 01403 pseudo_bit_t MulUncErrClearSendLaFIFO6_1[1]; 01404 pseudo_bit_t MulUncErrClearSendLaFIFO7_1[1]; 01405 pseudo_bit_t MulUncErrClearSendRmFIFO_0[1]; 01406 pseudo_bit_t MulUncErrClearSendRmFIFO_1[1]; 01407 pseudo_bit_t _unused_1[11]; 01408 pseudo_bit_t MulUncErrClearPCIeRetryBuf[1]; 01409 pseudo_bit_t MulUncErrClearPCIePostHdrBuf[1]; 01410 pseudo_bit_t MulUncErrClearPCIePostDataBuf[1]; 01411 pseudo_bit_t MulUncErrClearPCIeCompHdrBuf[1]; 01412 pseudo_bit_t MulUncErrClearPCIeCompDataBuf[1]; 01413 pseudo_bit_t MulUncErrClearMsixTable0[1]; 01414 pseudo_bit_t MulUncErrClearMsixTable1[1]; 01415 pseudo_bit_t MulUncErrClearMsixTable2[1]; 01416 pseudo_bit_t _unused_2[8]; 01417 }; 01418 struct QIB_7322_MemMultiUnCorErrClear { 01419 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrClear_pb ); 01420 }; 01421 /* Default value: 0x0000000000000000 */ 01422 01423 #define QIB_7322_MemUnCorErrMask_offset 0x00000628UL 01424 struct QIB_7322_MemUnCorErrMask_pb { 01425 pseudo_bit_t UncErrMskRcvBuf_0[1]; 01426 pseudo_bit_t UncErrMskRcvFlags_0[1]; 01427 pseudo_bit_t UncErrMskLookupiqBuf_0[1]; 01428 pseudo_bit_t UncErrMskRcvDMAHdrBuf_0[1]; 01429 pseudo_bit_t UncErrMskRcvDMADataBuf_0[1]; 01430 pseudo_bit_t UncErrMskRcvBuf_1[1]; 01431 pseudo_bit_t UncErrMskRcvFlags_1[1]; 01432 pseudo_bit_t UncErrMskLookupiqBuf_1[1]; 01433 pseudo_bit_t UncErrMskRcvDMAHdrBuf_1[1]; 01434 pseudo_bit_t UncErrMskRcvDMADataBuf_1[1]; 01435 pseudo_bit_t UncErrMskRcvTIDArray[1]; 01436 pseudo_bit_t UncErrMskRcvEgrArray[1]; 01437 pseudo_bit_t _unused_0[3]; 01438 pseudo_bit_t UncErrMskSendBufVL15[1]; 01439 pseudo_bit_t UncErrMskSendBufMain[1]; 01440 pseudo_bit_t UncErrMskSendBufExtra[1]; 01441 pseudo_bit_t UncErrMskSendPbcArray[1]; 01442 pseudo_bit_t UncErrMskSendLaFIFO0_0[1]; 01443 pseudo_bit_t UncErrMskSendLaFIFO1_0[1]; 01444 pseudo_bit_t UncErrMskSendLaFIFO2_0[1]; 01445 pseudo_bit_t UncErrMskSendLaFIFO3_0[1]; 01446 pseudo_bit_t UncErrMskSendLaFIFO4_0[1]; 01447 pseudo_bit_t UncErrMskSendLaFIFO5_0[1]; 01448 pseudo_bit_t UncErrMskSendLaFIFO6_0[1]; 01449 pseudo_bit_t UncErrMskSendLaFIFO7_0[1]; 01450 pseudo_bit_t UncErrMskSendLaFIFO0_1[1]; 01451 pseudo_bit_t UncErrMskSendLaFIFO1_1[1]; 01452 pseudo_bit_t UncErrMskSendLaFIFO2_1[1]; 01453 pseudo_bit_t UncErrMskSendLaFIFO3_1[1]; 01454 pseudo_bit_t UncErrMskSendLaFIFO4_1[1]; 01455 pseudo_bit_t UncErrMskSendLaFIFO5_1[1]; 01456 pseudo_bit_t UncErrMskSendLaFIFO6_1[1]; 01457 pseudo_bit_t UncErrMskSendLaFIFO7_1[1]; 01458 pseudo_bit_t UncErrMskSendRmFIFO_0[1]; 01459 pseudo_bit_t UncErrMskSendRmFIFO_1[1]; 01460 pseudo_bit_t _unused_1[11]; 01461 pseudo_bit_t UncErrMskPCIeRetryBuf[1]; 01462 pseudo_bit_t UncErrMskPCIePostHdrBuf[1]; 01463 pseudo_bit_t UncErrMskPCIePostDataBuf[1]; 01464 pseudo_bit_t UncErrMskPCIeCompHdrBuf[1]; 01465 pseudo_bit_t UncErrMskPCIeCompDataBuf[1]; 01466 pseudo_bit_t UncErrMskMsixTable0[1]; 01467 pseudo_bit_t UncErrMskMsixTable1[1]; 01468 pseudo_bit_t UncErrMskMsixTable2[1]; 01469 pseudo_bit_t _unused_2[8]; 01470 }; 01471 struct QIB_7322_MemUnCorErrMask { 01472 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrMask_pb ); 01473 }; 01474 /* Default value: 0x0000000000000000 */ 01475 01476 #define QIB_7322_MemUnCorErrStatus_offset 0x00000630UL 01477 struct QIB_7322_MemUnCorErrStatus_pb { 01478 pseudo_bit_t UncErrStatusRcvBuf_0[1]; 01479 pseudo_bit_t UncErrStatusRcvFlags_0[1]; 01480 pseudo_bit_t UncErrStatusLookupiqBuf_0[1]; 01481 pseudo_bit_t UncErrStatusRcvDMAHdrBuf_0[1]; 01482 pseudo_bit_t UncErrStatusRcvDMADataBuf_0[1]; 01483 pseudo_bit_t UncErrStatusRcvBuf_1[1]; 01484 pseudo_bit_t UncErrStatusRcvFlags_1[1]; 01485 pseudo_bit_t UncErrStatusLookupiqBuf_1[1]; 01486 pseudo_bit_t UncErrStatusRcvDMAHdrBuf_1[1]; 01487 pseudo_bit_t UncErrStatusRcvDMADataBuf_1[1]; 01488 pseudo_bit_t UncErrStatusRcvTIDArray[1]; 01489 pseudo_bit_t UncErrStatusRcvEgrArray[1]; 01490 pseudo_bit_t _unused_0[3]; 01491 pseudo_bit_t UncErrStatusSendBufVL15[1]; 01492 pseudo_bit_t UncErrStatusSendBufMain[1]; 01493 pseudo_bit_t UncErrStatusSendBufExtra[1]; 01494 pseudo_bit_t UncErrStatusSendPbcArray[1]; 01495 pseudo_bit_t UncErrStatusSendLaFIFO0_0[1]; 01496 pseudo_bit_t UncErrStatusSendLaFIFO1_0[1]; 01497 pseudo_bit_t UncErrStatusSendLaFIFO2_0[1]; 01498 pseudo_bit_t UncErrStatusSendLaFIFO3_0[1]; 01499 pseudo_bit_t UncErrStatusSendLaFIFO4_0[1]; 01500 pseudo_bit_t UncErrStatusSendLaFIFO5_0[1]; 01501 pseudo_bit_t UncErrStatusSendLaFIFO6_0[1]; 01502 pseudo_bit_t UncErrStatusSendLaFIFO7_0[1]; 01503 pseudo_bit_t UncErrStatusSendLaFIFO0_1[1]; 01504 pseudo_bit_t UncErrStatusSendLaFIFO1_1[1]; 01505 pseudo_bit_t UncErrStatusSendLaFIFO2_1[1]; 01506 pseudo_bit_t UncErrStatusSendLaFIFO3_1[1]; 01507 pseudo_bit_t UncErrStatusSendLaFIFO4_1[1]; 01508 pseudo_bit_t UncErrStatusSendLaFIFO5_1[1]; 01509 pseudo_bit_t UncErrStatusSendLaFIFO6_1[1]; 01510 pseudo_bit_t UncErrStatusSendLaFIFO7_1[1]; 01511 pseudo_bit_t UncErrStatusSendRmFIFO_0[1]; 01512 pseudo_bit_t UncErrStatusSendRmFIFO_1[1]; 01513 pseudo_bit_t _unused_1[11]; 01514 pseudo_bit_t UncErrStatusPCIeRetryBuf[1]; 01515 pseudo_bit_t UncErrStatusPCIePostHdrBuf[1]; 01516 pseudo_bit_t UncErrStatusPCIePostDataBuf[1]; 01517 pseudo_bit_t UncErrStatusPCIeCompHdrBuf[1]; 01518 pseudo_bit_t UncErrStatusPCIeCompDataBuf[1]; 01519 pseudo_bit_t UncErrStatusMsixTable0[1]; 01520 pseudo_bit_t UncErrStatusMsixTable1[1]; 01521 pseudo_bit_t UncErrStatusMsixTable2[1]; 01522 pseudo_bit_t _unused_2[8]; 01523 }; 01524 struct QIB_7322_MemUnCorErrStatus { 01525 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrStatus_pb ); 01526 }; 01527 /* Default value: 0x0000000000000000 */ 01528 01529 #define QIB_7322_MemUnCorErrClear_offset 0x00000638UL 01530 struct QIB_7322_MemUnCorErrClear_pb { 01531 pseudo_bit_t UncErrClearRcvBuf_0[1]; 01532 pseudo_bit_t UncErrClearRcvFlags_0[1]; 01533 pseudo_bit_t UncErrClearLookupiqBuf_0[1]; 01534 pseudo_bit_t UncErrClearRcvDMAHdrBuf_0[1]; 01535 pseudo_bit_t UncErrClearRcvDMADataBuf_0[1]; 01536 pseudo_bit_t UncErrClearRcvBuf_1[1]; 01537 pseudo_bit_t UncErrClearRcvFlags_1[1]; 01538 pseudo_bit_t UncErrClearLookupiqBuf_1[1]; 01539 pseudo_bit_t UncErrClearRcvDMAHdrBuf_1[1]; 01540 pseudo_bit_t UncErrClearRcvDMADataBuf_1[1]; 01541 pseudo_bit_t UncErrClearRcvTIDArray[1]; 01542 pseudo_bit_t UncErrClearRcvEgrArray[1]; 01543 pseudo_bit_t _unused_0[3]; 01544 pseudo_bit_t UncErrClearSendBufVL15[1]; 01545 pseudo_bit_t UncErrClearSendBufMain[1]; 01546 pseudo_bit_t UncErrClearSendBufExtra[1]; 01547 pseudo_bit_t UncErrClearSendPbcArray[1]; 01548 pseudo_bit_t UncErrClearSendLaFIFO0_0[1]; 01549 pseudo_bit_t UncErrClearSendLaFIFO1_0[1]; 01550 pseudo_bit_t UncErrClearSendLaFIFO2_0[1]; 01551 pseudo_bit_t UncErrClearSendLaFIFO3_0[1]; 01552 pseudo_bit_t UncErrClearSendLaFIFO4_0[1]; 01553 pseudo_bit_t UncErrClearSendLaFIFO5_0[1]; 01554 pseudo_bit_t UncErrClearSendLaFIFO6_0[1]; 01555 pseudo_bit_t UncErrClearSendLaFIFO7_0[1]; 01556 pseudo_bit_t UncErrClearSendLaFIFO0_1[1]; 01557 pseudo_bit_t UncErrClearSendLaFIFO1_1[1]; 01558 pseudo_bit_t UncErrClearSendLaFIFO2_1[1]; 01559 pseudo_bit_t UncErrClearSendLaFIFO3_1[1]; 01560 pseudo_bit_t UncErrClearSendLaFIFO4_1[1]; 01561 pseudo_bit_t UncErrClearSendLaFIFO5_1[1]; 01562 pseudo_bit_t UncErrClearSendLaFIFO6_1[1]; 01563 pseudo_bit_t UncErrClearSendLaFIFO7_1[1]; 01564 pseudo_bit_t UncErrClearSendRmFIFO_0[1]; 01565 pseudo_bit_t UncErrClearSendRmFIFO_1[1]; 01566 pseudo_bit_t _unused_1[11]; 01567 pseudo_bit_t UncErrClearPCIeRetryBuf[1]; 01568 pseudo_bit_t UncErrClearPCIePostHdrBuf[1]; 01569 pseudo_bit_t UncErrClearPCIePostDataBuf[1]; 01570 pseudo_bit_t UncErrClearPCIeCompHdrBuf[1]; 01571 pseudo_bit_t UncErrClearPCIeCompDataBuf[1]; 01572 pseudo_bit_t UncErrClearMsixTable0[1]; 01573 pseudo_bit_t UncErrClearMsixTable1[1]; 01574 pseudo_bit_t UncErrClearMsixTable2[1]; 01575 pseudo_bit_t _unused_2[8]; 01576 }; 01577 struct QIB_7322_MemUnCorErrClear { 01578 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrClear_pb ); 01579 }; 01580 /* Default value: 0x0000000000000000 */ 01581 01582 #define QIB_7322_MemMultiCorErrMask_offset 0x00000640UL 01583 struct QIB_7322_MemMultiCorErrMask_pb { 01584 pseudo_bit_t MulCorErrMskRcvBuf_0[1]; 01585 pseudo_bit_t MulCorErrMskRcvFlags_0[1]; 01586 pseudo_bit_t MulCorErrMskLookupiqBuf_0[1]; 01587 pseudo_bit_t MulCorErrMskRcvDMAHdrBuf_0[1]; 01588 pseudo_bit_t MulCorErrMskRcvDMADataBuf_0[1]; 01589 pseudo_bit_t MulCorErrMskRcvBuf_1[1]; 01590 pseudo_bit_t MulCorErrMskRcvFlags_1[1]; 01591 pseudo_bit_t MulCorErrMskLookupiqBuf_1[1]; 01592 pseudo_bit_t MulCorErrMskRcvDMAHdrBuf_1[1]; 01593 pseudo_bit_t MulCorErrMskRcvDMADataBuf_1[1]; 01594 pseudo_bit_t MulCorErrMskRcvTIDArray[1]; 01595 pseudo_bit_t MulCorErrMskRcvEgrArray[1]; 01596 pseudo_bit_t _unused_0[3]; 01597 pseudo_bit_t MulCorErrMskSendBufVL15[1]; 01598 pseudo_bit_t MulCorErrMskSendBufMain[1]; 01599 pseudo_bit_t MulCorErrMskSendBufExtra[1]; 01600 pseudo_bit_t MulCorErrMskSendPbcArray[1]; 01601 pseudo_bit_t MulCorErrMskSendLaFIFO0_0[1]; 01602 pseudo_bit_t MulCorErrMskSendLaFIFO1_0[1]; 01603 pseudo_bit_t MulCorErrMskSendLaFIFO2_0[1]; 01604 pseudo_bit_t MulCorErrMskSendLaFIFO3_0[1]; 01605 pseudo_bit_t MulCorErrMskSendLaFIFO4_0[1]; 01606 pseudo_bit_t MulCorErrMskSendLaFIFO5_0[1]; 01607 pseudo_bit_t MulCorErrMskSendLaFIFO6_0[1]; 01608 pseudo_bit_t MulCorErrMskSendLaFIFO7_0[1]; 01609 pseudo_bit_t MulCorErrMskSendLaFIFO0_1[1]; 01610 pseudo_bit_t MulCorErrMskSendLaFIFO1_1[1]; 01611 pseudo_bit_t MulCorErrMskSendLaFIFO2_1[1]; 01612 pseudo_bit_t MulCorErrMskSendLaFIFO3_1[1]; 01613 pseudo_bit_t MulCorErrMskSendLaFIFO4_1[1]; 01614 pseudo_bit_t MulCorErrMskSendLaFIFO5_1[1]; 01615 pseudo_bit_t MulCorErrMskSendLaFIFO6_1[1]; 01616 pseudo_bit_t MulCorErrMskSendLaFIFO7_1[1]; 01617 pseudo_bit_t MulCorErrMskSendRmFIFO_0[1]; 01618 pseudo_bit_t MulCorErrMskSendRmFIFO_1[1]; 01619 pseudo_bit_t _unused_1[11]; 01620 pseudo_bit_t MulCorErrMskPCIeRetryBuf[1]; 01621 pseudo_bit_t MulCorErrMskPCIePostHdrBuf[1]; 01622 pseudo_bit_t MulCorErrMskPCIePostDataBuf[1]; 01623 pseudo_bit_t MulCorErrMskPCIeCompHdrBuf[1]; 01624 pseudo_bit_t MulCorErrMskPCIeCompDataBuf[1]; 01625 pseudo_bit_t MulCorErrMskMsixTable0[1]; 01626 pseudo_bit_t MulCorErrMskMsixTable1[1]; 01627 pseudo_bit_t MulCorErrMskMsixTable2[1]; 01628 pseudo_bit_t _unused_2[8]; 01629 }; 01630 struct QIB_7322_MemMultiCorErrMask { 01631 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrMask_pb ); 01632 }; 01633 /* Default value: 0x0000000000000000 */ 01634 01635 #define QIB_7322_MemMultiCorErrStatus_offset 0x00000648UL 01636 struct QIB_7322_MemMultiCorErrStatus_pb { 01637 pseudo_bit_t MulCorErrStatusRcvBuf_0[1]; 01638 pseudo_bit_t MulCorErrStatusRcvFlags_0[1]; 01639 pseudo_bit_t MulCorErrStatusLookupiqBuf_0[1]; 01640 pseudo_bit_t MulCorErrStatusRcvDMAHdrBuf_0[1]; 01641 pseudo_bit_t MulCorErrStatusRcvDMADataBuf_0[1]; 01642 pseudo_bit_t MulCorErrStatusRcvBuf_1[1]; 01643 pseudo_bit_t MulCorErrStatusRcvFlags_1[1]; 01644 pseudo_bit_t MulCorErrStatusLookupiqBuf_1[1]; 01645 pseudo_bit_t MulCorErrStatusRcvDMAHdrBuf_1[1]; 01646 pseudo_bit_t MulCorErrStatusRcvDMADataBuf_1[1]; 01647 pseudo_bit_t MulCorErrStatusRcvTIDArray[1]; 01648 pseudo_bit_t MulCorErrStatusRcvEgrArray[1]; 01649 pseudo_bit_t _unused_0[3]; 01650 pseudo_bit_t MulCorErrStatusSendBufVL15[1]; 01651 pseudo_bit_t MulCorErrStatusSendBufMain[1]; 01652 pseudo_bit_t MulCorErrStatusSendBufExtra[1]; 01653 pseudo_bit_t MulCorErrStatusSendPbcArray[1]; 01654 pseudo_bit_t MulCorErrStatusSendLaFIFO0_0[1]; 01655 pseudo_bit_t MulCorErrStatusSendLaFIFO1_0[1]; 01656 pseudo_bit_t MulCorErrStatusSendLaFIFO2_0[1]; 01657 pseudo_bit_t MulCorErrStatusSendLaFIFO3_0[1]; 01658 pseudo_bit_t MulCorErrStatusSendLaFIFO4_0[1]; 01659 pseudo_bit_t MulCorErrStatusSendLaFIFO5_0[1]; 01660 pseudo_bit_t MulCorErrStatusSendLaFIFO6_0[1]; 01661 pseudo_bit_t MulCorErrStatusSendLaFIFO7_0[1]; 01662 pseudo_bit_t MulCorErrStatusSendLaFIFO0_1[1]; 01663 pseudo_bit_t MulCorErrStatusSendLaFIFO1_1[1]; 01664 pseudo_bit_t MulCorErrStatusSendLaFIFO2_1[1]; 01665 pseudo_bit_t MulCorErrStatusSendLaFIFO3_1[1]; 01666 pseudo_bit_t MulCorErrStatusSendLaFIFO4_1[1]; 01667 pseudo_bit_t MulCorErrStatusSendLaFIFO5_1[1]; 01668 pseudo_bit_t MulCorErrStatusSendLaFIFO6_1[1]; 01669 pseudo_bit_t MulCorErrStatusSendLaFIFO7_1[1]; 01670 pseudo_bit_t MulCorErrStatusSendRmFIFO_0[1]; 01671 pseudo_bit_t MulCorErrStatusSendRmFIFO_1[1]; 01672 pseudo_bit_t _unused_1[11]; 01673 pseudo_bit_t MulCorErrStatusPCIeRetryBuf[1]; 01674 pseudo_bit_t MulCorErrStatusPCIePostHdrBuf[1]; 01675 pseudo_bit_t MulCorErrStatusPCIePostDataBuf[1]; 01676 pseudo_bit_t MulCorErrStatusPCIeCompHdrBuf[1]; 01677 pseudo_bit_t MulCorErrStatusPCIeCompDataBuf[1]; 01678 pseudo_bit_t MulCorErrStatusMsixTable0[1]; 01679 pseudo_bit_t MulCorErrStatusMsixTable1[1]; 01680 pseudo_bit_t MulCorErrStatusMsixTable2[1]; 01681 pseudo_bit_t _unused_2[8]; 01682 }; 01683 struct QIB_7322_MemMultiCorErrStatus { 01684 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrStatus_pb ); 01685 }; 01686 /* Default value: 0x0000000000000000 */ 01687 01688 #define QIB_7322_MemMultiCorErrClear_offset 0x00000650UL 01689 struct QIB_7322_MemMultiCorErrClear_pb { 01690 pseudo_bit_t MulCorErrClearRcvBuf_0[1]; 01691 pseudo_bit_t MulCorErrClearRcvFlags_0[1]; 01692 pseudo_bit_t MulCorErrClearLookupiqBuf_0[1]; 01693 pseudo_bit_t MulCorErrClearRcvDMAHdrBuf_0[1]; 01694 pseudo_bit_t MulCorErrClearRcvDMADataBuf_0[1]; 01695 pseudo_bit_t MulCorErrClearRcvBuf_1[1]; 01696 pseudo_bit_t MulCorErrClearRcvFlags_1[1]; 01697 pseudo_bit_t MulCorErrClearLookupiqBuf_1[1]; 01698 pseudo_bit_t MulCorErrClearRcvDMAHdrBuf_1[1]; 01699 pseudo_bit_t MulCorErrClearRcvDMADataBuf_1[1]; 01700 pseudo_bit_t MulCorErrClearRcvTIDArray[1]; 01701 pseudo_bit_t MulCorErrClearRcvEgrArray[1]; 01702 pseudo_bit_t _unused_0[3]; 01703 pseudo_bit_t MulCorErrClearSendBufVL15[1]; 01704 pseudo_bit_t MulCorErrClearSendBufMain[1]; 01705 pseudo_bit_t MulCorErrClearSendBufExtra[1]; 01706 pseudo_bit_t MulCorErrClearSendPbcArray[1]; 01707 pseudo_bit_t MulCorErrClearSendLaFIFO0_0[1]; 01708 pseudo_bit_t MulCorErrClearSendLaFIFO1_0[1]; 01709 pseudo_bit_t MulCorErrClearSendLaFIFO2_0[1]; 01710 pseudo_bit_t MulCorErrClearSendLaFIFO3_0[1]; 01711 pseudo_bit_t MulCorErrClearSendLaFIFO4_0[1]; 01712 pseudo_bit_t MulCorErrClearSendLaFIFO5_0[1]; 01713 pseudo_bit_t MulCorErrClearSendLaFIFO6_0[1]; 01714 pseudo_bit_t MulCorErrClearSendLaFIFO7_0[1]; 01715 pseudo_bit_t MulCorErrClearSendLaFIFO0_1[1]; 01716 pseudo_bit_t MulCorErrClearSendLaFIFO1_1[1]; 01717 pseudo_bit_t MulCorErrClearSendLaFIFO2_1[1]; 01718 pseudo_bit_t MulCorErrClearSendLaFIFO3_1[1]; 01719 pseudo_bit_t MulCorErrClearSendLaFIFO4_1[1]; 01720 pseudo_bit_t MulCorErrClearSendLaFIFO5_1[1]; 01721 pseudo_bit_t MulCorErrClearSendLaFIFO6_1[1]; 01722 pseudo_bit_t MulCorErrClearSendLaFIFO7_1[1]; 01723 pseudo_bit_t MulCorErrClearSendRmFIFO_0[1]; 01724 pseudo_bit_t MulCorErrClearSendRmFIFO_1[1]; 01725 pseudo_bit_t _unused_1[11]; 01726 pseudo_bit_t MulCorErrClearPCIeRetryBuf[1]; 01727 pseudo_bit_t MulCorErrClearPCIePostHdrBuf[1]; 01728 pseudo_bit_t MulCorErrClearPCIePostDataBuf[1]; 01729 pseudo_bit_t MulCorErrClearPCIeCompHdrBuf[1]; 01730 pseudo_bit_t MulCorErrClearPCIeCompDataBuf[1]; 01731 pseudo_bit_t MulCorErrClearMsixTable0[1]; 01732 pseudo_bit_t MulCorErrClearMsixTable1[1]; 01733 pseudo_bit_t MulCorErrClearMsixTable2[1]; 01734 pseudo_bit_t _unused_2[8]; 01735 }; 01736 struct QIB_7322_MemMultiCorErrClear { 01737 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrClear_pb ); 01738 }; 01739 /* Default value: 0x0000000000000000 */ 01740 01741 #define QIB_7322_MemCorErrMask_offset 0x00000658UL 01742 struct QIB_7322_MemCorErrMask_pb { 01743 pseudo_bit_t CorErrMskRcvBuf_0[1]; 01744 pseudo_bit_t CorErrMskRcvFlags_0[1]; 01745 pseudo_bit_t CorErrMskLookupiqBuf_0[1]; 01746 pseudo_bit_t CorErrMskRcvDMAHdrBuf_0[1]; 01747 pseudo_bit_t CorErrMskRcvDMADataBuf_0[1]; 01748 pseudo_bit_t CorErrMskRcvBuf_1[1]; 01749 pseudo_bit_t CorErrMskRcvFlags_1[1]; 01750 pseudo_bit_t CorErrMskLookupiqBuf_1[1]; 01751 pseudo_bit_t CorErrMskRcvDMAHdrBuf_1[1]; 01752 pseudo_bit_t CorErrMskRcvDMADataBuf_1[1]; 01753 pseudo_bit_t CorErrMskRcvTIDArray[1]; 01754 pseudo_bit_t CorErrMskRcvEgrArray[1]; 01755 pseudo_bit_t _unused_0[3]; 01756 pseudo_bit_t CorErrMskSendBufVL15[1]; 01757 pseudo_bit_t CorErrMskSendBufMain[1]; 01758 pseudo_bit_t CorErrMskSendBufExtra[1]; 01759 pseudo_bit_t CorErrMskSendPbcArray[1]; 01760 pseudo_bit_t CorErrMskSendLaFIFO0_0[1]; 01761 pseudo_bit_t CorErrMskSendLaFIFO1_0[1]; 01762 pseudo_bit_t CorErrMskSendLaFIFO2_0[1]; 01763 pseudo_bit_t CorErrMskSendLaFIFO3_0[1]; 01764 pseudo_bit_t CorErrMskSendLaFIFO4_0[1]; 01765 pseudo_bit_t CorErrMskSendLaFIFO5_0[1]; 01766 pseudo_bit_t CorErrMskSendLaFIFO6_0[1]; 01767 pseudo_bit_t CorErrMskSendLaFIFO7_0[1]; 01768 pseudo_bit_t CorErrMskSendLaFIFO0_1[1]; 01769 pseudo_bit_t CorErrMskSendLaFIFO1_1[1]; 01770 pseudo_bit_t CorErrMskSendLaFIFO2_1[1]; 01771 pseudo_bit_t CorErrMskSendLaFIFO3_1[1]; 01772 pseudo_bit_t CorErrMskSendLaFIFO4_1[1]; 01773 pseudo_bit_t CorErrMskSendLaFIFO5_1[1]; 01774 pseudo_bit_t CorErrMskSendLaFIFO6_1[1]; 01775 pseudo_bit_t CorErrMskSendLaFIFO7_1[1]; 01776 pseudo_bit_t CorErrMskSendRmFIFO_0[1]; 01777 pseudo_bit_t CorErrMskSendRmFIFO_1[1]; 01778 pseudo_bit_t _unused_1[11]; 01779 pseudo_bit_t CorErrMskPCIeRetryBuf[1]; 01780 pseudo_bit_t CorErrMskPCIePostHdrBuf[1]; 01781 pseudo_bit_t CorErrMskPCIePostDataBuf[1]; 01782 pseudo_bit_t CorErrMskPCIeCompHdrBuf[1]; 01783 pseudo_bit_t CorErrMskPCIeCompDataBuf[1]; 01784 pseudo_bit_t CorErrMskMsixTable0[1]; 01785 pseudo_bit_t CorErrMskMsixTable1[1]; 01786 pseudo_bit_t CorErrMskMsixTable2[1]; 01787 pseudo_bit_t _unused_2[8]; 01788 }; 01789 struct QIB_7322_MemCorErrMask { 01790 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrMask_pb ); 01791 }; 01792 /* Default value: 0x0000000000000000 */ 01793 01794 #define QIB_7322_MemCorErrStatus_offset 0x00000660UL 01795 struct QIB_7322_MemCorErrStatus_pb { 01796 pseudo_bit_t CorErrStatusRcvBuf_0[1]; 01797 pseudo_bit_t CorErrStatusRcvFlags_0[1]; 01798 pseudo_bit_t CorErrStatusLookupiqBuf_0[1]; 01799 pseudo_bit_t CorErrStatusRcvDMAHdrBuf_0[1]; 01800 pseudo_bit_t CorErrStatusRcvDMADataBuf_0[1]; 01801 pseudo_bit_t CorErrStatusRcvBuf_1[1]; 01802 pseudo_bit_t CorErrStatusRcvFlags_1[1]; 01803 pseudo_bit_t CorErrStatusLookupiqBuf_1[1]; 01804 pseudo_bit_t CorErrStatusRcvDMAHdrBuf_1[1]; 01805 pseudo_bit_t CorErrStatusRcvDMADataBuf_1[1]; 01806 pseudo_bit_t CorErrStatusRcvTIDArray[1]; 01807 pseudo_bit_t CorErrStatusRcvEgrArray[1]; 01808 pseudo_bit_t _unused_0[3]; 01809 pseudo_bit_t CorErrStatusSendBufVL15[1]; 01810 pseudo_bit_t CorErrStatusSendBufMain[1]; 01811 pseudo_bit_t CorErrStatusSendBufExtra[1]; 01812 pseudo_bit_t CorErrStatusSendPbcArray[1]; 01813 pseudo_bit_t CorErrStatusSendLaFIFO0_0[1]; 01814 pseudo_bit_t CorErrStatusSendLaFIFO1_0[1]; 01815 pseudo_bit_t CorErrStatusSendLaFIFO2_0[1]; 01816 pseudo_bit_t CorErrStatusSendLaFIFO3_0[1]; 01817 pseudo_bit_t CorErrStatusSendLaFIFO4_0[1]; 01818 pseudo_bit_t CorErrStatusSendLaFIFO5_0[1]; 01819 pseudo_bit_t CorErrStatusSendLaFIFO6_0[1]; 01820 pseudo_bit_t CorErrStatusSendLaFIFO7_0[1]; 01821 pseudo_bit_t CorErrStatusSendLaFIFO0_1[1]; 01822 pseudo_bit_t CorErrStatusSendLaFIFO1_1[1]; 01823 pseudo_bit_t CorErrStatusSendLaFIFO2_1[1]; 01824 pseudo_bit_t CorErrStatusSendLaFIFO3_1[1]; 01825 pseudo_bit_t CorErrStatusSendLaFIFO4_1[1]; 01826 pseudo_bit_t CorErrStatusSendLaFIFO5_1[1]; 01827 pseudo_bit_t CorErrStatusSendLaFIFO6_1[1]; 01828 pseudo_bit_t CorErrStatusSendLaFIFO7_1[1]; 01829 pseudo_bit_t CorErrStatusSendRmFIFO_0[1]; 01830 pseudo_bit_t CorErrStatusSendRmFIFO_1[1]; 01831 pseudo_bit_t _unused_1[11]; 01832 pseudo_bit_t CorErrStatusPCIeRetryBuf[1]; 01833 pseudo_bit_t CorErrStatusPCIePostHdrBuf[1]; 01834 pseudo_bit_t CorErrStatusPCIePostDataBuf[1]; 01835 pseudo_bit_t CorErrStatusPCIeCompHdrBuf[1]; 01836 pseudo_bit_t CorErrStatusPCIeCompDataBuf[1]; 01837 pseudo_bit_t CorErrStatusMsixTable0[1]; 01838 pseudo_bit_t CorErrStatusMsixTable1[1]; 01839 pseudo_bit_t CorErrStatusMsixTable2[1]; 01840 pseudo_bit_t _unused_2[8]; 01841 }; 01842 struct QIB_7322_MemCorErrStatus { 01843 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrStatus_pb ); 01844 }; 01845 /* Default value: 0x0000000000000000 */ 01846 01847 #define QIB_7322_MemCorErrClear_offset 0x00000668UL 01848 struct QIB_7322_MemCorErrClear_pb { 01849 pseudo_bit_t CorErrClearRcvBuf_0[1]; 01850 pseudo_bit_t CorErrClearRcvFlags_0[1]; 01851 pseudo_bit_t CorErrClearLookupiqBuf_0[1]; 01852 pseudo_bit_t CorErrClearRcvDMAHdrBuf_0[1]; 01853 pseudo_bit_t CorErrClearRcvDMADataBuf_0[1]; 01854 pseudo_bit_t CorErrClearRcvBuf_1[1]; 01855 pseudo_bit_t CorErrClearRcvFlags_1[1]; 01856 pseudo_bit_t CorErrClearLookupiqBuf_1[1]; 01857 pseudo_bit_t CorErrClearRcvDMAHdrBuf_1[1]; 01858 pseudo_bit_t CorErrClearRcvDMADataBuf_1[1]; 01859 pseudo_bit_t CorErrClearRcvTIDArray[1]; 01860 pseudo_bit_t CorErrClearRcvEgrArray[1]; 01861 pseudo_bit_t _unused_0[3]; 01862 pseudo_bit_t CorErrClearSendBufVL15[1]; 01863 pseudo_bit_t CorErrClearSendBufMain[1]; 01864 pseudo_bit_t CorErrClearSendBufExtra[1]; 01865 pseudo_bit_t CorErrClearSendPbcArray[1]; 01866 pseudo_bit_t CorErrClearSendLaFIFO0_0[1]; 01867 pseudo_bit_t CorErrClearSendLaFIFO1_0[1]; 01868 pseudo_bit_t CorErrClearSendLaFIFO2_0[1]; 01869 pseudo_bit_t CorErrClearSendLaFIFO3_0[1]; 01870 pseudo_bit_t CorErrClearSendLaFIFO4_0[1]; 01871 pseudo_bit_t CorErrClearSendLaFIFO5_0[1]; 01872 pseudo_bit_t CorErrClearSendLaFIFO6_0[1]; 01873 pseudo_bit_t CorErrClearSendLaFIFO7_0[1]; 01874 pseudo_bit_t CorErrClearSendLaFIFO0_1[1]; 01875 pseudo_bit_t CorErrClearSendLaFIFO1_1[1]; 01876 pseudo_bit_t CorErrClearSendLaFIFO2_1[1]; 01877 pseudo_bit_t CorErrClearSendLaFIFO3_1[1]; 01878 pseudo_bit_t CorErrClearSendLaFIFO4_1[1]; 01879 pseudo_bit_t CorErrClearSendLaFIFO5_1[1]; 01880 pseudo_bit_t CorErrClearSendLaFIFO6_1[1]; 01881 pseudo_bit_t CorErrClearSendLaFIFO7_1[1]; 01882 pseudo_bit_t CorErrClearSendRmFIFO_0[1]; 01883 pseudo_bit_t CorErrClearSendRmFIFO_1[1]; 01884 pseudo_bit_t _unused_1[11]; 01885 pseudo_bit_t CorErrClearPCIeRetryBuf[1]; 01886 pseudo_bit_t CorErrClearPCIePostHdrBuf[1]; 01887 pseudo_bit_t CorErrClearPCIePostDataBuf[1]; 01888 pseudo_bit_t CorErrClearPCIeCompHdrBuf[1]; 01889 pseudo_bit_t CorErrClearPCIeCompDataBuf[1]; 01890 pseudo_bit_t CorErrClearMsixTable0[1]; 01891 pseudo_bit_t CorErrClearMsixTable1[1]; 01892 pseudo_bit_t CorErrClearMsixTable2[1]; 01893 pseudo_bit_t _unused_2[8]; 01894 }; 01895 struct QIB_7322_MemCorErrClear { 01896 PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrClear_pb ); 01897 }; 01898 /* Default value: 0x0000000000000000 */ 01899 01900 #define QIB_7322_MsixTableUnCorErrLogA_offset 0x00000680UL 01901 struct QIB_7322_MsixTableUnCorErrLogA_pb { 01902 pseudo_bit_t MsixTable_1_0_UnCorErrData[64]; 01903 }; 01904 struct QIB_7322_MsixTableUnCorErrLogA { 01905 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogA_pb ); 01906 }; 01907 /* Default value: 0x0000000000000000 */ 01908 01909 #define QIB_7322_MsixTableUnCorErrLogB_offset 0x00000688UL 01910 struct QIB_7322_MsixTableUnCorErrLogB_pb { 01911 pseudo_bit_t MsixTable_2_UnCorErrData[32]; 01912 pseudo_bit_t MsixTable_0_UnCorErrCheckBits[7]; 01913 pseudo_bit_t MsixTable_1_UnCorErrCheckBits[7]; 01914 pseudo_bit_t MsixTable_2_UnCorErrCheckBits[7]; 01915 pseudo_bit_t _unused_0[11]; 01916 }; 01917 struct QIB_7322_MsixTableUnCorErrLogB { 01918 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogB_pb ); 01919 }; 01920 /* Default value: 0x0000000000000000 */ 01921 01922 #define QIB_7322_MsixTableUnCorErrLogC_offset 0x00000690UL 01923 struct QIB_7322_MsixTableUnCorErrLogC_pb { 01924 pseudo_bit_t MsixTable_0_UnCorErrAddr[7]; 01925 pseudo_bit_t MsixTable_1_UnCorErrAddr[7]; 01926 pseudo_bit_t MsixTable_2_UnCorErrAddr[7]; 01927 pseudo_bit_t _unused_0[43]; 01928 }; 01929 struct QIB_7322_MsixTableUnCorErrLogC { 01930 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogC_pb ); 01931 }; 01932 /* Default value: 0x0000000000000000 */ 01933 01934 #define QIB_7322_MsixEntryWithUncorErr_offset 0x00000698UL 01935 /* Default value: 0x0000000000000000 */ 01936 01937 #define QIB_7322_MsixTableCorErrLogA_offset 0x000006a0UL 01938 struct QIB_7322_MsixTableCorErrLogA_pb { 01939 pseudo_bit_t MsixTable_1_0_CorErrData[64]; 01940 }; 01941 struct QIB_7322_MsixTableCorErrLogA { 01942 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogA_pb ); 01943 }; 01944 /* Default value: 0x0000000000000000 */ 01945 01946 #define QIB_7322_MsixTableCorErrLogB_offset 0x000006a8UL 01947 struct QIB_7322_MsixTableCorErrLogB_pb { 01948 pseudo_bit_t MsixTable_2_CorErrData[32]; 01949 pseudo_bit_t MsixTable_0_CorErrCheckBits[7]; 01950 pseudo_bit_t MsixTable_1_CorErrCheckBits[7]; 01951 pseudo_bit_t MsixTable_2_CorErrCheckBits[7]; 01952 pseudo_bit_t _unused_0[11]; 01953 }; 01954 struct QIB_7322_MsixTableCorErrLogB { 01955 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogB_pb ); 01956 }; 01957 /* Default value: 0x0000000000000000 */ 01958 01959 #define QIB_7322_MsixTableCorErrLogC_offset 0x000006b0UL 01960 struct QIB_7322_MsixTableCorErrLogC_pb { 01961 pseudo_bit_t MsixTable_0_CorErrAddr[7]; 01962 pseudo_bit_t MsixTable_1_CorErrAddr[7]; 01963 pseudo_bit_t MsixTable_2_CorErrAddr[7]; 01964 pseudo_bit_t _unused_0[43]; 01965 }; 01966 struct QIB_7322_MsixTableCorErrLogC { 01967 PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogC_pb ); 01968 }; 01969 /* Default value: 0x0000000000000000 */ 01970 01971 #define QIB_7322_PcieCplDataBufrUnCorErrLogA_offset 0x00000700UL 01972 struct QIB_7322_PcieCplDataBufrUnCorErrLogA_pb { 01973 pseudo_bit_t PcieCplDataBufrUnCorErrData_63_0[64]; 01974 }; 01975 struct QIB_7322_PcieCplDataBufrUnCorErrLogA { 01976 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogA_pb ); 01977 }; 01978 /* Default value: 0x0000000000000000 */ 01979 01980 #define QIB_7322_PcieCplDataBufrUnCorErrLogB_offset 0x00000708UL 01981 struct QIB_7322_PcieCplDataBufrUnCorErrLogB_pb { 01982 pseudo_bit_t PcieCplDataBufrUnCorErrData_127_64[64]; 01983 }; 01984 struct QIB_7322_PcieCplDataBufrUnCorErrLogB { 01985 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogB_pb ); 01986 }; 01987 /* Default value: 0x0000000000000000 */ 01988 01989 #define QIB_7322_PcieCplDataBufrUnCorErrLogC_offset 0x00000710UL 01990 struct QIB_7322_PcieCplDataBufrUnCorErrLogC_pb { 01991 pseudo_bit_t PcieCplDataBufrUnCorErrData_136_128[9]; 01992 pseudo_bit_t PcieCplDataBufrUnCorErrCheckBit_21_0[22]; 01993 pseudo_bit_t PcieCplDataBufrUnCorErrAddr_13_0[14]; 01994 pseudo_bit_t _unused_0[19]; 01995 }; 01996 struct QIB_7322_PcieCplDataBufrUnCorErrLogC { 01997 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogC_pb ); 01998 }; 01999 /* Default value: 0x0000000000000000 */ 02000 02001 #define QIB_7322_PcieCplHdrBufrUnCorErrLogA_offset 0x00000720UL 02002 struct QIB_7322_PcieCplHdrBufrUnCorErrLogA_pb { 02003 pseudo_bit_t PcieCplHdrBufrUnCorErrHdr_63_0[64]; 02004 }; 02005 struct QIB_7322_PcieCplHdrBufrUnCorErrLogA { 02006 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogA_pb ); 02007 }; 02008 /* Default value: 0x0000000000000000 */ 02009 02010 #define QIB_7322_PcieCplHdrBufrUnCorErrLogB_offset 0x00000728UL 02011 struct QIB_7322_PcieCplHdrBufrUnCorErrLogB_pb { 02012 pseudo_bit_t PcieCplHdrBufrUnCorErrHdr_103_64[40]; 02013 pseudo_bit_t _unused_0[24]; 02014 }; 02015 struct QIB_7322_PcieCplHdrBufrUnCorErrLogB { 02016 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogB_pb ); 02017 }; 02018 /* Default value: 0x0000000000000000 */ 02019 02020 #define QIB_7322_PcieCplHdrBufrUnCorErrLogC_offset 0x00000730UL 02021 struct QIB_7322_PcieCplHdrBufrUnCorErrLogC_pb { 02022 pseudo_bit_t PcieCplHdrBufrUnCorErrCheckBit_15_0[16]; 02023 pseudo_bit_t PcieCplHdrBufrUnCorErrAddr_8_0[9]; 02024 pseudo_bit_t _unused_0[39]; 02025 }; 02026 struct QIB_7322_PcieCplHdrBufrUnCorErrLogC { 02027 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogC_pb ); 02028 }; 02029 /* Default value: 0x0000000000000000 */ 02030 02031 #define QIB_7322_PciePDataBufrUnCorErrLogA_offset 0x00000740UL 02032 struct QIB_7322_PciePDataBufrUnCorErrLogA_pb { 02033 pseudo_bit_t PciePDataBufrUnCorErrData_63_0[64]; 02034 }; 02035 struct QIB_7322_PciePDataBufrUnCorErrLogA { 02036 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogA_pb ); 02037 }; 02038 /* Default value: 0x0000000000000000 */ 02039 02040 #define QIB_7322_PciePDataBufrUnCorErrLogB_offset 0x00000748UL 02041 struct QIB_7322_PciePDataBufrUnCorErrLogB_pb { 02042 pseudo_bit_t PciePDataBufrUnCorErrData_127_64[64]; 02043 }; 02044 struct QIB_7322_PciePDataBufrUnCorErrLogB { 02045 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogB_pb ); 02046 }; 02047 /* Default value: 0x0000000000000000 */ 02048 02049 #define QIB_7322_PciePDataBufrUnCorErrLogC_offset 0x00000750UL 02050 struct QIB_7322_PciePDataBufrUnCorErrLogC_pb { 02051 pseudo_bit_t PciePDataBufrUnCorErrData_136_128[9]; 02052 pseudo_bit_t PciePDataBufrUnCorErrCheckBit_21_0[22]; 02053 pseudo_bit_t PciePDataBufrUnCorErrAddr_13_0[14]; 02054 pseudo_bit_t _unused_0[19]; 02055 }; 02056 struct QIB_7322_PciePDataBufrUnCorErrLogC { 02057 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogC_pb ); 02058 }; 02059 /* Default value: 0x0000000000000000 */ 02060 02061 #define QIB_7322_PciePHdrBufrUnCorErrLogA_offset 0x00000760UL 02062 struct QIB_7322_PciePHdrBufrUnCorErrLogA_pb { 02063 pseudo_bit_t PciePHdrBufrUnCorErrData_63_0[64]; 02064 }; 02065 struct QIB_7322_PciePHdrBufrUnCorErrLogA { 02066 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogA_pb ); 02067 }; 02068 /* Default value: 0x0000000000000000 */ 02069 02070 #define QIB_7322_PciePHdrBufrUnCorErrLogB_offset 0x00000768UL 02071 struct QIB_7322_PciePHdrBufrUnCorErrLogB_pb { 02072 pseudo_bit_t PciePHdrBufrUnCorErrData_107_64[44]; 02073 pseudo_bit_t _unused_0[20]; 02074 }; 02075 struct QIB_7322_PciePHdrBufrUnCorErrLogB { 02076 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogB_pb ); 02077 }; 02078 /* Default value: 0x0000000000000000 */ 02079 02080 #define QIB_7322_PciePHdrBufrUnCorErrLogC_offset 0x00000770UL 02081 struct QIB_7322_PciePHdrBufrUnCorErrLogC_pb { 02082 pseudo_bit_t PciePHdrBufrUnCorErrCheckBit_15_0[16]; 02083 pseudo_bit_t PciePHdrBufrUnCorErrAddr_8_0[9]; 02084 pseudo_bit_t _unused_0[39]; 02085 }; 02086 struct QIB_7322_PciePHdrBufrUnCorErrLogC { 02087 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogC_pb ); 02088 }; 02089 /* Default value: 0x0000000000000000 */ 02090 02091 #define QIB_7322_PcieRetryBufrUnCorErrLogA_offset 0x00000780UL 02092 struct QIB_7322_PcieRetryBufrUnCorErrLogA_pb { 02093 pseudo_bit_t PcieRetryBufrUnCorErrData_63_0[64]; 02094 }; 02095 struct QIB_7322_PcieRetryBufrUnCorErrLogA { 02096 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogA_pb ); 02097 }; 02098 /* Default value: 0x0000000000000000 */ 02099 02100 #define QIB_7322_PcieRetryBufrUnCorErrLogB_offset 0x00000788UL 02101 struct QIB_7322_PcieRetryBufrUnCorErrLogB_pb { 02102 pseudo_bit_t PcieRetryBufrUnCorErrData_127_64[64]; 02103 }; 02104 struct QIB_7322_PcieRetryBufrUnCorErrLogB { 02105 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogB_pb ); 02106 }; 02107 /* Default value: 0x0000000000000000 */ 02108 02109 #define QIB_7322_PcieRetryBufrUnCorErrLogC_offset 0x00000790UL 02110 struct QIB_7322_PcieRetryBufrUnCorErrLogC_pb { 02111 pseudo_bit_t PcieRetryBufrUnCorErrData_133_128[6]; 02112 pseudo_bit_t PcieRetryBufrUnCorErrCheckBit_20_0[21]; 02113 pseudo_bit_t PcieRetryBufrUnCorErrAddr_13_0[14]; 02114 pseudo_bit_t _unused_0[23]; 02115 }; 02116 struct QIB_7322_PcieRetryBufrUnCorErrLogC { 02117 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogC_pb ); 02118 }; 02119 /* Default value: 0x0000000000000000 */ 02120 02121 #define QIB_7322_RxTIDArrayUnCorErrLogA_offset 0x00000800UL 02122 struct QIB_7322_RxTIDArrayUnCorErrLogA_pb { 02123 pseudo_bit_t RxTIDArrayUnCorErrData_39_0[40]; 02124 pseudo_bit_t RxTIDArrayUnCorErrCheckBit_11_0[12]; 02125 pseudo_bit_t _unused_0[12]; 02126 }; 02127 struct QIB_7322_RxTIDArrayUnCorErrLogA { 02128 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayUnCorErrLogA_pb ); 02129 }; 02130 /* Default value: 0x0000000000000000 */ 02131 02132 #define QIB_7322_RxTIDArrayUnCorErrLogB_offset 0x00000808UL 02133 struct QIB_7322_RxTIDArrayUnCorErrLogB_pb { 02134 pseudo_bit_t RxTIDArrayUnCorErrAddr_16_0[17]; 02135 pseudo_bit_t _unused_0[47]; 02136 }; 02137 struct QIB_7322_RxTIDArrayUnCorErrLogB { 02138 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayUnCorErrLogB_pb ); 02139 }; 02140 /* Default value: 0x0000000000000000 */ 02141 02142 #define QIB_7322_RxEagerArrayUnCorErrLogA_offset 0x00000810UL 02143 struct QIB_7322_RxEagerArrayUnCorErrLogA_pb { 02144 pseudo_bit_t RxEagerArrayUnCorErrData_39_0[40]; 02145 pseudo_bit_t RxEagerArrayUnCorErrCheckBit_11_0[12]; 02146 pseudo_bit_t _unused_0[12]; 02147 }; 02148 struct QIB_7322_RxEagerArrayUnCorErrLogA { 02149 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayUnCorErrLogA_pb ); 02150 }; 02151 /* Default value: 0x0000000000000000 */ 02152 02153 #define QIB_7322_RxEagerArrayUnCorErrLogB_offset 0x00000818UL 02154 struct QIB_7322_RxEagerArrayUnCorErrLogB_pb { 02155 pseudo_bit_t RxEagerArrayUnCorErrAddr_17_0[18]; 02156 pseudo_bit_t _unused_0[46]; 02157 }; 02158 struct QIB_7322_RxEagerArrayUnCorErrLogB { 02159 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayUnCorErrLogB_pb ); 02160 }; 02161 /* Default value: 0x0000000000000000 */ 02162 02163 #define QIB_7322_SBufMainArrayUnCorErrLogA_offset 0x00000880UL 02164 struct QIB_7322_SBufMainArrayUnCorErrLogA_pb { 02165 pseudo_bit_t SBufMainArrayUnCorErrData_63_0[64]; 02166 }; 02167 struct QIB_7322_SBufMainArrayUnCorErrLogA { 02168 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogA_pb ); 02169 }; 02170 /* Default value: 0x0000000000000000 */ 02171 02172 #define QIB_7322_SBufMainArrayUnCorErrLogB_offset 0x00000888UL 02173 struct QIB_7322_SBufMainArrayUnCorErrLogB_pb { 02174 pseudo_bit_t SBufMainArrayUnCorErrData_127_64[64]; 02175 }; 02176 struct QIB_7322_SBufMainArrayUnCorErrLogB { 02177 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogB_pb ); 02178 }; 02179 /* Default value: 0x0000000000000000 */ 02180 02181 #define QIB_7322_SBufMainArrayUnCorErrLogC_offset 0x00000890UL 02182 struct QIB_7322_SBufMainArrayUnCorErrLogC_pb { 02183 pseudo_bit_t SBufMainArrayUnCorErrCheckBit_27_0[28]; 02184 pseudo_bit_t SBufMainArrayUnCorErrAddr_18_0[19]; 02185 pseudo_bit_t _unused_0[13]; 02186 pseudo_bit_t SBufMainArrayUnCorErrDword_3_0[4]; 02187 }; 02188 struct QIB_7322_SBufMainArrayUnCorErrLogC { 02189 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogC_pb ); 02190 }; 02191 /* Default value: 0x0000000000000000 */ 02192 02193 #define QIB_7322_SBufExtraArrayUnCorErrLogA_offset 0x00000898UL 02194 struct QIB_7322_SBufExtraArrayUnCorErrLogA_pb { 02195 pseudo_bit_t SBufExtraArrayUnCorErrData_63_0[64]; 02196 }; 02197 struct QIB_7322_SBufExtraArrayUnCorErrLogA { 02198 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogA_pb ); 02199 }; 02200 /* Default value: 0x0000000000000000 */ 02201 02202 #define QIB_7322_SBufExtraArrayUnCorErrLogB_offset 0x000008a0UL 02203 struct QIB_7322_SBufExtraArrayUnCorErrLogB_pb { 02204 pseudo_bit_t SBufExtraArrayUnCorErrData_127_64[64]; 02205 }; 02206 struct QIB_7322_SBufExtraArrayUnCorErrLogB { 02207 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogB_pb ); 02208 }; 02209 /* Default value: 0x0000000000000000 */ 02210 02211 #define QIB_7322_SBufExtraArrayUnCorErrLogC_offset 0x000008a8UL 02212 struct QIB_7322_SBufExtraArrayUnCorErrLogC_pb { 02213 pseudo_bit_t SBufExtraArrayUnCorErrCheckBit_27_0[28]; 02214 pseudo_bit_t SBufExtraArrayUnCorErrAddr_14_0[15]; 02215 pseudo_bit_t _unused_0[17]; 02216 pseudo_bit_t SBufExtraArrayUnCorErrAdd_3_0[4]; 02217 }; 02218 struct QIB_7322_SBufExtraArrayUnCorErrLogC { 02219 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogC_pb ); 02220 }; 02221 /* Default value: 0x0000000000000000 */ 02222 02223 #define QIB_7322_SendPbcArrayUnCorErrLog_offset 0x000008b0UL 02224 struct QIB_7322_SendPbcArrayUnCorErrLog_pb { 02225 pseudo_bit_t SendPbcArrayUnCorErrData_21_0[22]; 02226 pseudo_bit_t SendPbcArrayUnCorErrCheckBit_6_0[7]; 02227 pseudo_bit_t SendPbcArrayUnCorErrAddr_9_0[10]; 02228 pseudo_bit_t _unused_0[25]; 02229 }; 02230 struct QIB_7322_SendPbcArrayUnCorErrLog { 02231 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbcArrayUnCorErrLog_pb ); 02232 }; 02233 /* Default value: 0x0000000000000000 */ 02234 02235 #define QIB_7322_SBufVL15ArrayUnCorErrLogA_offset 0x000008c0UL 02236 struct QIB_7322_SBufVL15ArrayUnCorErrLogA_pb { 02237 pseudo_bit_t SBufVL15ArrayUnCorErrData_63_0[64]; 02238 }; 02239 struct QIB_7322_SBufVL15ArrayUnCorErrLogA { 02240 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufVL15ArrayUnCorErrLogA_pb ); 02241 }; 02242 /* Default value: 0x0000000000000000 */ 02243 02244 #define QIB_7322_PcieCplDataBufrCorErrLogA_offset 0x00000900UL 02245 struct QIB_7322_PcieCplDataBufrCorErrLogA_pb { 02246 pseudo_bit_t PcieCplDataBufrCorErrData_63_0[64]; 02247 }; 02248 struct QIB_7322_PcieCplDataBufrCorErrLogA { 02249 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogA_pb ); 02250 }; 02251 /* Default value: 0x0000000000000000 */ 02252 02253 #define QIB_7322_PcieCplDataBufrCorErrLogB_offset 0x00000908UL 02254 struct QIB_7322_PcieCplDataBufrCorErrLogB_pb { 02255 pseudo_bit_t PcieCplDataBufrCorErrData_127_64[64]; 02256 }; 02257 struct QIB_7322_PcieCplDataBufrCorErrLogB { 02258 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogB_pb ); 02259 }; 02260 /* Default value: 0x0000000000000000 */ 02261 02262 #define QIB_7322_PcieCplDataBufrCorErrLogC_offset 0x00000910UL 02263 struct QIB_7322_PcieCplDataBufrCorErrLogC_pb { 02264 pseudo_bit_t PcieCplDataBufrCorErrData_136_128[9]; 02265 pseudo_bit_t PcieCplDataBufrCorErrCheckBit_21_0[22]; 02266 pseudo_bit_t PcieCplDataBufrCorErrAddr_13_0[14]; 02267 pseudo_bit_t _unused_0[19]; 02268 }; 02269 struct QIB_7322_PcieCplDataBufrCorErrLogC { 02270 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogC_pb ); 02271 }; 02272 /* Default value: 0x0000000000000000 */ 02273 02274 #define QIB_7322_PcieCplHdrBufrCorErrLogA_offset 0x00000920UL 02275 struct QIB_7322_PcieCplHdrBufrCorErrLogA_pb { 02276 pseudo_bit_t PcieCplHdrBufrCorErrHdr_63_0[64]; 02277 }; 02278 struct QIB_7322_PcieCplHdrBufrCorErrLogA { 02279 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogA_pb ); 02280 }; 02281 /* Default value: 0x0000000000000000 */ 02282 02283 #define QIB_7322_PcieCplHdrBufrCorErrLogB_offset 0x00000928UL 02284 struct QIB_7322_PcieCplHdrBufrCorErrLogB_pb { 02285 pseudo_bit_t PcieCplHdrBufrCorErrHdr_103_64[40]; 02286 pseudo_bit_t _unused_0[24]; 02287 }; 02288 struct QIB_7322_PcieCplHdrBufrCorErrLogB { 02289 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogB_pb ); 02290 }; 02291 /* Default value: 0x0000000000000000 */ 02292 02293 #define QIB_7322_PcieCplHdrBufrCorErrLogC_offset 0x00000930UL 02294 struct QIB_7322_PcieCplHdrBufrCorErrLogC_pb { 02295 pseudo_bit_t PcieCplHdrBufrCorErrCheckBit_15_0[16]; 02296 pseudo_bit_t PcieCplHdrBufrCorErrAddr_8_0[9]; 02297 pseudo_bit_t _unused_0[39]; 02298 }; 02299 struct QIB_7322_PcieCplHdrBufrCorErrLogC { 02300 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogC_pb ); 02301 }; 02302 /* Default value: 0x0000000000000000 */ 02303 02304 #define QIB_7322_PciePDataBufrCorErrLogA_offset 0x00000940UL 02305 struct QIB_7322_PciePDataBufrCorErrLogA_pb { 02306 pseudo_bit_t PciePDataBufrCorErrData_63_0[64]; 02307 }; 02308 struct QIB_7322_PciePDataBufrCorErrLogA { 02309 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogA_pb ); 02310 }; 02311 /* Default value: 0x0000000000000000 */ 02312 02313 #define QIB_7322_PciePDataBufrCorErrLogB_offset 0x00000948UL 02314 struct QIB_7322_PciePDataBufrCorErrLogB_pb { 02315 pseudo_bit_t PciePDataBufrCorErrData_127_64[64]; 02316 }; 02317 struct QIB_7322_PciePDataBufrCorErrLogB { 02318 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogB_pb ); 02319 }; 02320 /* Default value: 0x0000000000000000 */ 02321 02322 #define QIB_7322_PciePDataBufrCorErrLogC_offset 0x00000950UL 02323 struct QIB_7322_PciePDataBufrCorErrLogC_pb { 02324 pseudo_bit_t PciePDataBufrCorErrData_136_128[9]; 02325 pseudo_bit_t PciePDataBufrCorErrCheckBit_21_0[22]; 02326 pseudo_bit_t PciePDataBufrCorErrAddr_13_0[14]; 02327 pseudo_bit_t _unused_0[19]; 02328 }; 02329 struct QIB_7322_PciePDataBufrCorErrLogC { 02330 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogC_pb ); 02331 }; 02332 /* Default value: 0x0000000000000000 */ 02333 02334 #define QIB_7322_PciePHdrBufrCorErrLogA_offset 0x00000960UL 02335 struct QIB_7322_PciePHdrBufrCorErrLogA_pb { 02336 pseudo_bit_t PciePHdrBufrCorErrData_63_0[64]; 02337 }; 02338 struct QIB_7322_PciePHdrBufrCorErrLogA { 02339 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogA_pb ); 02340 }; 02341 /* Default value: 0x0000000000000000 */ 02342 02343 #define QIB_7322_PciePHdrBufrCorErrLogB_offset 0x00000968UL 02344 struct QIB_7322_PciePHdrBufrCorErrLogB_pb { 02345 pseudo_bit_t PciePHdrBufrCorErrData_107_64[44]; 02346 pseudo_bit_t _unused_0[20]; 02347 }; 02348 struct QIB_7322_PciePHdrBufrCorErrLogB { 02349 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogB_pb ); 02350 }; 02351 /* Default value: 0x0000000000000000 */ 02352 02353 #define QIB_7322_PciePHdrBufrCorErrLogC_offset 0x00000970UL 02354 struct QIB_7322_PciePHdrBufrCorErrLogC_pb { 02355 pseudo_bit_t PciePHdrBufrCorErrCheckBit_15_0[16]; 02356 pseudo_bit_t PciePHdrBufrCorErrAddr_8_0[9]; 02357 pseudo_bit_t _unused_0[39]; 02358 }; 02359 struct QIB_7322_PciePHdrBufrCorErrLogC { 02360 PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogC_pb ); 02361 }; 02362 /* Default value: 0x0000000000000000 */ 02363 02364 #define QIB_7322_PcieRetryBufrCorErrLogA_offset 0x00000980UL 02365 struct QIB_7322_PcieRetryBufrCorErrLogA_pb { 02366 pseudo_bit_t PcieRetryBufrCorErrData_63_0[64]; 02367 }; 02368 struct QIB_7322_PcieRetryBufrCorErrLogA { 02369 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogA_pb ); 02370 }; 02371 /* Default value: 0x0000000000000000 */ 02372 02373 #define QIB_7322_PcieRetryBufrCorErrLogB_offset 0x00000988UL 02374 struct QIB_7322_PcieRetryBufrCorErrLogB_pb { 02375 pseudo_bit_t PcieRetryBufrCorErrData_127_64[64]; 02376 }; 02377 struct QIB_7322_PcieRetryBufrCorErrLogB { 02378 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogB_pb ); 02379 }; 02380 /* Default value: 0x0000000000000000 */ 02381 02382 #define QIB_7322_PcieRetryBufrCorErrLogC_offset 0x00000990UL 02383 struct QIB_7322_PcieRetryBufrCorErrLogC_pb { 02384 pseudo_bit_t PcieRetryBufrCorErrData_133_128[6]; 02385 pseudo_bit_t PcieRetryBufrCorErrCheckBit_20_0[21]; 02386 pseudo_bit_t PcieRetryBufrCorErrAddr_13_0[14]; 02387 pseudo_bit_t _unused_0[23]; 02388 }; 02389 struct QIB_7322_PcieRetryBufrCorErrLogC { 02390 PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogC_pb ); 02391 }; 02392 /* Default value: 0x0000000000000000 */ 02393 02394 #define QIB_7322_RxTIDArrayCorErrLogA_offset 0x00000a00UL 02395 struct QIB_7322_RxTIDArrayCorErrLogA_pb { 02396 pseudo_bit_t RxTIDArrayCorErrData_39_0[40]; 02397 pseudo_bit_t RxTIDArrayCorErrCheckBit_11_0[12]; 02398 pseudo_bit_t _unused_0[12]; 02399 }; 02400 struct QIB_7322_RxTIDArrayCorErrLogA { 02401 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayCorErrLogA_pb ); 02402 }; 02403 /* Default value: 0x0000000000000000 */ 02404 02405 #define QIB_7322_RxTIDArrayCorErrLogB_offset 0x00000a08UL 02406 struct QIB_7322_RxTIDArrayCorErrLogB_pb { 02407 pseudo_bit_t RxTIDArrayCorErrAddr_16_0[17]; 02408 pseudo_bit_t _unused_0[47]; 02409 }; 02410 struct QIB_7322_RxTIDArrayCorErrLogB { 02411 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayCorErrLogB_pb ); 02412 }; 02413 /* Default value: 0x0000000000000000 */ 02414 02415 #define QIB_7322_RxEagerArrayCorErrLogA_offset 0x00000a10UL 02416 struct QIB_7322_RxEagerArrayCorErrLogA_pb { 02417 pseudo_bit_t RxEagerArrayCorErrData_39_0[40]; 02418 pseudo_bit_t RxEagerArrayCorErrCheckBit_11_0[12]; 02419 pseudo_bit_t _unused_0[12]; 02420 }; 02421 struct QIB_7322_RxEagerArrayCorErrLogA { 02422 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayCorErrLogA_pb ); 02423 }; 02424 /* Default value: 0x0000000000000000 */ 02425 02426 #define QIB_7322_RxEagerArrayCorErrLogB_offset 0x00000a18UL 02427 struct QIB_7322_RxEagerArrayCorErrLogB_pb { 02428 pseudo_bit_t RxEagerArrayCorErrAddr_17_0[18]; 02429 pseudo_bit_t _unused_0[46]; 02430 }; 02431 struct QIB_7322_RxEagerArrayCorErrLogB { 02432 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayCorErrLogB_pb ); 02433 }; 02434 /* Default value: 0x0000000000000000 */ 02435 02436 #define QIB_7322_SBufMainArrayCorErrLogA_offset 0x00000a80UL 02437 struct QIB_7322_SBufMainArrayCorErrLogA_pb { 02438 pseudo_bit_t SBufMainArrayCorErrData_63_0[64]; 02439 }; 02440 struct QIB_7322_SBufMainArrayCorErrLogA { 02441 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogA_pb ); 02442 }; 02443 /* Default value: 0x0000000000000000 */ 02444 02445 #define QIB_7322_SBufMainArrayCorErrLogB_offset 0x00000a88UL 02446 struct QIB_7322_SBufMainArrayCorErrLogB_pb { 02447 pseudo_bit_t SBufMainArrayCorErrData_127_64[64]; 02448 }; 02449 struct QIB_7322_SBufMainArrayCorErrLogB { 02450 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogB_pb ); 02451 }; 02452 /* Default value: 0x0000000000000000 */ 02453 02454 #define QIB_7322_SBufMainArrayCorErrLogC_offset 0x00000a90UL 02455 struct QIB_7322_SBufMainArrayCorErrLogC_pb { 02456 pseudo_bit_t SBufMainArrayCorErrCheckBit_27_0[28]; 02457 pseudo_bit_t SBufMainArrayCorErrAddr_18_0[19]; 02458 pseudo_bit_t _unused_0[13]; 02459 pseudo_bit_t SBufMainArrayCorErrDword_3_0[4]; 02460 }; 02461 struct QIB_7322_SBufMainArrayCorErrLogC { 02462 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogC_pb ); 02463 }; 02464 /* Default value: 0x0000000000000000 */ 02465 02466 #define QIB_7322_SBufExtraArrayCorErrLogA_offset 0x00000a98UL 02467 struct QIB_7322_SBufExtraArrayCorErrLogA_pb { 02468 pseudo_bit_t SBufExtraArrayCorErrData_63_0[64]; 02469 }; 02470 struct QIB_7322_SBufExtraArrayCorErrLogA { 02471 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogA_pb ); 02472 }; 02473 /* Default value: 0x0000000000000000 */ 02474 02475 #define QIB_7322_SBufExtraArrayCorErrLogB_offset 0x00000aa0UL 02476 struct QIB_7322_SBufExtraArrayCorErrLogB_pb { 02477 pseudo_bit_t SBufExtraArrayCorErrData_127_64[64]; 02478 }; 02479 struct QIB_7322_SBufExtraArrayCorErrLogB { 02480 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogB_pb ); 02481 }; 02482 /* Default value: 0x0000000000000000 */ 02483 02484 #define QIB_7322_SBufExtraArrayCorErrLogC_offset 0x00000aa8UL 02485 struct QIB_7322_SBufExtraArrayCorErrLogC_pb { 02486 pseudo_bit_t SBufExtraArrayCorErrCheckBit_27_0[28]; 02487 pseudo_bit_t SBufExtraArrayCorErrAddr_14_0[15]; 02488 pseudo_bit_t _unused_0[17]; 02489 pseudo_bit_t SBufExtraArrayCorErrAdd_3_0[4]; 02490 }; 02491 struct QIB_7322_SBufExtraArrayCorErrLogC { 02492 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogC_pb ); 02493 }; 02494 /* Default value: 0x0000000000000000 */ 02495 02496 #define QIB_7322_SendPbcArrayCorErrLog_offset 0x00000ab0UL 02497 struct QIB_7322_SendPbcArrayCorErrLog_pb { 02498 pseudo_bit_t SendPbcArrayCorErrData_21_0[22]; 02499 pseudo_bit_t SendPbcArrayCorErrCheckBit_6_0[7]; 02500 pseudo_bit_t SendPbcArrayCorErrAddr_9_0[10]; 02501 pseudo_bit_t _unused_0[25]; 02502 }; 02503 struct QIB_7322_SendPbcArrayCorErrLog { 02504 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbcArrayCorErrLog_pb ); 02505 }; 02506 /* Default value: 0x0000000000000000 */ 02507 02508 #define QIB_7322_SBufVL15ArrayCorErrLogA_offset 0x00000ac0UL 02509 struct QIB_7322_SBufVL15ArrayCorErrLogA_pb { 02510 pseudo_bit_t SBufVL15ArrayCorErrData_63_0[64]; 02511 }; 02512 struct QIB_7322_SBufVL15ArrayCorErrLogA { 02513 PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufVL15ArrayCorErrLogA_pb ); 02514 }; 02515 /* Default value: 0x0000000000000000 */ 02516 02517 #define QIB_7322_RcvAvailTimeOut0_offset 0x00000c00UL 02518 struct QIB_7322_RcvAvailTimeOut0_pb { 02519 pseudo_bit_t RcvAvailTOReload[16]; 02520 pseudo_bit_t RcvAvailTOCount[16]; 02521 pseudo_bit_t _unused_0[32]; 02522 }; 02523 struct QIB_7322_RcvAvailTimeOut0 { 02524 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvAvailTimeOut0_pb ); 02525 }; 02526 /* Default value: 0x0000000000000000 */ 02527 02528 #define QIB_7322_CntrRegBase_0_offset 0x00001028UL 02529 /* Default value: 0x0000000000012000 */ 02530 02531 #define QIB_7322_ErrMask_0_offset 0x00001080UL 02532 struct QIB_7322_ErrMask_0_pb { 02533 pseudo_bit_t RcvFormatErrMask[1]; 02534 pseudo_bit_t RcvVCRCErrMask[1]; 02535 pseudo_bit_t RcvICRCErrMask[1]; 02536 pseudo_bit_t RcvMinPktLenErrMask[1]; 02537 pseudo_bit_t RcvMaxPktLenErrMask[1]; 02538 pseudo_bit_t RcvLongPktLenErrMask[1]; 02539 pseudo_bit_t RcvShortPktLenErrMask[1]; 02540 pseudo_bit_t RcvUnexpectedCharErrMask[1]; 02541 pseudo_bit_t RcvUnsupportedVLErrMask[1]; 02542 pseudo_bit_t RcvEBPErrMask[1]; 02543 pseudo_bit_t RcvIBFlowErrMask[1]; 02544 pseudo_bit_t RcvBadVersionErrMask[1]; 02545 pseudo_bit_t _unused_0[2]; 02546 pseudo_bit_t RcvBadTidErrMask[1]; 02547 pseudo_bit_t RcvHdrLenErrMask[1]; 02548 pseudo_bit_t RcvHdrErrMask[1]; 02549 pseudo_bit_t RcvIBLostLinkErrMask[1]; 02550 pseudo_bit_t _unused_1[11]; 02551 pseudo_bit_t SendMinPktLenErrMask[1]; 02552 pseudo_bit_t SendMaxPktLenErrMask[1]; 02553 pseudo_bit_t SendUnderRunErrMask[1]; 02554 pseudo_bit_t SendPktLenErrMask[1]; 02555 pseudo_bit_t SendDroppedSmpPktErrMask[1]; 02556 pseudo_bit_t SendDroppedDataPktErrMask[1]; 02557 pseudo_bit_t _unused_2[1]; 02558 pseudo_bit_t SendUnexpectedPktNumErrMask[1]; 02559 pseudo_bit_t SendUnsupportedVLErrMask[1]; 02560 pseudo_bit_t SendBufMisuseErrMask[1]; 02561 pseudo_bit_t SDmaGenMismatchErrMask[1]; 02562 pseudo_bit_t SDmaOutOfBoundErrMask[1]; 02563 pseudo_bit_t SDmaTailOutOfBoundErrMask[1]; 02564 pseudo_bit_t SDmaBaseErrMask[1]; 02565 pseudo_bit_t SDma1stDescErrMask[1]; 02566 pseudo_bit_t SDmaRpyTagErrMask[1]; 02567 pseudo_bit_t SDmaDwEnErrMask[1]; 02568 pseudo_bit_t SDmaMissingDwErrMask[1]; 02569 pseudo_bit_t SDmaUnexpDataErrMask[1]; 02570 pseudo_bit_t SDmaDescAddrMisalignErrMask[1]; 02571 pseudo_bit_t SDmaHaltErrMask[1]; 02572 pseudo_bit_t _unused_3[4]; 02573 pseudo_bit_t VL15BufMisuseErrMask[1]; 02574 pseudo_bit_t _unused_4[2]; 02575 pseudo_bit_t SHeadersErrMask[1]; 02576 pseudo_bit_t IBStatusChangedMask[1]; 02577 pseudo_bit_t _unused_5[5]; 02578 }; 02579 struct QIB_7322_ErrMask_0 { 02580 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_0_pb ); 02581 }; 02582 /* Default value: 0x0000000000000000 */ 02583 02584 #define QIB_7322_ErrStatus_0_offset 0x00001088UL 02585 struct QIB_7322_ErrStatus_0_pb { 02586 pseudo_bit_t RcvFormatErr[1]; 02587 pseudo_bit_t RcvVCRCErr[1]; 02588 pseudo_bit_t RcvICRCErr[1]; 02589 pseudo_bit_t RcvMinPktLenErr[1]; 02590 pseudo_bit_t RcvMaxPktLenErr[1]; 02591 pseudo_bit_t RcvLongPktLenErr[1]; 02592 pseudo_bit_t RcvShortPktLenErr[1]; 02593 pseudo_bit_t RcvUnexpectedCharErr[1]; 02594 pseudo_bit_t RcvUnsupportedVLErr[1]; 02595 pseudo_bit_t RcvEBPErr[1]; 02596 pseudo_bit_t RcvIBFlowErr[1]; 02597 pseudo_bit_t RcvBadVersionErr[1]; 02598 pseudo_bit_t _unused_0[2]; 02599 pseudo_bit_t RcvBadTidErr[1]; 02600 pseudo_bit_t RcvHdrLenErr[1]; 02601 pseudo_bit_t RcvHdrErr[1]; 02602 pseudo_bit_t RcvIBLostLinkErr[1]; 02603 pseudo_bit_t _unused_1[11]; 02604 pseudo_bit_t SendMinPktLenErr[1]; 02605 pseudo_bit_t SendMaxPktLenErr[1]; 02606 pseudo_bit_t SendUnderRunErr[1]; 02607 pseudo_bit_t SendPktLenErr[1]; 02608 pseudo_bit_t SendDroppedSmpPktErr[1]; 02609 pseudo_bit_t SendDroppedDataPktErr[1]; 02610 pseudo_bit_t _unused_2[1]; 02611 pseudo_bit_t SendUnexpectedPktNumErr[1]; 02612 pseudo_bit_t SendUnsupportedVLErr[1]; 02613 pseudo_bit_t SendBufMisuseErr[1]; 02614 pseudo_bit_t SDmaGenMismatchErr[1]; 02615 pseudo_bit_t SDmaOutOfBoundErr[1]; 02616 pseudo_bit_t SDmaTailOutOfBoundErr[1]; 02617 pseudo_bit_t SDmaBaseErr[1]; 02618 pseudo_bit_t SDma1stDescErr[1]; 02619 pseudo_bit_t SDmaRpyTagErr[1]; 02620 pseudo_bit_t SDmaDwEnErr[1]; 02621 pseudo_bit_t SDmaMissingDwErr[1]; 02622 pseudo_bit_t SDmaUnexpDataErr[1]; 02623 pseudo_bit_t SDmaDescAddrMisalignErr[1]; 02624 pseudo_bit_t SDmaHaltErr[1]; 02625 pseudo_bit_t _unused_3[4]; 02626 pseudo_bit_t VL15BufMisuseErr[1]; 02627 pseudo_bit_t _unused_4[2]; 02628 pseudo_bit_t SHeadersErr[1]; 02629 pseudo_bit_t IBStatusChanged[1]; 02630 pseudo_bit_t _unused_5[5]; 02631 }; 02632 struct QIB_7322_ErrStatus_0 { 02633 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_0_pb ); 02634 }; 02635 /* Default value: 0x0000000000000000 */ 02636 02637 #define QIB_7322_ErrClear_0_offset 0x00001090UL 02638 struct QIB_7322_ErrClear_0_pb { 02639 pseudo_bit_t RcvFormatErrClear[1]; 02640 pseudo_bit_t RcvVCRCErrClear[1]; 02641 pseudo_bit_t RcvICRCErrClear[1]; 02642 pseudo_bit_t RcvMinPktLenErrClear[1]; 02643 pseudo_bit_t RcvMaxPktLenErrClear[1]; 02644 pseudo_bit_t RcvLongPktLenErrClear[1]; 02645 pseudo_bit_t RcvShortPktLenErrClear[1]; 02646 pseudo_bit_t RcvUnexpectedCharErrClear[1]; 02647 pseudo_bit_t RcvUnsupportedVLErrClear[1]; 02648 pseudo_bit_t RcvEBPErrClear[1]; 02649 pseudo_bit_t RcvIBFlowErrClear[1]; 02650 pseudo_bit_t RcvBadVersionErrClear[1]; 02651 pseudo_bit_t _unused_0[2]; 02652 pseudo_bit_t RcvBadTidErrClear[1]; 02653 pseudo_bit_t RcvHdrLenErrClear[1]; 02654 pseudo_bit_t RcvHdrErrClear[1]; 02655 pseudo_bit_t RcvIBLostLinkErrClear[1]; 02656 pseudo_bit_t _unused_1[11]; 02657 pseudo_bit_t SendMinPktLenErrClear[1]; 02658 pseudo_bit_t SendMaxPktLenErrClear[1]; 02659 pseudo_bit_t SendUnderRunErrClear[1]; 02660 pseudo_bit_t SendPktLenErrClear[1]; 02661 pseudo_bit_t SendDroppedSmpPktErrClear[1]; 02662 pseudo_bit_t SendDroppedDataPktErrClear[1]; 02663 pseudo_bit_t _unused_2[1]; 02664 pseudo_bit_t SendUnexpectedPktNumErrClear[1]; 02665 pseudo_bit_t SendUnsupportedVLErrClear[1]; 02666 pseudo_bit_t SendBufMisuseErrClear[1]; 02667 pseudo_bit_t SDmaGenMismatchErrClear[1]; 02668 pseudo_bit_t SDmaOutOfBoundErrClear[1]; 02669 pseudo_bit_t SDmaTailOutOfBoundErrClear[1]; 02670 pseudo_bit_t SDmaBaseErrClear[1]; 02671 pseudo_bit_t SDma1stDescErrClear[1]; 02672 pseudo_bit_t SDmaRpyTagErrClear[1]; 02673 pseudo_bit_t SDmaDwEnErrClear[1]; 02674 pseudo_bit_t SDmaMissingDwErrClear[1]; 02675 pseudo_bit_t SDmaUnexpDataErrClear[1]; 02676 pseudo_bit_t SDmaDescAddrMisalignErrClear[1]; 02677 pseudo_bit_t SDmaHaltErrClear[1]; 02678 pseudo_bit_t _unused_3[4]; 02679 pseudo_bit_t VL15BufMisuseErrClear[1]; 02680 pseudo_bit_t _unused_4[2]; 02681 pseudo_bit_t SHeadersErrClear[1]; 02682 pseudo_bit_t IBStatusChangedClear[1]; 02683 pseudo_bit_t _unused_5[5]; 02684 }; 02685 struct QIB_7322_ErrClear_0 { 02686 PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_0_pb ); 02687 }; 02688 /* Default value: 0x0000000000000000 */ 02689 02690 #define QIB_7322_TXEStatus_0_offset 0x000010b8UL 02691 struct QIB_7322_TXEStatus_0_pb { 02692 pseudo_bit_t LaFifoEmpty_VL0[1]; 02693 pseudo_bit_t LaFifoEmpty_VL1[1]; 02694 pseudo_bit_t LaFifoEmpty_VL2[1]; 02695 pseudo_bit_t LaFifoEmpty_VL3[1]; 02696 pseudo_bit_t LaFifoEmpty_VL4[1]; 02697 pseudo_bit_t LaFifoEmpty_VL5[1]; 02698 pseudo_bit_t LaFifoEmpty_VL6[1]; 02699 pseudo_bit_t LaFifoEmpty_VL7[1]; 02700 pseudo_bit_t _unused_0[7]; 02701 pseudo_bit_t LaFifoEmpty_VL15[1]; 02702 pseudo_bit_t _unused_1[14]; 02703 pseudo_bit_t RmFifoEmpty[1]; 02704 pseudo_bit_t TXE_IBC_Idle[1]; 02705 pseudo_bit_t _unused_2[32]; 02706 }; 02707 struct QIB_7322_TXEStatus_0 { 02708 PSEUDO_BIT_STRUCT ( struct QIB_7322_TXEStatus_0_pb ); 02709 }; 02710 /* Default value: 0x0000000XC00080FF */ 02711 02712 #define QIB_7322_RcvCtrl_0_offset 0x00001100UL 02713 struct QIB_7322_RcvCtrl_0_pb { 02714 pseudo_bit_t ContextEnableKernel[1]; 02715 pseudo_bit_t _unused_0[1]; 02716 pseudo_bit_t ContextEnableUser[16]; 02717 pseudo_bit_t _unused_1[21]; 02718 pseudo_bit_t RcvIBPortEnable[1]; 02719 pseudo_bit_t RcvQPMapEnable[1]; 02720 pseudo_bit_t RcvPartitionKeyDisable[1]; 02721 pseudo_bit_t RcvResetCredit[1]; 02722 pseudo_bit_t _unused_2[21]; 02723 }; 02724 struct QIB_7322_RcvCtrl_0 { 02725 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_0_pb ); 02726 }; 02727 /* Default value: 0x0000000000000000 */ 02728 02729 #define QIB_7322_RcvBTHQP_0_offset 0x00001108UL 02730 struct QIB_7322_RcvBTHQP_0_pb { 02731 pseudo_bit_t RcvBTHQP[24]; 02732 pseudo_bit_t _unused_0[40]; 02733 }; 02734 struct QIB_7322_RcvBTHQP_0 { 02735 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvBTHQP_0_pb ); 02736 }; 02737 /* Default value: 0x0000000000000000 */ 02738 02739 #define QIB_7322_RcvQPMapTableA_0_offset 0x00001110UL 02740 struct QIB_7322_RcvQPMapTableA_0_pb { 02741 pseudo_bit_t RcvQPMapContext0[5]; 02742 pseudo_bit_t RcvQPMapContext1[5]; 02743 pseudo_bit_t RcvQPMapContext2[5]; 02744 pseudo_bit_t RcvQPMapContext3[5]; 02745 pseudo_bit_t RcvQPMapContext4[5]; 02746 pseudo_bit_t RcvQPMapContext5[5]; 02747 pseudo_bit_t _unused_0[34]; 02748 }; 02749 struct QIB_7322_RcvQPMapTableA_0 { 02750 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableA_0_pb ); 02751 }; 02752 /* Default value: 0x0000000000000000 */ 02753 02754 #define QIB_7322_RcvQPMapTableB_0_offset 0x00001118UL 02755 struct QIB_7322_RcvQPMapTableB_0_pb { 02756 pseudo_bit_t RcvQPMapContext6[5]; 02757 pseudo_bit_t RcvQPMapContext7[5]; 02758 pseudo_bit_t RcvQPMapContext8[5]; 02759 pseudo_bit_t RcvQPMapContext9[5]; 02760 pseudo_bit_t RcvQPMapContext10[5]; 02761 pseudo_bit_t RcvQPMapContext11[5]; 02762 pseudo_bit_t _unused_0[34]; 02763 }; 02764 struct QIB_7322_RcvQPMapTableB_0 { 02765 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableB_0_pb ); 02766 }; 02767 /* Default value: 0x0000000000000000 */ 02768 02769 #define QIB_7322_RcvQPMapTableC_0_offset 0x00001120UL 02770 struct QIB_7322_RcvQPMapTableC_0_pb { 02771 pseudo_bit_t RcvQPMapContext12[5]; 02772 pseudo_bit_t RcvQPMapContext13[5]; 02773 pseudo_bit_t RcvQPMapContext14[5]; 02774 pseudo_bit_t RcvQPMapContext15[5]; 02775 pseudo_bit_t RcvQPMapContext16[5]; 02776 pseudo_bit_t RcvQPMapContext17[5]; 02777 pseudo_bit_t _unused_0[34]; 02778 }; 02779 struct QIB_7322_RcvQPMapTableC_0 { 02780 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableC_0_pb ); 02781 }; 02782 /* Default value: 0x0000000000000000 */ 02783 02784 #define QIB_7322_RcvQPMapTableD_0_offset 0x00001128UL 02785 struct QIB_7322_RcvQPMapTableD_0_pb { 02786 pseudo_bit_t RcvQPMapContext18[5]; 02787 pseudo_bit_t RcvQPMapContext19[5]; 02788 pseudo_bit_t RcvQPMapContext20[5]; 02789 pseudo_bit_t RcvQPMapContext21[5]; 02790 pseudo_bit_t RcvQPMapContext22[5]; 02791 pseudo_bit_t RcvQPMapContext23[5]; 02792 pseudo_bit_t _unused_0[34]; 02793 }; 02794 struct QIB_7322_RcvQPMapTableD_0 { 02795 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableD_0_pb ); 02796 }; 02797 /* Default value: 0x0000000000000000 */ 02798 02799 #define QIB_7322_RcvQPMapTableE_0_offset 0x00001130UL 02800 struct QIB_7322_RcvQPMapTableE_0_pb { 02801 pseudo_bit_t RcvQPMapContext24[5]; 02802 pseudo_bit_t RcvQPMapContext25[5]; 02803 pseudo_bit_t RcvQPMapContext26[5]; 02804 pseudo_bit_t RcvQPMapContext27[5]; 02805 pseudo_bit_t RcvQPMapContext28[5]; 02806 pseudo_bit_t RcvQPMapContext29[5]; 02807 pseudo_bit_t _unused_0[34]; 02808 }; 02809 struct QIB_7322_RcvQPMapTableE_0 { 02810 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableE_0_pb ); 02811 }; 02812 /* Default value: 0x0000000000000000 */ 02813 02814 #define QIB_7322_RcvQPMapTableF_0_offset 0x00001138UL 02815 struct QIB_7322_RcvQPMapTableF_0_pb { 02816 pseudo_bit_t RcvQPMapContext30[5]; 02817 pseudo_bit_t RcvQPMapContext31[5]; 02818 pseudo_bit_t _unused_0[54]; 02819 }; 02820 struct QIB_7322_RcvQPMapTableF_0 { 02821 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableF_0_pb ); 02822 }; 02823 /* Default value: 0x0000000000000000 */ 02824 02825 #define QIB_7322_PSStat_0_offset 0x00001140UL 02826 /* Default value: 0x0000000000000000 */ 02827 02828 #define QIB_7322_PSStart_0_offset 0x00001148UL 02829 /* Default value: 0x0000000000000000 */ 02830 02831 #define QIB_7322_PSInterval_0_offset 0x00001150UL 02832 /* Default value: 0x0000000000000000 */ 02833 02834 #define QIB_7322_RcvStatus_0_offset 0x00001160UL 02835 struct QIB_7322_RcvStatus_0_pb { 02836 pseudo_bit_t RxPktInProgress[1]; 02837 pseudo_bit_t DmaeqBlockingContext[5]; 02838 pseudo_bit_t _unused_0[58]; 02839 }; 02840 struct QIB_7322_RcvStatus_0 { 02841 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvStatus_0_pb ); 02842 }; 02843 /* Default value: 0x0000000000000000 */ 02844 02845 #define QIB_7322_RcvPartitionKey_0_offset 0x00001168UL 02846 /* Default value: 0x0000000000000000 */ 02847 02848 #define QIB_7322_RcvQPMulticastContext_0_offset 0x00001170UL 02849 struct QIB_7322_RcvQPMulticastContext_0_pb { 02850 pseudo_bit_t RcvQpMcContext[5]; 02851 pseudo_bit_t _unused_0[59]; 02852 }; 02853 struct QIB_7322_RcvQPMulticastContext_0 { 02854 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMulticastContext_0_pb ); 02855 }; 02856 /* Default value: 0x0000000000000000 */ 02857 02858 #define QIB_7322_RcvPktLEDCnt_0_offset 0x00001178UL 02859 struct QIB_7322_RcvPktLEDCnt_0_pb { 02860 pseudo_bit_t OFFperiod[32]; 02861 pseudo_bit_t ONperiod[32]; 02862 }; 02863 struct QIB_7322_RcvPktLEDCnt_0 { 02864 PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvPktLEDCnt_0_pb ); 02865 }; 02866 /* Default value: 0x0000000000000000 */ 02867 02868 #define QIB_7322_SendDmaIdleCnt_0_offset 0x00001180UL 02869 struct QIB_7322_SendDmaIdleCnt_0_pb { 02870 pseudo_bit_t SendDmaIdleCnt[16]; 02871 pseudo_bit_t _unused_0[48]; 02872 }; 02873 struct QIB_7322_SendDmaIdleCnt_0 { 02874 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaIdleCnt_0_pb ); 02875 }; 02876 /* Default value: 0x0000000000000000 */ 02877 02878 #define QIB_7322_SendDmaReloadCnt_0_offset 0x00001188UL 02879 struct QIB_7322_SendDmaReloadCnt_0_pb { 02880 pseudo_bit_t SendDmaReloadCnt[16]; 02881 pseudo_bit_t _unused_0[48]; 02882 }; 02883 struct QIB_7322_SendDmaReloadCnt_0 { 02884 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReloadCnt_0_pb ); 02885 }; 02886 /* Default value: 0x0000000000000000 */ 02887 02888 #define QIB_7322_SendDmaDescCnt_0_offset 0x00001190UL 02889 struct QIB_7322_SendDmaDescCnt_0_pb { 02890 pseudo_bit_t SendDmaDescCnt[16]; 02891 pseudo_bit_t _unused_0[48]; 02892 }; 02893 struct QIB_7322_SendDmaDescCnt_0 { 02894 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaDescCnt_0_pb ); 02895 }; 02896 /* Default value: 0x0000000000000000 */ 02897 02898 #define QIB_7322_SendCtrl_0_offset 0x000011c0UL 02899 struct QIB_7322_SendCtrl_0_pb { 02900 pseudo_bit_t TxeAbortIbc[1]; 02901 pseudo_bit_t TxeBypassIbc[1]; 02902 pseudo_bit_t _unused_0[1]; 02903 pseudo_bit_t SendEnable[1]; 02904 pseudo_bit_t _unused_1[3]; 02905 pseudo_bit_t ForceCreditUpToDate[1]; 02906 pseudo_bit_t SDmaCleanup[1]; 02907 pseudo_bit_t SDmaIntEnable[1]; 02908 pseudo_bit_t SDmaSingleDescriptor[1]; 02909 pseudo_bit_t SDmaEnable[1]; 02910 pseudo_bit_t SDmaHalt[1]; 02911 pseudo_bit_t TxeDrainLaFifo[1]; 02912 pseudo_bit_t TxeDrainRmFifo[1]; 02913 pseudo_bit_t IBVLArbiterEn[1]; 02914 pseudo_bit_t _unused_2[48]; 02915 }; 02916 struct QIB_7322_SendCtrl_0 { 02917 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_0_pb ); 02918 }; 02919 /* Default value: 0x0000000000000000 */ 02920 02921 #define QIB_7322_SendDmaBase_0_offset 0x000011f8UL 02922 struct QIB_7322_SendDmaBase_0_pb { 02923 pseudo_bit_t SendDmaBase[48]; 02924 pseudo_bit_t _unused_0[16]; 02925 }; 02926 struct QIB_7322_SendDmaBase_0 { 02927 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBase_0_pb ); 02928 }; 02929 /* Default value: 0x0000000000000000 */ 02930 02931 #define QIB_7322_SendDmaLenGen_0_offset 0x00001200UL 02932 struct QIB_7322_SendDmaLenGen_0_pb { 02933 pseudo_bit_t Length[16]; 02934 pseudo_bit_t Generation[3]; 02935 pseudo_bit_t _unused_0[45]; 02936 }; 02937 struct QIB_7322_SendDmaLenGen_0 { 02938 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaLenGen_0_pb ); 02939 }; 02940 /* Default value: 0x0000000000000000 */ 02941 02942 #define QIB_7322_SendDmaTail_0_offset 0x00001208UL 02943 struct QIB_7322_SendDmaTail_0_pb { 02944 pseudo_bit_t SendDmaTail[16]; 02945 pseudo_bit_t _unused_0[48]; 02946 }; 02947 struct QIB_7322_SendDmaTail_0 { 02948 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaTail_0_pb ); 02949 }; 02950 /* Default value: 0x0000000000000000 */ 02951 02952 #define QIB_7322_SendDmaHead_0_offset 0x00001210UL 02953 struct QIB_7322_SendDmaHead_0_pb { 02954 pseudo_bit_t SendDmaHead[16]; 02955 pseudo_bit_t _unused_0[16]; 02956 pseudo_bit_t InternalSendDmaHead[16]; 02957 pseudo_bit_t _unused_1[16]; 02958 }; 02959 struct QIB_7322_SendDmaHead_0 { 02960 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHead_0_pb ); 02961 }; 02962 /* Default value: 0x0000000000000000 */ 02963 02964 #define QIB_7322_SendDmaHeadAddr_0_offset 0x00001218UL 02965 struct QIB_7322_SendDmaHeadAddr_0_pb { 02966 pseudo_bit_t SendDmaHeadAddr[48]; 02967 pseudo_bit_t _unused_0[16]; 02968 }; 02969 struct QIB_7322_SendDmaHeadAddr_0 { 02970 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHeadAddr_0_pb ); 02971 }; 02972 /* Default value: 0x0000000000000000 */ 02973 02974 #define QIB_7322_SendDmaBufMask0_0_offset 0x00001220UL 02975 struct QIB_7322_SendDmaBufMask0_0_pb { 02976 pseudo_bit_t BufMask_63_0[64]; 02977 }; 02978 struct QIB_7322_SendDmaBufMask0_0 { 02979 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufMask0_0_pb ); 02980 }; 02981 /* Default value: 0x0000000000000000 */ 02982 02983 #define QIB_7322_SendDmaStatus_0_offset 0x00001238UL 02984 struct QIB_7322_SendDmaStatus_0_pb { 02985 pseudo_bit_t SplFifoDescIndex[16]; 02986 pseudo_bit_t SplFifoBufNum[8]; 02987 pseudo_bit_t SplFifoFull[1]; 02988 pseudo_bit_t SplFifoEmpty[1]; 02989 pseudo_bit_t SplFifoDisarmed[1]; 02990 pseudo_bit_t SplFifoReadyToGo[1]; 02991 pseudo_bit_t ScbFetchDescFlag[1]; 02992 pseudo_bit_t ScbEntryValid[1]; 02993 pseudo_bit_t ScbEmpty[1]; 02994 pseudo_bit_t ScbFull[1]; 02995 pseudo_bit_t RpyTag_7_0[8]; 02996 pseudo_bit_t RpyLowAddr_6_0[7]; 02997 pseudo_bit_t ScbDescIndex_13_0[14]; 02998 pseudo_bit_t InternalSDmaHalt[1]; 02999 pseudo_bit_t HaltInProg[1]; 03000 pseudo_bit_t ScoreBoardDrainInProg[1]; 03001 }; 03002 struct QIB_7322_SendDmaStatus_0 { 03003 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaStatus_0_pb ); 03004 }; 03005 /* Default value: 0x0000000042000000 */ 03006 03007 #define QIB_7322_SendDmaPriorityThld_0_offset 0x00001258UL 03008 struct QIB_7322_SendDmaPriorityThld_0_pb { 03009 pseudo_bit_t PriorityThreshold[4]; 03010 pseudo_bit_t _unused_0[60]; 03011 }; 03012 struct QIB_7322_SendDmaPriorityThld_0 { 03013 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaPriorityThld_0_pb ); 03014 }; 03015 /* Default value: 0x0000000000000000 */ 03016 03017 #define QIB_7322_SendHdrErrSymptom_0_offset 0x00001260UL 03018 struct QIB_7322_SendHdrErrSymptom_0_pb { 03019 pseudo_bit_t PacketTooSmall[1]; 03020 pseudo_bit_t RawIPV6[1]; 03021 pseudo_bit_t SLIDFail[1]; 03022 pseudo_bit_t QPFail[1]; 03023 pseudo_bit_t PkeyFail[1]; 03024 pseudo_bit_t GRHFail[1]; 03025 pseudo_bit_t NonKeyPacket[1]; 03026 pseudo_bit_t _unused_0[57]; 03027 }; 03028 struct QIB_7322_SendHdrErrSymptom_0 { 03029 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendHdrErrSymptom_0_pb ); 03030 }; 03031 /* Default value: 0x0000000000000000 */ 03032 03033 #define QIB_7322_RxCreditVL0_0_offset 0x00001280UL 03034 struct QIB_7322_RxCreditVL0_0_pb { 03035 pseudo_bit_t RxMaxCreditVL[12]; 03036 pseudo_bit_t _unused_0[4]; 03037 pseudo_bit_t RxBufrConsumedVL[12]; 03038 pseudo_bit_t _unused_1[36]; 03039 }; 03040 struct QIB_7322_RxCreditVL0_0 { 03041 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxCreditVL0_0_pb ); 03042 }; 03043 /* Default value: 0x0000000000000000 */ 03044 03045 #define QIB_7322_SendDmaBufUsed0_0_offset 0x00001480UL 03046 struct QIB_7322_SendDmaBufUsed0_0_pb { 03047 pseudo_bit_t BufUsed_63_0[64]; 03048 }; 03049 struct QIB_7322_SendDmaBufUsed0_0 { 03050 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufUsed0_0_pb ); 03051 }; 03052 /* Default value: 0x0000000000000000 */ 03053 03054 #define QIB_7322_SendDmaReqTagUsed_0_offset 0x00001498UL 03055 struct QIB_7322_SendDmaReqTagUsed_0_pb { 03056 pseudo_bit_t ReqTagUsed_7_0[8]; 03057 pseudo_bit_t _unused_0[56]; 03058 }; 03059 struct QIB_7322_SendDmaReqTagUsed_0 { 03060 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReqTagUsed_0_pb ); 03061 }; 03062 /* Default value: 0x0000000000000000 */ 03063 03064 #define QIB_7322_SendCheckControl_0_offset 0x000014a8UL 03065 struct QIB_7322_SendCheckControl_0_pb { 03066 pseudo_bit_t PacketTooSmall_En[1]; 03067 pseudo_bit_t RawIPV6_En[1]; 03068 pseudo_bit_t SLID_En[1]; 03069 pseudo_bit_t BTHQP_En[1]; 03070 pseudo_bit_t PKey_En[1]; 03071 pseudo_bit_t _unused_0[59]; 03072 }; 03073 struct QIB_7322_SendCheckControl_0 { 03074 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckControl_0_pb ); 03075 }; 03076 /* Default value: 0x0000000000000000 */ 03077 03078 #define QIB_7322_SendIBSLIDMask_0_offset 0x000014b0UL 03079 struct QIB_7322_SendIBSLIDMask_0_pb { 03080 pseudo_bit_t SendIBSLIDMask_15_0[16]; 03081 pseudo_bit_t _unused_0[48]; 03082 }; 03083 struct QIB_7322_SendIBSLIDMask_0 { 03084 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDMask_0_pb ); 03085 }; 03086 /* Default value: 0x0000000000000000 */ 03087 03088 #define QIB_7322_SendIBSLIDAssign_0_offset 0x000014b8UL 03089 struct QIB_7322_SendIBSLIDAssign_0_pb { 03090 pseudo_bit_t SendIBSLIDAssign_15_0[16]; 03091 pseudo_bit_t _unused_0[48]; 03092 }; 03093 struct QIB_7322_SendIBSLIDAssign_0 { 03094 PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDAssign_0_pb ); 03095 }; 03096 /* Default value: 0x0000000000000000 */ 03097 03098 #define QIB_7322_IBCStatusA_0_offset 0x00001540UL 03099 struct QIB_7322_IBCStatusA_0_pb { 03100 pseudo_bit_t LinkTrainingState[5]; 03101 pseudo_bit_t LinkState[3]; 03102 pseudo_bit_t LinkSpeedActive[1]; 03103 pseudo_bit_t LinkWidthActive[1]; 03104 pseudo_bit_t DDS_RXEQ_FAIL[1]; 03105 pseudo_bit_t _unused_0[1]; 03106 pseudo_bit_t IBRxLaneReversed[1]; 03107 pseudo_bit_t IBTxLaneReversed[1]; 03108 pseudo_bit_t ScrambleEn[1]; 03109 pseudo_bit_t ScrambleCapRemote[1]; 03110 pseudo_bit_t _unused_1[13]; 03111 pseudo_bit_t LinkSpeedQDR[1]; 03112 pseudo_bit_t TxReady[1]; 03113 pseudo_bit_t _unused_2[1]; 03114 pseudo_bit_t TxCreditOk_VL0[1]; 03115 pseudo_bit_t TxCreditOk_VL1[1]; 03116 pseudo_bit_t TxCreditOk_VL2[1]; 03117 pseudo_bit_t TxCreditOk_VL3[1]; 03118 pseudo_bit_t TxCreditOk_VL4[1]; 03119 pseudo_bit_t TxCreditOk_VL5[1]; 03120 pseudo_bit_t TxCreditOk_VL6[1]; 03121 pseudo_bit_t TxCreditOk_VL7[1]; 03122 pseudo_bit_t _unused_3[24]; 03123 }; 03124 struct QIB_7322_IBCStatusA_0 { 03125 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusA_0_pb ); 03126 }; 03127 /* Default value: 0x0000000000000X02 */ 03128 03129 #define QIB_7322_IBCStatusB_0_offset 0x00001548UL 03130 struct QIB_7322_IBCStatusB_0_pb { 03131 pseudo_bit_t LinkRoundTripLatency[26]; 03132 pseudo_bit_t ReqDDSLocalFromRmt[4]; 03133 pseudo_bit_t RxEqLocalDevice[2]; 03134 pseudo_bit_t heartbeat_crosstalk[4]; 03135 pseudo_bit_t heartbeat_timed_out[1]; 03136 pseudo_bit_t ibsd_adaptation_timer_started[1]; 03137 pseudo_bit_t ibsd_adaptation_timer_reached_threshold[1]; 03138 pseudo_bit_t ibsd_adaptation_timer_debug[1]; 03139 pseudo_bit_t _unused_0[24]; 03140 }; 03141 struct QIB_7322_IBCStatusB_0 { 03142 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusB_0_pb ); 03143 }; 03144 /* Default value: 0x00000000XXXXXXXX */ 03145 03146 #define QIB_7322_IBCCtrlA_0_offset 0x00001560UL 03147 struct QIB_7322_IBCCtrlA_0_pb { 03148 pseudo_bit_t FlowCtrlPeriod[8]; 03149 pseudo_bit_t FlowCtrlWaterMark[8]; 03150 pseudo_bit_t LinkInitCmd[3]; 03151 pseudo_bit_t LinkCmd[2]; 03152 pseudo_bit_t MaxPktLen[11]; 03153 pseudo_bit_t PhyerrThreshold[4]; 03154 pseudo_bit_t OverrunThreshold[4]; 03155 pseudo_bit_t _unused_0[8]; 03156 pseudo_bit_t NumVLane[3]; 03157 pseudo_bit_t _unused_1[9]; 03158 pseudo_bit_t IBStatIntReductionEn[1]; 03159 pseudo_bit_t IBLinkEn[1]; 03160 pseudo_bit_t LinkDownDefaultState[1]; 03161 pseudo_bit_t Loopback[1]; 03162 }; 03163 struct QIB_7322_IBCCtrlA_0 { 03164 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlA_0_pb ); 03165 }; 03166 /* Default value: 0x0000000000000000 */ 03167 03168 #define QIB_7322_IBCCtrlB_0_offset 0x00001568UL 03169 struct QIB_7322_IBCCtrlB_0_pb { 03170 pseudo_bit_t IB_ENHANCED_MODE[1]; 03171 pseudo_bit_t SD_SPEED[1]; 03172 pseudo_bit_t SD_SPEED_SDR[1]; 03173 pseudo_bit_t SD_SPEED_DDR[1]; 03174 pseudo_bit_t SD_SPEED_QDR[1]; 03175 pseudo_bit_t IB_NUM_CHANNELS[2]; 03176 pseudo_bit_t IB_POLARITY_REV_SUPP[1]; 03177 pseudo_bit_t IB_LANE_REV_SUPPORTED[1]; 03178 pseudo_bit_t SD_RX_EQUAL_ENABLE[1]; 03179 pseudo_bit_t SD_ADD_ENB[1]; 03180 pseudo_bit_t SD_DDSV[1]; 03181 pseudo_bit_t SD_DDS[4]; 03182 pseudo_bit_t HRTBT_ENB[1]; 03183 pseudo_bit_t HRTBT_AUTO[1]; 03184 pseudo_bit_t HRTBT_PORT[8]; 03185 pseudo_bit_t HRTBT_REQ[1]; 03186 pseudo_bit_t IB_ENABLE_FILT_DPKT[1]; 03187 pseudo_bit_t _unused_0[4]; 03188 pseudo_bit_t IB_DLID[16]; 03189 pseudo_bit_t IB_DLID_MASK[16]; 03190 }; 03191 struct QIB_7322_IBCCtrlB_0 { 03192 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlB_0_pb ); 03193 }; 03194 /* Default value: 0x00000000000305FF */ 03195 03196 #define QIB_7322_IBCCtrlC_0_offset 0x00001570UL 03197 struct QIB_7322_IBCCtrlC_0_pb { 03198 pseudo_bit_t IB_FRONT_PORCH[5]; 03199 pseudo_bit_t IB_BACK_PORCH[5]; 03200 pseudo_bit_t _unused_0[54]; 03201 }; 03202 struct QIB_7322_IBCCtrlC_0 { 03203 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlC_0_pb ); 03204 }; 03205 /* Default value: 0x0000000000000301 */ 03206 03207 #define QIB_7322_HRTBT_GUID_0_offset 0x00001588UL 03208 /* Default value: 0x0000000000000000 */ 03209 03210 #define QIB_7322_IB_SDTEST_IF_TX_0_offset 0x00001590UL 03211 struct QIB_7322_IB_SDTEST_IF_TX_0_pb { 03212 pseudo_bit_t TS_T_TX_VALID[1]; 03213 pseudo_bit_t TS_3_TX_VALID[1]; 03214 pseudo_bit_t VL_CAP[2]; 03215 pseudo_bit_t CREDIT_CHANGE[1]; 03216 pseudo_bit_t _unused_0[6]; 03217 pseudo_bit_t TS_TX_OPCODE[2]; 03218 pseudo_bit_t TS_TX_SPEED[3]; 03219 pseudo_bit_t _unused_1[16]; 03220 pseudo_bit_t TS_TX_TX_CFG[16]; 03221 pseudo_bit_t TS_TX_RX_CFG[16]; 03222 }; 03223 struct QIB_7322_IB_SDTEST_IF_TX_0 { 03224 PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_TX_0_pb ); 03225 }; 03226 /* Default value: 0x0000000000000000 */ 03227 03228 #define QIB_7322_IB_SDTEST_IF_RX_0_offset 0x00001598UL 03229 struct QIB_7322_IB_SDTEST_IF_RX_0_pb { 03230 pseudo_bit_t TS_T_RX_VALID[1]; 03231 pseudo_bit_t TS_3_RX_VALID[1]; 03232 pseudo_bit_t _unused_0[14]; 03233 pseudo_bit_t TS_RX_A[8]; 03234 pseudo_bit_t TS_RX_B[8]; 03235 pseudo_bit_t TS_RX_TX_CFG[16]; 03236 pseudo_bit_t TS_RX_RX_CFG[16]; 03237 }; 03238 struct QIB_7322_IB_SDTEST_IF_RX_0 { 03239 PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_RX_0_pb ); 03240 }; 03241 /* Default value: 0x0000000000000000 */ 03242 03243 #define QIB_7322_IBNCModeCtrl_0_offset 0x000015b8UL 03244 struct QIB_7322_IBNCModeCtrl_0_pb { 03245 pseudo_bit_t TSMEnable_send_TS1[1]; 03246 pseudo_bit_t TSMEnable_send_TS2[1]; 03247 pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1]; 03248 pseudo_bit_t _unused_0[5]; 03249 pseudo_bit_t TSMCode_TS1[9]; 03250 pseudo_bit_t TSMCode_TS2[9]; 03251 pseudo_bit_t _unused_1[6]; 03252 pseudo_bit_t ScrambleCapLocal[1]; 03253 pseudo_bit_t ScrambleCapRemoteMask[1]; 03254 pseudo_bit_t ScrambleCapRemoteForce[1]; 03255 pseudo_bit_t _unused_2[29]; 03256 }; 03257 struct QIB_7322_IBNCModeCtrl_0 { 03258 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBNCModeCtrl_0_pb ); 03259 }; 03260 /* Default value: 0x0000000000000000 */ 03261 03262 #define QIB_7322_IBSerdesStatus_0_offset 0x000015d0UL 03263 /* Default value: 0x0000000000000000 */ 03264 03265 #define QIB_7322_IBPCSConfig_0_offset 0x000015d8UL 03266 struct QIB_7322_IBPCSConfig_0_pb { 03267 pseudo_bit_t tx_rx_reset[1]; 03268 pseudo_bit_t xcv_treset[1]; 03269 pseudo_bit_t xcv_rreset[1]; 03270 pseudo_bit_t _unused_0[6]; 03271 pseudo_bit_t link_sync_mask[10]; 03272 pseudo_bit_t _unused_1[45]; 03273 }; 03274 struct QIB_7322_IBPCSConfig_0 { 03275 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBPCSConfig_0_pb ); 03276 }; 03277 /* Default value: 0x0000000000000007 */ 03278 03279 #define QIB_7322_IBSerdesCtrl_0_offset 0x000015e0UL 03280 struct QIB_7322_IBSerdesCtrl_0_pb { 03281 pseudo_bit_t CMODE[7]; 03282 pseudo_bit_t _unused_0[1]; 03283 pseudo_bit_t TXIDLE[1]; 03284 pseudo_bit_t RXPD[1]; 03285 pseudo_bit_t TXPD[1]; 03286 pseudo_bit_t PLLPD[1]; 03287 pseudo_bit_t LPEN[1]; 03288 pseudo_bit_t RXLOSEN[1]; 03289 pseudo_bit_t _unused_1[1]; 03290 pseudo_bit_t IB_LAT_MODE[1]; 03291 pseudo_bit_t CGMODE[4]; 03292 pseudo_bit_t CHANNEL_RESET_N[4]; 03293 pseudo_bit_t DISABLE_RXLATOFF_SDR[1]; 03294 pseudo_bit_t DISABLE_RXLATOFF_DDR[1]; 03295 pseudo_bit_t DISABLE_RXLATOFF_QDR[1]; 03296 pseudo_bit_t _unused_2[37]; 03297 }; 03298 struct QIB_7322_IBSerdesCtrl_0 { 03299 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSerdesCtrl_0_pb ); 03300 }; 03301 /* Default value: 0x0000000000FFA00F */ 03302 03303 #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_offset 0x00001600UL 03304 struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_pb { 03305 pseudo_bit_t txcn1_ena[3]; 03306 pseudo_bit_t txcn1_xtra_emph0[2]; 03307 pseudo_bit_t txcp1_ena[4]; 03308 pseudo_bit_t txc0_ena[5]; 03309 pseudo_bit_t txampcntl_d2a[4]; 03310 pseudo_bit_t _unused_0[12]; 03311 pseudo_bit_t reset_tx_deemphasis_override[1]; 03312 pseudo_bit_t tx_override_deemphasis_select[1]; 03313 pseudo_bit_t _unused_1[32]; 03314 }; 03315 struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0 { 03316 PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_pb ); 03317 }; 03318 /* Default value: 0x0000000000000000 */ 03319 03320 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_offset 0x00001640UL 03321 struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_pb { 03322 pseudo_bit_t static_disable_rxenadfe_sdr_ch0[8]; 03323 pseudo_bit_t static_disable_rxenadfe_sdr_ch1[8]; 03324 pseudo_bit_t static_disable_rxenadfe_sdr_ch2[8]; 03325 pseudo_bit_t static_disable_rxenadfe_sdr_ch3[8]; 03326 pseudo_bit_t static_disable_rxenale_sdr_ch0[1]; 03327 pseudo_bit_t static_disable_rxenale_sdr_ch1[1]; 03328 pseudo_bit_t static_disable_rxenale_sdr_ch2[1]; 03329 pseudo_bit_t static_disable_rxenale_sdr_ch3[1]; 03330 pseudo_bit_t static_disable_rxenagain_sdr_ch0[1]; 03331 pseudo_bit_t static_disable_rxenagain_sdr_ch1[1]; 03332 pseudo_bit_t static_disable_rxenagain_sdr_ch2[1]; 03333 pseudo_bit_t static_disable_rxenagain_sdr_ch3[1]; 03334 pseudo_bit_t _unused_0[24]; 03335 }; 03336 struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0 { 03337 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_pb ); 03338 }; 03339 /* Default value: 0x0000000000000000 */ 03340 03341 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_offset 0x00001648UL 03342 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_pb { 03343 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch0[8]; 03344 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch1[8]; 03345 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch2[8]; 03346 pseudo_bit_t dyn_disable_rxenadfe_sdr_ch3[8]; 03347 pseudo_bit_t dyn_disable_rxenale_sdr_ch0[1]; 03348 pseudo_bit_t dyn_disable_rxenale_sdr_ch1[1]; 03349 pseudo_bit_t dyn_disable_rxenale_sdr_ch2[1]; 03350 pseudo_bit_t dyn_disable_rxenale_sdr_ch3[1]; 03351 pseudo_bit_t dyn_disable_rxenagain_sdr_ch0[1]; 03352 pseudo_bit_t dyn_disable_rxenagain_sdr_ch1[1]; 03353 pseudo_bit_t dyn_disable_rxenagain_sdr_ch2[1]; 03354 pseudo_bit_t dyn_disable_rxenagain_sdr_ch3[1]; 03355 pseudo_bit_t _unused_0[24]; 03356 }; 03357 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0 { 03358 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_pb ); 03359 }; 03360 /* Default value: 0x0000000000000000 */ 03361 03362 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_offset 0x00001650UL 03363 struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_pb { 03364 pseudo_bit_t static_disable_rxenadfe_ddr_ch0[8]; 03365 pseudo_bit_t static_disable_rxenadfe_ddr_ch1[8]; 03366 pseudo_bit_t static_disable_rxenadfe_ddr_ch2[8]; 03367 pseudo_bit_t static_disable_rxenadfe_ddr_ch3[8]; 03368 pseudo_bit_t static_disable_rxenale_ddr_ch0[1]; 03369 pseudo_bit_t static_disable_rxenale_ddr_ch1[1]; 03370 pseudo_bit_t static_disable_rxenale_ddr_ch2[1]; 03371 pseudo_bit_t static_disable_rxenale_ddr_ch3[1]; 03372 pseudo_bit_t static_disable_rxenagain_ddr_ch0[1]; 03373 pseudo_bit_t static_disable_rxenagain_ddr_ch1[1]; 03374 pseudo_bit_t static_disable_rxenagain_ddr_ch2[1]; 03375 pseudo_bit_t static_disable_rxenagain_ddr_ch3[1]; 03376 pseudo_bit_t _unused_0[24]; 03377 }; 03378 struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0 { 03379 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_pb ); 03380 }; 03381 /* Default value: 0x0000000000000000 */ 03382 03383 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_offset 0x00001658UL 03384 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_pb { 03385 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch0[8]; 03386 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch1[8]; 03387 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch2[8]; 03388 pseudo_bit_t dyn_disable_rxenadfe_ddr_ch3[8]; 03389 pseudo_bit_t dyn_disable_rxenale_ddr_ch0[1]; 03390 pseudo_bit_t dyn_disable_rxenale_ddr_ch1[1]; 03391 pseudo_bit_t dyn_disable_rxenale_ddr_ch2[1]; 03392 pseudo_bit_t dyn_disable_rxenale_ddr_ch3[1]; 03393 pseudo_bit_t dyn_disable_rxenagain_ddr_ch0[1]; 03394 pseudo_bit_t dyn_disable_rxenagain_ddr_ch1[1]; 03395 pseudo_bit_t dyn_disable_rxenagain_ddr_ch2[1]; 03396 pseudo_bit_t dyn_disable_rxenagain_ddr_ch3[1]; 03397 pseudo_bit_t _unused_0[24]; 03398 }; 03399 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0 { 03400 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_pb ); 03401 }; 03402 /* Default value: 0x0000000000000000 */ 03403 03404 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_offset 0x00001660UL 03405 struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_pb { 03406 pseudo_bit_t static_disable_rxenadfe_qdr_ch0[8]; 03407 pseudo_bit_t static_disable_rxenadfe_qdr_ch1[8]; 03408 pseudo_bit_t static_disable_rxenadfe_qdr_ch2[8]; 03409 pseudo_bit_t static_disable_rxenadfe_qdr_ch3[8]; 03410 pseudo_bit_t static_disable_rxenale_qdr_ch0[1]; 03411 pseudo_bit_t static_disable_rxenale_qdr_ch1[1]; 03412 pseudo_bit_t static_disable_rxenale_qdr_ch2[1]; 03413 pseudo_bit_t static_disable_rxenale_qdr_ch3[1]; 03414 pseudo_bit_t static_disable_rxenagain_qdr_ch0[1]; 03415 pseudo_bit_t static_disable_rxenagain_qdr_ch1[1]; 03416 pseudo_bit_t static_disable_rxenagain_qdr_ch2[1]; 03417 pseudo_bit_t static_disable_rxenagain_qdr_ch3[1]; 03418 pseudo_bit_t _unused_0[24]; 03419 }; 03420 struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0 { 03421 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_pb ); 03422 }; 03423 /* Default value: 0x0000000000000000 */ 03424 03425 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_offset 0x00001668UL 03426 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_pb { 03427 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch0[8]; 03428 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch1[8]; 03429 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch2[8]; 03430 pseudo_bit_t dyn_disable_rxenadfe_qdr_ch3[8]; 03431 pseudo_bit_t dyn_disable_rxenale_qdr_ch0[1]; 03432 pseudo_bit_t dyn_disable_rxenale_qdr_ch1[1]; 03433 pseudo_bit_t dyn_disable_rxenale_qdr_ch2[1]; 03434 pseudo_bit_t dyn_disable_rxenale_qdr_ch3[1]; 03435 pseudo_bit_t dyn_disable_rxenagain_qdr_ch0[1]; 03436 pseudo_bit_t dyn_disable_rxenagain_qdr_ch1[1]; 03437 pseudo_bit_t dyn_disable_rxenagain_qdr_ch2[1]; 03438 pseudo_bit_t dyn_disable_rxenagain_qdr_ch3[1]; 03439 pseudo_bit_t _unused_0[24]; 03440 }; 03441 struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0 { 03442 PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_pb ); 03443 }; 03444 /* Default value: 0x0000000000000000 */ 03445 03446 #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_offset 0x00001670UL 03447 /* Default value: 0x0000000000000000 */ 03448 03449 #define QIB_7322_RxBufrUnCorErrLogA_0_offset 0x00001800UL 03450 struct QIB_7322_RxBufrUnCorErrLogA_0_pb { 03451 pseudo_bit_t RxBufrUnCorErrData_63_0[64]; 03452 }; 03453 struct QIB_7322_RxBufrUnCorErrLogA_0 { 03454 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogA_0_pb ); 03455 }; 03456 /* Default value: 0x0000000000000000 */ 03457 03458 #define QIB_7322_RxBufrUnCorErrLogB_0_offset 0x00001808UL 03459 struct QIB_7322_RxBufrUnCorErrLogB_0_pb { 03460 pseudo_bit_t RxBufrUnCorErrData_127_64[64]; 03461 }; 03462 struct QIB_7322_RxBufrUnCorErrLogB_0 { 03463 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogB_0_pb ); 03464 }; 03465 /* Default value: 0x0000000000000000 */ 03466 03467 #define QIB_7322_RxBufrUnCorErrLogC_0_offset 0x00001810UL 03468 struct QIB_7322_RxBufrUnCorErrLogC_0_pb { 03469 pseudo_bit_t RxBufrUnCorErrData_191_128[64]; 03470 }; 03471 struct QIB_7322_RxBufrUnCorErrLogC_0 { 03472 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogC_0_pb ); 03473 }; 03474 /* Default value: 0x0000000000000000 */ 03475 03476 #define QIB_7322_RxBufrUnCorErrLogD_0_offset 0x00001818UL 03477 struct QIB_7322_RxBufrUnCorErrLogD_0_pb { 03478 pseudo_bit_t RxBufrUnCorErrData_255_192[64]; 03479 }; 03480 struct QIB_7322_RxBufrUnCorErrLogD_0 { 03481 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogD_0_pb ); 03482 }; 03483 /* Default value: 0x0000000000000000 */ 03484 03485 #define QIB_7322_RxBufrUnCorErrLogE_0_offset 0x00001820UL 03486 struct QIB_7322_RxBufrUnCorErrLogE_0_pb { 03487 pseudo_bit_t RxBufrUnCorErrData_258_256[3]; 03488 pseudo_bit_t RxBufrUnCorErrCheckBit_36_0[37]; 03489 pseudo_bit_t RxBufrUnCorErrAddr_15_0[16]; 03490 pseudo_bit_t _unused_0[8]; 03491 }; 03492 struct QIB_7322_RxBufrUnCorErrLogE_0 { 03493 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogE_0_pb ); 03494 }; 03495 /* Default value: 0x0000000000000000 */ 03496 03497 #define QIB_7322_RxFlagUnCorErrLogA_0_offset 0x00001828UL 03498 struct QIB_7322_RxFlagUnCorErrLogA_0_pb { 03499 pseudo_bit_t RxFlagUnCorErrData_63_0[64]; 03500 }; 03501 struct QIB_7322_RxFlagUnCorErrLogA_0 { 03502 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogA_0_pb ); 03503 }; 03504 /* Default value: 0x0000000000000000 */ 03505 03506 #define QIB_7322_RxFlagUnCorErrLogB_0_offset 0x00001830UL 03507 struct QIB_7322_RxFlagUnCorErrLogB_0_pb { 03508 pseudo_bit_t RxFlagUnCorErrCheckBit_7_0[8]; 03509 pseudo_bit_t RxFlagUnCorErrAddr_12_0[13]; 03510 pseudo_bit_t _unused_0[43]; 03511 }; 03512 struct QIB_7322_RxFlagUnCorErrLogB_0 { 03513 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogB_0_pb ); 03514 }; 03515 /* Default value: 0x0000000000000000 */ 03516 03517 #define QIB_7322_RxLkupiqUnCorErrLogA_0_offset 0x00001840UL 03518 struct QIB_7322_RxLkupiqUnCorErrLogA_0_pb { 03519 pseudo_bit_t RxLkupiqUnCorErrData_45_0[46]; 03520 pseudo_bit_t RxLkupiqUnCorErrCheckBit_7_0[8]; 03521 pseudo_bit_t _unused_0[10]; 03522 }; 03523 struct QIB_7322_RxLkupiqUnCorErrLogA_0 { 03524 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogA_0_pb ); 03525 }; 03526 /* Default value: 0x0000000000000000 */ 03527 03528 #define QIB_7322_RxLkupiqUnCorErrLogB_0_offset 0x00001848UL 03529 struct QIB_7322_RxLkupiqUnCorErrLogB_0_pb { 03530 pseudo_bit_t RxLkupiqUnCorErrAddr_12_0[13]; 03531 pseudo_bit_t _unused_0[51]; 03532 }; 03533 struct QIB_7322_RxLkupiqUnCorErrLogB_0 { 03534 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogB_0_pb ); 03535 }; 03536 /* Default value: 0x0000000000000000 */ 03537 03538 #define QIB_7322_RxHdrFifoUnCorErrLogA_0_offset 0x00001850UL 03539 struct QIB_7322_RxHdrFifoUnCorErrLogA_0_pb { 03540 pseudo_bit_t RxHdrFifoUnCorErrData_63_0[64]; 03541 }; 03542 struct QIB_7322_RxHdrFifoUnCorErrLogA_0 { 03543 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogA_0_pb ); 03544 }; 03545 /* Default value: 0x0000000000000000 */ 03546 03547 #define QIB_7322_RxHdrFifoUnCorErrLogB_0_offset 0x00001858UL 03548 struct QIB_7322_RxHdrFifoUnCorErrLogB_0_pb { 03549 pseudo_bit_t RxHdrFifoUnCorErrData_127_64[64]; 03550 }; 03551 struct QIB_7322_RxHdrFifoUnCorErrLogB_0 { 03552 PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogB_0_pb ); 03553 }; 03554 /* Default value: 0x0000000000000000 */ 03555 03556 #define QIB_7322_RxHdrFifoUnCorErrLogC_0_offset 0x00001860UL