iPXE
sis900.h
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00001 /* -*- Mode:C; c-basic-offset:4; -*- */
00002 
00003 /* Definitions for SiS ethernet controllers including 7014/7016 and 900 
00004  * References:
00005  *   SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
00006  *      preliminary Rev. 1.0 Jan. 14, 1998
00007  *   SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
00008  *      preliminary Rev. 1.0 Nov. 10, 1998
00009  *   SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
00010  *      preliminary Rev. 1.0 Jan. 18, 1998
00011  *   http://www.sis.com.tw/support/databook.htm
00012  */
00013 
00014 FILE_LICENCE ( GPL_ANY );
00015 
00016 /* MAC operationl registers of SiS 7016 and SiS 900 ethernet controller */
00017 /* The I/O extent, SiS 900 needs 256 bytes of io address */
00018 #define SIS900_TOTAL_SIZE 0x100
00019 
00020 /* Symbolic offsets to registers. */
00021 enum sis900_registers {
00022     cr=0x0,                 /* Command Register */
00023     cfg=0x4,                /* Configuration Register */
00024     mear=0x8,               /* EEPROM Access Register */
00025     ptscr=0xc,              /* PCI Test Control Register */
00026     isr=0x10,               /* Interrupt Status Register */
00027     imr=0x14,               /* Interrupt Mask Register */
00028     ier=0x18,               /* Interrupt Enable Register */
00029     epar=0x18,              /* Enhanced PHY Access Register */
00030     txdp=0x20,              /* Transmit Descriptor Pointer Register */
00031     txcfg=0x24,             /* Transmit Configuration Register */
00032     rxdp=0x30,              /* Receive Descriptor Pointer Register */
00033     rxcfg=0x34,             /* Receive Configuration Register */
00034     flctrl=0x38,            /* Flow Control Register */
00035     rxlen=0x3c,             /* Receive Packet Length Register */
00036     rfcr=0x48,              /* Receive Filter Control Register */
00037     rfdr=0x4C,              /* Receive Filter Data Register */
00038     pmctrl=0xB0,            /* Power Management Control Register */
00039     pmer=0xB4               /* Power Management Wake-up Event Register */
00040 };
00041 
00042 /* Symbolic names for bits in various registers */
00043 enum sis900_command_register_bits {
00044     RELOAD     = 0x00000400,
00045     ACCESSMODE = 0x00000200,
00046     RESET      = 0x00000100, 
00047     SWI        = 0x00000080, 
00048     RxRESET    = 0x00000020,
00049     TxRESET    = 0x00000010, 
00050     RxDIS      = 0x00000008, 
00051     RxENA      = 0x00000004,
00052     TxDIS      = 0x00000002, 
00053     TxENA      = 0x00000001
00054 };
00055 
00056 enum sis900_configuration_register_bits {
00057     DESCRFMT = 0x00000100, /* 7016 specific */
00058     REQALG   = 0x00000080, 
00059     SB       = 0x00000040, 
00060     POW      = 0x00000020, 
00061     EXD      = 0x00000010, 
00062     PESEL    = 0x00000008, 
00063     LPM      = 0x00000004, 
00064     BEM      = 0x00000001,
00065     RND_CNT  = 0x00000400,
00066     FAIR_BACKOFF = 0x00000200,
00067     EDB_MASTER_EN = 0x00002000
00068 };
00069 
00070 enum sis900_eeprom_access_reigster_bits {
00071     MDC   = 0x00000040, 
00072     MDDIR = 0x00000020, 
00073     MDIO  = 0x00000010, /* 7016 specific */ 
00074     EECS  = 0x00000008, 
00075     EECLK = 0x00000004, 
00076     EEDO  = 0x00000002,
00077     EEDI  = 0x00000001
00078 };
00079 
00080 enum sis900_interrupt_register_bits {
00081     WKEVT      = 0x10000000, 
00082     TxPAUSEEND = 0x08000000,
00083     TxPAUSE    = 0x04000000,
00084     TxRCMP     = 0x02000000,
00085     RxRCMP     = 0x01000000,
00086     DPERR      = 0x00800000,
00087     SSERR      = 0x00400000,
00088     RMABT      = 0x00200000,
00089     RTABT      = 0x00100000,
00090     RxSOVR     = 0x00010000, 
00091     HIBERR     = 0x00008000, 
00092     SWINT      = 0x00001000,
00093     MIBINT     = 0x00000800, 
00094     TxURN      = 0x00000400,
00095     TxIDLE     = 0x00000200,
00096     TxERR      = 0x00000100,
00097     TxDESC     = 0x00000080,
00098     TxOK       = 0x00000040,
00099     RxORN      = 0x00000020, 
00100     RxIDLE     = 0x00000010,
00101     RxEARLY    = 0x00000008,
00102     RxERR      = 0x00000004,
00103     RxDESC     = 0x00000002,
00104     RxOK       = 0x00000001
00105 };
00106 
00107 enum sis900_interrupt_enable_reigster_bits {
00108     IE = 0x00000001
00109 };
00110 
00111 /* maximum dma burst fro transmission and receive*/
00112 #define MAX_DMA_RANGE   7       /* actually 0 means MAXIMUM !! */
00113 #define TxMXDMA_shift   20
00114 #define RxMXDMA_shift   20
00115 #define TX_DMA_BURST    0
00116 #define RX_DMA_BURST    0
00117 
00118 enum sis900_tx_rx_dma{
00119                 DMA_BURST_512 = 0,      DMA_BURST_64 = 5
00120 };
00121 
00122 /* transmit FIFO threshholds */
00123 #define TX_FILL_THRESH  16      /* 1/4 FIFO size */
00124 #define TxFILLT_shift   8
00125 #define TxDRNT_shift    0
00126 #define TxDRNT_100      48      /* 3/4 FIFO size */
00127 #define TxDRNT_10       16      /* 1/2 FIFO size */
00128 
00129 enum sis900_transmit_config_register_bits {
00130     TxCSI   = 0x80000000,
00131     TxHBI   = 0x40000000,
00132     TxMLB   = 0x20000000,
00133     TxATP   = 0x10000000,
00134     TxIFG   = 0x0C000000,
00135     TxFILLT = 0x00003F00,
00136     TxDRNT  = 0x0000003F
00137 };
00138 
00139 /* recevie FIFO thresholds */
00140 #define RxDRNT_shift     1
00141 #define RxDRNT_100      16      /* 1/2 FIFO size */
00142 #define RxDRNT_10       24      /* 3/4 FIFO size */
00143 
00144 enum sis900_reveive_config_register_bits {
00145     RxAEP  = 0x80000000, 
00146     RxARP  = 0x40000000, 
00147     RxATX  = 0x10000000,
00148     RxAJAB = 0x08000000, 
00149     RxDRNT = 0x0000007F
00150 };
00151 
00152 #define RFAA_shift      28
00153 #define RFADDR_shift    16
00154 
00155 enum sis900_receive_filter_control_register_bits {
00156     RFEN  = 0x80000000, 
00157     RFAAB = 0x40000000, 
00158     RFAAM = 0x20000000,
00159     RFAAP = 0x10000000, 
00160     RFPromiscuous = (RFAAB|RFAAM|RFAAP)
00161 };
00162 
00163 enum sis900_reveive_filter_data_mask {
00164     RFDAT =  0x0000FFFF
00165 };
00166 
00167 /* EEPROM Addresses */
00168 enum sis900_eeprom_address {
00169     EEPROMSignature = 0x00, 
00170     EEPROMVendorID  = 0x02, 
00171     EEPROMDeviceID  = 0x03,
00172     EEPROMMACAddr   = 0x08, 
00173     EEPROMChecksum  = 0x0b
00174 };
00175 
00176 /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
00177 enum sis900_eeprom_command {
00178     EEread          = 0x0180, 
00179     EEwrite         = 0x0140, 
00180     EEerase         = 0x01C0, 
00181     EEwriteEnable   = 0x0130,
00182     EEwriteDisable  = 0x0100,
00183     EEeraseAll      = 0x0120,
00184     EEwriteAll      = 0x0110, 
00185     EEaddrMask      = 0x013F, 
00186     EEcmdShift      = 16
00187 };
00188 /* For SiS962 or SiS963, request the eeprom software access */
00189 enum sis96x_eeprom_command {
00190         EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
00191 };
00192 
00193 /* Manamgement Data I/O (mdio) frame */
00194 #define MIIread         0x6000
00195 #define MIIwrite        0x5002
00196 #define MIIpmdShift     7
00197 #define MIIregShift     2
00198 #define MIIcmdLen       16
00199 #define MIIcmdShift     16
00200 
00201 /* Buffer Descriptor Status*/
00202 enum sis900_buffer_status {
00203     OWN    = 0x80000000, 
00204     MORE   = 0x40000000, 
00205     INTR   = 0x20000000,
00206     SUPCRC = 0x10000000, 
00207     INCCRC = 0x10000000,
00208     OK     = 0x08000000, 
00209     DSIZE  = 0x00000FFF
00210 };
00211 
00212 /* Status for TX Buffers */
00213 enum sis900_tx_buffer_status {
00214     ABORT      = 0x04000000,
00215     UNDERRUN   = 0x02000000, 
00216     NOCARRIER  = 0x01000000,
00217     DEFERD     = 0x00800000, 
00218     EXCDEFER   = 0x00400000, 
00219     OWCOLL     = 0x00200000,
00220     EXCCOLL    = 0x00100000, 
00221     COLCNT     = 0x000F0000
00222 };
00223 
00224 enum sis900_rx_bufer_status {
00225     OVERRUN    = 0x02000000,
00226     DEST       = 0x00800000,
00227     BCAST      = 0x01800000,
00228     MCAST      = 0x01000000,
00229     UNIMATCH   = 0x00800000,
00230     TOOLONG    = 0x00400000,
00231     RUNT       = 0x00200000,
00232     RXISERR    = 0x00100000,
00233     CRCERR     = 0x00080000,
00234     FAERR      = 0x00040000,
00235     LOOPBK     = 0x00020000,
00236     RXCOL      = 0x00010000
00237 };
00238 
00239 /* MII register offsets */
00240 enum mii_registers {
00241     MII_CONTROL = 0x0000, 
00242     MII_STATUS  = 0x0001,
00243     MII_PHY_ID0 = 0x0002,
00244     MII_PHY_ID1 = 0x0003,
00245     MII_ANADV   = 0x0004,
00246     MII_ANLPAR  = 0x0005,
00247     MII_ANEXT   = 0x0006
00248 };
00249 
00250 /* mii registers specific to SiS 900 */
00251 enum sis_mii_registers {
00252     MII_CONFIG1 = 0x0010,
00253     MII_CONFIG2 = 0x0011,
00254     MII_STSOUT  = 0x0012,
00255     MII_MASK    = 0x0013,
00256     MII_RESV    = 0x0014
00257 };
00258 
00259 /* mii registers specific to AMD 79C901 */
00260 enum amd_mii_registers {
00261     MII_STATUS_SUMMARY = 0x0018
00262 };
00263 
00264 /* mii registers specific to ICS 1893 */
00265 enum ics_mii_registers {
00266         MII_EXTCTRL  = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
00267         MII_EXTCTRL2 = 0x0013
00268 };
00269 
00270 
00271 
00272 /* MII Control register bit definitions. */
00273 enum mii_control_register_bits {
00274     MII_CNTL_FDX      = 0x0100,
00275     MII_CNTL_RST_AUTO = 0x0200, 
00276     MII_CNTL_ISOLATE  = 0x0400,
00277     MII_CNTL_PWRDWN   = 0x0800,
00278     MII_CNTL_AUTO     = 0x1000,
00279     MII_CNTL_SPEED    = 0x2000,
00280     MII_CNTL_LPBK     = 0x4000,
00281     MII_CNTL_RESET    = 0x8000
00282 };
00283 
00284 /* MII Status register bit  */
00285 enum mii_status_register_bits {
00286     MII_STAT_EXT        = 0x0001,
00287     MII_STAT_JAB        = 0x0002, 
00288     MII_STAT_LINK       = 0x0004,
00289     MII_STAT_CAN_AUTO   = 0x0008, 
00290     MII_STAT_FAULT      = 0x0010,
00291     MII_STAT_AUTO_DONE  = 0x0020,
00292     MII_STAT_CAN_T      = 0x0800, 
00293     MII_STAT_CAN_T_FDX  = 0x1000,
00294     MII_STAT_CAN_TX     = 0x2000, 
00295     MII_STAT_CAN_TX_FDX = 0x4000,
00296     MII_STAT_CAN_T4     = 0x8000
00297 };
00298 
00299 #define         MII_ID1_OUI_LO          0xFC00  /* low bits of OUI mask */
00300 #define         MII_ID1_MODEL           0x03F0  /* model number */
00301 #define         MII_ID1_REV             0x000F  /* model number */
00302 
00303 /* MII NWAY Register Bits ...
00304    valid for the ANAR (Auto-Negotiation Advertisement) and
00305    ANLPAR (Auto-Negotiation Link Partner) registers */
00306 enum mii_nway_register_bits {
00307     MII_NWAY_NODE_SEL = 0x001f,
00308     MII_NWAY_CSMA_CD  = 0x0001,
00309     MII_NWAY_T        = 0x0020,
00310     MII_NWAY_T_FDX    = 0x0040,
00311     MII_NWAY_TX       = 0x0080,
00312     MII_NWAY_TX_FDX   = 0x0100,
00313     MII_NWAY_T4       = 0x0200,
00314     MII_NWAY_PAUSE    = 0x0400,
00315     MII_NWAY_RF       = 0x2000,
00316     MII_NWAY_ACK      = 0x4000,
00317     MII_NWAY_NP       = 0x8000
00318 };
00319 
00320 enum mii_stsout_register_bits {
00321     MII_STSOUT_LINK_FAIL = 0x4000,
00322     MII_STSOUT_SPD       = 0x0080,
00323     MII_STSOUT_DPLX      = 0x0040
00324 };
00325 
00326 enum mii_stsics_register_bits {
00327         MII_STSICS_SPD  = 0x8000, MII_STSICS_DPLX = 0x4000,
00328         MII_STSICS_LINKSTS = 0x0001
00329 };
00330 
00331 enum mii_stssum_register_bits {
00332     MII_STSSUM_LINK = 0x0008,
00333     MII_STSSUM_DPLX = 0x0004,
00334     MII_STSSUM_AUTO = 0x0002,
00335     MII_STSSUM_SPD  = 0x0001
00336 };
00337 
00338 enum sis900_revision_id {
00339         SIS630A_900_REV = 0x80,         SIS630E_900_REV = 0x81,
00340         SIS630S_900_REV = 0x82,         SIS630EA1_900_REV = 0x83,
00341         SIS630ET_900_REV = 0x84,        SIS635A_900_REV = 0x90,
00342         SIS96x_900_REV = 0X91,          SIS900B_900_REV = 0x03
00343 };
00344 
00345 enum sis630_revision_id {
00346         SIS630A0    = 0x00, SIS630A1      = 0x01,
00347         SIS630B0    = 0x10, SIS630B1      = 0x11
00348 };
00349 
00350 #define FDX_CAPABLE_DUPLEX_UNKNOWN      0
00351 #define FDX_CAPABLE_HALF_SELECTED       1
00352 #define FDX_CAPABLE_FULL_SELECTED       2
00353 
00354 #define HW_SPEED_UNCONFIG               0
00355 #define HW_SPEED_HOME                   1
00356 #define HW_SPEED_10_MBPS                10
00357 #define HW_SPEED_100_MBPS               100
00358 #define HW_SPEED_DEFAULT                (HW_SPEED_100_MBPS)
00359 
00360 #define CRC_SIZE        4
00361 #define MAC_HEADER_SIZE 14
00362 
00363 #define TX_BUF_SIZE     1536
00364 #define RX_BUF_SIZE     1536
00365 
00366 #define NUM_RX_DESC     4              /* Number of Rx descriptor registers. */
00367 
00368 /* Time in ticks before concluding the transmitter is hung. */
00369 #define TX_TIMEOUT       (4*TICKS_PER_SEC)
00370 
00371 typedef struct _BufferDesc {
00372     u32              link;
00373     volatile u32     cmdsts;
00374     u32              bufptr;
00375 } BufferDesc;