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smc9000.h
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00001 /*------------------------------------------------------------------------
00002  * smc9000.h
00003  *
00004  * Copyright (C) 1998 by Daniel Engström
00005  * Copyright (C) 1996 by Erik Stahlman
00006  *
00007  * This software may be used and distributed according to the terms
00008  * of the GNU Public License, incorporated herein by reference.
00009  *
00010  * This file contains register information and access macros for
00011  * the SMC91xxx chipset.
00012  *
00013  * Information contained in this file was obtained from the SMC91C94
00014  * manual from SMC.  To get a copy, if you really want one, you can find
00015  * information under www.smsc.com in the components division.
00016  * ( this thanks to advice from Donald Becker ).
00017  *
00018  * Authors
00019  *      Daniel Engström                         <daniel.engstrom@riksnett.no>
00020  *      Erik Stahlman                           <erik@vt.edu>
00021  *
00022  * History
00023  * 96-01-06              Erik Stahlman   moved definitions here from main .c
00024  *                                       file
00025  * 96-01-19              Erik Stahlman   polished this up some, and added
00026  *                                       better error handling
00027  * 98-09-25              Daniel Engström adjusted for Etherboot
00028  * 98-09-27              Daniel Engström moved some static strings back to the
00029  *                                       main .c file
00030  * --------------------------------------------------------------------------*/
00031 
00032 FILE_LICENCE ( GPL_ANY );
00033 
00034 #ifndef _SMC9000_H_
00035 # define _SMC9000_H_
00036 
00037 /* I want some simple types */
00038 typedef unsigned char                   byte;
00039 typedef unsigned short                  word;
00040 typedef unsigned long int               dword;
00041 
00042 /*---------------------------------------------------------------
00043  *
00044  * A description of the SMC registers is probably in order here,
00045  * although for details, the SMC datasheet is invaluable.
00046  *
00047  * Basically, the chip has 4 banks of registers ( 0 to 3 ), which
00048  * are accessed by writing a number into the BANK_SELECT register
00049  * ( I also use a SMC_SELECT_BANK macro for this ).
00050  *
00051  * The banks are configured so that for most purposes, bank 2 is all
00052  * that is needed for simple run time tasks.
00053  * ----------------------------------------------------------------------*/
00054 
00055 /*
00056  * Bank Select Register:
00057  *
00058  *              yyyy yyyy 0000 00xx
00059  *              xx              = bank number
00060  *              yyyy yyyy       = 0x33, for identification purposes.
00061  */
00062 #define BANK_SELECT             14
00063 
00064 /* BANK 0  */
00065 
00066 #define TCR             0       /* transmit control register */
00067 #define TCR_ENABLE      0x0001  /* if this is 1, we can transmit */
00068 #define TCR_FDUPLX      0x0800  /* receive packets sent out */
00069 #define TCR_STP_SQET    0x1000  /* stop transmitting if Signal quality error */
00070 #define TCR_MON_CNS     0x0400  /* monitors the carrier status */
00071 #define TCR_PAD_ENABLE  0x0080  /* pads short packets to 64 bytes */
00072 
00073 #define TCR_CLEAR       0       /* do NOTHING */
00074 /* the normal settings for the TCR register : */
00075 #define TCR_NORMAL      (TCR_ENABLE | TCR_PAD_ENABLE)
00076 
00077 
00078 #define EPH_STATUS      2
00079 #define ES_LINK_OK      0x4000  /* is the link integrity ok ? */
00080 
00081 #define RCR             4
00082 #define RCR_SOFTRESET   0x8000  /* resets the chip */
00083 #define RCR_STRIP_CRC   0x200   /* strips CRC */
00084 #define RCR_ENABLE      0x100   /* IFF this is set, we can receive packets */
00085 #define RCR_ALMUL       0x4     /* receive all multicast packets */
00086 #define RCR_PROMISC     0x2     /* enable promiscuous mode */
00087 
00088 /* the normal settings for the RCR register : */
00089 #define RCR_NORMAL      (RCR_STRIP_CRC | RCR_ENABLE)
00090 #define RCR_CLEAR       0x0             /* set it to a base state */
00091 
00092 #define COUNTER         6
00093 #define MIR             8
00094 #define MCR             10
00095 /* 12 is reserved */
00096 
00097 // Receive/Phy Control Register
00098 /* BANK 0  */
00099 #define RPC_REG         0x000A
00100 #define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
00101 #define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
00102 #define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
00103 #define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
00104 #define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
00105 #define RPC_LED_100_10  (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
00106 #define RPC_LED_RES     (0x01)  // LED = Reserved
00107 #define RPC_LED_10      (0x02)  // LED = 10Mbps link detect
00108 #define RPC_LED_FD      (0x03)  // LED = Full Duplex Mode
00109 #define RPC_LED_TX_RX   (0x04)  // LED = TX or RX packet occurred
00110 #define RPC_LED_100     (0x05)  // LED = 100Mbps link detect
00111 #define RPC_LED_TX      (0x06)  // LED = TX packet occurred
00112 #define RPC_LED_RX      (0x07)  // LED = RX packet occurred
00113 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
00114 
00115 // Receive/Phy Control Register
00116 /* BANK 0  */
00117 #define RPC_REG         0x000A
00118 #define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
00119 #define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
00120 #define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
00121 #define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
00122 #define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
00123 #define RPC_LED_100_10  (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
00124 #define RPC_LED_RES     (0x01)  // LED = Reserved
00125 #define RPC_LED_10      (0x02)  // LED = 10Mbps link detect
00126 #define RPC_LED_FD      (0x03)  // LED = Full Duplex Mode
00127 #define RPC_LED_TX_RX   (0x04)  // LED = TX or RX packet occurred
00128 #define RPC_LED_100     (0x05)  // LED = 100Mbps link detect
00129 #define RPC_LED_TX      (0x06)  // LED = TX packet occurred
00130 #define RPC_LED_RX      (0x07)  // LED = RX packet occurred
00131 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
00132 
00133 /* BANK 1 */
00134 #define CFG                     0
00135 #define CFG_AUI_SELECT          0x100
00136 #define BASE                    2
00137 #define ADDR0                   4
00138 #define ADDR1                   6
00139 #define ADDR2                   8
00140 #define GENERAL                 10
00141 #define CONTROL                 12
00142 #define CTL_POWERDOWN           0x2000
00143 #define CTL_LE_ENABLE           0x80
00144 #define CTL_CR_ENABLE           0x40
00145 #define CTL_TE_ENABLE           0x0020
00146 #define CTL_AUTO_RELEASE        0x0800
00147 #define CTL_EPROM_ACCESS        0x0003 /* high if Eprom is being read */
00148 
00149 /* BANK 2 */
00150 #define MMU_CMD         0
00151 #define MC_BUSY         1       /* only readable bit in the register */
00152 #define MC_NOP          0
00153 #define MC_ALLOC        0x20    /* or with number of 256 byte packets */
00154 #define MC_RESET        0x40
00155 #define MC_REMOVE       0x60    /* remove the current rx packet */
00156 #define MC_RELEASE      0x80    /* remove and release the current rx packet */
00157 #define MC_FREEPKT      0xA0    /* Release packet in PNR register */
00158 #define MC_ENQUEUE      0xC0    /* Enqueue the packet for transmit */
00159 
00160 #define PNR_ARR         2
00161 #define FIFO_PORTS      4
00162 
00163 #define FP_RXEMPTY      0x8000
00164 #define FP_TXEMPTY      0x80
00165 
00166 #define POINTER         6
00167 #define PTR_READ        0x2000
00168 #define PTR_RCV         0x8000
00169 #define PTR_AUTOINC     0x4000
00170 #define PTR_AUTO_INC    0x0040
00171 
00172 #define DATA_1          8
00173 #define DATA_2          10
00174 #define INTERRUPT       12
00175 
00176 #define INT_MASK        13
00177 #define IM_RCV_INT      0x1
00178 #define IM_TX_INT       0x2
00179 #define IM_TX_EMPTY_INT 0x4
00180 #define IM_ALLOC_INT    0x8
00181 #define IM_RX_OVRN_INT  0x10
00182 #define IM_EPH_INT      0x20
00183 #define IM_ERCV_INT     0x40 /* not on SMC9192 */
00184 
00185 /* BANK 3 */
00186 #define MULTICAST1      0
00187 #define MULTICAST2      2
00188 #define MULTICAST3      4
00189 #define MULTICAST4      6
00190 #define MGMT            8
00191 #define REVISION        10 /* ( hi: chip id   low: rev # ) */
00192 
00193 // Management Interface Register (MII)
00194 #define MII_REG         0x0008
00195 #define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
00196 #define MII_MDOE        0x0008 // MII Output Enable
00197 #define MII_MCLK        0x0004 // MII Clock, pin MDCLK
00198 #define MII_MDI         0x0002 // MII Input, pin MDI
00199 #define MII_MDO         0x0001 // MII Output, pin MDO
00200 
00201 /* this is NOT on SMC9192 */
00202 #define ERCV            12
00203 
00204 /* Note that 9194 and 9196 have the smame chip id,
00205  * the 9196 will have revisions starting at 6 */
00206 #define CHIP_9190       3
00207 #define CHIP_9194       4
00208 #define CHIP_9195       5
00209 #define CHIP_9196       4
00210 #define CHIP_91100      7
00211 #define CHIP_91100FD    8
00212 
00213 #define REV_9196        6
00214 
00215 /*
00216  * Transmit status bits
00217  */
00218 #define TS_SUCCESS      0x0001
00219 #define TS_LOSTCAR      0x0400
00220 #define TS_LATCOL       0x0200
00221 #define TS_16COL        0x0010
00222 
00223 /*
00224  * Receive status bits
00225  */
00226 #define RS_ALGNERR      0x8000
00227 #define RS_BADCRC       0x2000
00228 #define RS_ODDFRAME     0x1000
00229 #define RS_TOOLONG      0x0800
00230 #define RS_TOOSHORT     0x0400
00231 #define RS_MULTICAST    0x0001
00232 #define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
00233 
00234 // PHY Register Addresses (LAN91C111 Internal PHY)
00235 
00236 // PHY Control Register
00237 #define PHY_CNTL_REG            0x00
00238 #define PHY_CNTL_RST            0x8000  // 1=PHY Reset
00239 #define PHY_CNTL_LPBK           0x4000  // 1=PHY Loopback
00240 #define PHY_CNTL_SPEED          0x2000  // 1=100Mbps, 0=10Mpbs
00241 #define PHY_CNTL_ANEG_EN        0x1000 // 1=Enable Auto negotiation
00242 #define PHY_CNTL_PDN            0x0800  // 1=PHY Power Down mode
00243 #define PHY_CNTL_MII_DIS        0x0400  // 1=MII 4 bit interface disabled
00244 #define PHY_CNTL_ANEG_RST       0x0200 // 1=Reset Auto negotiate
00245 #define PHY_CNTL_DPLX           0x0100  // 1=Full Duplex, 0=Half Duplex
00246 #define PHY_CNTL_COLTST         0x0080  // 1= MII Colision Test
00247 
00248 // PHY Status Register
00249 #define PHY_STAT_REG            0x01
00250 #define PHY_STAT_CAP_T4         0x8000  // 1=100Base-T4 capable
00251 #define PHY_STAT_CAP_TXF        0x4000  // 1=100Base-X full duplex capable
00252 #define PHY_STAT_CAP_TXH        0x2000  // 1=100Base-X half duplex capable
00253 #define PHY_STAT_CAP_TF         0x1000  // 1=10Mbps full duplex capable
00254 #define PHY_STAT_CAP_TH         0x0800  // 1=10Mbps half duplex capable
00255 #define PHY_STAT_CAP_SUPR       0x0040  // 1=recv mgmt frames with not preamble
00256 #define PHY_STAT_ANEG_ACK       0x0020  // 1=ANEG has completed
00257 #define PHY_STAT_REM_FLT        0x0010  // 1=Remote Fault detected
00258 #define PHY_STAT_CAP_ANEG       0x0008  // 1=Auto negotiate capable
00259 #define PHY_STAT_LINK           0x0004  // 1=valid link
00260 #define PHY_STAT_JAB            0x0002  // 1=10Mbps jabber condition
00261 #define PHY_STAT_EXREG          0x0001  // 1=extended registers implemented
00262 
00263 // PHY Identifier Registers
00264 #define PHY_ID1_REG             0x02    // PHY Identifier 1
00265 #define PHY_ID2_REG             0x03    // PHY Identifier 2
00266 
00267 // PHY Auto-Negotiation Advertisement Register
00268 #define PHY_AD_REG              0x04
00269 #define PHY_AD_NP               0x8000  // 1=PHY requests exchange of Next Page
00270 #define PHY_AD_ACK              0x4000  // 1=got link code word from remote
00271 #define PHY_AD_RF               0x2000  // 1=advertise remote fault
00272 #define PHY_AD_T4               0x0200  // 1=PHY is capable of 100Base-T4
00273 #define PHY_AD_TX_FDX           0x0100  // 1=PHY is capable of 100Base-TX FDPLX
00274 #define PHY_AD_TX_HDX           0x0080  // 1=PHY is capable of 100Base-TX HDPLX
00275 #define PHY_AD_10_FDX           0x0040  // 1=PHY is capable of 10Base-T FDPLX
00276 #define PHY_AD_10_HDX           0x0020  // 1=PHY is capable of 10Base-T HDPLX
00277 #define PHY_AD_CSMA             0x0001  // 1=PHY is capable of 802.3 CMSA
00278 
00279 // PHY Auto-negotiation Remote End Capability Register
00280 #define PHY_RMT_REG             0x05
00281 // Uses same bit definitions as PHY_AD_REG
00282 
00283 // PHY Configuration Register 1
00284 #define PHY_CFG1_REG            0x10
00285 #define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
00286 #define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
00287 #define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
00288 #define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
00289 #define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
00290 #define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
00291 #define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
00292 #define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
00293 #define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
00294 #define PHY_CFG1_TLVL_MASK      0x003C
00295 #define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
00296 
00297 
00298 // PHY Configuration Register 2
00299 #define PHY_CFG2_REG            0x11
00300 #define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
00301 #define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
00302 #define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
00303 #define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
00304 
00305 // PHY Status Output (and Interrupt status) Register
00306 #define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
00307 #define PHY_INT_INT             0x8000  // 1=bits have changed since last read
00308 #define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
00309 #define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
00310 #define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
00311 #define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
00312 #define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
00313 #define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
00314 #define PHY_INT_JAB             0x0100  // 1=Jabber detected
00315 #define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
00316 #define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
00317 
00318 // PHY Interrupt/Status Mask Register
00319 #define PHY_MASK_REG            0x13    // Interrupt Mask
00320 // Uses the same bit definitions as PHY_INT_REG
00321 
00322 
00323 // PHY Register Addresses (LAN91C111 Internal PHY)
00324 
00325 // PHY Control Register
00326 #define PHY_CNTL_REG            0x00
00327 #define PHY_CNTL_RST            0x8000  // 1=PHY Reset
00328 #define PHY_CNTL_LPBK           0x4000  // 1=PHY Loopback
00329 #define PHY_CNTL_SPEED          0x2000  // 1=100Mbps, 0=10Mpbs
00330 #define PHY_CNTL_ANEG_EN        0x1000 // 1=Enable Auto negotiation
00331 #define PHY_CNTL_PDN            0x0800  // 1=PHY Power Down mode
00332 #define PHY_CNTL_MII_DIS        0x0400  // 1=MII 4 bit interface disabled
00333 #define PHY_CNTL_ANEG_RST       0x0200 // 1=Reset Auto negotiate
00334 #define PHY_CNTL_DPLX           0x0100  // 1=Full Duplex, 0=Half Duplex
00335 #define PHY_CNTL_COLTST         0x0080  // 1= MII Colision Test
00336 
00337 // PHY Status Register
00338 #define PHY_STAT_REG            0x01
00339 #define PHY_STAT_CAP_T4         0x8000  // 1=100Base-T4 capable
00340 #define PHY_STAT_CAP_TXF        0x4000  // 1=100Base-X full duplex capable
00341 #define PHY_STAT_CAP_TXH        0x2000  // 1=100Base-X half duplex capable
00342 #define PHY_STAT_CAP_TF         0x1000  // 1=10Mbps full duplex capable
00343 #define PHY_STAT_CAP_TH         0x0800  // 1=10Mbps half duplex capable
00344 #define PHY_STAT_CAP_SUPR       0x0040  // 1=recv mgmt frames with not preamble
00345 #define PHY_STAT_ANEG_ACK       0x0020  // 1=ANEG has completed
00346 #define PHY_STAT_REM_FLT        0x0010  // 1=Remote Fault detected
00347 #define PHY_STAT_CAP_ANEG       0x0008  // 1=Auto negotiate capable
00348 #define PHY_STAT_LINK           0x0004  // 1=valid link
00349 #define PHY_STAT_JAB            0x0002  // 1=10Mbps jabber condition
00350 #define PHY_STAT_EXREG          0x0001  // 1=extended registers implemented
00351 
00352 // PHY Identifier Registers
00353 #define PHY_ID1_REG             0x02    // PHY Identifier 1
00354 #define PHY_ID2_REG             0x03    // PHY Identifier 2
00355 
00356 // PHY Auto-Negotiation Advertisement Register
00357 #define PHY_AD_REG              0x04
00358 #define PHY_AD_NP               0x8000  // 1=PHY requests exchange of Next Page
00359 #define PHY_AD_ACK              0x4000  // 1=got link code word from remote
00360 #define PHY_AD_RF               0x2000  // 1=advertise remote fault
00361 #define PHY_AD_T4               0x0200  // 1=PHY is capable of 100Base-T4
00362 #define PHY_AD_TX_FDX           0x0100  // 1=PHY is capable of 100Base-TX FDPLX
00363 #define PHY_AD_TX_HDX           0x0080  // 1=PHY is capable of 100Base-TX HDPLX
00364 #define PHY_AD_10_FDX           0x0040  // 1=PHY is capable of 10Base-T FDPLX
00365 #define PHY_AD_10_HDX           0x0020  // 1=PHY is capable of 10Base-T HDPLX
00366 #define PHY_AD_CSMA             0x0001  // 1=PHY is capable of 802.3 CMSA
00367 
00368 // PHY Auto-negotiation Remote End Capability Register
00369 #define PHY_RMT_REG             0x05
00370 // Uses same bit definitions as PHY_AD_REG
00371 
00372 // PHY Configuration Register 1
00373 #define PHY_CFG1_REG            0x10
00374 #define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
00375 #define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
00376 #define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
00377 #define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
00378 #define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
00379 #define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
00380 #define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
00381 #define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
00382 #define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
00383 #define PHY_CFG1_TLVL_MASK      0x003C
00384 #define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
00385 
00386 
00387 // PHY Configuration Register 2
00388 #define PHY_CFG2_REG            0x11
00389 #define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
00390 #define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
00391 #define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
00392 #define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
00393 
00394 // PHY Status Output (and Interrupt status) Register
00395 #define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
00396 #define PHY_INT_INT             0x8000  // 1=bits have changed since last read
00397 #define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
00398 #define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
00399 #define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
00400 #define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
00401 #define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
00402 #define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
00403 #define PHY_INT_JAB             0x0100  // 1=Jabber detected
00404 #define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
00405 #define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
00406 
00407 // PHY Interrupt/Status Mask Register
00408 #define PHY_MASK_REG            0x13    // Interrupt Mask
00409 // Uses the same bit definitions as PHY_INT_REG
00410 
00411 
00412 /*-------------------------------------------------------------------------
00413  *  I define some macros to make it easier to do somewhat common
00414  * or slightly complicated, repeated tasks.
00415  --------------------------------------------------------------------------*/
00416 
00417 /* select a register bank, 0 to 3  */
00418 
00419 #define SMC_SELECT_BANK(x, y) { _outw( y, x + BANK_SELECT ); }
00420 
00421 /* define a small delay for the reset */
00422 #define SMC_DELAY(x) { inw( x + RCR );\
00423                         inw( x + RCR );\
00424                         inw( x + RCR ); }
00425 
00426 
00427 #endif  /* _SMC_9000_H_ */
00428