iPXE
smsc95xx.h
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00001 #ifndef _SMSC95XX_H
00002 #define _SMSC95XX_H
00003 
00004 /** @file
00005  *
00006  * SMSC LAN95xx USB Ethernet driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include "smscusb.h"
00013 
00014 /** Interrupt status register */
00015 #define SMSC95XX_INT_STS 0x008
00016 #define SMSC95XX_INT_STS_RXDF_INT       0x00000800UL    /**< RX FIFO overflow */
00017 #define SMSC95XX_INT_STS_PHY_INT        0x00008000UL    /**< PHY interrupt */
00018 
00019 /** Transmit configuration register */
00020 #define SMSC95XX_TX_CFG 0x010
00021 #define SMSC95XX_TX_CFG_ON              0x00000004UL    /**< TX enable */
00022 
00023 /** Hardware configuration register */
00024 #define SMSC95XX_HW_CFG 0x014
00025 #define SMSC95XX_HW_CFG_BIR             0x00001000UL    /**< Bulk IN use NAK */
00026 #define SMSC95XX_HW_CFG_LRST            0x00000008UL    /**< Soft lite reset */
00027 
00028 /** LED GPIO configuration register */
00029 #define SMSC95XX_LED_GPIO_CFG 0x024
00030 #define SMSC95XX_LED_GPIO_CFG_GPCTL2(x) ( (x) << 24 )   /**< GPIO 2 control */
00031 #define SMSC95XX_LED_GPIO_CFG_GPCTL2_NSPD_LED \
00032         SMSC95XX_LED_GPIO_CFG_GPCTL2 ( 1 )              /**< Link speed LED */
00033 #define SMSC95XX_LED_GPIO_CFG_GPCTL1(x) ( (x) << 20 )   /**< GPIO 1 control */
00034 #define SMSC95XX_LED_GPIO_CFG_GPCTL1_NLNKA_LED \
00035         SMSC95XX_LED_GPIO_CFG_GPCTL1 ( 1 )              /**< Activity LED */
00036 #define SMSC95XX_LED_GPIO_CFG_GPCTL0(x) ( (x) << 16 )   /**< GPIO 0 control */
00037 #define SMSC95XX_LED_GPIO_CFG_GPCTL0_NFDX_LED \
00038         SMSC95XX_LED_GPIO_CFG_GPCTL0 ( 1 )              /**< Full-duplex LED */
00039 
00040 /** EEPROM register base */
00041 #define SMSC95XX_E2P_BASE 0x030
00042 
00043 /** Interrupt endpoint control register */
00044 #define SMSC95XX_INT_EP_CTL 0x068
00045 #define SMSC95XX_INT_EP_CTL_RXDF_EN     0x00000800UL    /**< RX FIFO overflow */
00046 #define SMSC95XX_INT_EP_CTL_PHY_EN      0x00008000UL    /**< PHY interrupt */
00047 
00048 /** Bulk IN delay register */
00049 #define SMSC95XX_BULK_IN_DLY 0x06c
00050 #define SMSC95XX_BULK_IN_DLY_SET(ticks) ( (ticks) << 0 ) /**< Delay / 16.7ns */
00051 
00052 /** MAC control register */
00053 #define SMSC95XX_MAC_CR 0x100
00054 #define SMSC95XX_MAC_CR_RXALL           0x80000000UL    /**< Receive all */
00055 #define SMSC95XX_MAC_CR_FDPX            0x00100000UL    /**< Full duplex */
00056 #define SMSC95XX_MAC_CR_MCPAS           0x00080000UL    /**< All multicast */
00057 #define SMSC95XX_MAC_CR_PRMS            0x00040000UL    /**< Promiscuous */
00058 #define SMSC95XX_MAC_CR_PASSBAD         0x00010000UL    /**< Pass bad frames */
00059 #define SMSC95XX_MAC_CR_TXEN            0x00000008UL    /**< TX enabled */
00060 #define SMSC95XX_MAC_CR_RXEN            0x00000004UL    /**< RX enabled */
00061 
00062 /** MAC address register base */
00063 #define SMSC95XX_ADDR_BASE 0x104
00064 
00065 /** MII register base */
00066 #define SMSC95XX_MII_BASE 0x0114
00067 
00068 /** PHY interrupt source MII register */
00069 #define SMSC95XX_MII_PHY_INTR_SOURCE 29
00070 
00071 /** PHY interrupt mask MII register */
00072 #define SMSC95XX_MII_PHY_INTR_MASK 30
00073 
00074 /** PHY interrupt: auto-negotiation complete */
00075 #define SMSC95XX_PHY_INTR_ANEG_DONE 0x0040
00076 
00077 /** PHY interrupt: link down */
00078 #define SMSC95XX_PHY_INTR_LINK_DOWN 0x0010
00079 
00080 /** Receive packet header */
00081 struct smsc95xx_rx_header {
00082         /** Command word */
00083         uint32_t command;
00084 } __attribute__ (( packed ));
00085 
00086 /** Runt frame */
00087 #define SMSC95XX_RX_RUNT 0x00004000UL
00088 
00089 /** Late collision */
00090 #define SMSC95XX_RX_LATE 0x00000040UL
00091 
00092 /** CRC error */
00093 #define SMSC95XX_RX_CRC 0x00000002UL
00094 
00095 /** Transmit packet header */
00096 struct smsc95xx_tx_header {
00097         /** Command word */
00098         uint32_t command;
00099         /** Frame length */
00100         uint32_t len;
00101 } __attribute__ (( packed ));
00102 
00103 /** First segment */
00104 #define SMSC95XX_TX_FIRST 0x00002000UL
00105 
00106 /** Last segment */
00107 #define SMSC95XX_TX_LAST 0x00001000UL
00108 
00109 /** Buffer size */
00110 #define SMSC95XX_TX_LEN(len) ( (len) << 0 )
00111 
00112 /** Receive statistics */
00113 struct smsc95xx_rx_statistics {
00114         /** Good frames */
00115         uint32_t good;
00116         /** CRC errors */
00117         uint32_t crc;
00118         /** Runt frame errors */
00119         uint32_t undersize;
00120         /** Alignment errors */
00121         uint32_t alignment;
00122         /** Frame too long errors */
00123         uint32_t oversize;
00124         /** Later collision errors */
00125         uint32_t late;
00126         /** Bad frames */
00127         uint32_t bad;
00128         /** Dropped frames */
00129         uint32_t dropped;
00130 } __attribute__ (( packed ));
00131 
00132 /** Receive statistics */
00133 #define SMSC95XX_RX_STATISTICS 0
00134 
00135 /** Transmit statistics */
00136 struct smsc95xx_tx_statistics {
00137         /** Good frames */
00138         uint32_t good;
00139         /** Pause frames */
00140         uint32_t pause;
00141         /** Single collisions */
00142         uint32_t single;
00143         /** Multiple collisions */
00144         uint32_t multiple;
00145         /** Excessive collisions */
00146         uint32_t excessive;
00147         /** Late collisions */
00148         uint32_t late;
00149         /** Buffer underruns */
00150         uint32_t underrun;
00151         /** Excessive deferrals */
00152         uint32_t deferred;
00153         /** Carrier errors */
00154         uint32_t carrier;
00155         /** Bad frames */
00156         uint32_t bad;
00157 } __attribute__ (( packed ));
00158 
00159 /** Transmit statistics */
00160 #define SMSC95XX_TX_STATISTICS 1
00161 
00162 /** Reset delay (in microseconds) */
00163 #define SMSC95XX_RESET_DELAY_US 2
00164 
00165 /** Bulk IN maximum fill level
00166  *
00167  * This is a policy decision.
00168  */
00169 #define SMSC95XX_IN_MAX_FILL 8
00170 
00171 /** Bulk IN buffer size */
00172 #define SMSC95XX_IN_MTU                                         \
00173         ( sizeof ( struct smsc95xx_rx_header ) +                \
00174           ETH_FRAME_LEN + 4 /* possible VLAN header */          \
00175           + 4 /* CRC */ )
00176 
00177 /** Honeywell VM3 MAC address OEM string index */
00178 #define SMSC95XX_VM3_OEM_STRING_MAC 2
00179 
00180 #endif /* _SMSC95XX_H */