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trace.h
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00001 /******************************************************************************
00002  * include/public/trace.h
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a copy
00005  * of this software and associated documentation files (the "Software"), to
00006  * deal in the Software without restriction, including without limitation the
00007  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
00008  * sell copies of the Software, and to permit persons to whom the Software is
00009  * furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included in
00012  * all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
00017  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
00019  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
00020  * DEALINGS IN THE SOFTWARE.
00021  *
00022  * Mark Williamson, (C) 2004 Intel Research Cambridge
00023  * Copyright (C) 2005 Bin Ren
00024  */
00025 
00026 #ifndef __XEN_PUBLIC_TRACE_H__
00027 #define __XEN_PUBLIC_TRACE_H__
00028 
00029 FILE_LICENCE ( MIT );
00030 
00031 #define TRACE_EXTRA_MAX    7
00032 #define TRACE_EXTRA_SHIFT 28
00033 
00034 /* Trace classes */
00035 #define TRC_CLS_SHIFT 16
00036 #define TRC_GEN      0x0001f000    /* General trace            */
00037 #define TRC_SCHED    0x0002f000    /* Xen Scheduler trace      */
00038 #define TRC_DOM0OP   0x0004f000    /* Xen DOM0 operation trace */
00039 #define TRC_HVM      0x0008f000    /* Xen HVM trace            */
00040 #define TRC_MEM      0x0010f000    /* Xen memory trace         */
00041 #define TRC_PV       0x0020f000    /* Xen PV traces            */
00042 #define TRC_SHADOW   0x0040f000    /* Xen shadow tracing       */
00043 #define TRC_HW       0x0080f000    /* Xen hardware-related traces */
00044 #define TRC_GUEST    0x0800f000    /* Guest-generated traces   */
00045 #define TRC_ALL      0x0ffff000
00046 #define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff)
00047 #define TRC_HD_CYCLE_FLAG (1UL<<31)
00048 #define TRC_HD_INCLUDES_CYCLE_COUNT(x) ( !!( (x) & TRC_HD_CYCLE_FLAG ) )
00049 #define TRC_HD_EXTRA(x)    (((x)>>TRACE_EXTRA_SHIFT)&TRACE_EXTRA_MAX)
00050 
00051 /* Trace subclasses */
00052 #define TRC_SUBCLS_SHIFT 12
00053 
00054 /* trace subclasses for SVM */
00055 #define TRC_HVM_ENTRYEXIT   0x00081000   /* VMENTRY and #VMEXIT       */
00056 #define TRC_HVM_HANDLER     0x00082000   /* various HVM handlers      */
00057 #define TRC_HVM_EMUL        0x00084000   /* emulated devices */
00058 
00059 #define TRC_SCHED_MIN       0x00021000   /* Just runstate changes */
00060 #define TRC_SCHED_CLASS     0x00022000   /* Scheduler-specific    */
00061 #define TRC_SCHED_VERBOSE   0x00028000   /* More inclusive scheduling */
00062 
00063 /*
00064  * The highest 3 bits of the last 12 bits of TRC_SCHED_CLASS above are
00065  * reserved for encoding what scheduler produced the information. The
00066  * actual event is encoded in the last 9 bits.
00067  *
00068  * This means we have 8 scheduling IDs available (which means at most 8
00069  * schedulers generating events) and, in each scheduler, up to 512
00070  * different events.
00071  */
00072 #define TRC_SCHED_ID_BITS 3
00073 #define TRC_SCHED_ID_SHIFT (TRC_SUBCLS_SHIFT - TRC_SCHED_ID_BITS)
00074 #define TRC_SCHED_ID_MASK (((1UL<<TRC_SCHED_ID_BITS) - 1) << TRC_SCHED_ID_SHIFT)
00075 #define TRC_SCHED_EVT_MASK (~(TRC_SCHED_ID_MASK))
00076 
00077 /* Per-scheduler IDs, to identify scheduler specific events */
00078 #define TRC_SCHED_CSCHED   0
00079 #define TRC_SCHED_CSCHED2  1
00080 #define TRC_SCHED_SEDF     2
00081 #define TRC_SCHED_ARINC653 3
00082 
00083 /* Per-scheduler tracing */
00084 #define TRC_SCHED_CLASS_EVT(_c, _e) \
00085   ( ( TRC_SCHED_CLASS | \
00086       ((TRC_SCHED_##_c << TRC_SCHED_ID_SHIFT) & TRC_SCHED_ID_MASK) ) + \
00087     (_e & TRC_SCHED_EVT_MASK) )
00088 
00089 /* Trace classes for Hardware */
00090 #define TRC_HW_PM           0x00801000   /* Power management traces */
00091 #define TRC_HW_IRQ          0x00802000   /* Traces relating to the handling of IRQs */
00092 
00093 /* Trace events per class */
00094 #define TRC_LOST_RECORDS        (TRC_GEN + 1)
00095 #define TRC_TRACE_WRAP_BUFFER  (TRC_GEN + 2)
00096 #define TRC_TRACE_CPU_CHANGE    (TRC_GEN + 3)
00097 
00098 #define TRC_SCHED_RUNSTATE_CHANGE   (TRC_SCHED_MIN + 1)
00099 #define TRC_SCHED_CONTINUE_RUNNING  (TRC_SCHED_MIN + 2)
00100 #define TRC_SCHED_DOM_ADD        (TRC_SCHED_VERBOSE +  1)
00101 #define TRC_SCHED_DOM_REM        (TRC_SCHED_VERBOSE +  2)
00102 #define TRC_SCHED_SLEEP          (TRC_SCHED_VERBOSE +  3)
00103 #define TRC_SCHED_WAKE           (TRC_SCHED_VERBOSE +  4)
00104 #define TRC_SCHED_YIELD          (TRC_SCHED_VERBOSE +  5)
00105 #define TRC_SCHED_BLOCK          (TRC_SCHED_VERBOSE +  6)
00106 #define TRC_SCHED_SHUTDOWN       (TRC_SCHED_VERBOSE +  7)
00107 #define TRC_SCHED_CTL            (TRC_SCHED_VERBOSE +  8)
00108 #define TRC_SCHED_ADJDOM         (TRC_SCHED_VERBOSE +  9)
00109 #define TRC_SCHED_SWITCH         (TRC_SCHED_VERBOSE + 10)
00110 #define TRC_SCHED_S_TIMER_FN     (TRC_SCHED_VERBOSE + 11)
00111 #define TRC_SCHED_T_TIMER_FN     (TRC_SCHED_VERBOSE + 12)
00112 #define TRC_SCHED_DOM_TIMER_FN   (TRC_SCHED_VERBOSE + 13)
00113 #define TRC_SCHED_SWITCH_INFPREV (TRC_SCHED_VERBOSE + 14)
00114 #define TRC_SCHED_SWITCH_INFNEXT (TRC_SCHED_VERBOSE + 15)
00115 #define TRC_SCHED_SHUTDOWN_CODE  (TRC_SCHED_VERBOSE + 16)
00116 
00117 #define TRC_MEM_PAGE_GRANT_MAP      (TRC_MEM + 1)
00118 #define TRC_MEM_PAGE_GRANT_UNMAP    (TRC_MEM + 2)
00119 #define TRC_MEM_PAGE_GRANT_TRANSFER (TRC_MEM + 3)
00120 #define TRC_MEM_SET_P2M_ENTRY       (TRC_MEM + 4)
00121 #define TRC_MEM_DECREASE_RESERVATION (TRC_MEM + 5)
00122 #define TRC_MEM_POD_POPULATE        (TRC_MEM + 16)
00123 #define TRC_MEM_POD_ZERO_RECLAIM    (TRC_MEM + 17)
00124 #define TRC_MEM_POD_SUPERPAGE_SPLINTER (TRC_MEM + 18)
00125 
00126 #define TRC_PV_ENTRY   0x00201000 /* Hypervisor entry points for PV guests. */
00127 #define TRC_PV_SUBCALL 0x00202000 /* Sub-call in a multicall hypercall */
00128 
00129 #define TRC_PV_HYPERCALL             (TRC_PV_ENTRY +  1)
00130 #define TRC_PV_TRAP                  (TRC_PV_ENTRY +  3)
00131 #define TRC_PV_PAGE_FAULT            (TRC_PV_ENTRY +  4)
00132 #define TRC_PV_FORCED_INVALID_OP     (TRC_PV_ENTRY +  5)
00133 #define TRC_PV_EMULATE_PRIVOP        (TRC_PV_ENTRY +  6)
00134 #define TRC_PV_EMULATE_4GB           (TRC_PV_ENTRY +  7)
00135 #define TRC_PV_MATH_STATE_RESTORE    (TRC_PV_ENTRY +  8)
00136 #define TRC_PV_PAGING_FIXUP          (TRC_PV_ENTRY +  9)
00137 #define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV_ENTRY + 10)
00138 #define TRC_PV_PTWR_EMULATION        (TRC_PV_ENTRY + 11)
00139 #define TRC_PV_PTWR_EMULATION_PAE    (TRC_PV_ENTRY + 12)
00140 #define TRC_PV_HYPERCALL_V2          (TRC_PV_ENTRY + 13)
00141 #define TRC_PV_HYPERCALL_SUBCALL     (TRC_PV_SUBCALL + 14)
00142 
00143 /*
00144  * TRC_PV_HYPERCALL_V2 format
00145  *
00146  * Only some of the hypercall argument are recorded. Bit fields A0 to
00147  * A5 in the first extra word are set if the argument is present and
00148  * the arguments themselves are packed sequentially in the following
00149  * words.
00150  *
00151  * The TRC_64_FLAG bit is not set for these events (even if there are
00152  * 64-bit arguments in the record).
00153  *
00154  * Word
00155  * 0    bit 31 30|29 28|27 26|25 24|23 22|21 20|19 ... 0
00156  *          A5   |A4   |A3   |A2   |A1   |A0   |Hypercall op
00157  * 1    First 32 bit (or low word of first 64 bit) arg in record
00158  * 2    Second 32 bit (or high word of first 64 bit) arg in record
00159  * ...
00160  *
00161  * A0-A5 bitfield values:
00162  *
00163  *   00b  Argument not present
00164  *   01b  32-bit argument present
00165  *   10b  64-bit argument present
00166  *   11b  Reserved
00167  */
00168 #define TRC_PV_HYPERCALL_V2_ARG_32(i) (0x1 << (20 + 2*(i)))
00169 #define TRC_PV_HYPERCALL_V2_ARG_64(i) (0x2 << (20 + 2*(i)))
00170 #define TRC_PV_HYPERCALL_V2_ARG_MASK  (0xfff00000)
00171 
00172 #define TRC_SHADOW_NOT_SHADOW                 (TRC_SHADOW +  1)
00173 #define TRC_SHADOW_FAST_PROPAGATE             (TRC_SHADOW +  2)
00174 #define TRC_SHADOW_FAST_MMIO                  (TRC_SHADOW +  3)
00175 #define TRC_SHADOW_FALSE_FAST_PATH            (TRC_SHADOW +  4)
00176 #define TRC_SHADOW_MMIO                       (TRC_SHADOW +  5)
00177 #define TRC_SHADOW_FIXUP                      (TRC_SHADOW +  6)
00178 #define TRC_SHADOW_DOMF_DYING                 (TRC_SHADOW +  7)
00179 #define TRC_SHADOW_EMULATE                    (TRC_SHADOW +  8)
00180 #define TRC_SHADOW_EMULATE_UNSHADOW_USER      (TRC_SHADOW +  9)
00181 #define TRC_SHADOW_EMULATE_UNSHADOW_EVTINJ    (TRC_SHADOW + 10)
00182 #define TRC_SHADOW_EMULATE_UNSHADOW_UNHANDLED (TRC_SHADOW + 11)
00183 #define TRC_SHADOW_WRMAP_BF                   (TRC_SHADOW + 12)
00184 #define TRC_SHADOW_PREALLOC_UNPIN             (TRC_SHADOW + 13)
00185 #define TRC_SHADOW_RESYNC_FULL                (TRC_SHADOW + 14)
00186 #define TRC_SHADOW_RESYNC_ONLY                (TRC_SHADOW + 15)
00187 
00188 /* trace events per subclass */
00189 #define TRC_HVM_NESTEDFLAG      (0x400)
00190 #define TRC_HVM_VMENTRY         (TRC_HVM_ENTRYEXIT + 0x01)
00191 #define TRC_HVM_VMEXIT          (TRC_HVM_ENTRYEXIT + 0x02)
00192 #define TRC_HVM_VMEXIT64        (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02)
00193 #define TRC_HVM_PF_XEN          (TRC_HVM_HANDLER + 0x01)
00194 #define TRC_HVM_PF_XEN64        (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01)
00195 #define TRC_HVM_PF_INJECT       (TRC_HVM_HANDLER + 0x02)
00196 #define TRC_HVM_PF_INJECT64     (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02)
00197 #define TRC_HVM_INJ_EXC         (TRC_HVM_HANDLER + 0x03)
00198 #define TRC_HVM_INJ_VIRQ        (TRC_HVM_HANDLER + 0x04)
00199 #define TRC_HVM_REINJ_VIRQ      (TRC_HVM_HANDLER + 0x05)
00200 #define TRC_HVM_IO_READ         (TRC_HVM_HANDLER + 0x06)
00201 #define TRC_HVM_IO_WRITE        (TRC_HVM_HANDLER + 0x07)
00202 #define TRC_HVM_CR_READ         (TRC_HVM_HANDLER + 0x08)
00203 #define TRC_HVM_CR_READ64       (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08)
00204 #define TRC_HVM_CR_WRITE        (TRC_HVM_HANDLER + 0x09)
00205 #define TRC_HVM_CR_WRITE64      (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09)
00206 #define TRC_HVM_DR_READ         (TRC_HVM_HANDLER + 0x0A)
00207 #define TRC_HVM_DR_WRITE        (TRC_HVM_HANDLER + 0x0B)
00208 #define TRC_HVM_MSR_READ        (TRC_HVM_HANDLER + 0x0C)
00209 #define TRC_HVM_MSR_WRITE       (TRC_HVM_HANDLER + 0x0D)
00210 #define TRC_HVM_CPUID           (TRC_HVM_HANDLER + 0x0E)
00211 #define TRC_HVM_INTR            (TRC_HVM_HANDLER + 0x0F)
00212 #define TRC_HVM_NMI             (TRC_HVM_HANDLER + 0x10)
00213 #define TRC_HVM_SMI             (TRC_HVM_HANDLER + 0x11)
00214 #define TRC_HVM_VMMCALL         (TRC_HVM_HANDLER + 0x12)
00215 #define TRC_HVM_HLT             (TRC_HVM_HANDLER + 0x13)
00216 #define TRC_HVM_INVLPG          (TRC_HVM_HANDLER + 0x14)
00217 #define TRC_HVM_INVLPG64        (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14)
00218 #define TRC_HVM_MCE             (TRC_HVM_HANDLER + 0x15)
00219 #define TRC_HVM_IOPORT_READ     (TRC_HVM_HANDLER + 0x16)
00220 #define TRC_HVM_IOMEM_READ      (TRC_HVM_HANDLER + 0x17)
00221 #define TRC_HVM_CLTS            (TRC_HVM_HANDLER + 0x18)
00222 #define TRC_HVM_LMSW            (TRC_HVM_HANDLER + 0x19)
00223 #define TRC_HVM_LMSW64          (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19)
00224 #define TRC_HVM_RDTSC           (TRC_HVM_HANDLER + 0x1a)
00225 #define TRC_HVM_INTR_WINDOW     (TRC_HVM_HANDLER + 0x20)
00226 #define TRC_HVM_NPF             (TRC_HVM_HANDLER + 0x21)
00227 #define TRC_HVM_REALMODE_EMULATE (TRC_HVM_HANDLER + 0x22)
00228 #define TRC_HVM_TRAP             (TRC_HVM_HANDLER + 0x23)
00229 #define TRC_HVM_TRAP_DEBUG       (TRC_HVM_HANDLER + 0x24)
00230 #define TRC_HVM_VLAPIC           (TRC_HVM_HANDLER + 0x25)
00231 
00232 #define TRC_HVM_IOPORT_WRITE    (TRC_HVM_HANDLER + 0x216)
00233 #define TRC_HVM_IOMEM_WRITE     (TRC_HVM_HANDLER + 0x217)
00234 
00235 /* Trace events for emulated devices */
00236 #define TRC_HVM_EMUL_HPET_START_TIMER  (TRC_HVM_EMUL + 0x1)
00237 #define TRC_HVM_EMUL_PIT_START_TIMER   (TRC_HVM_EMUL + 0x2)
00238 #define TRC_HVM_EMUL_RTC_START_TIMER   (TRC_HVM_EMUL + 0x3)
00239 #define TRC_HVM_EMUL_LAPIC_START_TIMER (TRC_HVM_EMUL + 0x4)
00240 #define TRC_HVM_EMUL_HPET_STOP_TIMER   (TRC_HVM_EMUL + 0x5)
00241 #define TRC_HVM_EMUL_PIT_STOP_TIMER    (TRC_HVM_EMUL + 0x6)
00242 #define TRC_HVM_EMUL_RTC_STOP_TIMER    (TRC_HVM_EMUL + 0x7)
00243 #define TRC_HVM_EMUL_LAPIC_STOP_TIMER  (TRC_HVM_EMUL + 0x8)
00244 #define TRC_HVM_EMUL_PIT_TIMER_CB      (TRC_HVM_EMUL + 0x9)
00245 #define TRC_HVM_EMUL_LAPIC_TIMER_CB    (TRC_HVM_EMUL + 0xA)
00246 #define TRC_HVM_EMUL_PIC_INT_OUTPUT    (TRC_HVM_EMUL + 0xB)
00247 #define TRC_HVM_EMUL_PIC_KICK          (TRC_HVM_EMUL + 0xC)
00248 #define TRC_HVM_EMUL_PIC_INTACK        (TRC_HVM_EMUL + 0xD)
00249 #define TRC_HVM_EMUL_PIC_POSEDGE       (TRC_HVM_EMUL + 0xE)
00250 #define TRC_HVM_EMUL_PIC_NEGEDGE       (TRC_HVM_EMUL + 0xF)
00251 #define TRC_HVM_EMUL_PIC_PEND_IRQ_CALL (TRC_HVM_EMUL + 0x10)
00252 #define TRC_HVM_EMUL_LAPIC_PIC_INTR    (TRC_HVM_EMUL + 0x11)
00253 
00254 /* trace events for per class */
00255 #define TRC_PM_FREQ_CHANGE      (TRC_HW_PM + 0x01)
00256 #define TRC_PM_IDLE_ENTRY       (TRC_HW_PM + 0x02)
00257 #define TRC_PM_IDLE_EXIT        (TRC_HW_PM + 0x03)
00258 
00259 /* Trace events for IRQs */
00260 #define TRC_HW_IRQ_MOVE_CLEANUP_DELAY (TRC_HW_IRQ + 0x1)
00261 #define TRC_HW_IRQ_MOVE_CLEANUP       (TRC_HW_IRQ + 0x2)
00262 #define TRC_HW_IRQ_BIND_VECTOR        (TRC_HW_IRQ + 0x3)
00263 #define TRC_HW_IRQ_CLEAR_VECTOR       (TRC_HW_IRQ + 0x4)
00264 #define TRC_HW_IRQ_MOVE_FINISH        (TRC_HW_IRQ + 0x5)
00265 #define TRC_HW_IRQ_ASSIGN_VECTOR      (TRC_HW_IRQ + 0x6)
00266 #define TRC_HW_IRQ_UNMAPPED_VECTOR    (TRC_HW_IRQ + 0x7)
00267 #define TRC_HW_IRQ_HANDLED            (TRC_HW_IRQ + 0x8)
00268 
00269 /*
00270  * Event Flags
00271  *
00272  * Some events (e.g, TRC_PV_TRAP and TRC_HVM_IOMEM_READ) have multiple
00273  * record formats.  These event flags distinguish between the
00274  * different formats.
00275  */
00276 #define TRC_64_FLAG 0x100 /* Addresses are 64 bits (instead of 32 bits) */
00277 
00278 /* This structure represents a single trace buffer record. */
00279 struct t_rec {
00280     uint32_t event:28;
00281     uint32_t extra_u32:3;         /* # entries in trailing extra_u32[] array */
00282     uint32_t cycles_included:1;   /* u.cycles or u.no_cycles? */
00283     union {
00284         struct {
00285             uint32_t cycles_lo, cycles_hi; /* cycle counter timestamp */
00286             uint32_t extra_u32[7];         /* event data items */
00287         } cycles;
00288         struct {
00289             uint32_t extra_u32[7];         /* event data items */
00290         } nocycles;
00291     } u;
00292 };
00293 
00294 /*
00295  * This structure contains the metadata for a single trace buffer.  The head
00296  * field, indexes into an array of struct t_rec's.
00297  */
00298 struct t_buf {
00299     /* Assume the data buffer size is X.  X is generally not a power of 2.
00300      * CONS and PROD are incremented modulo (2*X):
00301      *     0 <= cons < 2*X
00302      *     0 <= prod < 2*X
00303      * This is done because addition modulo X breaks at 2^32 when X is not a
00304      * power of 2:
00305      *     (((2^32 - 1) % X) + 1) % X != (2^32) % X
00306      */
00307     uint32_t cons;   /* Offset of next item to be consumed by control tools. */
00308     uint32_t prod;   /* Offset of next item to be produced by Xen.           */
00309     /*  Records follow immediately after the meta-data header.    */
00310 };
00311 
00312 /* Structure used to pass MFNs to the trace buffers back to trace consumers.
00313  * Offset is an offset into the mapped structure where the mfn list will be held.
00314  * MFNs will be at ((unsigned long *)(t_info))+(t_info->cpu_offset[cpu]).
00315  */
00316 struct t_info {
00317     uint16_t tbuf_size; /* Size in pages of each trace buffer */
00318     uint16_t mfn_offset[];  /* Offset within t_info structure of the page list per cpu */
00319     /* MFN lists immediately after the header */
00320 };
00321 
00322 #endif /* __XEN_PUBLIC_TRACE_H__ */
00323 
00324 /*
00325  * Local variables:
00326  * mode: C
00327  * c-file-style: "BSD"
00328  * c-basic-offset: 4
00329  * tab-width: 4
00330  * indent-tabs-mode: nil
00331  * End:
00332  */