iPXE
vga.h
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00001 /*
00002  *
00003  * modified
00004  * by Steve M. Gehlbach <steve@kesa.com>
00005  *
00006  * Originally  from linux/drivers/video/vga16.c by
00007  * Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
00008  * Copyright 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
00009  * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
00010  * Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
00011  *
00012  */ 
00013 
00014 #ifndef VGA_H_INCL
00015 #define VGA_H_INCL 1
00016 
00017 //#include <cpu/p5/io.h>
00018 
00019 #define u8 unsigned char
00020 #define u16 unsigned short
00021 #define u32 unsigned int
00022 #define __u32 u32
00023 
00024 #define VERROR -1
00025 #define CHAR_HEIGHT 16
00026 #define LINES 25
00027 #define COLS 80
00028 
00029 // macros for writing to vga regs
00030 #define write_crtc(data,addr) outb(addr,CRT_IC); outb(data,CRT_DC)
00031 #define write_att(data,addr) inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80)
00032 #define write_seq(data,addr) outb(addr,SEQ_I); outb(data,SEQ_D)
00033 #define write_gra(data,addr) outb(addr,GRA_I); outb(data,GRA_D)
00034 u8 read_seq_b(u16 addr);
00035 u8 read_gra_b(u16 addr);
00036 u8 read_crtc_b(u16 addr);
00037 u8 read_att_b(u16 addr);
00038 
00039 
00040 #ifdef VGA_HARDWARE_FIXUP
00041 void vga_hardware_fixup(void);
00042 #else
00043 #define vga_hardware_fixup() do{} while(0)
00044 #endif
00045 
00046 #define SYNC_HOR_HIGH_ACT    1       /* horizontal sync high active  */
00047 #define SYNC_VERT_HIGH_ACT   2       /* vertical sync high active    */
00048 #define SYNC_EXT             4       /* external sync                */
00049 #define SYNC_COMP_HIGH_ACT   8       /* composite sync high active   */
00050 #define SYNC_BROADCAST       16      /* broadcast video timings      */
00051                                         /* vtotal = 144d/288n/576i => PAL  */
00052                                         /* vtotal = 121d/242n/484i => NTSC */
00053 
00054 #define SYNC_ON_GREEN        32      /* sync on green */
00055 
00056 #define VMODE_NONINTERLACED  0       /* non interlaced */
00057 #define VMODE_INTERLACED     1       /* interlaced   */
00058 #define VMODE_DOUBLE         2       /* double scan */
00059 #define VMODE_MASK           255
00060 
00061 #define VMODE_YWRAP          256     /* ywrap instead of panning     */
00062 #define VMODE_SMOOTH_XPAN    512     /* smooth xpan possible (internally used) */
00063 #define VMODE_CONUPDATE      512     /* don't update x/yoffset       */
00064 
00065 /* VGA data register ports */
00066 #define CRT_DC  0x3D5           /* CRT Controller Data Register - color emulation */
00067 #define CRT_DM  0x3B5           /* CRT Controller Data Register - mono emulation */
00068 #define ATT_R   0x3C1           /* Attribute Controller Data Read Register */
00069 #define GRA_D   0x3CF           /* Graphics Controller Data Register */
00070 #define SEQ_D   0x3C5           /* Sequencer Data Register */
00071 
00072 #define MIS_R   0x3CC           // Misc Output Read Register
00073 #define MIS_W   0x3C2           // Misc Output Write Register
00074 
00075 #define IS1_RC  0x3DA           /* Input Status Register 1 - color emulation */
00076 #define IS1_RM  0x3BA           /* Input Status Register 1 - mono emulation */
00077 #define PEL_D   0x3C9           /* PEL Data Register */
00078 #define PEL_MSK 0x3C6           /* PEL mask register */
00079 
00080 /* EGA-specific registers */
00081 #define GRA_E0  0x3CC           /* Graphics enable processor 0 */
00082 #define GRA_E1  0x3CA           /* Graphics enable processor 1 */
00083 
00084 
00085 /* VGA index register ports */
00086 #define CRT_IC  0x3D4           /* CRT Controller Index - color emulation */
00087 #define CRT_IM  0x3B4           /* CRT Controller Index - mono emulation */
00088 #define ATT_IW  0x3C0           /* Attribute Controller Index & Data Write Register */
00089 #define GRA_I   0x3CE           /* Graphics Controller Index */
00090 #define SEQ_I   0x3C4           /* Sequencer Index */
00091 #define PEL_IW  0x3C8           /* PEL Write Index */
00092 #define PEL_IR  0x3C7           /* PEL Read Index */
00093 
00094 /* standard VGA indexes max counts */
00095 #define CRTC_C   25              /* 25 CRT Controller Registers sequentially set*/
00096                                                                  // the remainder are not in the par array
00097 #define ATT_C   21              /* 21 Attribute Controller Registers */
00098 #define GRA_C   9               /* 9  Graphics Controller Registers */
00099 #define SEQ_C   5               /* 5  Sequencer Registers */
00100 #define MIS_C   1               /* 1  Misc Output Register */
00101 
00102 #define CRTC_H_TOTAL            0
00103 #define CRTC_H_DISP             1
00104 #define CRTC_H_BLANK_START      2
00105 #define CRTC_H_BLANK_END        3
00106 #define CRTC_H_SYNC_START       4
00107 #define CRTC_H_SYNC_END         5
00108 #define CRTC_V_TOTAL            6
00109 #define CRTC_OVERFLOW           7
00110 #define CRTC_PRESET_ROW         8
00111 #define CRTC_MAX_SCAN           9
00112 #define CRTC_CURSOR_START       0x0A
00113 #define CRTC_CURSOR_END         0x0B
00114 #define CRTC_START_HI           0x0C
00115 #define CRTC_START_LO           0x0D
00116 #define CRTC_CURSOR_HI          0x0E
00117 #define CRTC_CURSOR_LO          0x0F
00118 #define CRTC_V_SYNC_START       0x10
00119 #define CRTC_V_SYNC_END         0x11
00120 #define CRTC_V_DISP_END         0x12
00121 #define CRTC_OFFSET             0x13
00122 #define CRTC_UNDERLINE          0x14
00123 #define CRTC_V_BLANK_START      0x15
00124 #define CRTC_V_BLANK_END        0x16
00125 #define CRTC_MODE               0x17
00126 #define CRTC_LINE_COMPARE       0x18
00127 
00128 #define ATC_MODE                0x10
00129 #define ATC_OVERSCAN            0x11
00130 #define ATC_PLANE_ENABLE        0x12
00131 #define ATC_PEL                 0x13
00132 #define ATC_COLOR_PAGE          0x14
00133 
00134 #define SEQ_CLOCK_MODE          0x01
00135 #define SEQ_PLANE_WRITE         0x02
00136 #define SEQ_CHARACTER_MAP       0x03
00137 #define SEQ_MEMORY_MODE         0x04
00138 
00139 #define GDC_SR_VALUE            0x00
00140 #define GDC_SR_ENABLE           0x01
00141 #define GDC_COMPARE_VALUE       0x02
00142 #define GDC_DATA_ROTATE         0x03
00143 #define GDC_PLANE_READ          0x04
00144 #define GDC_MODE                0x05
00145 #define GDC_MISC                0x06
00146 #define GDC_COMPARE_MASK        0x07
00147 #define GDC_BIT_MASK            0x08
00148 
00149 // text attributes
00150 #define VGA_ATTR_CLR_RED 0x4
00151 #define VGA_ATTR_CLR_GRN 0x2
00152 #define VGA_ATTR_CLR_BLU 0x1
00153 #define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN)
00154 #define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
00155 #define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED)
00156 #define VGA_ATTR_CLR_BLK 0
00157 #define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
00158 #define VGA_ATTR_BNK     0x80
00159 #define VGA_ATTR_ITN     0x08
00160 
00161 /*
00162  * vga register parameters
00163  * these are copied to the 
00164  * registers.
00165  *
00166  */
00167 struct vga_par {
00168         u8 crtc[CRTC_C];
00169         u8 atc[ATT_C];
00170         u8 gdc[GRA_C];
00171         u8 seq[SEQ_C];
00172         u8 misc; // the misc register, MIS_W
00173         u8 vss;
00174 };
00175 
00176 
00177 /* Interpretation of offset for color fields: All offsets are from the right,
00178  * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
00179  * can use the offset as right argument to <<). A pixel afterwards is a bit
00180  * stream and is written to video memory as that unmodified. This implies
00181  * big-endian byte order if bits_per_pixel is greater than 8.
00182  */
00183 struct fb_bitfield {
00184         __u32 offset;                   /* beginning of bitfield        */
00185         __u32 length;                   /* length of bitfield           */
00186         __u32 msb_right;                /* != 0 : Most significant bit is */ 
00187                                         /* right */ 
00188 };
00189 
00190 struct screeninfo {
00191         __u32 xres;                     /* visible resolution           */
00192         __u32 yres;
00193         __u32 xres_virtual;             /* virtual resolution           */
00194         __u32 yres_virtual;
00195         __u32 xoffset;                  /* offset from virtual to visible */
00196         __u32 yoffset;                  /* resolution                   */
00197 
00198         __u32 bits_per_pixel;           /* guess what                   */
00199         __u32 grayscale;                /* != 0 Graylevels instead of colors */
00200 
00201         struct fb_bitfield red;         /* bitfield in fb mem if true color, */
00202         struct fb_bitfield green;       /* else only length is significant */
00203         struct fb_bitfield blue;
00204         struct fb_bitfield transp;      /* transparency                 */      
00205 
00206         __u32 nonstd;                   /* != 0 Non standard pixel format */
00207 
00208         __u32 activate;                 /* see FB_ACTIVATE_*            */
00209 
00210         __u32 height;                   /* height of picture in mm    */
00211         __u32 width;                    /* width of picture in mm     */
00212 
00213         __u32 accel_flags;              /* acceleration flags (hints)   */
00214 
00215         /* Timing: All values in pixclocks, except pixclock (of course) */
00216         __u32 pixclock;                 /* pixel clock in ps (pico seconds) */
00217         __u32 left_margin;              /* time from sync to picture    */
00218         __u32 right_margin;             /* time from picture to sync    */
00219         __u32 upper_margin;             /* time from sync to picture    */
00220         __u32 lower_margin;
00221         __u32 hsync_len;                /* length of horizontal sync    */
00222         __u32 vsync_len;                /* length of vertical sync      */
00223         __u32 sync;                     /* sync polarity                */
00224         __u32 vmode;                    /* interlaced etc                               */
00225         __u32 reserved[6];              /* Reserved for future compatibility */
00226 };
00227 
00228 #endif