iPXE
MT25408_PRM.h
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1 /*
2  This software is available to you under a choice of one of two
3  licenses. You may choose to be licensed under the terms of the GNU
4  General Public License (GPL) Version 2, available at
5  <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD
6  license, available in the LICENSE.TXT file accompanying this
7  software. These details are also available at
8  <http://openib.org/license.html>.
9 
10  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13  NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15  ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16  CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17  SOFTWARE.
18 
19  Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved.
20 */
21 
22 FILE_LICENCE ( GPL2_ONLY );
23 
24 /***
25  *** This file was generated at "Mon Apr 16 23:22:02 2007"
26  *** by:
27  *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix hermonprm_ -bits -fixnames MT25408_PRM.csp
28  ***/
29 
30 #ifndef H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H
31 #define H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H
32 
33 /* UD Address Vector */
34 
35 struct hermonprm_ud_address_vector_st { /* Little Endian */
36  pseudo_bit_t pd[0x00018]; /* Protection Domain */
37  pseudo_bit_t port_number[0x00002]; /* Port number
38  1 - Port 1
39  2 - Port 2
40  other - reserved */
42  pseudo_bit_t fl[0x00001]; /* force loopback */
43 /* -------------- */
44  pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
45  pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
46  pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
48 /* -------------- */
49  pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
50  pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control.
51  0 - 4X injection rate
52  1 - 1X injection rate
53  other - reserved
54  */
56  pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table
57  mgid_index = (port_number-1) * 2^log_max_gid + gid_index
58  Where:
59  1. log_max_gid is taken from QUERY_DEV_CAP command
60  2. gid_index is the index to the GID table */
62 /* -------------- */
63  pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
64  pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
65  pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */
66 /* -------------- */
67  pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
68 /* -------------- */
69  pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
70 /* -------------- */
71  pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
72 /* -------------- */
73  pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */
74 /* -------------- */
75 };
76 
77 /* Send doorbell */
78 
79 struct hermonprm_send_doorbell_st { /* Little Endian */
80  pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */
81  pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */
83  pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */
84  pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */
85 /* -------------- */
86  pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */
88  pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
89 /* -------------- */
90 };
91 
92 /* Send wqe segment data inline */
93 
94 struct hermonprm_wqe_segment_data_inline_st { /* Little Endian */
95  pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */
98 /* -------------- */
99  pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */
101 /* -------------- */
103 /* -------------- */
104 };
105 
106 /* Send wqe segment data ptr */
107 
108 struct hermonprm_wqe_segment_data_ptr_st { /* Little Endian */
111 /* -------------- */
112  pseudo_bit_t l_key[0x00020];
113 /* -------------- */
115 /* -------------- */
117 /* -------------- */
118 };
119 
120 /* Send wqe segment rd */
121 
122 struct hermonprm_local_invalidate_segment_st { /* Little Endian */
124 /* -------------- */
127 /* -------------- */
129 /* -------------- */
130 };
131 
132 /* Fast_Registration_Segment ####michal - doesn't match PRM (fields were added, see below) new table size in bytes - 0x30 */
133 
134 struct hermonprm_fast_registration_segment_st { /* Little Endian */
136  pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */
137  pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */
138  pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */
139  pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */
140  pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */
141 /* -------------- */
142  pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list ### michal - this field is replaced with mem_key .32 */
143 /* -------------- */
144  pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. ###michal-this field is replaced with pbl_ptr_63_32 */
145 /* -------------- */
146  pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes.
147  page_size should be less than 20. ###michal - field doesn't exsist (see replacement above) */
149  pseudo_bit_t zb[0x00001]; /* Zero Based Region ###michal - field doesn't exsist (see replacement above) */
150  pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list ###michal - field doesn't exsist (see replacement above) */
151 /* -------------- */
152  pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */
153 /* -------------- */
154  pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */
155 /* -------------- */
156  pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */
157 /* -------------- */
158  pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */
159 /* -------------- */
160 };
161 
162 /* Send wqe segment atomic */
163 
164 struct hermonprm_wqe_segment_atomic_st { /* Little Endian */
166 /* -------------- */
168 /* -------------- */
170 /* -------------- */
172 /* -------------- */
173 };
174 
175 /* Send wqe segment remote address */
176 
177 struct hermonprm_wqe_segment_remote_address_st { /* Little Endian */
179 /* -------------- */
181 /* -------------- */
182  pseudo_bit_t rkey[0x00020];
183 /* -------------- */
185 /* -------------- */
186 };
187 
188 /* end wqe segment bind */
189 
190 struct hermonprm_wqe_segment_bind_st { /* Little Endian */
192  pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */
193  pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window.
194  */
195  pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */
196 /* -------------- */
198  pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */
199  pseudo_bit_t type[0x00001]; /* Window type.
200  0 - Type one window
201  1 - Type two window
202  */
203 /* -------------- */
204  pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */
205 /* -------------- */
206  pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */
207 /* -------------- */
209 /* -------------- */
211 /* -------------- */
213 /* -------------- */
215 /* -------------- */
216 };
217 
218 /* Send wqe segment ud */
219 
220 struct hermonprm_wqe_segment_ud_st { /* Little Endian */
221  struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
222 /* -------------- */
225 /* -------------- */
226  pseudo_bit_t q_key[0x00020];
227 /* -------------- */
229 /* -------------- */
230 };
231 
232 /* Send wqe segment rd */
233 
234 struct hermonprm_wqe_segment_rd_st { /* Little Endian */
237 /* -------------- */
238  pseudo_bit_t q_key[0x00020];
239 /* -------------- */
241 /* -------------- */
242 };
243 
244 /* Send wqe segment ctrl */
245 
246 struct hermonprm_wqe_segment_ctrl_send_st { /* Little Endian */
249  pseudo_bit_t owner[0x00001];
250 /* -------------- */
251  pseudo_bit_t ds[0x00006]; /* descriptor (wqe) size in 16bytes chunk */
252  pseudo_bit_t f[0x00001]; /* fence */
254 /* -------------- */
255  pseudo_bit_t fl[0x00001]; /* Force LoopBack */
256  pseudo_bit_t s[0x00001]; /* Remote Solicited Event */
257  pseudo_bit_t c[0x00002]; /* completion required: 0b00 - no 0b11 - yes */
258  pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */
259  pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */
261  pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */
263 /* -------------- */
264  pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */
265 /* -------------- */
266 };
267 
268 /* Address Path # ###michal - match to PRM */
269 
270 struct hermonprm_address_path_st { /* Little Endian */
271  pseudo_bit_t pkey_index[0x00007]; /* PKey table index */
273  pseudo_bit_t sv[0x00001]; /* Service VLAN on QP */
274  pseudo_bit_t cv[0x00001]; /* Customer VLAN in QP */
275  pseudo_bit_t fl[0x00001]; /* Force LoopBack */
276 /* -------------- */
277  pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */
278  pseudo_bit_t my_lid_smac_idx[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */
279  pseudo_bit_t grh_ip[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */
281 /* -------------- */
282  pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */
283  pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control.
284  0 - 100% injection rate
285  1 - 25% injection rate
286  2 - 12.5% injection rate
287  3 - 50% injection rate
288  7: 2.5 Gb/s.
289  8: 10 Gb/s.
290  9: 30 Gb/s.
291  10: 5 Gb/s.
292  11: 20 Gb/s.
293  12: 40 Gb/s.
294  13: 60 Gb/s.
295  14: 80 Gb/s.
296  15: 120 Gb/s. */
298  pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table */
300  pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details.
301  The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */
302 /* -------------- */
303  pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */
304  pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */
306 /* -------------- */
307  pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */
308 /* -------------- */
309  pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */
310 /* -------------- */
311  pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */
312 /* -------------- */
313  pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */
314 /* -------------- */
316  pseudo_bit_t sp[0x00001]; /* if set, spoofing protection is enforced on this QP and Ethertype headers are restricted */
318  pseudo_bit_t fvl[0x00001]; /* force VLAN */
319  pseudo_bit_t fsip[0x00001]; /* force source IP */
320  pseudo_bit_t fsm[0x00001]; /* force source MAC */
323 /* -------------- */
327  pseudo_bit_t counter_index[0x00008];/* Index to a table of counters that counts egress packets and bytes, 0xFF not valid */
328 /* -------------- */
330 /* -------------- */
331 };
332 
333 /* HCA Command Register (HCR) #### michal - match PRM */
334 
335 struct hermonprm_hca_command_register_st { /* Little Endian */
336  pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */
337 /* -------------- */
338  pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */
339 /* -------------- */
340  pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */
341 /* -------------- */
342  pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */
343 /* -------------- */
344  pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */
345 /* -------------- */
347  pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */
348 /* -------------- */
349  pseudo_bit_t opcode[0x0000c]; /* Command opcode */
350  pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */
352  pseudo_bit_t t[0x00001]; /* Toggle */
353  pseudo_bit_t e[0x00001]; /* Event Request
354  0 - Don't report event (software will poll the GO bit)
355  1 - Report event to EQ when the command completes */
356  pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR)
357  Software can write to the HCR only if Go bit is cleared.
358  Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */
359  pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared)
360  0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */
361 /* -------------- */
362 };
363 
364 /* CQ Doorbell */
365 
366 struct hermonprm_cq_cmd_doorbell_st { /* Little Endian */
367  pseudo_bit_t cqn[0x00018]; /* CQ number accessed */
368  pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ
369  0x0 - Reserved
370  0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter.
371  0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter.
372  0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated
373  Other - Reserved */
375  pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ.
376  This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited
377  completion or Request notification for multiple completions doorbells after receiving completion notification.
378  This field is initialized to Zero */
380 /* -------------- */
381  pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */
382 /* -------------- */
383 };
384 
385 /* RD-send doorbell */
386 
387 struct hermonprm_rd_send_doorbell_st { /* Little Endian */
389  pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram)
390  Must be zero for Nop and Bind operations */
391 /* -------------- */
393  pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */
394 /* -------------- */
395  struct hermonprm_send_doorbell_st send_doorbell;/* Send Parameters */
396 /* -------------- */
397 };
398 
399 /* Multicast Group Member QP #### michal - match PRM */
400 
401 struct hermonprm_mgmqp_st { /* Little Endian */
402  pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */
404  pseudo_bit_t blck_lb[0x00001]; /* Block self-loopback messages arriving to this qp */
405  pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */
406 /* -------------- */
407 };
408 
409 /* vsd */
410 
411 struct hermonprm_vsd_st { /* Little Endian */
413 /* -------------- */
415 /* -------------- */
417 /* -------------- */
419 /* -------------- */
421 /* -------------- */
423 /* -------------- */
425 /* -------------- */
427 /* -------------- */
429 /* -------------- */
431 /* -------------- */
433 /* -------------- */
435 /* -------------- */
437 /* -------------- */
439 /* -------------- */
441 /* -------------- */
443 /* -------------- */
445 /* -------------- */
447 /* -------------- */
449 /* -------------- */
451 /* -------------- */
453 /* -------------- */
455 /* -------------- */
457 /* -------------- */
459 /* -------------- */
461 /* -------------- */
463 /* -------------- */
465 /* -------------- */
467 /* -------------- */
469 /* -------------- */
471 /* -------------- */
473 /* -------------- */
475 /* -------------- */
477 /* -------------- */
479 /* -------------- */
481 /* -------------- */
483 /* -------------- */
485 /* -------------- */
487 /* -------------- */
489 /* -------------- */
491 /* -------------- */
493 /* -------------- */
495 /* -------------- */
497 /* -------------- */
499 /* -------------- */
501 /* -------------- */
503 /* -------------- */
505 /* -------------- */
507 /* -------------- */
509 /* -------------- */
511 /* -------------- */
513 /* -------------- */
515 /* -------------- */
517 /* -------------- */
519 /* -------------- */
521 /* -------------- */
523 /* -------------- */
524 };
525 
526 /* UAR Parameters */
527 
528 struct hermonprm_uar_params_st { /* Little Endian */
530 /* -------------- */
531  pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page.
532  Size of UAR Page is 4KB*2^UAR_Page_Size */
533  pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */
535 /* -------------- */
537 /* -------------- */
538 };
539 
540 /* Translation and Protection Tables Parameters */
541 
542 struct hermonprm_tptparams_st { /* Little Endian */
543  pseudo_bit_t dmpt_base_adr_h[0x00020];/* dMPT - Memory Protection Table base physical address [63:32].
544  Entry size is 64 bytes.
545  Table must be aligned to its size.
546  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
547 /* -------------- */
548  pseudo_bit_t dmpt_base_adr_l[0x00020];/* dMPT - Memory Protection Table base physical address [31:0].
549  Entry size is 64 bytes.
550  Table must be aligned to its size.
551  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
552 /* -------------- */
553  pseudo_bit_t log_dmpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the dMPT table. */
555  pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout -
556  The field returned in RNR Naks generated when a page fault is detected.
557  It has no effect when on-demand-paging is not used. */
559 /* -------------- */
561 /* -------------- */
562  pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32].
563  Table must be aligned to its size.
564  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
565 /* -------------- */
566  pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0].
567  Table must be aligned to its size.
568  Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */
569 /* -------------- */
570  pseudo_bit_t cmpt_base_adr_h[0x00020];/* cMPT - Memory Protection Table base physical address [63:32].
571  Entry size is 64 bytes.
572  Table must be aligned to its size. */
573 /* -------------- */
574  pseudo_bit_t cmpt_base_adr_l[0x00020];/* cMPT - Memory Protection Table base physical address [31:0].
575  Entry size is 64 bytes.
576  Table must be aligned to its size. */
577 /* -------------- */
578 };
579 
580 /* Multicast Support Parameters #### michal - match PRM */
581 
582 struct hermonprm_multicastparam_st { /* Little Endian */
583  pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32].
584  The base address must be aligned to the entry size.
585  Address may be set to 0xFFFFFFFF if multicast is not supported. */
586 /* -------------- */
587  pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0].
588  The base address must be aligned to the entry size.
589  Address may be set to 0xFFFFFFFF if multicast is not supported. */
590 /* -------------- */
592 /* -------------- */
593  pseudo_bit_t log_mc_table_entry_sz[0x00005];/* Log2 of the Size of multicast group member (MGM) entry.
594  Must be greater than 5 (to allow CTRL and GID sections).
595  That implies the number of QPs per MC table entry. */
598 /* -------------- */
599  pseudo_bit_t log_mc_table_hash_sz[0x00005];/* Number of entries in multicast DGID hash table (must be power of 2)
600  INIT_HCA - the required number of entries
601  QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */
603 /* -------------- */
604  pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */
606  pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function
607  0 - Default hash function
608  other - reserved */
611 /* -------------- */
613 /* -------------- */
614 };
615 
616 /* QPC/EEC/CQC/EQC/RDB Parameters #### michal - doesn't match PRM (field name are differs. see below) */
617 
618 struct hermonprm_qpcbaseaddr_st { /* Little Endian */
620 /* -------------- */
621  pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32]
622  Table must be aligned on its size */
623 /* -------------- */
624  pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */
625  pseudo_bit_t qpc_base_addr_l[0x0001b];/* QPC Base Address [31:7]
626  Table must be aligned on its size */
627 /* -------------- */
629 /* -------------- */
631 /* -------------- */
632  pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32]
633  Table must be aligned on its size
634  Address may be set to 0xFFFFFFFF if SRQ is not supported. */
635 /* -------------- */
636  pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */
637  pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5]
638  Table must be aligned on its size
639  Address may be set to 0xFFFFFFFF if SRQ is not supported. */
640 /* -------------- */
641  pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32]
642  Table must be aligned on its size */
643 /* -------------- */
644  pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */
645  pseudo_bit_t cqc_base_addr_l[0x0001b];/* CQC Base Address [31:6]
646  Table must be aligned on its size */
647 /* -------------- */
649 /* -------------- */
650  pseudo_bit_t altc_base_addr_h[0x00020];/* AltC Base Address (altc_base_addr_h) [63:32]
651  Table has same number of entries as QPC table.
652  Table must be aligned to entry size. */
653 /* -------------- */
654  pseudo_bit_t altc_base_addr_l[0x00020];/* AltC Base Address (altc_base_addr_l) [31:0]
655  Table has same number of entries as QPC table.
656  Table must be aligned to entry size. */
657 /* -------------- */
659 /* -------------- */
661 /* -------------- */
663 /* -------------- */
665 /* -------------- */
666  pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32]
667  Address may be set to 0xFFFFFFFF if EQs are not supported.
668  Table must be aligned to entry size. */
669 /* -------------- */
670  pseudo_bit_t log_num_of_eq[0x00005];/* Log base 2 of number of supported EQs.
671  Must be 6 or less in InfiniHost-III-EX. */
672  pseudo_bit_t eqc_base_addr_l[0x0001b];/* EQC Base Address [31:6]
673  Address may be set to 0xFFFFFFFF if EQs are not supported.
674  Table must be aligned to entry size. */
675 /* -------------- */
677 /* -------------- */
678  pseudo_bit_t rdmardc_base_addr_h[0x00020];/* rdmardc_base_addr_h: Base address of table that holds remote read and remote atomic requests [63:32]. */
679 /* -------------- */
680  pseudo_bit_t log_num_rd[0x00003]; /* Log (base 2) of the maximum number of RdmaRdC entries per QP. This denotes the maximum number of outstanding reads/atomics as a responder. */
682  pseudo_bit_t rdmardc_base_addr_l[0x0001b];/* rdmardc_base_addr_l: Base address of table that holds remote read and remote atomic requests [31:0].
683  Table must be aligned to RDB entry size (32 bytes). */
684 /* -------------- */
686 /* -------------- */
687 };
688 
689 /* Header_Log_Register */
690 
691 struct hermonprm_header_log_register_st { /* Little Endian */
693 /* -------------- */
695 /* -------------- */
696 };
697 
698 /* Performance Monitors */
699 
700 struct hermonprm_performance_monitors_st { /* Little Endian */
701  pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */
702  pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */
703  pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */
705  pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
706  pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
707  pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */
709  pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
710  pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
711  pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */
713  pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
714  pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
715  pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */
717  pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */
719  pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */
721 /* -------------- */
723 /* -------------- */
725 /* -------------- */
726  pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */
727 /* -------------- */
728 };
729 
730 /* MLX WQE segment format */
731 
732 struct hermonprm_wqe_segment_ctrl_mlx_st { /* Little Endian */
733  pseudo_bit_t opcode[0x00005]; /* must be 0xA = SEND */
735  pseudo_bit_t owner[0x00001];
736 /* -------------- */
737  pseudo_bit_t ds[0x00006]; /* Descriptor Size */
739 /* -------------- */
740  pseudo_bit_t fl[0x00001]; /* Force LoopBack */
742  pseudo_bit_t c[0x00002]; /* Create CQE (for "requested signalling" QP) */
743  pseudo_bit_t icrc[0x00001]; /* last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. 1 - Leave last dword as is. */
745  pseudo_bit_t sl[0x00004];
747  pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */
748  pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */
750 /* -------------- */
752  pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */
753 /* -------------- */
754 };
755 
756 /* Send WQE segment format */
757 
758 struct hermonprm_send_wqe_segment_st { /* Little Endian */
760 /* -------------- */
761  struct hermonprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */
762 /* -------------- */
763  struct hermonprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */
764 /* -------------- */
765  struct hermonprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */
766 /* -------------- */
768 /* -------------- */
769  struct hermonprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */
770 /* -------------- */
771  struct hermonprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */
772 /* -------------- */
774 /* -------------- */
776 /* -------------- */
777  struct hermonprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */
778 /* -------------- */
779  struct hermonprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */
780 /* -------------- */
782 /* -------------- */
783 };
784 
785 /* QP and EE Context Entry */
786 
787 struct hermonprm_queue_pair_ee_context_entry_st { /* Little Endian */
791  pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm)
792  11-Migrated
793  00-Armed
794  01-Rearm
795  10-Reserved
796  Should be set to 11 for UD QPs and for QPs which do not support APM */
798  pseudo_bit_t st[0x00004]; /* Transport Service Type: RC: 0, UC: 1, RD: 2, UD: 3, FCMND:4, FEXCH:5, SRC:6, MLX 7, Raw Eth 11 */
800  pseudo_bit_t state[0x00004]; /* QP/EE state:
801  0 - RST
802  1 - INIT
803  2 - RTR
804  3 - RTS
805  4 - SQEr
806  5 - SQD (Send Queue Drained)
807  6 - ERR
808  7 - Send Queue Draining
809  8 - Reserved
810  9 - Suspended
811  A- F - Reserved
812  (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */
813 /* -------------- */
814  pseudo_bit_t pd[0x00018];
816 /* -------------- */
818  pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */
820  pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes.
821  Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
822  pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */
824  pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes.
825  Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */
826  pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */
828  pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max.
829  Must be equal to MTU for UD and MLX QPs. */
830  pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative):
831  0x1 - 256 bytes
832  0x2 - 512
833  0x3 - 1024
834  0x4 - 2048
835  other - reserved
836 
837  Should be configured to 0x4 for UD and MLX QPs. */
838 /* -------------- */
839  pseudo_bit_t usr_page[0x00018]; /* UAR number to ring doorbells for this QP (aliased to doorbell and Blue Flame pages) */
841 /* -------------- */
842  pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained
843  This field is valid for QUERY and ERR2RST commands only. */
845 /* -------------- */
846  pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */
848 /* -------------- */
849  struct hermonprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */
850 /* -------------- */
851  struct hermonprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */
852 /* -------------- */
856  pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only).
857  The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */
858  pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only).
859  The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */
860  pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */
863  pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */
865  pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */
867  pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */
868 /* -------------- */
870 /* -------------- */
871  pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */
873 /* -------------- */
874  pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */
876 /* -------------- */
878 /* -------------- */
879  pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */
881 /* -------------- */
882  pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */
884 /* -------------- */
886  pseudo_bit_t ric[0x00001]; /* Invalid Credits.
887  1 - place "Invalid Credits" to ACKs sent from this queue.
888  0 - ACKs report the actual number of end to end credits on the connection.
889  Not valid (reserved) in EE context.
890  Must be set to 1 on QPs which are attached to SRQ. */
892  pseudo_bit_t page_offset[0x00006]; /* start address of wqes in first page (11:6), bits [5:0] reserved */
894  pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */
895  pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */
896  pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */
898  pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max.
899  Must be 0 for EE context. */
901 /* -------------- */
902  pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */
903  pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8).
904  Not valid (reserved) in EE context. */
906 /* -------------- */
907  pseudo_bit_t srcd[0x00010]; /* Scalable Reliable Connection Domain. Valid for SRC transport service */
909 /* -------------- */
910  pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */
912 /* -------------- */
913  pseudo_bit_t db_record_addr_h[0x00020];/* QP DB Record physical address */
914 /* -------------- */
916  pseudo_bit_t db_record_addr_l[0x0001e];/* QP DB Record physical address */
917 /* -------------- */
918  pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams.
919  On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message.
920  Not valid (reserved) in EE context. */
921 /* -------------- */
922  pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors.
923  SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */
924  pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */
926 /* -------------- */
927  pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */
929 /* -------------- */
930  pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ.
931  Must be 0x0 in SQ initialization.
932  (QUERY_QPEE only). */
933  pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ.
934  Must be 0x0 in RQ initialization.
935  (QUERY_QPEE only). */
936 /* -------------- */
938 /* -------------- */
939  pseudo_bit_t rmc_parent_qpn[0x00018];/* reliable multicast parent queue number */
940  pseudo_bit_t hs[0x00001]; /* Header Separation. If set, the byte count of the first scatter entry will be ignored. The buffer specified by the first scatter entry will contain packet headers (up to TCP). CQE will report number of bytes scattered to the first scatter entry. Intended for use on IPoverIB on UD QP or Raw Ethernet QP. */
941  pseudo_bit_t is[0x00001]; /* when set - inline scatter is enabled for this RQ */
943  pseudo_bit_t rme[0x00002]; /* Reliable Multicast
944  00 - disabled
945  01 - parent QP (requester)
946  10 - child QP (requester)
947  11 - responder QP
948  Note that Reliable Multicast is a preliminary definition which can be subject to change. */
950  pseudo_bit_t mkey_rmp[0x00001]; /* If set, MKey used to access TPT for incoming RDMA-write request is calculated by adding MKey from the packet to base_MKey field in the QPC. Can be set only for QPs that are not target for RDMA-read request. */
951 /* -------------- */
952  pseudo_bit_t base_mkey[0x00018]; /* Base Mkey bits [31:8]. Lower 8 bits must be zero. */
953  pseudo_bit_t num_rmc_peers[0x00008];/* Number of remote peers in Reliable Multicast group */
954 /* -------------- */
955  pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */
957  pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
959 /* -------------- */
961  pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */
962 /* -------------- */
964  pseudo_bit_t vft_prio[0x00003]; /* The Priority filed in the VFT header for FCP */
966  pseudo_bit_t cs_ctl[0x00009]; /* The Priority filed in the VFT header for FCP */
968  pseudo_bit_t ve[0x00001]; /* Should we add/check the VFT header */
969 /* -------------- */
970  pseudo_bit_t exch_base[0x00010]; /* For init QP only - The base exchanges */
972  pseudo_bit_t exch_size[0x00004]; /* For CMMD QP only - The size (from base) exchanges is 2exchanges_size */
974  pseudo_bit_t fc[0x00001]; /* When set it mean that this QP is used for FIBRE CHANNEL. */
975 /* -------------- */
976  pseudo_bit_t remote_id[0x00018]; /* Peer NX port ID */
978 /* -------------- */
979  pseudo_bit_t fcp_mtu[0x0000a]; /* In 4*Bytes units. The MTU Size */
981  pseudo_bit_t my_id_indx[0x00008]; /* Index to My NX port ID table */
982  pseudo_bit_t vft_hop_count[0x00008];/* HopCnt value for the VFT header */
983 /* -------------- */
985 /* -------------- */
986 };
987 
988 /* */
989 
990 struct hermonprm_mcg_qp_dw_st { /* Little Endian */
991  pseudo_bit_t qpn[0x00018];
995 /* -------------- */
996 };
997 
998 /* Clear Interrupt [63:0] #### michal - match to PRM */
999 
1000 struct hermonprm_clr_int_st { /* Little Endian */
1001  pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32]
1002  Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1003  This register is write-only. Reading from this register will cause undefined result
1004  */
1005 /* -------------- */
1006  pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0]
1007  Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot.
1008  This register is write-only. Reading from this register will cause undefined result */
1009 /* -------------- */
1010 };
1011 
1012 /* EQ Set CI DBs Table */
1013 
1014 struct hermonprm_eq_set_ci_table_st { /* Little Endian */
1015  pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */
1016 /* -------------- */
1018 /* -------------- */
1019  pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */
1020 /* -------------- */
1022 /* -------------- */
1023  pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */
1024 /* -------------- */
1026 /* -------------- */
1027  pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */
1028 /* -------------- */
1030 /* -------------- */
1031  pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */
1032 /* -------------- */
1034 /* -------------- */
1035  pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */
1036 /* -------------- */
1038 /* -------------- */
1039  pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */
1040 /* -------------- */
1042 /* -------------- */
1043  pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */
1044 /* -------------- */
1046 /* -------------- */
1047  pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */
1048 /* -------------- */
1050 /* -------------- */
1051  pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */
1052 /* -------------- */
1054 /* -------------- */
1055  pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */
1056 /* -------------- */
1058 /* -------------- */
1059  pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */
1060 /* -------------- */
1062 /* -------------- */
1063  pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */
1064 /* -------------- */
1066 /* -------------- */
1067  pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */
1068 /* -------------- */
1070 /* -------------- */
1071  pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */
1072 /* -------------- */
1074 /* -------------- */
1075  pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */
1076 /* -------------- */
1078 /* -------------- */
1079  pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */
1080 /* -------------- */
1082 /* -------------- */
1083  pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */
1084 /* -------------- */
1086 /* -------------- */
1087  pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */
1088 /* -------------- */
1090 /* -------------- */
1091  pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */
1092 /* -------------- */
1094 /* -------------- */
1095  pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */
1096 /* -------------- */
1098 /* -------------- */
1099  pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */
1100 /* -------------- */
1102 /* -------------- */
1103  pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */
1104 /* -------------- */
1106 /* -------------- */
1107  pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */
1108 /* -------------- */
1110 /* -------------- */
1111  pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */
1112 /* -------------- */
1114 /* -------------- */
1115  pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */
1116 /* -------------- */
1118 /* -------------- */
1119  pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */
1120 /* -------------- */
1122 /* -------------- */
1123  pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */
1124 /* -------------- */
1126 /* -------------- */
1127  pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */
1128 /* -------------- */
1130 /* -------------- */
1131  pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */
1132 /* -------------- */
1134 /* -------------- */
1135  pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */
1136 /* -------------- */
1138 /* -------------- */
1139  pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */
1140 /* -------------- */
1142 /* -------------- */
1143  pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */
1144 /* -------------- */
1146 /* -------------- */
1147  pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */
1148 /* -------------- */
1150 /* -------------- */
1151  pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */
1152 /* -------------- */
1154 /* -------------- */
1155  pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */
1156 /* -------------- */
1158 /* -------------- */
1159  pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */
1160 /* -------------- */
1162 /* -------------- */
1163  pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */
1164 /* -------------- */
1166 /* -------------- */
1167  pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */
1168 /* -------------- */
1170 /* -------------- */
1171  pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */
1172 /* -------------- */
1174 /* -------------- */
1175  pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */
1176 /* -------------- */
1178 /* -------------- */
1179  pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */
1180 /* -------------- */
1182 /* -------------- */
1183  pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */
1184 /* -------------- */
1186 /* -------------- */
1187  pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */
1188 /* -------------- */
1190 /* -------------- */
1191  pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */
1192 /* -------------- */
1194 /* -------------- */
1195  pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */
1196 /* -------------- */
1198 /* -------------- */
1199  pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */
1200 /* -------------- */
1202 /* -------------- */
1203  pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */
1204 /* -------------- */
1206 /* -------------- */
1207  pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */
1208 /* -------------- */
1210 /* -------------- */
1211  pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */
1212 /* -------------- */
1214 /* -------------- */
1215  pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */
1216 /* -------------- */
1218 /* -------------- */
1219  pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */
1220 /* -------------- */
1222 /* -------------- */
1223  pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */
1224 /* -------------- */
1226 /* -------------- */
1227  pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */
1228 /* -------------- */
1230 /* -------------- */
1231  pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */
1232 /* -------------- */
1234 /* -------------- */
1235  pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */
1236 /* -------------- */
1238 /* -------------- */
1239  pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */
1240 /* -------------- */
1242 /* -------------- */
1243  pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */
1244 /* -------------- */
1246 /* -------------- */
1247  pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */
1248 /* -------------- */
1250 /* -------------- */
1251  pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */
1252 /* -------------- */
1254 /* -------------- */
1255  pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */
1256 /* -------------- */
1258 /* -------------- */
1259  pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */
1260 /* -------------- */
1262 /* -------------- */
1263  pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */
1264 /* -------------- */
1266 /* -------------- */
1267  pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */
1268 /* -------------- */
1270 /* -------------- */
1271 };
1272 
1273 /* InfiniHost-III-EX Configuration Registers #### michal - match to PRM */
1274 
1275 struct hermonprm_configuration_registers_st { /* Little Endian */
1277 /* -------------- */
1279 /* -------------- */
1281 /* -------------- */
1282 };
1283 
1284 /* QP_DB_Record ### michal = gdror fixed */
1285 
1286 struct hermonprm_qp_db_record_st { /* Little Endian */
1287  pseudo_bit_t receive_wqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */
1289 /* -------------- */
1290 };
1291 
1292 /* CQ_ARM_DB_Record */
1293 
1294 struct hermonprm_cq_arm_db_record_st { /* Little Endian */
1295  pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */
1296 /* -------------- */
1297  pseudo_bit_t cmd[0x00003]; /* 0x0 - No command
1298  0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter.
1299  0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter.
1300  0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated
1301  Other - Reserved */
1302  pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */
1303  pseudo_bit_t res[0x00003]; /* Must be 0x2 */
1304  pseudo_bit_t cq_number[0x00018]; /* CQ number */
1305 /* -------------- */
1306 };
1307 
1308 /* CQ_CI_DB_Record */
1309 
1310 struct hermonprm_cq_ci_db_record_st { /* Little Endian */
1311  pseudo_bit_t counter[0x00020]; /* CQ counter */
1312 /* -------------- */
1314  pseudo_bit_t res[0x00003]; /* Must be 0x1 */
1315  pseudo_bit_t cq_number[0x00018]; /* CQ number */
1316 /* -------------- */
1317 };
1318 
1319 /* Virtual_Physical_Mapping */
1320 
1321 struct hermonprm_virtual_physical_mapping_st { /* Little Endian */
1322  pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */
1323 /* -------------- */
1325  pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */
1326 /* -------------- */
1327  pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */
1328 /* -------------- */
1329  pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */
1331  pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */
1332 /* -------------- */
1333 };
1334 
1335 /* MOD_STAT_CFG #### michal - gdror fix */
1336 
1337 struct hermonprm_mod_stat_cfg_st { /* Little Endian */
1341  pseudo_bit_t dife[0x00001];
1343  pseudo_bit_t rx_options[0x00004]; /* number of RX options to sweep when doing SerDes parameters AutoNegotiation. */
1345  pseudo_bit_t rx_options_m[0x00001]; /* Modify rx_options */
1346  pseudo_bit_t tx_options[0x00004]; /* number of TX options to sweep when doing SerDes parameters AutoNegotiation. */
1348  pseudo_bit_t tx_options_m[0x00001]; /* Modify tx_options */
1349 /* -------------- */
1357 /* -------------- */
1359 /* -------------- */
1360  pseudo_bit_t lid[0x00010]; /* default LID */
1361  pseudo_bit_t lid_m[0x00001]; /* Modify default LID */
1363  pseudo_bit_t port_en[0x00001]; /* enable port (E_Key) */
1364  pseudo_bit_t port_en_m[0x00001]; /* Modify port_en */
1370 /* -------------- */
1372  pseudo_bit_t guid_hi_m[0x00001]; /* Modify guid_hi */
1373 /* -------------- */
1375 /* -------------- */
1377  pseudo_bit_t guid_lo_m[0x00001]; /* Modify guid_lo */
1378 /* -------------- */
1380 /* -------------- */
1383 /* -------------- */
1385 /* -------------- */
1388 /* -------------- */
1390 /* -------------- */
1400 /* -------------- */
1413 /* -------------- */
1415 /* -------------- */
1422 /* -------------- */
1425 /* -------------- */
1427 /* -------------- */
1431 /* -------------- */
1434 /* -------------- */
1437 /* -------------- */
1439 /* -------------- */
1443 /* -------------- */
1445 /* -------------- */
1449 /* -------------- */
1451 /* -------------- */
1459 /* -------------- */
1461 /* -------------- */
1464 /* -------------- */
1467 /* -------------- */
1470 /* -------------- */
1472 };
1473 
1474 /* SRQ Context */
1475 
1476 struct hermonprm_srq_context_st { /* Little Endian */
1477  pseudo_bit_t srqn[0x00018]; /* SRQ number */
1478  pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue.
1479  Maximum value is 0x10, i.e. 16M WQEs. */
1480  pseudo_bit_t state[0x00004]; /* SRQ State:
1481  1111 - SW Ownership
1482  0000 - HW Ownership
1483  0001 - Error
1484  Valid only on QUERY_SRQ and HW2SW_SRQ commands. */
1485 /* -------------- */
1486  pseudo_bit_t src_domain[0x00010]; /* The Scalable RC Domain. Messages coming to receive ports specifying this SRQ as receive queue will be served only if SRC_Domain of the SRQ matches SRC_Domain of the transport QP of this message. */
1488  pseudo_bit_t log_srq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */
1490 /* -------------- */
1491  pseudo_bit_t cqn[0x00018]; /* Completion Queue to report SRC messages directed to this SRQ. */
1492  pseudo_bit_t page_offset[0x00006]; /* The offset of the first WQE from the beginning of 4Kbyte page (Figure 52,“Work Queue Buffer Structure”) */
1494 /* -------------- */
1496 /* -------------- */
1497  pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */
1499  pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
1501 /* -------------- */
1503  pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */
1504 /* -------------- */
1505  pseudo_bit_t pd[0x00018]; /* SRQ protection domain */
1507 /* -------------- */
1508  pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */
1509  pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then an SRQ limit event is fired and the LWM is set to zero. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */
1510 /* -------------- */
1511  pseudo_bit_t srq_wqe_counter[0x00010];/* A 16-bit counter incremented for each WQE posted to the SRQ. Must be 0x0 in SRQ initialization. Valid only upon the QUERY_SRQ command. */
1513 /* -------------- */
1515 /* -------------- */
1516  pseudo_bit_t db_record_addr_h[0x00020];/* SRQ DB Record physical address [63:32] */
1517 /* -------------- */
1519  pseudo_bit_t db_record_addr_l[0x0001e];/* SRQ DB Record physical address [31:2] */
1520 /* -------------- */
1521 };
1522 
1523 /* PBL */
1524 
1525 struct hermonprm_pbl_st { /* Little Endian */
1526  pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */
1527 /* -------------- */
1528  pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */
1529 /* -------------- */
1530  pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */
1531 /* -------------- */
1532  pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */
1533 /* -------------- */
1534  pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */
1535 /* -------------- */
1536  pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */
1537 /* -------------- */
1538  pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */
1539 /* -------------- */
1540  pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */
1541 /* -------------- */
1542 };
1543 
1544 /* Performance Counters #### michal - gdror fixed */
1545 
1546 struct hermonprm_performance_counters_st { /* Little Endian */
1548 /* -------------- */
1550 /* -------------- */
1552 /* -------------- */
1554 /* -------------- */
1556 /* -------------- */
1557 };
1558 
1559 /* Transport and CI Error Counters */
1560 
1562  pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */
1563 /* -------------- */
1564  pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */
1565 /* -------------- */
1566  pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */
1567 /* -------------- */
1568  pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */
1569 /* -------------- */
1570  pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */
1571 /* -------------- */
1572  pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */
1573 /* -------------- */
1574  pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */
1575 /* -------------- */
1576  pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */
1577 /* -------------- */
1578  pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error.
1579  Incremented each time a CQE with error is generated */
1580 /* -------------- */
1581  pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error.
1582  Incremented each time a CQE with error is generated */
1583 /* -------------- */
1585 /* -------------- */
1586  pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */
1587 /* -------------- */
1589 /* -------------- */
1590  pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */
1591 /* -------------- */
1592  pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */
1593 /* -------------- */
1595 /* -------------- */
1596  pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors
1597  NAK-Invalid Request on:
1598  1. Unsupported OpCode: Responder detected an unsupported OpCode.
1599  2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such
1600  as a missing "Last" packet.
1601  Note: there is no PSN error, thus this does not indicate a dropped packet. */
1602 /* -------------- */
1603  pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors.
1604  NAK may or may not be sent.
1605  1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only):
1606  Inbound request OpCode was either reserved, or was for a function not supported by this
1607  QP. (E.g. RDMA or ATOMIC on QP not set up for this).
1608  2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion.
1609  3. Too many RDMA READ or ATOMIC Requests: There were more requests received
1610  and not ACKed than allowed for the connection.
1611  4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder
1612  detected an error in the sequence of OpCodes; a missing "Last" packet
1613  5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder
1614  detected an error in the sequence of OpCodes; a missing "First" packet
1615  6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able
1616  buffer space.
1617  7. Length error: RDMA WRITE request message contained too much or too little pay-load
1618  data compared to the DMA length advertised in the first or only packet.
1619  8. Length error: Payload length was not consistent with the opcode:
1620  a: 0 byte <= "only" <= PMTU bytes
1621  b: ("first" or "middle") == PMTU bytes
1622  c: 1byte <= "last" <= PMTU bytes
1623  9. Length error: Inbound message exceeded the size supported by the CA port. */
1624 /* -------------- */
1625  pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors.
1626  NAK-Remote Access Error on:
1627  R_Key Violation: Responder detected an invalid R_Key while executing an RDMA
1628  Request. */
1629 /* -------------- */
1630  pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors.
1631  R_Key Violation Responder detected an R_Key violation while executing an RDMA
1632  request.
1633  NAK may or may not be sent. */
1634 /* -------------- */
1635  pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors.
1636  NAK-Remote Operation Error on:
1637  Remote Operation Error: Responder encountered an error, (local to the responder),
1638  which prevented it from completing the request. */
1639 /* -------------- */
1640  pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors.
1641  NAK-Remote Operation Error on:
1642  1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing
1643  the packet.
1644  2. Remote Operation Error: Responder encountered an error, (local to the responder),
1645  which prevented it from completing the request. */
1646 /* -------------- */
1647  pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */
1648 /* -------------- */
1650 /* -------------- */
1651  pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */
1652 /* -------------- */
1653  pseudo_bit_t rq_num_rnr[0x00020]; /* Responder - the number of RNR Naks sent */
1654 /* -------------- */
1655  pseudo_bit_t sq_num_rnr[0x00020]; /* Requester - the number of RNR Naks received */
1656 /* -------------- */
1658 /* -------------- */
1660 /* -------------- */
1661  pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */
1662 /* -------------- */
1664 /* -------------- */
1665  pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */
1666 /* -------------- */
1668 /* -------------- */
1669  pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */
1670 /* -------------- */
1672 /* -------------- */
1673  pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */
1674 /* -------------- */
1675  pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */
1676 /* -------------- */
1677  pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */
1678 /* -------------- */
1680 /* -------------- */
1681  pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */
1682 /* -------------- */
1683  pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */
1684 /* -------------- */
1685  pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */
1686 /* -------------- */
1688 /* -------------- */
1689  pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */
1690 /* -------------- */
1692 /* -------------- */
1693  pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */
1694 /* -------------- */
1695  pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */
1696 /* -------------- */
1697  pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */
1698 /* -------------- */
1700 /* -------------- */
1701 };
1702 
1703 /* Event_data Field - HCR Completion Event #### michal - match PRM */
1704 
1705 struct hermonprm_hcr_completion_event_st { /* Little Endian */
1706  pseudo_bit_t token[0x00010]; /* HCR Token */
1708 /* -------------- */
1710 /* -------------- */
1711  pseudo_bit_t status[0x00008]; /* HCR Status */
1713 /* -------------- */
1714  pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */
1715 /* -------------- */
1716  pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */
1717 /* -------------- */
1719 /* -------------- */
1720 };
1721 
1722 /* Completion with Error CQE #### michal - gdror fixed */
1723 
1724 struct hermonprm_completion_with_error_st { /* Little Endian */
1725  pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */
1727 /* -------------- */
1729 /* -------------- */
1730  pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome:
1731  0x01 - Local Length Error
1732  0x02 - Local QP Operation Error
1733  0x03 - Local EE Context Operation Error
1734  0x04 - Local Protection Error
1735  0x05 - Work Request Flushed Error
1736  0x06 - Memory Window Bind Error
1737  0x10 - Bad Response Error
1738  0x11 - Local Access Error
1739  0x12 - Remote Invalid Request Error
1740  0x13 - Remote Access Error
1741  0x14 - Remote Operation Error
1742  0x15 - Transport Retry Counter Exceeded
1743  0x16 - RNR Retry Counter Exceeded
1744  0x20 - Local RDD Violation Error
1745  0x21 - Remote Invalid RD Request
1746  0x22 - Remote Aborted Error
1747  0x23 - Invalid EE Context Number
1748  0x24 - Invalid EE Context State
1749  other - Reserved
1750  Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */
1753 /* -------------- */
1754  pseudo_bit_t opcode[0x00005]; /* The opcode of WQE completion is reported for.
1755 
1756  The following values are reported in case of completion with error:
1757  0xFE - For completion with error on Receive Queues
1758  0xFF - For completion with error on Send Queues */
1760  pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */
1761  pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */
1763 /* -------------- */
1764 };
1765 
1766 /* Resize CQ Input Mailbox */
1767 
1768 struct hermonprm_resize_cq_st { /* Little Endian */
1770 /* -------------- */
1774 /* -------------- */
1776  pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */
1778 /* -------------- */
1780 /* -------------- */
1785 /* -------------- */
1788 /* -------------- */
1790 /* -------------- */
1792 /* -------------- */
1793 };
1794 
1795 /* MAD_IFC Input Modifier */
1796 
1797 struct hermonprm_mad_ifc_input_modifier_st { /* Little Endian */
1798  pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */
1799  pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set.
1800  Required for trap generation when BKey check is enabled and for global routed packets. */
1802  pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD.
1803  This field is required for trap generation upon MKey/BKey validation. */
1804 /* -------------- */
1805 };
1806 
1807 /* MAD_IFC Input Mailbox ###michal -gdror fixed */
1808 
1809 struct hermonprm_mad_ifc_st { /* Little Endian */
1810  pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */
1811 /* -------------- */
1812  pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD.
1813  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1815 /* -------------- */
1817 /* -------------- */
1818  pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD.
1819  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1821 /* -------------- */
1823  pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD.
1824  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1825  pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid.
1826  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1828  pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD.
1829  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1830 /* -------------- */
1831  pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD.
1832  This field is reserved if Mad_extended_info indication in the input modifier is clear. */
1834 /* -------------- */
1836 /* -------------- */
1837  pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list.
1838  Valid if Mad_extended_info bit (in the input modifier) and g bit are set.
1839  Otherwise this field is reserved. */
1840 /* -------------- */
1842 /* -------------- */
1843 };
1844 
1845 /* Query Debug Message #### michal - gdror fixed */
1846 
1847 struct hermonprm_query_debug_msg_st { /* Little Endian */
1848  pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */
1849 /* -------------- */
1850  pseudo_bit_t v[0x00001]; /* Physical translation is valid */
1852  pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */
1853 /* -------------- */
1854  pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */
1855 /* -------------- */
1856  pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */
1857 /* -------------- */
1858  pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */
1859 /* -------------- */
1860  pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */
1861 /* -------------- */
1863 /* -------------- */
1864  pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */
1865 /* -------------- */
1866  pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */
1867 /* -------------- */
1869 /* -------------- */
1870  pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */
1871 /* -------------- */
1872  pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */
1873 /* -------------- */
1874  pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */
1875 /* -------------- */
1876  pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */
1877 /* -------------- */
1878  pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */
1879 /* -------------- */
1880  pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */
1881 /* -------------- */
1882  pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */
1883 /* -------------- */
1884  pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */
1885 /* -------------- */
1886  pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */
1887 /* -------------- */
1888  pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */
1889 /* -------------- */
1890  pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */
1891 /* -------------- */
1892  pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */
1893 /* -------------- */
1895 /* -------------- */
1896  pseudo_bit_t hw_buff_addr[0x00020]; /* Dror Mux Bohrer tracer */
1897 /* -------------- */
1899 /* -------------- */
1901 /* -------------- */
1902 };
1903 
1904 /* User Access Region */
1905 
1906 struct hermonprm_uar_st { /* Little Endian */
1907  struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */
1908 /* -------------- */
1909  struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */
1910 /* -------------- */
1912 /* -------------- */
1914 /* -------------- */
1916 /* -------------- */
1917 };
1918 
1919 /* Receive doorbell */
1920 
1921 struct hermonprm_receive_doorbell_st { /* Little Endian */
1923  pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */
1925 /* -------------- */
1927  pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */
1929  pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */
1930 /* -------------- */
1931 };
1932 
1933 /* SET_IB Parameters */
1934 
1935 struct hermonprm_set_ib_st { /* Little Endian */
1936  pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */
1938  pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
1939  system_image_guid and sig must be the same for all ports. */
1941 /* -------------- */
1942  pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */
1943 /* -------------- */
1944  pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
1945  Must be the same for both ports. */
1946 /* -------------- */
1947  pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
1948  Must be the same for both ports. */
1949 /* -------------- */
1951 /* -------------- */
1952 };
1953 
1954 /* Multicast Group Member #### michal - gdror fixed */
1955 
1956 struct hermonprm_mgm_entry_st { /* Little Endian */
1958  pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number.
1959  The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables.
1960  next_gid_index=0 means end of the chain. */
1961 /* -------------- */
1963 /* -------------- */
1964  pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format.
1965  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1966 /* -------------- */
1967  pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format.
1968  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1969 /* -------------- */
1970  pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format.
1971  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1972 /* -------------- */
1973  pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format.
1974  Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */
1975 /* -------------- */
1976  struct hermonprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */
1977 /* -------------- */
1978  struct hermonprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */
1979 /* -------------- */
1980  struct hermonprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */
1981 /* -------------- */
1982  struct hermonprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */
1983 /* -------------- */
1984  struct hermonprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */
1985 /* -------------- */
1986  struct hermonprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */
1987 /* -------------- */
1988  struct hermonprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */
1989 /* -------------- */
1990  struct hermonprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */
1991 /* -------------- */
1992 };
1993 
1994 /* INIT_PORT Parameters #### michal - match PRM */
1995 
1996 struct hermonprm_init_port_st { /* Little Endian */
1998  pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15.
1999  Legal values are 1,2,4 and 8. */
2000  pseudo_bit_t port_width_cap[0x00004];/* IB Port Width
2001  1 - 1x
2002  3 - 1x, 4x
2003  11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208)
2004  else - Reserved */
2006  pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */
2007  pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified.
2008  node_guid and ng must be the same for all ports. */
2009  pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified.
2010  system_image_guid and sig must be the same for all ports. */
2012 /* -------------- */
2013  pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */
2014  pseudo_bit_t mtu[0x00010]; /* Maximum MTU Supported in bytes
2015  must be: 256, 512, 1024, 2048 or 4096
2016  For Eth port, can be any
2017  Field must not cross device capabilities as reported
2018  */
2019 /* -------------- */
2020  pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port.
2021  Must be the same for both ports. */
2023 /* -------------- */
2025 /* -------------- */
2026  pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */
2027 /* -------------- */
2028  pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */
2029 /* -------------- */
2030  pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set
2031  Must be the same for both ports. */
2032 /* -------------- */
2033  pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set
2034  Must be the same for both ports. */
2035 /* -------------- */
2036  pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set
2037  Must be the same for both ports. */
2038 /* -------------- */
2039  pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set
2040  Must be the same for both ports. */
2041 /* -------------- */
2043 /* -------------- */
2044 };
2045 
2046 /* Query Device Capablities #### michal - gdror fixed */
2047 
2048 struct hermonprm_query_dev_cap_st { /* Little Endian */
2050 /* -------------- */
2051  pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */
2053  pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use
2054  The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */
2056  pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */
2057  pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */
2058 /* -------------- */
2059  pseudo_bit_t log_max_scqs[0x00004]; /* log base 2 of number of supported schedule queues */
2066 /* -------------- */
2067  pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */
2069  pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use
2070  The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */
2072  pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */
2073  pseudo_bit_t num_rsvd_eqs[0x00008]; /* The number of EQs reserved for firmware use
2074  The reserved resources are numbered from 0 to num_rsvd_eqs-1
2075  If 0 - no resources are reserved. */
2076 /* -------------- */
2077  pseudo_bit_t log_max_eq[0x00004]; /* Log2 of the Maximum number of EQs */
2079  pseudo_bit_t log2_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use
2080  The reserved resources are numbered from 0 to num_rsvd_eqs-1
2081  If 0 - no resources are reserved. */
2083  pseudo_bit_t log_max_d_mpts[0x00006];/* Log (base 2) of the maximum number of data MPT entries (the number of Regions/Windows) */
2085  pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */
2086 /* -------------- */
2087  pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */
2089  pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use
2090  The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */
2092  pseudo_bit_t log_max_mrw_sz[0x00007];/* Log2 of the Maximum Size of Memory Region/Window. is it in PRM layout? */
2094  pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use
2095  The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1
2096  */
2097 /* -------------- */
2099 /* -------------- */
2100  pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */
2102  pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */
2104 /* -------------- */
2105  pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */
2107 /* -------------- */
2108  pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */
2110 /* -------------- */
2111  pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */
2113  pseudo_bit_t pci_pf_num[0x00008]; /* Number of supported physical functions */
2114  pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb.
2115  The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */
2116  pseudo_bit_t port_type[0x00004]; /* Hermon New. bit per port. bit0 is first port. value '1' is ehternet. '0' is IB */
2118  pseudo_bit_t w[0x00001]; /* Hermon New. 10GB eth support */
2119  pseudo_bit_t j[0x00001]; /* Hermon New. Jumbo frame support */
2121 /* -------------- */
2122  pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */
2124  pseudo_bit_t log_ethtype[0x00004]; /* Hermon New. log2 eth type table size */
2126  pseudo_bit_t log_drain_size[0x00008];/* Log (base 2) of minimum size of the NoDropVLDrain buffer, specified in 4Kpages units */
2127  pseudo_bit_t log_max_msg[0x00005]; /* Log (base 2) of the maximum message size supported by the device */
2129 /* -------------- */
2130  pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */
2132  pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported
2133  bit 0 - full bw
2134  bit 1 - 1/4 bw
2135  bit 2 - 1/8 bw
2136  bit 3 - 1/2 bw; */
2137 /* -------------- */
2143 
2144 /* -------------- */
2145  pseudo_bit_t rc[0x00001]; /* RC Transport supported */
2146  pseudo_bit_t uc[0x00001]; /* UC Transport Supported */
2147  pseudo_bit_t ud[0x00001]; /* UD Transport Supported */
2148  pseudo_bit_t src[0x00001]; /* SRC Transport Supported. Hermon New instead of RD. */
2149  pseudo_bit_t rcm[0x00001]; /* Reliable Multicast support. Hermon New instead of IPv6 Transport Supported */
2150  pseudo_bit_t fcoib[0x00001]; /* Hermon New */
2151  pseudo_bit_t srq[0x00001]; /* SRQ is supported
2152  */
2153  pseudo_bit_t checksum[0x00001]; /* IP over IB checksum is supported */
2154  pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */
2155  pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */
2156  pseudo_bit_t vmm[0x00001]; /* Hermon New */
2157  pseudo_bit_t fcoe[0x00001];
2158  pseudo_bit_t dpdp[0x00001]; /* Dual Port Different Protocols */
2161  pseudo_bit_t blh[0x00001];
2162  pseudo_bit_t mw[0x00001]; /* Memory windows supported */
2163  pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */
2164  pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */
2165  pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */
2166  pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */
2167  pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */
2169  pseudo_bit_t pg[0x00001]; /* Paging on demand supported */
2170  pseudo_bit_t r[0x00001]; /* Router mode supported */
2172 /* -------------- */
2173  pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2).
2174  For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */
2176  pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */
2178  pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use
2179  The reserved resources are numbered from 0 to num_reserved_uars-1
2180  Note that UAR number num_reserved_uars is always for the kernel. */
2181 /* -------------- */
2182  pseudo_bit_t log_max_bf_pages[0x00006];/* Maximum number of BlueFlame pages is 2^log_max_bf_pages */
2184  pseudo_bit_t log_max_bf_regs_per_page[0x00006];/* Maximum number of BlueFlame registers per page is 2^log_max_bf_regs_per_page. It may be that only the beginning of a page contains BlueFlame registers. */
2186  pseudo_bit_t log_bf_reg_size[0x00005];/* BlueFlame register size in bytes is 2^log_bf_reg_size */
2188  pseudo_bit_t bf[0x00001]; /* If set to "1" then BlueFlame may be used. */
2189 /* -------------- */
2190  pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */
2191  pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */
2193 /* -------------- */
2194  pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */
2195  pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */
2197 /* -------------- */
2199  pseudo_bit_t fexch_base_mpt_31_25[0x00007];/* Hermon New. FC mpt base mpt number */
2200  pseudo_bit_t fcp_ud_base_23_8[0x00010];/* Hermon New. FC ud QP base QPN */
2201  pseudo_bit_t fexch_base_qp_23_16[0x00008];/* Hermon New. FC Exchange QP base QPN */
2202 /* -------------- */
2204 /* -------------- */
2205  pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */
2206  pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT.
2207  The reserved resources are numbered from 0 to num_reserved_mcgs-1
2208  If 0 - no resources are reserved. */
2210  pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */
2212 /* -------------- */
2213  pseudo_bit_t log_max_srcds[0x00004];/* Log2 of the maximum number of SRC Domains */
2215  pseudo_bit_t num_rsvd_scrds[0x00004];/* The number of SRCDs reserved for firmware use
2216  The reserved resources are numbered from 0 to num_reserved_rdds-1.
2217  If 0 - no resources are reserved. */
2218  pseudo_bit_t log_max_pd[0x00005]; /* Log2 of the maximum number of PDs */
2220  pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use
2221  The reserved resources are numbered from 0 to num_reserved_pds-1
2222  If 0 - no resources are reserved. */
2223 /* -------------- */
2225 /* -------------- */
2226  pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device
2227  For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2228  pseudo_bit_t rdmardc_entry_sz[0x00010];/* RdmaRdC Entry Size for the device
2229  For the InfiniHost-III-EX MT25208 entry size is 256 bytes */
2230 /* -------------- */
2231  pseudo_bit_t altc_entry_sz[0x00010];/* Extended QPC entry size for the device
2232  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2233  pseudo_bit_t aux_entry_sz[0x00010]; /* Auxilary context entry size */
2234 /* -------------- */
2235  pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device
2236  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2237  pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device
2238  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2239 /* -------------- */
2240  pseudo_bit_t c_mpt_entry_sz[0x00010];/* cMPT entry size in Bytes for the device.
2241  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2242  pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device
2243  For the InfiniHost-III-EX MT25208 entry size is 32 bytes */
2244 /* -------------- */
2245  pseudo_bit_t d_mpt_entry_sz[0x00010];/* dMPT entry size in Bytes for the device.
2246  For the InfiniHost-III-EX MT25208 entry size is 64 bytes */
2247  pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device.
2248  For the InfiniHost-III-EX MT25208 entry size is 8 bytes */
2249 /* -------------- */
2250  pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */
2251  pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism:
2252  0 - Type 2A - QP Number Association; or
2253  1 - Type 2B - QP Number and PD Association. */
2254  pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */
2255  pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. */
2256  pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */
2257  pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */
2259 /* -------------- */
2260  pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */
2261 /* -------------- */
2263 /* -------------- */
2264  pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */
2265 /* -------------- */
2266  pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */
2267 /* -------------- */
2269 /* -------------- */
2270 };
2271 
2272 /* QUERY_ADAPTER Parameters Block #### michal - gdror fixed */
2273 
2274 struct hermonprm_query_adapter_st { /* Little Endian */
2276 /* -------------- */
2278  pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */
2279 /* -------------- */
2281 /* -------------- */
2282  struct hermonprm_vsd_st vsd; /* ###michal- this field was replaced by 2 fields : vsd .1664; vsd(continued/psid .128; */
2283 /* -------------- */
2284 };
2285 
2286 /* QUERY_FW Parameters Block #### michal - doesn't match PRM */
2287 
2288 struct hermonprm_query_fw_st { /* Little Endian */
2289  pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */
2290  pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */
2291 /* -------------- */
2292  pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */
2293  pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */
2294 /* -------------- */
2295  pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */
2297 /* -------------- */
2298  pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */
2300  pseudo_bit_t dt[0x00001]; /* Debug Trace Support
2301  0 - Debug trace is not supported
2302  1 - Debug trace is supported */
2303 /* -------------- */
2305  pseudo_bit_t ccq[0x00001]; /* CCQ support */
2307  pseudo_bit_t fw_seconds[0x00008]; /* FW timestamp - seconds. Dispalyed as Hexadecimal number */
2308  pseudo_bit_t fw_minutes[0x00008]; /* FW timestamp - minutes. Dispalyed as Hexadecimal number */
2309  pseudo_bit_t fw_hour[0x00008]; /* FW timestamp - hour. Dispalyed as Hexadecimal number */
2310 /* -------------- */
2311  pseudo_bit_t fw_day[0x00008]; /* FW timestamp - day. Dispalyed as Hexadecimal number */
2312  pseudo_bit_t fw_month[0x00008]; /* FW timestamp - month. Dispalyed as Hexadecimal number */
2313  pseudo_bit_t fw_year[0x00010]; /* FW timestamp - year. Dispalyed as Hexadecimal number (e.g. 0x2005) */
2314 /* -------------- */
2316 /* -------------- */
2317  pseudo_bit_t clr_int_base_offset_h[0x00020];/* Bits [63:32] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */
2318 /* -------------- */
2319  pseudo_bit_t clr_int_base_offset_l[0x00020];/* Bits [31:0] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */
2320 /* -------------- */
2322  pseudo_bit_t clr_int_bar[0x00002]; /* PCI base address register (BAR) where clr_int register is located.
2323  00 - BAR 0-1
2324  01 - BAR 2-3
2325  10 - BAR 4-5
2326  11 - Reserved
2327  The PCI BARs of ConnectX are 64 bit BARs.
2328  In ConnectX, clr_int register is located on BAR 0-1. */
2329 /* -------------- */
2331 /* -------------- */
2332  pseudo_bit_t error_buf_offset_h[0x00020];/* Read Only buffer for catastrophic error reports (bits [63:32] of offset from error_buf_bar register in PCI address space.) */
2333 /* -------------- */
2334  pseudo_bit_t error_buf_offset_l[0x00020];/* Read Only buffer for catastrophic error reports (bits [31:0] of offset from error_buf_bar register in PCI address space.) */
2335 /* -------------- */
2336  pseudo_bit_t error_buf_size[0x00020];/* Size in words */
2337 /* -------------- */
2339  pseudo_bit_t error_buf_bar[0x00002];/* PCI base address register (BAR) where error_buf register is located.
2340  00 - BAR 0-1
2341  01 - BAR 2-3
2342  10 - BAR 4-5
2343  11 - Reserved
2344  The PCI BARs of ConnectX are 64 bit BARs.
2345  In ConnectX, error_buf register is located on BAR 0-1. */
2346 /* -------------- */
2348 /* -------------- */
2349 };
2350 
2351 /* Memory Access Parameters for UD Address Vector Table */
2352 
2353 struct hermonprm_udavtable_memory_parameters_st { /* Little Endian */
2354  pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */
2355 /* -------------- */
2356  pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */
2358  pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */
2360 /* -------------- */
2361 };
2362 
2363 /* INIT_HCA & QUERY_HCA Parameters Block ####michal-doesn't match PRM (see differs below) new size in bytes:0x300 */
2364 
2365 struct hermonprm_init_hca_st { /* Little Endian */
2368 /* -------------- */
2370 /* -------------- */
2372  pseudo_bit_t hca_core_clock[0x00010];/* Internal Clock freq in MHz */
2373 /* -------------- */
2374  pseudo_bit_t router_qp[0x00018]; /* QP number for router mode (8 LSBits should be 0). Low order 8 bits are taken from the TClass field of the incoming packet.
2375  Valid only if RE bit is set */
2377  pseudo_bit_t ipr2[0x00001]; /* Hermon New. IP router on port 2 */
2378  pseudo_bit_t ipr1[0x00001]; /* Hermon New. IP router on port 1 */
2379  pseudo_bit_t ibr[0x00001]; /* InfiniBand Router Mode */
2380 /* -------------- */
2381  pseudo_bit_t udp[0x00001]; /* UD Port Check Enable
2382  0 - Port field in Address Vector is ignored
2383  1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */
2384  pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations
2385  0 - Host is Little Endian
2386  1 - Host is Big endian
2387  */
2389  pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */
2391 /* -------------- */
2393 /* -------------- */
2394  struct hermonprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;/* ## michal - this field has chenged to - "qpc_cqc_eqc_parameters" - gdror, this is ok for now */
2395 /* -------------- */
2397 /* -------------- */
2398  struct hermonprm_multicastparam_st multicast_parameters;/* ##michal- this field has chenged to - "IBUD/IPv6_multicast_parameters" - gdror - this is OK for now */
2399 /* -------------- */
2401 /* -------------- */
2403 /* -------------- */
2405 /* -------------- */
2406  struct hermonprm_uar_params_st uar_parameters;/* UAR Parameters */
2407 /* -------------- */
2409 /* -------------- */
2410 };
2411 
2412 /* Event Queue Context Table Entry #### michal - gdror fixed */
2413 
2414 struct hermonprm_eqc_st { /* Little Endian */
2416  pseudo_bit_t st[0x00004]; /* Event delivery state machine
2417  0x9 - Armed
2418  0xA - Fired
2419  0xB - Always_Armed (auto-rearm)
2420  other - reserved */
2422  pseudo_bit_t oi[0x00001]; /* Oerrun ignore.
2423  If set, HW will not check EQ full condition when writing new EQEs. */
2424  pseudo_bit_t ec[0x00001]; /* is set, all EQEs are written (coalesced) to first EQ entry */
2426  pseudo_bit_t status[0x00004]; /* EQ status:
2427  0000 - OK
2428  1010 - EQ write failure
2429  Valid for the QUERY_EQ and HW2SW_EQ commands only */
2430 /* -------------- */
2432 /* -------------- */
2434  pseudo_bit_t page_offset[0x00007]; /* offset bits[11:5] of first EQE in the EQ relative to the first page in memory region mapping this EQ */
2436 /* -------------- */
2438  pseudo_bit_t log_eq_size[0x00005]; /* Log (base 2) of the EQ size (in entries). Maximum EQ size is 2^22 EQEs (max log_eq_size is 22) */
2440 /* -------------- */
2441  pseudo_bit_t eq_max_count[0x00010]; /* Event Generation Moderation counter */
2442  pseudo_bit_t eq_period[0x00010]; /* Event Generation moderation timed, microseconds */
2443 /* -------------- */
2444  pseudo_bit_t intr[0x0000a]; /* MSI-X table entry index to be used to signal interrupts on this EQ. Reserved if MSI-X are not enabled in the PCI configuration header. */
2446 /* -------------- */
2447  pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] relative to INIT_HCA.mtt_base_addr */
2449  pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */
2451 /* -------------- */
2453  pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] relative to INIT_HCA.mtt_base_addr */
2454 /* -------------- */
2456 /* -------------- */
2457  pseudo_bit_t consumer_counter[0x00018];/* Consumer counter. The counter is incremented for each EQE polled from the EQ.
2458  Must be 0x0 in EQ initialization.
2459  Maintained by HW (valid for the QUERY_EQ command only). */
2461 /* -------------- */
2462  pseudo_bit_t producer_counter[0x00018];/* Producer Coutner. The counter is incremented for each EQE that is written by the HW to the EQ.
2463  EQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a EQE needs to be added.
2464  Maintained by HW (valid for the QUERY_EQ command only) */
2466 /* -------------- */
2468 /* -------------- */
2469 };
2470 
2471 /* Memory Translation Table (MTT) Entry #### michal - match to PRM */
2472 
2473 struct hermonprm_mtt_st { /* Little Endian */
2474  pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2475 /* -------------- */
2476  pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */
2478  pseudo_bit_t ptag_l[0x0001d]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */
2479 /* -------------- */
2480 };
2481 
2482 /* Memory Protection Table (MPT) Entry ### doesn't match PRM (new fields were added). new size in bytes : 0x54 */
2483 
2484 struct hermonprm_mpt_st { /* Little Endian */
2486  pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */
2487  pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation is performed for this region */
2488  pseudo_bit_t lr[0x00001]; /* If set - local read access is enabled. Must be set for all MPT Entries. */
2489  pseudo_bit_t lw[0x00001]; /* If set - local write access is enabled */
2490  pseudo_bit_t rr[0x00001]; /* If set - remote read access is enabled. */
2491  pseudo_bit_t rw[0x00001]; /* If set - remote write access is enabled */
2492  pseudo_bit_t atomic[0x00001]; /* If set - remote Atomic access is allowed. */
2493  pseudo_bit_t eb[0x00001]; /* If set - bind is enabled. Valid only for regions. */
2494  pseudo_bit_t atc_req[0x00001]; /* If set, second hop of address translation (PA to MA) to be performed in the device prior to issuing the uplink request. */
2495  pseudo_bit_t atc_xlated[0x00001]; /* If set, uplink cycle to be issues with “ATC_translated” indicator to force bypass of the chipset IOMMU. */
2497  pseudo_bit_t no_snoop[0x00001]; /* If set, issue PCIe cycle with Ă»no SnoopĂż attribute - cycle not to be snooped in CPU caches */
2499  pseudo_bit_t status[0x00004]; /* 0xF - Not Valid 0x3 - Free. else - HW ownership.Unbound Type1 windows are denoted by reg_wnd_len=0. Unbound Type II windows are denoted by Status = Free. */
2500 /* -------------- */
2502  pseudo_bit_t bqp[0x00001]; /* 0 - not bound to qp (type 1 window, MR)1 - bound to qp (type 2 window) */
2503  pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */
2504 /* -------------- */
2505  pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. */
2506 /* -------------- */
2507  pseudo_bit_t pd[0x00018]; /* Protection Domain. If VMM support is enabled PD[17:23] specify Guest VM Identifier */
2508  pseudo_bit_t en_rinv[0x00001]; /* Enable remote invalidation */
2509  pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. Must be set for type2 windows and non-shared physical memory regions. Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */
2510  pseudo_bit_t nce[0x00001]; /* Data can be cached in Network Cache (see Ă»Network CacheĂż on page 81) */
2511  pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */
2512  pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail */
2513  pseudo_bit_t w_dif[0x00001]; /* Wire space contains dif */
2514  pseudo_bit_t m_dif[0x00001]; /* Memory space contains dif */
2516 /* -------------- */
2517  pseudo_bit_t start_addr_h[0x00020]; /* Start Address - Virtual Address where this region/window starts */
2518 /* -------------- */
2519  pseudo_bit_t start_addr_l[0x00020]; /* Start Address - Virtual Address where this region/window starts */
2520 /* -------------- */
2521  pseudo_bit_t len_h[0x00020]; /* Region/Window Length */
2522 /* -------------- */
2523  pseudo_bit_t len_l[0x00020]; /* Region/Window Length */
2524 /* -------------- */
2525  pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */
2526 /* -------------- */
2527  pseudo_bit_t win_cnt[0x00018]; /* Number of windows bound to this region. Valid for regions only.The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */
2529 /* -------------- */
2530  pseudo_bit_t mtt_rep[0x00004]; /* Log (base 2) of the number of time an MTT is replicated.E.g. for 64KB virtual blocks from 512B blocks, a replication factor of 2^7 is needed (MTT_REPLICATION_FACTOR=7).Up to 1MB of replicated block works */
2532  pseudo_bit_t block_mode[0x00001]; /* If set, the page size is not power of two, and entity_size is in bytes. */
2533  pseudo_bit_t len64[0x00001]; /* Region/Window Length[64]. This bit added to enable registering 2^64 bytes per region */
2534  pseudo_bit_t fbo_en[0x00001]; /* If set, mtt_fbo field is valid, otherwise it is calculated from least significant bytes of the address. Must be set when mtt_rep is used or MPT is block-mode region */
2536 /* -------------- */
2537  pseudo_bit_t mtt_adr_h[0x00008]; /* Offset to MTT list for this region. Must be aligned on 8 bytes. */
2539 /* -------------- */
2540  pseudo_bit_t mtt_adr_l[0x00020]; /* Offset to MTT list for this region. Must be aligned on 8 bytes.###michal-relpaced with: RESERVED .3;mtt_adr_l .29; gdror - this is OK to leave it this way. */
2541 /* -------------- */
2542  pseudo_bit_t mtt_size[0x00020]; /* Number of MTT entries allocated for this MR.When Fast Registration Operations cannot be executed on this region (FRE bit is zero) this field is reserved.When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value cannot be zero. */
2543 /* -------------- */
2544  pseudo_bit_t entity_size[0x00015]; /* Page/block size. If MPT maps pages, the page size is 2entiry_size. If MPT maps blocks, the entity_size field specifies block size in bytes. The minimum amount of memory that can be mapped with single MTT is 512 bytes. */
2546 /* -------------- */
2547  pseudo_bit_t mtt_fbo[0x00015]; /* First byte offset in the zero-based region - the first byte within the first block/page start address refers to. When mtt_rep is being used, fbo points within the replicated block (i.e. block-size x 2^mtt_rep) */
2549 /* -------------- */
2550 };
2551 
2552 /* Completion Queue Context Table Entry #### michal - match PRM */
2553 
2554 struct hermonprm_completion_queue_context_st { /* Little Endian */
2556  pseudo_bit_t st[0x00004]; /* Event delivery state machine
2557  0x0 - reserved
2558  0x9 - ARMED (Request for Notification)
2559  0x6 - ARMED SOLICITED (Request Solicited Notification)
2560  0xA - FIRED
2561  other - reserved
2562 
2563  Must be 0x0 in CQ initialization.
2564  Valid for the QUERY_CQ and HW2SW_CQ commands only. */
2566  pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled.
2567  When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */
2568  pseudo_bit_t cc[0x00001]; /* is set, all CQEs are written (coalesced) to first CQ entry */
2570  pseudo_bit_t status[0x00004]; /* CQ status
2571  0000 - OK
2572  1001 - CQ overflow
2573  1010 - CQ write failure
2574  Valid for the QUERY_CQ and HW2SW_CQ commands only */
2575 /* -------------- */
2577 /* -------------- */
2579  pseudo_bit_t page_offset[0x00007]; /* offset of first CQE in the CQ relative to the first page in memory region mapping this CQ */
2581 /* -------------- */
2582  pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */
2583  pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries).
2584  Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */
2586 /* -------------- */
2587  pseudo_bit_t cq_max_count[0x00010]; /* Event Generation Moderation counter */
2588  pseudo_bit_t cq_period[0x00010]; /* Event Generation moderation timed, microseconds */
2589 /* -------------- */
2590  pseudo_bit_t c_eqn[0x00009]; /* Event Queue this CQ reports completion events to.
2591  Valid values are 0 to 63
2592  If configured to value other than 0-63, completion events will not be reported on the CQ. */
2594 /* -------------- */
2595  pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */
2599 /* -------------- */
2601  pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */
2602 /* -------------- */
2603  pseudo_bit_t last_notified_indx[0x00018];/* Maintained by HW.
2604  Valid for QUERY_CQ and HW2SW_CQ commands only. */
2606 /* -------------- */
2607  pseudo_bit_t solicit_producer_indx[0x00018];/* Maintained by HW.
2608  Valid for QUERY_CQ and HW2SW_CQ commands only.
2609  */
2611 /* -------------- */
2612  pseudo_bit_t consumer_counter[0x00018];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ.
2613  */
2615 /* -------------- */
2616  pseudo_bit_t producer_counter[0x00018];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ.
2617  CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added..
2618  Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */
2620 /* -------------- */
2622 /* -------------- */
2624 /* -------------- */
2625  pseudo_bit_t db_record_addr_h[0x00020];/* CQ DB Record physical address [63:32] */
2626 /* -------------- */
2628  pseudo_bit_t db_record_addr_l[0x0001d];/* CQ DB Record physical address [31:3] */
2629 /* -------------- */
2630 };
2631 
2632 /* GPIO_event_data #### michal - gdror fixed */
2633 
2634 struct hermonprm_gpio_event_data_st { /* Little Endian */
2636 /* -------------- */
2637  pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2638 /* -------------- */
2639  pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */
2640 /* -------------- */
2642 /* -------------- */
2643 };
2644 
2645 /* Event_data Field - QP/EE Events #### michal - doesn't match PRM */
2646 
2647 struct hermonprm_qp_ee_event_st { /* Little Endian */
2648  pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for ###michal - field changed to QP number */
2650 /* -------------- */
2652 /* -------------- */
2654  pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field
2655  Not valid on SRQ events ###michal - field replaced with RESERVED */
2657 /* -------------- */
2659 /* -------------- */
2660 };
2661 
2662 /* InfiniHost-III-EX Type0 Configuration Header ####michal - doesn't match PRM (new fields added, see below) */
2663 
2664 struct hermonprm_mt25208_type0_st { /* Little Endian */
2665  pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */
2666  pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode
2667  25408 (decimal) - InfiniHost-III EX mode (the mode described in this manual)
2668  25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode
2669  */
2670 /* -------------- */
2671  pseudo_bit_t command[0x00010]; /* PCI Command Register */
2672  pseudo_bit_t status[0x00010]; /* PCI Status Register */
2673 /* -------------- */
2676 /* -------------- */
2677  pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */
2679  pseudo_bit_t header_type[0x00008]; /* hardwired to zero */
2680  pseudo_bit_t bist[0x00008];
2681 /* -------------- */
2682  pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */
2684  pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */
2685 /* -------------- */
2686  pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */
2687 /* -------------- */
2688  pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */
2690  pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */
2691 /* -------------- */
2692  pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */
2693 /* -------------- */
2694  pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */
2696  pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2697 /* -------------- */
2698  pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */
2699 /* -------------- */
2701 /* -------------- */
2702  pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */
2703  pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */
2704 /* -------------- */
2705  pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2707  pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */
2708 /* -------------- */
2709  pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */
2711 /* -------------- */
2713 /* -------------- */
2718 /* -------------- */
2720 /* -------------- */
2728 /* -------------- */
2730 /* -------------- */
2732 /* -------------- */
2735 /* -------------- */
2737 /* -------------- */
2738  pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */
2740  pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h
2741  [3] PME clock - 0h
2742  [4] RsvP
2743  [5] Device specific initialization - 0h
2744  [8:6] AUX current - 0h
2745  [9] D1 support - 0h
2746  [10] D2 support - 0h
2747  [15:11] PME support - 0h */
2748 /* -------------- */
2749  pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */
2751  pseudo_bit_t data[0x00008];
2752 /* -------------- */
2754 /* -------------- */
2755  pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */
2758  pseudo_bit_t f[0x00001];
2759 /* -------------- */
2761 /* -------------- */
2763 /* -------------- */
2764  pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */
2766  pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h
2767  [7:4] Device/Port Type - 0h
2768  [8] Slot implemented - 0h
2769  [13:9] Interrupt message number
2770  */
2771 /* -------------- */
2772  pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h
2773  [4:3] Phantom Function supported - 0h
2774  [5] Extended Tag Filed supported - 0h
2775  [8:6] Endpoint L0s Acceptable Latency - TBD
2776  [11:9] Endpoint L1 Acceptable Latency - TBD
2777  [12] Attention Button Present - configured through InfiniBurn
2778  [13] Attention Indicator Present - configured through InfiniBurn
2779  [14] Power Indicator Present - configured through InfiniBurn
2780  [25:18] Captured Slot Power Limit Value
2781  [27:26] Captured Slot Power Limit Scale */
2782 /* -------------- */
2785 /* -------------- */
2786  pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h
2787  [9:4] Maximum Link Width - 8h
2788  [11:10] Active State Power Management Support - 3h
2789  [14:12] L0s Exit Latency - TBD
2790  [17:15] L1 Exit Latency - TBD
2791  [31:24] Port Number - 0h */
2792 /* -------------- */
2794  pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h
2795  [9:4] Negotiated Link Width
2796  [12] Slot clock configuration - 1h */
2797 /* -------------- */
2799 /* -------------- */
2803 /* -------------- */
2804  pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status
2805  4 Data Link Protocol Error Status
2806  12 Poisoned TLP Status
2807  13 Flow Control Protocol Error Status
2808  14 Completion Timeout Status
2809  15 Completer Abort Status
2810  16 Unexpected Completion Status
2811  17 Receiver Overflow Status
2812  18 Malformed TLP Status
2813  19 ECRC Error Status
2814  20 Unsupported Request Error Status */
2815 /* -------------- */
2816  pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask
2817  4 Data Link Protocol Error Mask
2818  12 Poisoned TLP Mask
2819  13 Flow Control Protocol Error Mask
2820  14 Completion Timeout Mask
2821  15 Completer Abort Mask
2822  16 Unexpected Completion Mask
2823  17 Receiver Overflow Mask
2824  18 Malformed TLP Mask
2825  19 ECRC Error Mask
2826  20 Unsupported Request Error Mask */
2827 /* -------------- */
2828  pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity
2829  4 Data Link Protocol Error Severity
2830  12 Poisoned TLP Severity
2831  13 Flow Control Protocol Error Severity
2832  14 Completion Timeout Severity
2833  15 Completer Abort Severity
2834  16 Unexpected Completion Severity
2835  17 Receiver Overflow Severity
2836  18 Malformed TLP Severity
2837  19 ECRC Error Severity
2838  20 Unsupported Request Error Severity */
2839 /* -------------- */
2840  pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status
2841  6 Bad TLP Status
2842  7 Bad DLLP Status
2843  8 REPLAY_NUM Rollover Status
2844  12 Replay Timer Timeout Status */
2845 /* -------------- */
2846  pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask
2847  6 Bad TLP Mask
2848  7 Bad DLLP Mask
2849  8 REPLAY_NUM Rollover Mask
2850  12 Replay Timer Timeout Mask */
2851 /* -------------- */
2853 /* -------------- */
2855 /* -------------- */
2857 /* -------------- */
2858 };
2859 
2860 /* Event Data Field - Performance Monitor */
2861 
2862 struct hermonprm_performance_monitor_event_st { /* Little Endian */
2863  struct hermonprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */
2864 /* -------------- */
2865  pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC
2866  0x02 - RQPC
2867  0x03 - CQC
2868  0x04 - Rkey
2869  0x05 - TLB
2870  0x06 - port0
2871  0x07 - port1 */
2873 /* -------------- */
2875 /* -------------- */
2876 };
2877 
2878 /* Event_data Field - Page Faults */
2879 
2880 struct hermonprm_page_fault_event_data_st { /* Little Endian */
2881  pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */
2882 /* -------------- */
2883  pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */
2884 /* -------------- */
2885  pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */
2886 /* -------------- */
2887  pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */
2889  pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */
2890  pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */
2891  pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */
2892  pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */
2893  pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */
2894 /* -------------- */
2895  pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */
2897 /* -------------- */
2898  pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */
2899 /* -------------- */
2900 };
2901 
2902 /* WQE segments format */
2903 
2904 struct hermonprm_wqe_segment_st { /* Little Endian */
2905  struct hermonprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */
2906 /* -------------- */
2908 /* -------------- */
2909  struct hermonprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */
2910 /* -------------- */
2912 /* -------------- */
2913  pseudo_bit_t recv_wqe_segment_ctrl[4][0x00020];/* Receive segment format */
2914 /* -------------- */
2916 /* -------------- */
2917 };
2918 
2919 /* Event_data Field - Port State Change #### michal - match PRM */
2920 
2921 struct hermonprm_port_state_change_st { /* Little Endian */
2923 /* -------------- */
2925  pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */
2927 /* -------------- */
2929 /* -------------- */
2930 };
2931 
2932 /* Event_data Field - Completion Queue Error #### michal - match PRM */
2933 
2934 struct hermonprm_completion_queue_error_st { /* Little Endian */
2935  pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
2937 /* -------------- */
2939 /* -------------- */
2940  pseudo_bit_t syndrome[0x00008]; /* Error syndrome
2941  0x01 - CQ overrun
2942  0x02 - CQ access violation error */
2944 /* -------------- */
2946 /* -------------- */
2947 };
2948 
2949 /* Event_data Field - Completion Event #### michal - match PRM */
2950 
2951 struct hermonprm_completion_event_st { /* Little Endian */
2952  pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */
2954 /* -------------- */
2956 /* -------------- */
2957 };
2958 
2959 /* Event Queue Entry #### michal - match to PRM */
2960 
2961 struct hermonprm_event_queue_entry_st { /* Little Endian */
2962  pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type.
2963  Defined for events which have sub types, zero elsewhere. */
2965  pseudo_bit_t event_type[0x00008]; /* Event Type */
2967 /* -------------- */
2968  pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */
2969 /* -------------- */
2971  pseudo_bit_t owner[0x00001]; /* Owner of the entry
2972  0 SW
2973  1 HW */
2975 /* -------------- */
2976 };
2977 
2978 /* QP/EE State Transitions Command Parameters ###michal - doesn't match PRM (field name changed) */
2979 
2980 struct hermonprm_qp_ee_state_transitions_st { /* Little Endian */
2981  pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */
2982 /* -------------- */
2984 /* -------------- */
2985  struct hermonprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data ###michal - field has replaced with "qpc_data" (size .1948) */
2986 /* -------------- */
2988 /* -------------- */
2989 };
2990 
2991 /* Completion Queue Entry Format #### michal - fixed by gdror */
2992 
2993 struct hermonprm_completion_queue_entry_st { /* Little Endian */
2994  pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */
2996  pseudo_bit_t d2s[0x00001]; /* Duplicate to Sniffer. This bit is set if both Send and Receive queues are subject for sniffer queue. The HW delivers
2997  packet only to send-associated sniffer receive queue. */
2998  pseudo_bit_t fcrc_sd[0x00001]; /* FCRC: If set, FC CRC is correct in FC frame encapsulated in payload. Valid for Raw Frame FC receive queue only.
2999  SD: CQ associated with Sniffer receive queue. If set, packets were skipped due to lack of receive buffers on the Sniffer receive queue */
3000  pseudo_bit_t fl[0x00001]; /* Force Loopback Valid for responder RawEth and UD only. */
3001  pseudo_bit_t vlan[0x00002]; /* Valid for RawEth and UD over Ethernet only. Applicable for RawEth and UD over Ethernet Receive queue
3002  00 - No VLAN header was present in the packet
3003  01 - C-VLAN (802.1q) Header was present in the frame.
3004  10 - S-VLAN (802.1ad) Header was present in the frame. */
3005  pseudo_bit_t dife[0x00001]; /* DIF Error */
3006 /* -------------- */
3007  pseudo_bit_t immediate_rssvalue_invalidatekey[0x00020];/* For a responder CQE, if completed WQE Opcode is Send With Immediate or Write With Immediate, this field contains immediate field of the received message.
3008  For a responder CQE, if completed WQE Opcode is Send With Invalidate, this field contains the R_key that was invalidated.
3009  For a responder CQE of a GSI packet this filed contains the Pkey Index of the packet.
3010  For IPoIB (UD) and RawEth CQEs this field contains the RSS hash function value.
3011  Otherwise, this field is reserved. */
3012 /* -------------- */
3013  pseudo_bit_t srq_rqpn[0x00018]; /* For Responder UD QPs, Remote (source) QP number.
3014  For Responder SRC QPs, SRQ number.
3015  Otherwise, this field is reserved. */
3016  pseudo_bit_t ml_path_mac_index[0x00007];/* For responder UD over IB CQE: These are the lower LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. Invalid if incoming message DLID is the permissive LID or incoming message is multicast.
3017  For responder UD over Ethernet and RawEth CQEs: Index of the MAC Table entry that the packet DMAC was matched against.
3018  Otherwise, this field is reserved. */
3019  pseudo_bit_t g[0x00001]; /* For responder UD over IB CQE this bit indicates the presence of a GRH
3020  For responder UD over Ethernet CQE this bit is set if IPv6 L3 header was present in the packet, this bit is cleared if IPv4 L3 Header was present in the packet.
3021  Otherwise, this field is reserved. */
3022 /* -------------- */
3023  pseudo_bit_t slid_smac47_32[0x00010];/* For responder UD over IB CQE it is the source LID of the packet.
3024  For responder UD over Ethernet and RawEth CQEs it is the source-MAC[47:32] of the packet.
3025  Otherwise, this field is reserved. */
3026  pseudo_bit_t vid[0x0000c]; /* Frame VID, valid for Responder Raw Ethernet and UD over Ethernet QP. Otherwise, this field is reserved. */
3027  pseudo_bit_t sl[0x00004]; /* For responder UD over IB - the Service Level of the packet.
3028  For responder UD over Ethernet and RawEth - it is VLAN-header[15:12]
3029  Otherwise, this field is reserved. */
3030 /* -------------- */
3031  pseudo_bit_t smac31_0_rawether_ipoib_status[0x00020];/* For responder UD over Ethernet - source MAC[31:0] of the packet.
3032  For responder RawEth and UD over IB - RawEth-IPoIB status {3 reserved, ipok,udp,tcp,ipv4opt,ipv6,ipv4vf,ipv4,rht(6),ipv6extmask(6),reserved(2),l2am,reserved(2),bfcs,reserved(2),enc}
3033  Otherwise, this field is reserved. */
3034 /* -------------- */
3035  pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data transferred. Applicable for RDMA-read, Atomic and all receive operations. completions.
3036  For Receive Queue that is subject for headers. separation, byte_cnt[31:24] specify number of bytes scattered to the first scatter entry (headers. length). Byte_cnt[23:0] specify total byte count received (including headers). */
3037 /* -------------- */
3038  pseudo_bit_t checksum[0x00010]; /* Valid for RawEth and IPoIB only. */
3040 /* -------------- */
3041  pseudo_bit_t opcode[0x00005]; /* Send completions - same encoding as WQE.
3042  Error coding is 0x1F
3043  Receive:
3044  0x0 - RDMA-Write with Immediate
3045  0x1 - Send
3046  0x2 - Send with Immediate
3047  0x3 - Send & Invalidate
3048  */
3049  pseudo_bit_t is[0x00001]; /* inline scatter */
3050  pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */
3051  pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */
3054 /* -------------- */
3055 };
3056 
3057 /* */
3058 
3059 struct hermonprm_mcg_qps_st { /* Little Endian */
3061 /* -------------- */
3062 };
3063 
3064 /* */
3065 
3066 struct hermonprm_mcg_hdr_st { /* Little Endian */
3069 /* -------------- */
3074 /* -------------- */
3076 /* -------------- */
3078 /* -------------- */
3079  pseudo_bit_t gid3[0x00020];
3080 /* -------------- */
3081  pseudo_bit_t gid2[0x00020];
3082 /* -------------- */
3083  pseudo_bit_t gid1[0x00020];
3084 /* -------------- */
3085  pseudo_bit_t gid0[0x00020];
3086 /* -------------- */
3087 };
3088 
3089 /* */
3090 
3091 struct hermonprm_sched_queue_context_st { /* Little Endian */
3092  pseudo_bit_t policy[0x00003]; /* Schedule Queue Policy - 0 - LLSQ, 1 - GBSQ, 2 - BESQ */
3093  pseudo_bit_t vl15[0x00001];
3094  pseudo_bit_t sl[0x00004]; /* SL this Schedule Queue is associated with (if vl15 bit is 0) */
3095  pseudo_bit_t port[0x00002]; /* Port this Schedule Queue is associated with */
3097  pseudo_bit_t weight[0x00010]; /* Weight of this SchQ */
3098 /* -------------- */
3099 };
3100 
3101 /* */
3102 
3103 struct hermonprm_ecc_detect_event_data_st { /* Little Endian */
3105 /* -------------- */
3116 /* -------------- */
3119 /* -------------- */
3120 };
3121 
3122 /* Event_data Field - ECC Detection Event */
3123 
3124 struct hermonprm_scrubbing_event_st { /* Little Endian */
3126 /* -------------- */
3127  pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause:
3128  single ECC error in the 64bit lsb data, on the rise edge of the clock */
3130  pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause:
3131  single ECC error in the 64bit msb data, on the fall edge of the clock */
3133  pseudo_bit_t err_rmw[0x00001]; /* transaction type:
3134  0 - read
3135  1 - read/modify/write */
3136  pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */
3137  pseudo_bit_t err_da[0x00002]; /* Error DIMM address */
3138  pseudo_bit_t err_ba[0x00002]; /* Error bank address */
3140  pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */
3141 /* -------------- */
3142  pseudo_bit_t err_ra[0x00010]; /* Error row address */
3143  pseudo_bit_t err_ca[0x00010]; /* Error column address */
3144 /* -------------- */
3145 };
3146 
3147 /* */
3148 
3149 struct hermonprm_eq_cmd_doorbell_st { /* Little Endian */
3151 /* -------------- */
3152 };
3153 
3154 /* 0 */
3155 
3156 struct hermonprm_hermon_prm_st { /* Little Endian */
3157  struct hermonprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */
3158 /* -------------- */
3160 /* -------------- */
3161  struct hermonprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */
3162 /* -------------- */
3164 /* -------------- */
3165  struct hermonprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */
3166 /* -------------- */
3168 /* -------------- */
3169  struct hermonprm_completion_event_st completion_event;/* Event_data Field - Completion Event */
3170 /* -------------- */
3172 /* -------------- */
3173  struct hermonprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */
3174 /* -------------- */
3176 /* -------------- */
3177  struct hermonprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */
3178 /* -------------- */
3180 /* -------------- */
3181  struct hermonprm_wqe_segment_st wqe_segment;/* WQE segments format */
3182 /* -------------- */
3184 /* -------------- */
3185  struct hermonprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */
3186 /* -------------- */
3188 /* -------------- */
3189  struct hermonprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */
3190 /* -------------- */
3192 /* -------------- */
3193  struct hermonprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */
3194 /* -------------- */
3196 /* -------------- */
3197  struct hermonprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */
3198 /* -------------- */
3200 /* -------------- */
3202 /* -------------- */
3204 /* -------------- */
3205  struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */
3206 /* -------------- */
3208 /* -------------- */
3210 /* -------------- */
3212 /* -------------- */
3213  struct hermonprm_address_path_st address_path;/* Address Path */
3214 /* -------------- */
3216 /* -------------- */
3217  struct hermonprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */
3218 /* -------------- */
3220 /* -------------- */
3221  struct hermonprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */
3222 /* -------------- */
3224 /* -------------- */
3225  struct hermonprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */
3226 /* -------------- */
3228 /* -------------- */
3229  struct hermonprm_eqc_st eqc; /* Event Queue Context Table Entry */
3230 /* -------------- */
3232 /* -------------- */
3234 /* -------------- */
3236 /* -------------- */
3237  struct hermonprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */
3238 /* -------------- */
3240 /* -------------- */
3241  struct hermonprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */
3242 /* -------------- */
3244 /* -------------- */
3245  struct hermonprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */
3246 /* -------------- */
3248 /* -------------- */
3249  struct hermonprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */
3250 /* -------------- */
3252 /* -------------- */
3253  struct hermonprm_multicastparam_st multicastparam;/* Multicast Support Parameters */
3254 /* -------------- */
3256 /* -------------- */
3257  struct hermonprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */
3258 /* -------------- */
3260 /* -------------- */
3262 /* -------------- */
3264 /* -------------- */
3266 /* -------------- */
3268 /* -------------- */
3270 /* -------------- */
3271  struct hermonprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */
3272 /* -------------- */
3274 /* -------------- */
3275  struct hermonprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */
3276 /* -------------- */
3278 /* -------------- */
3279  struct hermonprm_query_dev_cap_st query_dev_cap;/* Query Device Limitations */
3280 /* -------------- */
3282 /* -------------- */
3283  struct hermonprm_uar_params_st uar_params;/* UAR Parameters */
3284 /* -------------- */
3286 /* -------------- */
3287  struct hermonprm_init_port_st init_port;/* INIT_PORT Parameters */
3288 /* -------------- */
3290 /* -------------- */
3291  struct hermonprm_mgm_entry_st mgm_entry;/* Multicast Group Member */
3292 /* -------------- */
3294 /* -------------- */
3295  struct hermonprm_set_ib_st set_ib; /* SET_IB Parameters */
3296 /* -------------- */
3298 /* -------------- */
3299  struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */
3300 /* -------------- */
3302 /* -------------- */
3303  struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */
3304 /* -------------- */
3306 /* -------------- */
3307  struct hermonprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */
3308 /* -------------- */
3310 /* -------------- */
3312 /* -------------- */
3314 /* -------------- */
3315  struct hermonprm_uar_st uar; /* User Access Region */
3316 /* -------------- */
3318 /* -------------- */
3319  struct hermonprm_mgmqp_st mgmqp; /* Multicast Group Member QP */
3320 /* -------------- */
3322 /* -------------- */
3323  struct hermonprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */
3324 /* -------------- */
3326 /* -------------- */
3327  struct hermonprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */
3328 /* -------------- */
3330 /* -------------- */
3332 /* -------------- */
3334 /* -------------- */
3335  struct hermonprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */
3336 /* -------------- */
3338 /* -------------- */
3339  struct hermonprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */
3340 /* -------------- */
3342 /* -------------- */
3343  struct hermonprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */
3344 /* -------------- */
3346 /* -------------- */
3348 /* -------------- */
3350 /* -------------- */
3352 /* -------------- */
3354 /* -------------- */
3356 /* -------------- */
3358 /* -------------- */
3359  struct hermonprm_pbl_st pbl; /* Physical Buffer List */
3360 /* -------------- */
3362 /* -------------- */
3363  struct hermonprm_srq_context_st srq_context;/* SRQ Context */
3364 /* -------------- */
3366 /* -------------- */
3367  struct hermonprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */
3368 /* -------------- */
3370 /* -------------- */
3371  struct hermonprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */
3372 /* -------------- */
3374 /* -------------- */
3375  struct hermonprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */
3376 /* -------------- */
3378 /* -------------- */
3379  struct hermonprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */
3380 /* -------------- */
3382 /* -------------- */
3383  struct hermonprm_qp_db_record_st qp_db_record;/* QP_DB_Record */
3384 /* -------------- */
3386 /* -------------- */
3388 /* -------------- */
3389  struct hermonprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */
3390 /* -------------- */
3391  struct hermonprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */
3392 /* -------------- */
3394 /* -------------- */
3396 /* -------------- */
3398 /* -------------- */
3399  struct hermonprm_clr_int_st clr_int; /* Clear Interrupt Register */
3400 /* -------------- */
3402 /* -------------- */
3403 };
3404 #endif /* H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H */
pseudo_bit_t fw_day[0x00008]
Definition: MT25408_PRM.h:2311
pseudo_bit_t vsd_dw21[0x00020]
Definition: MT25408_PRM.h:454
pseudo_bit_t event_counter1[0x00020]
Definition: MT25408_PRM.h:724
pseudo_bit_t eq57_set_ci[0x00020]
Definition: MT25408_PRM.h:1243
pseudo_bit_t reserved3[0x00060]
Definition: MT25408_PRM.h:1553
pseudo_bit_t fbo_en[0x00001]
Definition: MT25408_PRM.h:2534
pseudo_bit_t reserved7[0x00008]
Definition: MT25408_PRM.h:2727
pseudo_bit_t reserved2[0x00001]
Definition: MT25408_PRM.h:741
pseudo_bit_t vpd_address[0x0000f]
Definition: MT25408_PRM.h:2757
pseudo_bit_t reserved4[0x00040]
Definition: MT25408_PRM.h:2315
pseudo_bit_t reserved31[0x00010]
Definition: MT25408_PRM.h:908
pseudo_bit_t eqc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:666
pseudo_bit_t log2_page_size[0x00006]
Definition: MT25408_PRM.h:1499
pseudo_bit_t log_num_of_qp[0x00005]
Definition: MT25408_PRM.h:624
pseudo_bit_t in_param_l[0x00020]
Definition: MT25408_PRM.h:338
pseudo_bit_t cqn_snd[0x00018]
Definition: MT25408_PRM.h:874
pseudo_bit_t l_key[0x00020]
Definition: MT25408_PRM.h:112
pseudo_bit_t vsd_dw12[0x00020]
Definition: MT25408_PRM.h:436
pseudo_bit_t token[0x00010]
Definition: MT25408_PRM.h:347
pseudo_bit_t qdr_tx_options[0x00004]
Definition: MT25408_PRM.h:1354
pseudo_bit_t err_ca[0x00010]
Definition: MT25408_PRM.h:3143
pseudo_bit_t ipr1[0x00001]
Definition: MT25408_PRM.h:2378
pseudo_bit_t request_mad_packet[64][0x00020]
Definition: MT25408_PRM.h:1810
pseudo_bit_t vsd_dw38[0x00020]
Definition: MT25408_PRM.h:488
struct hermonprm_srq_context_st srq_context
Definition: MT25408_PRM.h:3363
pseudo_bit_t eqc_base_addr_l[0x0001b]
Definition: MT25408_PRM.h:672
pseudo_bit_t rx_options_m[0x00001]
Definition: MT25408_PRM.h:1345
pseudo_bit_t reserved2[0x00010]
Definition: MT25408_PRM.h:2695
pseudo_bit_t nodeguid_lo_m[0x00001]
Definition: MT25408_PRM.h:1387
pseudo_bit_t mc_base_addr_h[0x00020]
Definition: MT25408_PRM.h:583
pseudo_bit_t eq16_set_ci[0x00020]
Definition: MT25408_PRM.h:1079
pseudo_bit_t reserved25[0x00004]
Definition: MT25408_PRM.h:885
struct hermonprm_tptparams_st tpt_parameters
Definition: MT25408_PRM.h:2402
pseudo_bit_t reserved37[0x00002]
Definition: MT25408_PRM.h:1454
pseudo_bit_t log_max_scqs[0x00004]
Definition: MT25408_PRM.h:2059
pseudo_bit_t reserved24[0x00020]
Definition: MT25408_PRM.h:1113
pseudo_bit_t solicit_producer_indx[0x00018]
Definition: MT25408_PRM.h:2607
struct hermonprm_init_port_st init_port
Definition: MT25408_PRM.h:3287
pseudo_bit_t next_mcg[0x0001a]
Definition: MT25408_PRM.h:3068
pseudo_bit_t link_control[0x00010]
Definition: MT25408_PRM.h:2793
pseudo_bit_t page_offset[0x00006]
Definition: MT25408_PRM.h:1772
pseudo_bit_t msg_max[0x00005]
Definition: MT25408_PRM.h:828
pseudo_bit_t reserved53[0x00020]
Definition: MT25408_PRM.h:1229
pseudo_bit_t fl[0x00001]
Definition: MT25408_PRM.h:3000
pseudo_bit_t cardbus_cis_pointer[0x00020]
Definition: MT25408_PRM.h:2700
pseudo_bit_t status[0x00004]
Definition: MT25408_PRM.h:2499
pseudo_bit_t eq50_set_ci[0x00020]
Definition: MT25408_PRM.h:1215