Asix 10/100/1000 USB Ethernet driver. More...

#include <ipxe/usb.h>
#include <ipxe/usbnet.h>

Data Structures
struct	axge_bulk_in_control
	Bulk IN Control (undocumented) More...

struct	axge_tx_header
	Transmit packet header. More...

struct	axge_rx_footer
	Receive packet footer. More...

struct	axge_rx_descriptor
	Receive packet descriptor. More...

struct	axge_interrupt
	Interrupt data. More...

struct	axge_device
	An AXGE network device. More...

Macros
#define	AXGE_READ_MAC_REGISTER
	Read MAC register. More...

#define	AXGE_WRITE_MAC_REGISTER
	Write MAC register. More...

#define	AXGE_PLSR 0x02
	Physical Link Status Register. More...

#define	AXGE_PLSR_EPHY_10 0x10
	Ethernet at 10Mbps. More...

#define	AXGE_PLSR_EPHY_100 0x20
	Ethernet at 100Mbps. More...

#define	AXGE_PLSR_EPHY_1000 0x40
	Ethernet at 1000Mbps. More...

#define	AXGE_PLSR_EPHY_ANY

#define	AXGE_RCR 0x0b
	RX Control Register. More...

#define	AXGE_RCR_PRO 0x0001
	Promiscuous mode. More...

#define	AXGE_RCR_AMALL 0x0002
	Accept all multicasts. More...

#define	AXGE_RCR_AB 0x0008
	Accept broadcasts. More...

#define	AXGE_RCR_SO 0x0080
	Start operation. More...

#define	AXGE_NIDR 0x10
	Node ID Register. More...

#define	AXGE_MSR 0x22
	Medium Status Register. More...

#define	AXGE_MSR_GM 0x0001
	Gigabit mode. More...

#define	AXGE_MSR_FD 0x0002
	Full duplex. More...

#define	AXGE_MSR_RFC 0x0010
	RX flow control enable. More...

#define	AXGE_MSR_TFC 0x0020
	TX flow control enable. More...

#define	AXGE_MSR_RE 0x0100
	Receive enable. More...

#define	AXGE_MSR_PS 0x0200
	100Mbps port speed More...

#define	AXGE_EPPRCR 0x26
	Ethernet PHY Power and Reset Control Register. More...

#define	AXGE_EPPRCR_IPRL 0x0020
	Undocumented. More...

#define	AXGE_EPPRCR_DELAY_MS 200
	Delay after initialising EPPRCR. More...

#define	AXGE_BICR 0x2e
	Bulk IN Control Register (undocumented) More...

#define	AXGE_CSR 0x33
	Clock Select Register (undocumented) More...

#define	AXGE_CSR_BCS 0x01
	Undocumented. More...

#define	AXGE_CSR_ACS 0x02
	Undocumented. More...

#define	AXGE_CSR_DELAY_MS 100
	Delay after initialising CSR. More...

#define	AXGE_RX_LEN_MASK 0x1fff
	Receive packet length mask. More...

#define	AXGE_RX_LEN_PAD_ALIGN 8
	Receive packet length alignment. More...

#define	AXGE_RX_CRC_ERROR 0x2000
	Receive packet CRC error. More...

#define	AXGE_RX_DROP_ERROR 0x8000
	Receive packet dropped error. More...

#define	AXGE_INTR_MAGIC 0x00a1
	Interrupt magic signature. More...

#define	AXGE_INTR_LINK_PPLS 0x0001
	Link is up. More...

#define	AXGE_INTR_MAX_FILL 2
	Interrupt maximum fill level. More...

#define	AXGE_IN_MAX_FILL 8
	Bulk IN maximum fill level. More...

#define	AXGE_IN_MTU 2048
	Bulk IN buffer size. More...

#define	AXGE_IN_RESERVE sizeof ( struct axge_tx_header )
	Amount of space to reserve at start of bulk IN buffers. More...

Functions
	FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)

Detailed Description

Asix 10/100/1000 USB Ethernet driver.

Definition in file axge.h.

Macro Definition Documentation

◆ AXGE_READ_MAC_REGISTER

#define AXGE_READ_MAC_REGISTER

Value:

( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \

USB_REQUEST_TYPE ( 0x01 ) )

USB_TYPE_VENDOR

#define USB_TYPE_VENDOR

Vendor-specific request type.

Definition: usb.h:92

USB_DIR_IN

#define USB_DIR_IN

Data transfer is from device to host.

Definition: usb.h:83

USB_RECIP_DEVICE

#define USB_RECIP_DEVICE

Request recipient is the device.

Definition: usb.h:98

Read MAC register.

Definition at line 16 of file axge.h.

◆ AXGE_WRITE_MAC_REGISTER

#define AXGE_WRITE_MAC_REGISTER

Value:

( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \

USB_REQUEST_TYPE ( 0x01 ) )

USB_DIR_OUT

#define USB_DIR_OUT

Data transfer is from host to device.

Definition: usb.h:80

USB_TYPE_VENDOR

#define USB_TYPE_VENDOR

Vendor-specific request type.

Definition: usb.h:92

USB_RECIP_DEVICE

#define USB_RECIP_DEVICE

Request recipient is the device.

Definition: usb.h:98

Write MAC register.

Definition at line 21 of file axge.h.

◆ AXGE_PLSR

#define AXGE_PLSR 0x02

Physical Link Status Register.

Definition at line 26 of file axge.h.

◆ AXGE_PLSR_EPHY_10

#define AXGE_PLSR_EPHY_10 0x10

Ethernet at 10Mbps.

Definition at line 27 of file axge.h.

◆ AXGE_PLSR_EPHY_100

#define AXGE_PLSR_EPHY_100 0x20

Ethernet at 100Mbps.

Definition at line 28 of file axge.h.

◆ AXGE_PLSR_EPHY_1000

#define AXGE_PLSR_EPHY_1000 0x40

Ethernet at 1000Mbps.

Definition at line 29 of file axge.h.

◆ AXGE_PLSR_EPHY_ANY

#define AXGE_PLSR_EPHY_ANY

Value:

( AXGE_PLSR_EPHY_10 |                                           \
          AXGE_PLSR_EPHY_100 |                                          \
          AXGE_PLSR_EPHY_1000 )

Definition at line 30 of file axge.h.

◆ AXGE_RCR

#define AXGE_RCR 0x0b

RX Control Register.

Definition at line 36 of file axge.h.

◆ AXGE_RCR_PRO

#define AXGE_RCR_PRO 0x0001

Promiscuous mode.

Definition at line 37 of file axge.h.

◆ AXGE_RCR_AMALL

#define AXGE_RCR_AMALL 0x0002

Accept all multicasts.

Definition at line 38 of file axge.h.

◆ AXGE_RCR_AB

#define AXGE_RCR_AB 0x0008

Accept broadcasts.

Definition at line 39 of file axge.h.

◆ AXGE_RCR_SO

#define AXGE_RCR_SO 0x0080

Start operation.

Definition at line 40 of file axge.h.

◆ AXGE_NIDR

#define AXGE_NIDR 0x10

Node ID Register.

Definition at line 43 of file axge.h.

◆ AXGE_MSR

#define AXGE_MSR 0x22

Medium Status Register.

Definition at line 46 of file axge.h.

◆ AXGE_MSR_GM

#define AXGE_MSR_GM 0x0001

Gigabit mode.

Definition at line 47 of file axge.h.

◆ AXGE_MSR_FD

#define AXGE_MSR_FD 0x0002

Full duplex.

Definition at line 48 of file axge.h.

◆ AXGE_MSR_RFC

#define AXGE_MSR_RFC 0x0010

RX flow control enable.

Definition at line 49 of file axge.h.

◆ AXGE_MSR_TFC

#define AXGE_MSR_TFC 0x0020

TX flow control enable.

Definition at line 50 of file axge.h.

◆ AXGE_MSR_RE

#define AXGE_MSR_RE 0x0100

Receive enable.

Definition at line 51 of file axge.h.

◆ AXGE_MSR_PS

#define AXGE_MSR_PS 0x0200

100Mbps port speed

Definition at line 52 of file axge.h.

◆ AXGE_EPPRCR

#define AXGE_EPPRCR 0x26

Ethernet PHY Power and Reset Control Register.

Definition at line 55 of file axge.h.

◆ AXGE_EPPRCR_IPRL

#define AXGE_EPPRCR_IPRL 0x0020

Undocumented.

Definition at line 56 of file axge.h.

◆ AXGE_EPPRCR_DELAY_MS

#define AXGE_EPPRCR_DELAY_MS 200

Delay after initialising EPPRCR.

Definition at line 59 of file axge.h.

◆ AXGE_BICR

#define AXGE_BICR 0x2e

Bulk IN Control Register (undocumented)

Definition at line 62 of file axge.h.

◆ AXGE_CSR

#define AXGE_CSR 0x33

Clock Select Register (undocumented)

Definition at line 77 of file axge.h.

◆ AXGE_CSR_BCS

#define AXGE_CSR_BCS 0x01

Undocumented.

Definition at line 78 of file axge.h.

◆ AXGE_CSR_ACS

#define AXGE_CSR_ACS 0x02

Undocumented.

Definition at line 79 of file axge.h.

◆ AXGE_CSR_DELAY_MS

#define AXGE_CSR_DELAY_MS 100

Delay after initialising CSR.

Definition at line 82 of file axge.h.

◆ AXGE_RX_LEN_MASK

#define AXGE_RX_LEN_MASK 0x1fff

Receive packet length mask.

Definition at line 109 of file axge.h.

◆ AXGE_RX_LEN_PAD_ALIGN

#define AXGE_RX_LEN_PAD_ALIGN 8

Receive packet length alignment.

Definition at line 112 of file axge.h.

◆ AXGE_RX_CRC_ERROR

#define AXGE_RX_CRC_ERROR 0x2000

Receive packet CRC error.

Definition at line 115 of file axge.h.

◆ AXGE_RX_DROP_ERROR

#define AXGE_RX_DROP_ERROR 0x8000

Receive packet dropped error.

Definition at line 118 of file axge.h.

◆ AXGE_INTR_MAGIC

#define AXGE_INTR_MAGIC 0x00a1

Interrupt magic signature.

Definition at line 133 of file axge.h.

◆ AXGE_INTR_LINK_PPLS

#define AXGE_INTR_LINK_PPLS 0x0001

Link is up.

Definition at line 136 of file axge.h.

◆ AXGE_INTR_MAX_FILL

#define AXGE_INTR_MAX_FILL 2

Interrupt maximum fill level.

This is a policy decision.

Definition at line 158 of file axge.h.

◆ AXGE_IN_MAX_FILL

#define AXGE_IN_MAX_FILL 8

Bulk IN maximum fill level.

This is a policy decision.

Definition at line 164 of file axge.h.

◆ AXGE_IN_MTU

#define AXGE_IN_MTU 2048

Bulk IN buffer size.

This is a policy decision.

Definition at line 170 of file axge.h.

◆ AXGE_IN_RESERVE

#define AXGE_IN_RESERVE sizeof ( struct axge_tx_header )

Amount of space to reserve at start of bulk IN buffers.

This is required to allow for protocols such as ARP which may reuse a received I/O buffer for transmission.

Definition at line 177 of file axge.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL )

Data Structures

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ AXGE_READ_MAC_REGISTER

◆ AXGE_WRITE_MAC_REGISTER

◆ AXGE_PLSR

◆ AXGE_PLSR_EPHY_10

◆ AXGE_PLSR_EPHY_100

◆ AXGE_PLSR_EPHY_1000

◆ AXGE_PLSR_EPHY_ANY

◆ AXGE_RCR

◆ AXGE_RCR_PRO

◆ AXGE_RCR_AMALL

◆ AXGE_RCR_AB

◆ AXGE_RCR_SO

◆ AXGE_NIDR

◆ AXGE_MSR

◆ AXGE_MSR_GM

◆ AXGE_MSR_FD

◆ AXGE_MSR_RFC

◆ AXGE_MSR_TFC

◆ AXGE_MSR_RE

◆ AXGE_MSR_PS

◆ AXGE_EPPRCR

◆ AXGE_EPPRCR_IPRL

◆ AXGE_EPPRCR_DELAY_MS

◆ AXGE_BICR

◆ AXGE_CSR

◆ AXGE_CSR_BCS

◆ AXGE_CSR_ACS

◆ AXGE_CSR_DELAY_MS

◆ AXGE_RX_LEN_MASK

◆ AXGE_RX_LEN_PAD_ALIGN

◆ AXGE_RX_CRC_ERROR

◆ AXGE_RX_DROP_ERROR

◆ AXGE_INTR_MAGIC

◆ AXGE_INTR_LINK_PPLS

◆ AXGE_INTR_MAX_FILL

◆ AXGE_IN_MAX_FILL

◆ AXGE_IN_MTU

◆ AXGE_IN_RESERVE

Function Documentation

◆ FILE_LICENCE()