16 #ifndef EFX_EF10_REGS_H 17 #define EFX_EF10_REGS_H 53 #define ER_DZ_BIU_HW_REV_ID 0x00000000 54 #define ERF_DZ_HW_REV_ID_LBN 0 55 #define ERF_DZ_HW_REV_ID_WIDTH 32 58 #define ER_DZ_BIU_MC_SFT_STATUS 0x00000010 59 #define ER_DZ_BIU_MC_SFT_STATUS_STEP 4 60 #define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8 61 #define ERF_DZ_MC_SFT_STATUS_LBN 0 62 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 65 #define ER_DZ_BIU_INT_ISR 0x00000090 66 #define ERF_DZ_ISR_REG_LBN 0 67 #define ERF_DZ_ISR_REG_WIDTH 32 70 #define ER_DZ_MC_DB_LWRD 0x00000200 71 #define ERF_DZ_MC_DOORBELL_L_LBN 0 72 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 75 #define ER_DZ_MC_DB_HWRD 0x00000204 76 #define ERF_DZ_MC_DOORBELL_H_LBN 0 77 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 80 #define ER_DZ_EVQ_RPTR 0x00000400 81 #define ER_DZ_EVQ_RPTR_STEP 8192 82 #define ER_DZ_EVQ_RPTR_ROWS 2048 83 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 84 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 85 #define ERF_DZ_EVQ_RPTR_LBN 0 86 #define ERF_DZ_EVQ_RPTR_WIDTH 15 89 #define ER_DZ_EVQ_TMR 0x00000420 90 #define ER_DZ_EVQ_TMR_STEP 8192 91 #define ER_DZ_EVQ_TMR_ROWS 2048 92 #define ERF_DZ_TC_TIMER_MODE_LBN 14 93 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 94 #define ERF_DZ_TC_TIMER_VAL_LBN 0 95 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 98 #define ER_DZ_RX_DESC_UPD 0x00000830 99 #define ER_DZ_RX_DESC_UPD_STEP 8192 100 #define ER_DZ_RX_DESC_UPD_ROWS 2048 101 #define ERF_DZ_RX_DESC_WPTR_LBN 0 102 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 105 #define ER_DZ_TX_DESC_UPD 0x00000a10 106 #define ER_DZ_TX_DESC_UPD_STEP 8192 107 #define ER_DZ_TX_DESC_UPD_ROWS 2048 108 #define ERF_DZ_RSVD_LBN 76 109 #define ERF_DZ_RSVD_WIDTH 20 110 #define ERF_DZ_TX_DESC_WPTR_LBN 64 111 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 112 #define ERF_DZ_TX_DESC_HWORD_LBN 32 113 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 114 #define ERF_DZ_TX_DESC_LWORD_LBN 0 115 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 118 #define ESF_DZ_DRV_CODE_LBN 60 119 #define ESF_DZ_DRV_CODE_WIDTH 4 120 #define ESF_DZ_DRV_SUB_CODE_LBN 56 121 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 122 #define ESE_DZ_DRV_TIMER_EV 3 123 #define ESE_DZ_DRV_START_UP_EV 2 124 #define ESE_DZ_DRV_WAKE_UP_EV 1 125 #define ESF_DZ_DRV_SUB_DATA_LBN 0 126 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 127 #define ESF_DZ_DRV_EVQ_ID_LBN 0 128 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 129 #define ESF_DZ_DRV_TMR_ID_LBN 0 130 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 133 #define ESF_DZ_EV_CODE_LBN 60 134 #define ESF_DZ_EV_CODE_WIDTH 4 135 #define ESE_DZ_EV_CODE_MCDI_EV 12 136 #define ESE_DZ_EV_CODE_DRIVER_EV 5 137 #define ESE_DZ_EV_CODE_TX_EV 2 138 #define ESE_DZ_EV_CODE_RX_EV 0 139 #define ESE_DZ_OTHER other 140 #define ESF_DZ_EV_DATA_LBN 0 141 #define ESF_DZ_EV_DATA_WIDTH 60 144 #define ESF_DZ_MC_CODE_LBN 60 145 #define ESF_DZ_MC_CODE_WIDTH 4 146 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 147 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 148 #define ESF_DZ_MC_DROP_EVENT_LBN 58 149 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 150 #define ESF_DZ_MC_SOFT_LBN 0 151 #define ESF_DZ_MC_SOFT_WIDTH 58 154 #define ESF_DZ_RX_CODE_LBN 60 155 #define ESF_DZ_RX_CODE_WIDTH 4 156 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 157 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 158 #define ESF_DZ_RX_DROP_EVENT_LBN 58 159 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 160 #define ESF_DZ_RX_EV_RSVD2_LBN 54 161 #define ESF_DZ_RX_EV_RSVD2_WIDTH 4 162 #define ESF_DZ_RX_EV_SOFT2_LBN 52 163 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 164 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 165 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 166 #define ESF_DZ_RX_L4_CLASS_LBN 45 167 #define ESF_DZ_RX_L4_CLASS_WIDTH 3 168 #define ESE_DZ_L4_CLASS_RSVD7 7 169 #define ESE_DZ_L4_CLASS_RSVD6 6 170 #define ESE_DZ_L4_CLASS_RSVD5 5 171 #define ESE_DZ_L4_CLASS_RSVD4 4 172 #define ESE_DZ_L4_CLASS_RSVD3 3 173 #define ESE_DZ_L4_CLASS_UDP 2 174 #define ESE_DZ_L4_CLASS_TCP 1 175 #define ESE_DZ_L4_CLASS_UNKNOWN 0 176 #define ESF_DZ_RX_L3_CLASS_LBN 42 177 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 178 #define ESE_DZ_L3_CLASS_RSVD7 7 179 #define ESE_DZ_L3_CLASS_IP6_FRAG 6 180 #define ESE_DZ_L3_CLASS_ARP 5 181 #define ESE_DZ_L3_CLASS_IP4_FRAG 4 182 #define ESE_DZ_L3_CLASS_FCOE 3 183 #define ESE_DZ_L3_CLASS_IP6 2 184 #define ESE_DZ_L3_CLASS_IP4 1 185 #define ESE_DZ_L3_CLASS_UNKNOWN 0 186 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 187 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 188 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 189 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 190 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 191 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 192 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 193 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 194 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 195 #define ESE_DZ_ETH_TAG_CLASS_NONE 0 196 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 197 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 198 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 199 #define ESE_DZ_ETH_BASE_CLASS_LLC 1 200 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 201 #define ESF_DZ_RX_MAC_CLASS_LBN 35 202 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 203 #define ESE_DZ_MAC_CLASS_MCAST 1 204 #define ESE_DZ_MAC_CLASS_UCAST 0 205 #define ESF_DZ_RX_EV_SOFT1_LBN 32 206 #define ESF_DZ_RX_EV_SOFT1_WIDTH 3 207 #define ESF_DZ_RX_EV_RSVD1_LBN 31 208 #define ESF_DZ_RX_EV_RSVD1_WIDTH 1 209 #define ESF_DZ_RX_ABORT_LBN 30 210 #define ESF_DZ_RX_ABORT_WIDTH 1 211 #define ESF_DZ_RX_ECC_ERR_LBN 29 212 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 213 #define ESF_DZ_RX_CRC1_ERR_LBN 28 214 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 215 #define ESF_DZ_RX_CRC0_ERR_LBN 27 216 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 217 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 218 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 219 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 220 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 221 #define ESF_DZ_RX_ECRC_ERR_LBN 24 222 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 223 #define ESF_DZ_RX_QLABEL_LBN 16 224 #define ESF_DZ_RX_QLABEL_WIDTH 5 225 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 226 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 227 #define ESF_DZ_RX_CONT_LBN 14 228 #define ESF_DZ_RX_CONT_WIDTH 1 229 #define ESF_DZ_RX_BYTES_LBN 0 230 #define ESF_DZ_RX_BYTES_WIDTH 14 233 #define ESF_DZ_RX_KER_RESERVED_LBN 62 234 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 235 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 236 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 237 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 238 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 241 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 242 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 243 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 244 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 245 #define ESE_DZ_TX_OPTION_DESC_TSO 7 246 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 247 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 248 #define ESF_DZ_TX_TIMESTAMP_LBN 5 249 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 250 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 251 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 252 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 253 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 254 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 255 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 256 #define ESE_DZ_TX_OPTION_CRC_FCOE 1 257 #define ESE_DZ_TX_OPTION_CRC_OFF 0 258 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 259 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 260 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 261 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 264 #define ESF_DZ_TX_CODE_LBN 60 265 #define ESF_DZ_TX_CODE_WIDTH 4 266 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 267 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 268 #define ESF_DZ_TX_DROP_EVENT_LBN 58 269 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 270 #define ESF_DZ_TX_EV_RSVD_LBN 48 271 #define ESF_DZ_TX_EV_RSVD_WIDTH 10 272 #define ESF_DZ_TX_SOFT2_LBN 32 273 #define ESF_DZ_TX_SOFT2_WIDTH 16 274 #define ESF_DZ_TX_CAN_MERGE_LBN 31 275 #define ESF_DZ_TX_CAN_MERGE_WIDTH 1 276 #define ESF_DZ_TX_SOFT1_LBN 24 277 #define ESF_DZ_TX_SOFT1_WIDTH 7 278 #define ESF_DZ_TX_QLABEL_LBN 16 279 #define ESF_DZ_TX_QLABEL_WIDTH 5 280 #define ESF_DZ_TX_DESCR_INDX_LBN 0 281 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 284 #define ESF_DZ_TX_KER_TYPE_LBN 63 285 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 286 #define ESF_DZ_TX_KER_CONT_LBN 62 287 #define ESF_DZ_TX_KER_CONT_WIDTH 1 288 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 289 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 290 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 291 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 294 #define ESF_DZ_TX_PIO_TYPE_LBN 63 295 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 296 #define ESF_DZ_TX_PIO_OPT_LBN 60 297 #define ESF_DZ_TX_PIO_OPT_WIDTH 3 298 #define ESF_DZ_TX_PIO_CONT_LBN 59 299 #define ESF_DZ_TX_PIO_CONT_WIDTH 1 300 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 301 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 302 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 303 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 306 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 307 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 308 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 309 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 310 #define ESE_DZ_TX_OPTION_DESC_TSO 7 311 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 312 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 313 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 314 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 315 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 316 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 317 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 318 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 325 #define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4) 326 #define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32) 327 #define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH 335 #define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD 336 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 337 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 338 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 339 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 340 #define ERF_DD_EVQ_IND_RPTR_LBN 0 341 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 342 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 343 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 344 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 345 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 346 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 347 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 348 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 353 #define ER_DZ_TX_PIOBUF 4096 354 #define ER_DZ_TX_PIOBUF_SIZE 2048 357 #define ES_DZ_RX_PREFIX_HASH_OFST 0 358 #define ES_DZ_RX_PREFIX_VLAN1_OFST 4 359 #define ES_DZ_RX_PREFIX_VLAN2_OFST 6 360 #define ES_DZ_RX_PREFIX_PKTLEN_OFST 8 361 #define ES_DZ_RX_PREFIX_TSTAMP_OFST 10 362 #define ES_DZ_RX_PREFIX_SIZE 14 FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)