iPXE
ena.h
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1 #ifndef _ENA_H
2 #define _ENA_H
3 
4 /** @file
5  *
6  * Amazon ENA network driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14 
15 /** BAR size */
16 #define ENA_BAR_SIZE 16384
17 
18 /** Queue alignment */
19 #define ENA_ALIGN 4096
20 
21 /** Number of admin queue entries */
22 #define ENA_AQ_COUNT 2
23 
24 /** Number of admin completion queue entries */
25 #define ENA_ACQ_COUNT 2
26 
27 /** Number of async event notification queue entries */
28 #define ENA_AENQ_COUNT 2
29 
30 /** Number of transmit queue entries */
31 #define ENA_TX_COUNT 16
32 
33 /** Number of receive queue entries */
34 #define ENA_RX_COUNT 128
35 
36 /** Receive queue maximum fill level */
37 #define ENA_RX_FILL 16
38 
39 /** Base address low register offset */
40 #define ENA_BASE_LO 0x0
41 
42 /** Base address high register offset */
43 #define ENA_BASE_HI 0x4
44 
45 /** Capability register value */
46 #define ENA_CAPS( count, size ) ( ( (size) << 16 ) | ( (count) << 0 ) )
47 
48 /** Admin queue base address register */
49 #define ENA_AQ_BASE 0x10
50 
51 /** Admin queue capabilities register */
52 #define ENA_AQ_CAPS 0x18
53 
54 /** Admin completion queue base address register */
55 #define ENA_ACQ_BASE 0x20
56 
57 /** Admin completion queue capabilities register */
58 #define ENA_ACQ_CAPS 0x28
59 
60 /** Admin queue doorbell register */
61 #define ENA_AQ_DB 0x2c
62 
63 /** Maximum time to wait for admin requests */
64 #define ENA_ADMIN_MAX_WAIT_MS 5000
65 
66 /** Async event notification queue capabilities register */
67 #define ENA_AENQ_CAPS 0x34
68 
69 /** Async event notification queue base address register */
70 #define ENA_AENQ_BASE 0x38
71 
72 /** Device control register */
73 #define ENA_CTRL 0x54
74 #define ENA_CTRL_RESET 0x00000001UL /**< Reset */
75 
76 /** Maximum time to wait for reset */
77 #define ENA_RESET_MAX_WAIT_MS 1000
78 
79 /** Device status register */
80 #define ENA_STAT 0x58
81 #define ENA_STAT_RESET 0x00000008UL /**< Reset in progress */
82 
83 /** Admin queue entry header */
84 struct ena_aq_header {
85  /** Request identifier */
87  /** Reserved */
89  /** Opcode */
91  /** Flags */
93 } __attribute__ (( packed ));
94 
95 /** Admin queue ownership phase flag */
96 #define ENA_AQ_PHASE 0x01
97 
98 /** Admin completion queue entry header */
100  /** Request identifier */
102  /** Reserved */
104  /** Status */
106  /** Flags */
108  /** Extended status */
110  /** Consumer index */
112 } __attribute__ (( packed ));
113 
114 /** Admin completion queue ownership phase flag */
115 #define ENA_ACQ_PHASE 0x01
116 
117 /** Device attributes */
118 #define ENA_DEVICE_ATTRIBUTES 1
119 
120 /** Device attributes */
122  /** Implementation */
124  /** Device version */
126  /** Supported features */
128  /** Reserved */
130  /** Physical address width */
132  /** Virtual address width */
133  uint32_t virtual;
134  /** MAC address */
136  /** Reserved */
138  /** Maximum MTU */
140 } __attribute__ (( packed ));
141 
142 /** Async event notification queue config */
143 #define ENA_AENQ_CONFIG 26
144 
145 /** Async event notification queue config */
147  /** Bitmask of supported AENQ groups (device -> host) */
149  /** Bitmask of enabled AENQ groups (host -> device) */
151 } __attribute__ (( packed ));
152 
153 /** Host attributes */
154 #define ENA_HOST_ATTRIBUTES 28
155 
156 /** Host attributes */
158  /** Host info base address */
160  /** Debug area base address */
162  /** Debug area size */
164 } __attribute__ (( packed ));
165 
166 /** Host information */
168  /** Operating system type */
170  /** Operating system distribution (string) */
171  char dist_str[128];
172  /** Operating system distribution (numeric) */
174  /** Kernel version (string) */
175  char kernel_str[32];
176  /** Kernel version (numeric) */
178  /** Driver version */
180  /** Linux network device features */
182  /** ENA specification version */
184  /** PCI bus:dev.fn address */
186  /** Number of CPUs */
188  /** Reserved */
190  /** Supported features */
192 } __attribute__ (( packed ));
193 
194 /** Operating system type
195  *
196  * Some very broken older versions of the ENA firmware will refuse to
197  * allow a completion queue to be created if "iPXE" (type 5) is used,
198  * and require us to pretend that we are "Linux" (type 1) instead.
199  *
200  * The ENA team at AWS assures us that the entire AWS fleet has been
201  * upgraded to fix this bug, and that we are now safe to use the
202  * correct operating system type value.
203  */
204 #define ENA_HOST_INFO_TYPE_IPXE 5
205 
206 /** Driver version
207  *
208  * The driver version field is nominally used to report a version
209  * number outside of the VM for consumption by humans (and potentially
210  * by automated monitoring tools that could e.g. check for outdated
211  * versions with known security flaws).
212  *
213  * However, at some point in the development of the ENA firmware, some
214  * unknown person at AWS thought it would be sensible to apply a
215  * machine interpretation to this field and adjust the behaviour of
216  * the firmware based on its value, thereby creating a maintenance and
217  * debugging nightmare for all existing and future drivers.
218  *
219  * Hint to engineers: if you ever find yourself writing code of the
220  * form "if (version == SOME_MAGIC_NUMBER)" then something has gone
221  * very, very wrong. This *always* indicates that something is
222  * broken, either in your own code or in the code with which you are
223  * forced to interact.
224  */
225 #define ENA_HOST_INFO_VERSION_WTF 0x00000002UL
226 
227 /** ENA specification version */
228 #define ENA_HOST_INFO_SPEC_2_0 0x0200
229 
230 /** Feature */
231 union ena_feature {
232  /** Device attributes */
234  /** Async event notification queue config */
236  /** Host attributes */
238 };
239 
240 /** Submission queue direction */
242  /** Transmit */
243  ENA_SQ_TX = 0x20,
244  /** Receive */
245  ENA_SQ_RX = 0x40,
246 };
247 
248 /** Create submission queue */
249 #define ENA_CREATE_SQ 1
250 
251 /** Create submission queue request */
253  /** Header */
255  /** Direction */
257  /** Reserved */
259  /** Policy */
261  /** Completion queue identifier */
263  /** Number of entries */
265  /** Base address */
267  /** Writeback address */
269  /** Reserved */
271 } __attribute__ (( packed ));
272 
273 /** Submission queue policy */
275  /** Use host memory */
277  /** Memory is contiguous */
279 };
280 
281 /** Create submission queue response */
283  /** Header */
285  /** Submission queue identifier */
287  /** Reserved */
289  /** Doorbell register offset */
291  /** LLQ descriptor ring offset */
293  /** LLQ header offset */
295 } __attribute__ (( packed ));
296 
297 /** Destroy submission queue */
298 #define ENA_DESTROY_SQ 2
299 
300 /** Destroy submission queue request */
302  /** Header */
304  /** Submission queue identifier */
306  /** Direction */
308  /** Reserved */
310 } __attribute__ (( packed ));
311 
312 /** Destroy submission queue response */
314  /** Header */
316 } __attribute__ (( packed ));
317 
318 /** Create completion queue */
319 #define ENA_CREATE_CQ 3
320 
321 /** Create completion queue request */
323  /** Header */
325  /** Interrupts enabled */
327  /** Entry size (in 32-bit words) */
329  /** Number of entries */
331  /** MSI-X vector */
333  /** Base address */
335 } __attribute__ (( packed ));
336 
337 /** Empty MSI-X vector
338  *
339  * Some versions of the ENA firmware will complain if the completion
340  * queue's MSI-X vector field is left empty, even though the queue
341  * configuration specifies that interrupts are not used.
342  */
343 #define ENA_MSIX_NONE 0xffffffffUL
344 
345 /** Create completion queue response */
347  /** Header */
349  /** Completion queue identifier */
351  /** Actual number of entries */
353  /** NUMA node register offset */
355  /** Doorbell register offset */
357  /** Interrupt unmask register offset */
359 } __attribute__ (( packed ));
360 
361 /** Destroy completion queue */
362 #define ENA_DESTROY_CQ 4
363 
364 /** Destroy completion queue request */
366  /** Header */
368  /** Completion queue identifier */
370  /** Reserved */
372 } __attribute__ (( packed ));
373 
374 /** Destroy completion queue response */
376  /** Header */
378 } __attribute__ (( packed ));
379 
380 /** Get feature */
381 #define ENA_GET_FEATURE 8
382 
383 /** Get feature request */
385  /** Header */
387  /** Length */
389  /** Address */
391  /** Flags */
393  /** Feature identifier */
395  /** Reserved */
397 } __attribute__ (( packed ));
398 
399 /** Get feature response */
401  /** Header */
403  /** Feature */
405 } __attribute__ (( packed ));
406 
407 /** Set feature */
408 #define ENA_SET_FEATURE 9
409 
410 /** Set feature request */
412  /** Header */
414  /** Length */
416  /** Address */
418  /** Flags */
420  /** Feature identifier */
422  /** Reserved */
424  /** Feature */
426 } __attribute__ (( packed ));
427 
428 /** Get statistics */
429 #define ENA_GET_STATS 11
430 
431 /** Get statistics request */
433  /** Header */
435  /** Reserved */
437  /** Type */
439  /** Scope */
441  /** Reserved */
443  /** Queue ID */
445  /** Device ID */
447 } __attribute__ (( packed ));
448 
449 /** Basic statistics */
450 #define ENA_STATS_TYPE_BASIC 0
451 
452 /** Ethernet statistics */
453 #define ENA_STATS_SCOPE_ETH 1
454 
455 /** My device */
456 #define ENA_DEVICE_MINE 0xffff
457 
458 /** Get statistics response */
460  /** Header */
462  /** Transmit byte count */
464  /** Transmit packet count */
466  /** Receive byte count */
468  /** Receive packet count */
470  /** Receive drop count */
472 } __attribute__ (( packed ));
473 
474 /** Admin queue request */
475 union ena_aq_req {
476  /** Header */
478  /** Create submission queue */
480  /** Destroy submission queue */
482  /** Create completion queue */
484  /** Destroy completion queue */
486  /** Get feature */
488  /** Set feature */
490  /** Get statistics */
492  /** Padding */
494 };
495 
496 /** Admin completion queue response */
497 union ena_acq_rsp {
498  /** Header */
500  /** Create submission queue */
502  /** Destroy submission queue */
504  /** Create completion queue */
506  /** Destroy completion queue */
508  /** Get feature */
510  /** Get statistics */
512  /** Padding */
514 };
515 
516 /** Admin queue */
517 struct ena_aq {
518  /** Requests */
519  union ena_aq_req *req;
520  /** Producer counter */
521  unsigned int prod;
522 };
523 
524 /** Admin completion queue */
525 struct ena_acq {
526  /** Responses */
527  union ena_acq_rsp *rsp;
528  /** Consumer counter */
529  unsigned int cons;
530  /** Phase */
531  unsigned int phase;
532 };
533 
534 /** Async event notification queue event */
536  /** Type of event */
538  /** ID of event */
540  /** Phase */
542  /** Reserved */
544  /** Timestamp */
546  /** Additional event data */
548 } __attribute__ (( packed ));
549 
550 /** Async event notification queue */
551 struct ena_aenq {
552  /** Events */
554 };
555 
556 /** Transmit submission queue entry */
557 struct ena_tx_sqe {
558  /** Length */
560  /** Reserved */
562  /** Flags */
564  /** Reserved */
566  /** Request identifier */
568  /** Address */
570 } __attribute__ (( packed ));
571 
572 /** Receive submission queue entry */
573 struct ena_rx_sqe {
574  /** Length */
576  /** Reserved */
578  /** Flags */
580  /** Request identifier */
582  /** Reserved */
584  /** Address */
586 } __attribute__ (( packed ));
587 
588 /** Submission queue ownership phase flag */
589 #define ENA_SQE_PHASE 0x01
590 
591 /** This is the first descriptor */
592 #define ENA_SQE_FIRST 0x04
593 
594 /** This is the last descriptor */
595 #define ENA_SQE_LAST 0x08
596 
597 /** Request completion */
598 #define ENA_SQE_CPL 0x10
599 
600 /** Transmit completion queue entry */
601 struct ena_tx_cqe {
602  /** Request identifier */
604  /** Status */
606  /** Flags */
608  /** Reserved */
610  /** Consumer index */
612 } __attribute__ (( packed ));
613 
614 /** Transmit completion request identifier */
615 #define ENA_TX_CQE_ID(id) ( (id) >> 2 )
616 
617 /** Receive completion queue entry */
618 struct ena_rx_cqe {
619  /** Reserved */
621  /** Flags */
623  /** Length */
625  /** Request identifier */
627  /** Reserved */
629 } __attribute__ (( packed ));
630 
631 /** Completion queue ownership phase flag */
632 #define ENA_CQE_PHASE 0x01
633 
634 /** Submission queue */
635 struct ena_sq {
636  /** Entries */
637  union {
638  /** Transmit submission queue entries */
639  struct ena_tx_sqe *tx;
640  /** Receive submission queue entries */
641  struct ena_rx_sqe *rx;
642  /** Raw data */
643  void *raw;
644  } sqe;
645  /** Buffer IDs */
647  /** Doorbell register offset */
648  unsigned int doorbell;
649  /** Total length of entries */
650  size_t len;
651  /** Producer counter */
652  unsigned int prod;
653  /** Phase */
654  unsigned int phase;
655  /** Submission queue identifier */
657  /** Direction */
659  /** Number of entries */
661  /** Maximum fill level */
663  /** Fill level (limited to completion queue size) */
665 };
666 
667 /**
668  * Initialise submission queue
669  *
670  * @v sq Submission queue
671  * @v direction Direction
672  * @v count Number of entries
673  * @v max Maximum fill level
674  * @v size Size of each entry
675  * @v ids Buffer IDs
676  */
677 static inline __attribute__ (( always_inline )) void
678 ena_sq_init ( struct ena_sq *sq, unsigned int direction, unsigned int count,
679  unsigned int max, size_t size, uint8_t *ids ) {
680 
681  sq->len = ( count * size );
682  sq->direction = direction;
683  sq->count = count;
684  sq->max = max;
685  sq->ids = ids;
686 }
687 
688 /** Completion queue */
689 struct ena_cq {
690  /** Entries */
691  union {
692  /** Transmit completion queue entries */
693  struct ena_tx_cqe *tx;
694  /** Receive completion queue entries */
695  struct ena_rx_cqe *rx;
696  /** Raw data */
697  void *raw;
698  } cqe;
699  /** Doorbell register offset */
700  unsigned int doorbell;
701  /** Total length of entries */
702  size_t len;
703  /** Consumer counter */
704  unsigned int cons;
705  /** Phase */
706  unsigned int phase;
707  /** Completion queue identifier */
709  /** Entry size (in 32-bit words) */
711  /** Requested number of entries */
713  /** Actual number of entries */
715  /** Actual number of entries minus one */
717 };
718 
719 /**
720  * Initialise completion queue
721  *
722  * @v cq Completion queue
723  * @v count Number of entries
724  * @v size Size of each entry
725  */
726 static inline __attribute__ (( always_inline )) void
727 ena_cq_init ( struct ena_cq *cq, unsigned int count, size_t size ) {
728 
729  cq->len = ( count * size );
730  cq->size = ( size / sizeof ( uint32_t ) );
732 }
733 
734 /** Queue pair */
735 struct ena_qp {
736  /** Submission queue */
737  struct ena_sq sq;
738  /** Completion queue */
739  struct ena_cq cq;
740 };
741 
742 /** An ENA network card */
743 struct ena_nic {
744  /** Registers */
745  void *regs;
746  /** Host info */
748  /** Admin queue */
749  struct ena_aq aq;
750  /** Admin completion queue */
751  struct ena_acq acq;
752  /** Async event notification queue */
753  struct ena_aenq aenq;
754  /** Transmit queue */
755  struct ena_qp tx;
756  /** Receive queue */
757  struct ena_qp rx;
758  /** Transmit buffer IDs */
760  /** Transmit I/O buffers, indexed by buffer ID */
762  /** Receive buffer IDs */
764  /** Receive I/O buffers, indexed by buffer ID */
766 };
767 
768 #endif /* _ENA_H */
uint8_t reserved_b[2]
Reserved.
Definition: ena.h:583
Destroy completion queue response.
Definition: ena.h:375
uint8_t reserved_a[12]
Reserved.
Definition: ena.h:436
struct ena_aq aq
Admin queue.
Definition: ena.h:749
Queue pair.
Definition: ena.h:735
uint16_t id
Completion queue identifier.
Definition: ena.h:350
uint32_t intr
Interrupt unmask register offset.
Definition: ena.h:358
struct ena_tx_sqe * tx
Transmit submission queue entries.
Definition: ena.h:639
uint8_t reserved[3]
Reserved.
Definition: ena.h:543
struct ena_qp rx
Receive queue.
Definition: ena.h:757
uint8_t type
Type.
Definition: ena.h:438
struct ena_acq_header header
Header.
Definition: ena.h:284
unsigned short uint16_t
Definition: stdint.h:11
void * raw
Raw data.
Definition: ena.h:697
struct ena_aq_header header
Header.
Definition: ena.h:324
uint64_t address
Address.
Definition: ena.h:390
Host information.
Definition: ena.h:167
uint8_t reserved[2]
Reserved.
Definition: ena.h:371
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:135
#define ENA_RX_COUNT
Number of receive queue entries.
Definition: ena.h:34
uint64_t info
Host info base address.
Definition: ena.h:159
uint8_t reserved_a
Reserved.
Definition: ena.h:561
uint8_t rx_ids[ENA_RX_COUNT]
Receive buffer IDs.
Definition: ena.h:763
Create completion queue request.
Definition: ena.h:322
uint8_t mask
Actual number of entries minus one.
Definition: ena.h:716
uint8_t reserved_a
Reserved.
Definition: ena.h:258
uint8_t reserved_b[8]
Reserved.
Definition: ena.h:270
size_t len
Total length of entries.
Definition: ena.h:650
static unsigned int unsigned int unsigned int size_t uint8_t * ids
Definition: ena.h:679
unsigned int doorbell
Doorbell register offset.
Definition: ena.h:648
uint8_t count
Number of entries.
Definition: ena.h:660
struct ena_aq_header header
Header.
Definition: ena.h:386
uint8_t flags
Flags.
Definition: ena.h:392
uint8_t * ids
Buffer IDs.
Definition: ena.h:646
unsigned int prod
Producer counter.
Definition: ena.h:652
uint16_t id
Completion queue identifier.
Definition: ena.h:369
uint8_t reserved[2]
Reserved.
Definition: ena.h:423
uint64_t linux_features
Linux network device features.
Definition: ena.h:181
struct ena_tx_cqe * tx
Transmit completion queue entries.
Definition: ena.h:693
Create submission queue response.
Definition: ena.h:282
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
uint32_t doorbell
Doorbell register offset.
Definition: ena.h:290
uint8_t reserved_a[3]
Reserved.
Definition: ena.h:620
struct ena_get_stats_rsp get_stats
Get statistics.
Definition: ena.h:511
Transmit submission queue entry.
Definition: ena.h:557
struct ena_qp tx
Transmit queue.
Definition: ena.h:755
uint8_t reserved[2]
Reserved.
Definition: ena.h:609
struct ena_set_feature_req set_feature
Set feature.
Definition: ena.h:489
uint16_t count
Number of entries.
Definition: ena.h:264
union ena_sq::@39 sqe
Entries.
struct ena_aenq aenq
Async event notification queue.
Definition: ena.h:753
Transmit completion queue entry.
Definition: ena.h:601
Get feature response.
Definition: ena.h:400
unsigned long long uint64_t
Definition: stdint.h:13
uint8_t id
Request identifier.
Definition: ena.h:567
Admin queue.
Definition: ena.h:517
union ena_cq::@40 cqe
Entries.
uint32_t features
Supported features.
Definition: ena.h:127
uint16_t count
Number of entries.
Definition: ena.h:330
uint32_t mtu
Maximum MTU.
Definition: ena.h:139
uint8_t direction
Direction.
Definition: ena.h:14
struct ena_acq_header header
Header.
Definition: ena.h:402
static unsigned int unsigned int unsigned int max
Definition: ena.h:678
uint64_t rx_drops
Receive drop count.
Definition: ena.h:471
uint16_t len
Length.
Definition: ena.h:575
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:710
Destroy completion queue request.
Definition: ena.h:365
uint32_t llq_desc
LLQ descriptor ring offset.
Definition: ena.h:292
uint8_t reserved_a[4]
Reserved.
Definition: ena.h:129
uint32_t doorbell
Doorbell register offset.
Definition: ena.h:356
uint32_t features
Supported features.
Definition: ena.h:191
unsigned int phase
Phase.
Definition: ena.h:706
uint16_t spec
ENA specification version.
Definition: ena.h:183
uint64_t address
Address.
Definition: ena.h:585
struct ena_aq_header header
Header.
Definition: ena.h:367
struct ena_aq_header header
Header.
Definition: ena.h:254
#define ENA_TX_COUNT
Number of transmit queue entries.
Definition: ena.h:31
uint64_t address
Base address.
Definition: ena.h:334
unsigned int doorbell
Doorbell register offset.
Definition: ena.h:700
struct ena_aq_header header
Header.
Definition: ena.h:413
void * regs
Registers.
Definition: ena.h:745
uint32_t dist
Operating system distribution (numeric)
Definition: ena.h:173
uint8_t tx_ids[ENA_TX_COUNT]
Transmit buffer IDs.
Definition: ena.h:759
uint32_t debug_len
Debug area size.
Definition: ena.h:163
uint32_t llq_data
LLQ header offset.
Definition: ena.h:294
Completion queue.
Definition: ena.h:689
uint32_t enabled
Bitmask of enabled AENQ groups (host -> device)
Definition: ena.h:150
Submission queue.
Definition: ena.h:635
struct ena_destroy_sq_rsp destroy_sq
Destroy submission queue.
Definition: ena.h:503
Feature.
Definition: ena.h:231
uint8_t status
Status.
Definition: ena.h:105
uint8_t reserved[2]
Reserved.
Definition: ena.h:288
size_t len
Total length of entries.
Definition: ena.h:702
struct ena_get_feature_rsp get_feature
Get feature.
Definition: ena.h:509
uint16_t id
Request identifier.
Definition: ena.h:603
uint16_t group
Type of event.
Definition: ena.h:537
struct ena_acq_header header
Header.
Definition: ena.h:377
A hardware device.
Definition: device.h:73
uint64_t writeback
Writeback address.
Definition: ena.h:268
uint8_t reserved
Reserved.
Definition: ena.h:309
uint8_t reserved_a[2]
Reserved.
Definition: ena.h:189
uint64_t tx_packets
Transmit packet count.
Definition: ena.h:465
uint16_t id
Request identifier.
Definition: ena.h:581
uint8_t id
Feature identifier.
Definition: ena.h:394
uint16_t cpus
Number of CPUs.
Definition: ena.h:187
uint32_t len
Length.
Definition: ena.h:415
uint16_t cons
Consumer index.
Definition: ena.h:611
Host attributes.
Definition: ena.h:157
uint8_t reserved_b[2]
Reserved.
Definition: ena.h:137
union ena_aq_req * req
Requests.
Definition: ena.h:519
Transmit.
Definition: ena.h:243
uint64_t address
Base address.
Definition: ena.h:266
uint16_t cq_id
Completion queue identifier.
Definition: ena.h:262
uint8_t reserved
Reserved.
Definition: ena.h:103
ena_sq_policy
Submission queue policy.
Definition: ena.h:274
unsigned int cons
Consumer counter.
Definition: ena.h:529
uint8_t flags
Flags.
Definition: ena.h:607
unsigned int cons
Consumer counter.
Definition: ena.h:704
uint16_t policy
Policy.
Definition: ena.h:260
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:328
uint16_t count
Number of entries.
Definition: ena.h:22
uint8_t flags
Flags.
Definition: ena.h:92
uint16_t ext
Extended status.
Definition: ena.h:109
uint16_t busdevfn
PCI bus:dev.fn address.
Definition: ena.h:185
struct ena_aenq_event * evt
Events.
Definition: ena.h:553
uint64_t debug
Debug area base address.
Definition: ena.h:161
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
uint8_t id
Feature identifier.
Definition: ena.h:421
unsigned int phase
Phase.
Definition: ena.h:654
struct ena_get_stats_req get_stats
Get statistics.
Definition: ena.h:491
uint32_t supported
Bitmask of supported AENQ groups (device -> host)
Definition: ena.h:148
uint16_t count
Actual number of entries.
Definition: ena.h:352
struct ena_create_cq_req create_cq
Create completion queue.
Definition: ena.h:483
struct ena_destroy_cq_req destroy_cq
Destroy completion queue.
Definition: ena.h:485
Create completion queue response.
Definition: ena.h:346
uint8_t direction
Direction.
Definition: ena.h:256
Create submission queue request.
Definition: ena.h:252
struct ena_rx_cqe * rx
Receive completion queue entries.
Definition: ena.h:695
struct ena_cq cq
Completion queue.
Definition: ena.h:739
uint8_t flags
Flags.
Definition: ena.h:622
uint32_t vector
MSI-X vector.
Definition: ena.h:332
struct ena_aq_header header
Header.
Definition: ena.h:303
uint8_t flags
Flags.
Definition: ena.h:563
Destroy submission queue response.
Definition: ena.h:313
struct ena_acq_header header
Header.
Definition: ena.h:499
uint32_t len
Length.
Definition: ena.h:388
uint8_t pad[64]
Padding.
Definition: ena.h:513
struct ena_acq_header header
Header.
Definition: ena.h:315
uint16_t id
Completion queue identifier.
Definition: ena.h:708
unsigned char uint8_t
Definition: stdint.h:10
uint8_t reserved_b[2]
Reserved.
Definition: ena.h:442
struct ena_host_attributes host
Host attributes.
Definition: ena.h:237
uint8_t actual
Actual number of entries.
Definition: ena.h:714
Destroy submission queue request.
Definition: ena.h:301
struct ena_create_cq_rsp create_cq
Create completion queue.
Definition: ena.h:505
#define ETH_ALEN
Definition: if_ether.h:8
uint16_t queue
Queue ID.
Definition: ena.h:444
ena_sq_direction
Submission queue direction.
Definition: ena.h:241
uint32_t node
NUMA node register offset.
Definition: ena.h:354
unsigned int uint32_t
Definition: stdint.h:12
uint8_t requested
Requested number of entries.
Definition: ena.h:712
struct ena_acq acq
Admin completion queue.
Definition: ena.h:751
Async event notification queue config.
Definition: ena.h:146
uint32_t version
Driver version.
Definition: ena.h:179
struct ena_create_sq_rsp create_sq
Create submission queue.
Definition: ena.h:501
uint8_t reserved_b[3]
Reserved.
Definition: ena.h:565
uint16_t id
Submission queue identifier.
Definition: ena.h:305
struct io_buffer * rx_iobuf[ENA_RX_COUNT]
Receive I/O buffers, indexed by buffer ID.
Definition: ena.h:765
uint8_t reserved_a
Reserved.
Definition: ena.h:577
Async event notification queue event.
Definition: ena.h:535
uint8_t reserved_b[8]
Reserved.
Definition: ena.h:628
Use host memory.
Definition: ena.h:276
uint8_t reserved
Reserved.
Definition: ena.h:88
Memory is contiguous.
Definition: ena.h:278
uint8_t intr
Interrupts enabled.
Definition: ena.h:326
uint64_t address
Address.
Definition: ena.h:417
uint8_t max
Maximum fill level.
Definition: ena.h:662
struct ena_acq_header header
Header.
Definition: ena.h:348
uint16_t syndrome
ID of event.
Definition: ena.h:539
A named feature.
Definition: features.h:78
struct ena_get_feature_req get_feature
Get feature.
Definition: ena.h:487
Get statistics response.
Definition: ena.h:459
struct ena_host_info * info
Host info.
Definition: ena.h:747
struct ena_sq sq
Submission queue.
Definition: ena.h:737
uint64_t rx_bytes
Receive byte count.
Definition: ena.h:467
uint32_t version
Device version.
Definition: ena.h:125
uint16_t len
Length.
Definition: ena.h:624
uint16_t id
Request identifier.
Definition: ena.h:626
Receive submission queue entry.
Definition: ena.h:573
uint8_t pad[64]
Padding.
Definition: ena.h:493
uint8_t flags
Flags.
Definition: ena.h:107
uint64_t address
Address.
Definition: ena.h:569
Receive completion queue entry.
Definition: ena.h:618
uint8_t direction
Direction.
Definition: ena.h:307
Admin completion queue response.
Definition: ena.h:497
uint8_t flags
Flags.
Definition: ena.h:419
uint32_t physical
Physical address width.
Definition: ena.h:131
uint8_t opcode
Opcode.
Definition: ena.h:90
Async event notification queue.
Definition: ena.h:551
union ena_acq_rsp * rsp
Responses.
Definition: ena.h:527
uint64_t tx_bytes
Transmit byte count.
Definition: ena.h:463
uint16_t id
Submission queue identifier.
Definition: ena.h:286
uint8_t flags
Flags.
Definition: ena.h:579
struct ena_acq_header header
Header.
Definition: ena.h:461
uint16_t len
Length.
Definition: ena.h:559
char dist_str[128]
Operating system distribution (string)
Definition: ena.h:171
uint64_t timestamp
Timestamp.
Definition: ena.h:545
uint16_t id
Submission queue identifier.
Definition: ena.h:656
uint8_t scope
Scope.
Definition: ena.h:440
char kernel_str[32]
Kernel version (string)
Definition: ena.h:175
struct ena_destroy_sq_req destroy_sq
Destroy submission queue.
Definition: ena.h:481
struct ena_rx_sqe * rx
Receive submission queue entries.
Definition: ena.h:641
uint8_t fill
Fill level (limited to completion queue size)
Definition: ena.h:664
Get feature request.
Definition: ena.h:384
uint8_t flags
Phase.
Definition: ena.h:541
Device attributes.
Definition: ena.h:121
An ENA network card.
Definition: ena.h:743
uint32_t kernel
Kernel version (numeric)
Definition: ena.h:177
uint8_t reserved[2]
Reserved.
Definition: ena.h:396
Admin queue request.
Definition: ena.h:475
Admin queue entry header.
Definition: ena.h:84
uint8_t id
Request identifier.
Definition: ena.h:86
uint8_t status
Status.
Definition: ena.h:605
struct ena_aq_header header
Header.
Definition: ena.h:477
struct ena_aq_header header
Header.
Definition: ena.h:434
unsigned int prod
Producer counter.
Definition: ena.h:521
struct io_buffer * tx_iobuf[ENA_TX_COUNT]
Transmit I/O buffers, indexed by buffer ID.
Definition: ena.h:761
uint64_t rx_packets
Receive packet count.
Definition: ena.h:469
Admin completion queue entry header.
Definition: ena.h:99
struct ena_aenq_config aenq
Async event notification queue config.
Definition: ena.h:235
union ena_feature __attribute__
Admin completion queue.
Definition: ena.h:525
Receive.
Definition: ena.h:245
Set feature request.
Definition: ena.h:411
struct ena_destroy_cq_rsp destroy_cq
Destroy completion queue.
Definition: ena.h:507
uint8_t direction
Direction.
Definition: ena.h:658
void * raw
Raw data.
Definition: ena.h:643
struct ena_create_sq_req create_sq
Create submission queue.
Definition: ena.h:479
Get statistics request.
Definition: ena.h:432
unsigned int phase
Phase.
Definition: ena.h:531
uint16_t device
Device ID.
Definition: ena.h:446
uint16_t cons
Consumer index.
Definition: ena.h:111
uint32_t implementation
Implementation.
Definition: ena.h:123
uint8_t data[48]
Additional event data.
Definition: ena.h:547
uint8_t id
Request identifier.
Definition: ena.h:101
A persistent I/O buffer.
Definition: iobuf.h:33
uint32_t type
Operating system type.
Definition: ena.h:169