iPXE
ena.h
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1 #ifndef _ENA_H
2 #define _ENA_H
3 
4 /** @file
5  *
6  * Amazon ENA network driver
7  *
8  */
9 
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11 
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14 
15 /** BAR size */
16 #define ENA_BAR_SIZE 16384
17 
18 /** Queue alignment */
19 #define ENA_ALIGN 4096
20 
21 /** Number of admin queue entries */
22 #define ENA_AQ_COUNT 2
23 
24 /** Number of admin completion queue entries */
25 #define ENA_ACQ_COUNT 2
26 
27 /** Number of transmit queue entries */
28 #define ENA_TX_COUNT 16
29 
30 /** Number of receive queue entries */
31 #define ENA_RX_COUNT 16
32 
33 /** Base address low register offset */
34 #define ENA_BASE_LO 0x0
35 
36 /** Base address high register offset */
37 #define ENA_BASE_HI 0x4
38 
39 /** Capability register value */
40 #define ENA_CAPS( count, size ) ( ( (size) << 16 ) | ( (count) << 0 ) )
41 
42 /** Admin queue base address register */
43 #define ENA_AQ_BASE 0x10
44 
45 /** Admin queue capabilities register */
46 #define ENA_AQ_CAPS 0x18
47 
48 /** Admin completion queue base address register */
49 #define ENA_ACQ_BASE 0x20
50 
51 /** Admin completion queue capabilities register */
52 #define ENA_ACQ_CAPS 0x28
53 
54 /** Admin queue doorbell register */
55 #define ENA_AQ_DB 0x2c
56 
57 /** Maximum time to wait for admin requests */
58 #define ENA_ADMIN_MAX_WAIT_MS 5000
59 
60 /** Device control register */
61 #define ENA_CTRL 0x54
62 #define ENA_CTRL_RESET 0x00000001UL /**< Reset */
63 
64 /** Maximum time to wait for reset */
65 #define ENA_RESET_MAX_WAIT_MS 1000
66 
67 /** Device status register */
68 #define ENA_STAT 0x58
69 #define ENA_STAT_READY 0x00000001UL /**< Ready */
70 
71 /** Admin queue entry header */
72 struct ena_aq_header {
73  /** Request identifier */
75  /** Reserved */
77  /** Opcode */
79  /** Flags */
81 } __attribute__ (( packed ));
82 
83 /** Admin queue ownership phase flag */
84 #define ENA_AQ_PHASE 0x01
85 
86 /** Admin completion queue entry header */
88  /** Request identifier */
90  /** Reserved */
92  /** Status */
94  /** Flags */
96  /** Extended status */
98  /** Consumer index */
100 } __attribute__ (( packed ));
101 
102 /** Admin completion queue ownership phase flag */
103 #define ENA_ACQ_PHASE 0x01
104 
105 /** Device attributes */
106 #define ENA_DEVICE_ATTRIBUTES 1
107 
108 /** Device attributes */
110  /** Implementation */
112  /** Device version */
114  /** Supported features */
116  /** Reserved */
118  /** Physical address width */
120  /** Virtual address width */
121  uint32_t virtual;
122  /** MAC address */
124  /** Reserved */
126  /** Maximum MTU */
128 } __attribute__ (( packed ));
129 
130 /** Feature */
131 union ena_feature {
132  /** Device attributes */
134 };
135 
136 /** Submission queue direction */
138  /** Transmit */
139  ENA_SQ_TX = 0x20,
140  /** Receive */
141  ENA_SQ_RX = 0x40,
142 };
143 
144 /** Create submission queue */
145 #define ENA_CREATE_SQ 1
146 
147 /** Create submission queue request */
149  /** Header */
151  /** Direction */
153  /** Reserved */
155  /** Policy */
157  /** Completion queue identifier */
159  /** Number of entries */
161  /** Base address */
163  /** Writeback address */
165  /** Reserved */
167 } __attribute__ (( packed ));
168 
169 /** Submission queue policy */
171  /** Use host memory */
173  /** Memory is contiguous */
175 };
176 
177 /** Create submission queue response */
179  /** Header */
181  /** Submission queue identifier */
183  /** Reserved */
185  /** Doorbell register offset */
187  /** LLQ descriptor ring offset */
189  /** LLQ header offset */
191 } __attribute__ (( packed ));
192 
193 /** Destroy submission queue */
194 #define ENA_DESTROY_SQ 2
195 
196 /** Destroy submission queue request */
198  /** Header */
200  /** Submission queue identifier */
202  /** Direction */
204  /** Reserved */
206 } __attribute__ (( packed ));
207 
208 /** Destroy submission queue response */
210  /** Header */
212 } __attribute__ (( packed ));
213 
214 /** Create completion queue */
215 #define ENA_CREATE_CQ 3
216 
217 /** Create completion queue request */
219  /** Header */
221  /** Interrupts enabled */
223  /** Entry size (in 32-bit words) */
225  /** Number of entries */
227  /** MSI-X vector */
229  /** Base address */
231 } __attribute__ (( packed ));
232 
233 /** Create completion queue response */
235  /** Header */
237  /** Completion queue identifier */
239  /** Actual number of entries */
241  /** NUMA node register offset */
243  /** Doorbell register offset */
245  /** Interrupt unmask register offset */
247 } __attribute__ (( packed ));
248 
249 /** Destroy completion queue */
250 #define ENA_DESTROY_CQ 4
251 
252 /** Destroy completion queue request */
254  /** Header */
256  /** Completion queue identifier */
258  /** Reserved */
260 } __attribute__ (( packed ));
261 
262 /** Destroy completion queue response */
264  /** Header */
266 } __attribute__ (( packed ));
267 
268 /** Get feature */
269 #define ENA_GET_FEATURE 8
270 
271 /** Get feature request */
273  /** Header */
275  /** Length */
277  /** Address */
279  /** Flags */
281  /** Feature identifier */
283  /** Reserved */
285 } __attribute__ (( packed ));
286 
287 /** Get feature response */
289  /** Header */
291  /** Feature */
293 } __attribute__ (( packed ));
294 
295 /** Get statistics */
296 #define ENA_GET_STATS 11
297 
298 /** Get statistics request */
300  /** Header */
302  /** Reserved */
304  /** Type */
306  /** Scope */
308  /** Reserved */
310  /** Queue ID */
312  /** Device ID */
314 } __attribute__ (( packed ));
315 
316 /** Basic statistics */
317 #define ENA_STATS_TYPE_BASIC 0
318 
319 /** Ethernet statistics */
320 #define ENA_STATS_SCOPE_ETH 1
321 
322 /** My device */
323 #define ENA_DEVICE_MINE 0xffff
324 
325 /** Get statistics response */
327  /** Header */
329  /** Transmit byte count */
331  /** Transmit packet count */
333  /** Receive byte count */
335  /** Receive packet count */
337  /** Receive drop count */
339 } __attribute__ (( packed ));
340 
341 /** Admin queue request */
342 union ena_aq_req {
343  /** Header */
345  /** Create submission queue */
347  /** Destroy submission queue */
349  /** Create completion queue */
351  /** Destroy completion queue */
353  /** Get feature */
355  /** Get statistics */
357  /** Padding */
359 };
360 
361 /** Admin completion queue response */
362 union ena_acq_rsp {
363  /** Header */
365  /** Create submission queue */
367  /** Destroy submission queue */
369  /** Create completion queue */
371  /** Destroy completion queue */
373  /** Get feature */
375  /** Get statistics */
377  /** Padding */
379 };
380 
381 /** Admin queue */
382 struct ena_aq {
383  /** Requests */
384  union ena_aq_req *req;
385  /** Producer counter */
386  unsigned int prod;
387 };
388 
389 /** Admin completion queue */
390 struct ena_acq {
391  /** Responses */
392  union ena_acq_rsp *rsp;
393  /** Consumer counter */
394  unsigned int cons;
395  /** Phase */
396  unsigned int phase;
397 };
398 
399 /** Transmit submission queue entry */
400 struct ena_tx_sqe {
401  /** Length */
403  /** Reserved */
405  /** Flags */
407  /** Reserved */
409  /** Request identifier */
411  /** Address */
413 } __attribute__ (( packed ));
414 
415 /** Receive submission queue entry */
416 struct ena_rx_sqe {
417  /** Length */
419  /** Reserved */
421  /** Flags */
423  /** Request identifier */
425  /** Reserved */
427  /** Address */
429 } __attribute__ (( packed ));
430 
431 /** Submission queue ownership phase flag */
432 #define ENA_SQE_PHASE 0x01
433 
434 /** This is the first descriptor */
435 #define ENA_SQE_FIRST 0x04
436 
437 /** This is the last descriptor */
438 #define ENA_SQE_LAST 0x08
439 
440 /** Request completion */
441 #define ENA_SQE_CPL 0x10
442 
443 /** Transmit completion queue entry */
444 struct ena_tx_cqe {
445  /** Request identifier */
447  /** Status */
449  /** Flags */
451  /** Reserved */
453  /** Consumer index */
455 } __attribute__ (( packed ));
456 
457 /** Receive completion queue entry */
458 struct ena_rx_cqe {
459  /** Reserved */
461  /** Flags */
463  /** Length */
465  /** Request identifier */
467  /** Reserved */
469 } __attribute__ (( packed ));
470 
471 /** Completion queue ownership phase flag */
472 #define ENA_CQE_PHASE 0x01
473 
474 /** Submission queue */
475 struct ena_sq {
476  /** Entries */
477  union {
478  /** Transmit submission queue entries */
479  struct ena_tx_sqe *tx;
480  /** Receive submission queue entries */
481  struct ena_rx_sqe *rx;
482  /** Raw data */
483  void *raw;
484  } sqe;
485  /** Doorbell register offset */
486  unsigned int doorbell;
487  /** Total length of entries */
488  size_t len;
489  /** Producer counter */
490  unsigned int prod;
491  /** Phase */
492  unsigned int phase;
493  /** Submission queue identifier */
495  /** Direction */
497  /** Number of entries */
499 };
500 
501 /**
502  * Initialise submission queue
503  *
504  * @v sq Submission queue
505  * @v direction Direction
506  * @v count Number of entries
507  * @v size Size of each entry
508  */
509 static inline __attribute__ (( always_inline )) void
510 ena_sq_init ( struct ena_sq *sq, unsigned int direction, unsigned int count,
511  size_t size ) {
512 
513  sq->len = ( count * size );
514  sq->direction = direction;
515  sq->count = count;
516 }
517 
518 /** Completion queue */
519 struct ena_cq {
520  /** Entries */
521  union {
522  /** Transmit completion queue entries */
523  struct ena_tx_cqe *tx;
524  /** Receive completion queue entries */
525  struct ena_rx_cqe *rx;
526  /** Raw data */
527  void *raw;
528  } cqe;
529  /** Doorbell register offset */
530  unsigned int doorbell;
531  /** Total length of entries */
532  size_t len;
533  /** Consumer counter */
534  unsigned int cons;
535  /** Phase */
536  unsigned int phase;
537  /** Completion queue identifier */
539  /** Entry size (in 32-bit words) */
541  /** Requested number of entries */
543  /** Actual number of entries */
545  /** Actual number of entries minus one */
547 };
548 
549 /**
550  * Initialise completion queue
551  *
552  * @v cq Completion queue
553  * @v count Number of entries
554  * @v size Size of each entry
555  */
556 static inline __attribute__ (( always_inline )) void
557 ena_cq_init ( struct ena_cq *cq, unsigned int count, size_t size ) {
558 
559  cq->len = ( count * size );
560  cq->size = ( size / sizeof ( uint32_t ) );
562 }
563 
564 /** Queue pair */
565 struct ena_qp {
566  /** Submission queue */
567  struct ena_sq sq;
568  /** Completion queue */
569  struct ena_cq cq;
570 };
571 
572 /** An ENA network card */
573 struct ena_nic {
574  /** Registers */
575  void *regs;
576  /** Admin queue */
577  struct ena_aq aq;
578  /** Admin completion queue */
579  struct ena_acq acq;
580  /** Transmit queue */
581  struct ena_qp tx;
582  /** Receive queue */
583  struct ena_qp rx;
584  /** Receive I/O buffers */
586 };
587 
588 #endif /* _ENA_H */
uint8_t reserved_b[2]
Reserved.
Definition: ena.h:426
Destroy completion queue response.
Definition: ena.h:263
uint8_t reserved_a[12]
Reserved.
Definition: ena.h:303
struct ena_aq aq
Admin queue.
Definition: ena.h:577
Queue pair.
Definition: ena.h:565
uint16_t id
Completion queue identifier.
Definition: ena.h:238
uint32_t intr
Interrupt unmask register offset.
Definition: ena.h:246
struct ena_tx_sqe * tx
Transmit submission queue entries.
Definition: ena.h:479
struct ena_qp rx
Receive queue.
Definition: ena.h:583
uint8_t type
Type.
Definition: ena.h:305
struct ena_acq_header header
Header.
Definition: ena.h:180
unsigned short uint16_t
Definition: stdint.h:11
void * raw
Raw data.
Definition: ena.h:527
struct ena_aq_header header
Header.
Definition: ena.h:220
uint64_t address
Address.
Definition: ena.h:278
uint8_t reserved[2]
Reserved.
Definition: ena.h:259
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:123
#define ENA_RX_COUNT
Number of receive queue entries.
Definition: ena.h:31
uint8_t reserved_a
Reserved.
Definition: ena.h:404
Create completion queue request.
Definition: ena.h:218
uint8_t mask
Actual number of entries minus one.
Definition: ena.h:546
uint8_t reserved_a
Reserved.
Definition: ena.h:154
uint8_t reserved_b[8]
Reserved.
Definition: ena.h:166
size_t len
Total length of entries.
Definition: ena.h:488
unsigned int doorbell
Doorbell register offset.
Definition: ena.h:486
uint8_t count
Number of entries.
Definition: ena.h:498
struct ena_aq_header header
Header.
Definition: ena.h:274
uint8_t flags
Flags.
Definition: ena.h:280
unsigned int prod
Producer counter.
Definition: ena.h:490
uint16_t id
Completion queue identifier.
Definition: ena.h:257
struct ena_tx_cqe * tx
Transmit completion queue entries.
Definition: ena.h:523
Create submission queue response.
Definition: ena.h:178
uint32_t doorbell
Doorbell register offset.
Definition: ena.h:186
uint8_t reserved_a[3]
Reserved.
Definition: ena.h:460
struct ena_get_stats_rsp get_stats
Get statistics.
Definition: ena.h:376
Transmit submission queue entry.
Definition: ena.h:400
struct ena_qp tx
Transmit queue.
Definition: ena.h:581
uint8_t reserved[2]
Reserved.
Definition: ena.h:452
uint16_t count
Number of entries.
Definition: ena.h:160
Transmit completion queue entry.
Definition: ena.h:444
Get feature response.
Definition: ena.h:288
unsigned long long uint64_t
Definition: stdint.h:13
uint8_t id
Request identifier.
Definition: ena.h:410
Admin queue.
Definition: ena.h:382
uint32_t features
Supported features.
Definition: ena.h:115
uint16_t count
Number of entries.
Definition: ena.h:226
uint32_t mtu
Maximum MTU.
Definition: ena.h:127
uint8_t direction
Direction.
Definition: ena.h:14
struct ena_acq_header header
Header.
Definition: ena.h:290
uint64_t rx_drops
Receive drop count.
Definition: ena.h:338
uint16_t len
Length.
Definition: ena.h:418
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:540
Destroy completion queue request.
Definition: ena.h:253
uint32_t llq_desc
LLQ descriptor ring offset.
Definition: ena.h:188
uint8_t reserved_a[4]
Reserved.
Definition: ena.h:117
uint32_t doorbell
Doorbell register offset.
Definition: ena.h:244
unsigned int phase
Phase.
Definition: ena.h:536
uint64_t address
Address.
Definition: ena.h:428
struct ena_aq_header header
Header.
Definition: ena.h:255
struct ena_aq_header header
Header.
Definition: ena.h:150
union ena_sq::@38 sqe
Entries.
uint64_t address
Base address.
Definition: ena.h:230
unsigned int doorbell
Doorbell register offset.
Definition: ena.h:530
void * regs
Registers.
Definition: ena.h:575
uint32_t llq_data
LLQ header offset.
Definition: ena.h:190
Completion queue.
Definition: ena.h:519
Submission queue.
Definition: ena.h:475
struct ena_destroy_sq_rsp destroy_sq
Destroy submission queue.
Definition: ena.h:368
Feature.
Definition: ena.h:131
uint8_t status
Status.
Definition: ena.h:93
uint8_t reserved[2]
Reserved.
Definition: ena.h:184
size_t len
Total length of entries.
Definition: ena.h:532
struct ena_get_feature_rsp get_feature
Get feature.
Definition: ena.h:374
uint16_t id
Request identifier.
Definition: ena.h:446
struct ena_acq_header header
Header.
Definition: ena.h:265
A hardware device.
Definition: device.h:73
uint64_t writeback
Writeback address.
Definition: ena.h:164
uint8_t reserved
Reserved.
Definition: ena.h:205
uint64_t tx_packets
Transmit packet count.
Definition: ena.h:332
uint16_t id
Request identifier.
Definition: ena.h:424
uint8_t id
Feature identifier.
Definition: ena.h:282
uint16_t cons
Consumer index.
Definition: ena.h:454
uint8_t reserved_b[2]
Reserved.
Definition: ena.h:125
union ena_aq_req * req
Requests.
Definition: ena.h:384
Transmit.
Definition: ena.h:139
uint64_t address
Base address.
Definition: ena.h:162
uint16_t cq_id
Completion queue identifier.
Definition: ena.h:158
uint8_t reserved
Reserved.
Definition: ena.h:91
ena_sq_policy
Submission queue policy.
Definition: ena.h:170
unsigned int cons
Consumer counter.
Definition: ena.h:394
uint8_t flags
Flags.
Definition: ena.h:450
unsigned int cons
Consumer counter.
Definition: ena.h:534
uint16_t policy
Policy.
Definition: ena.h:156
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:224
uint8_t flags
Flags.
Definition: ena.h:80
uint16_t ext
Extended status.
Definition: ena.h:97
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
unsigned int phase
Phase.
Definition: ena.h:492
struct ena_get_stats_req get_stats
Get statistics.
Definition: ena.h:356
uint16_t count
Actual number of entries.
Definition: ena.h:240
struct ena_create_cq_req create_cq
Create completion queue.
Definition: ena.h:350
struct ena_destroy_cq_req destroy_cq
Destroy completion queue.
Definition: ena.h:352
Create completion queue response.
Definition: ena.h:234
uint8_t direction
Direction.
Definition: ena.h:152
Create submission queue request.
Definition: ena.h:148
struct ena_rx_cqe * rx
Receive completion queue entries.
Definition: ena.h:525
struct ena_cq cq
Completion queue.
Definition: ena.h:569
uint8_t flags
Flags.
Definition: ena.h:462
uint32_t vector
MSI-X vector.
Definition: ena.h:228
struct ena_aq_header header
Header.
Definition: ena.h:199
uint8_t flags
Flags.
Definition: ena.h:406
Destroy submission queue response.
Definition: ena.h:209
struct ena_acq_header header
Header.
Definition: ena.h:364
uint32_t len
Length.
Definition: ena.h:276
uint8_t pad[64]
Padding.
Definition: ena.h:378
struct ena_acq_header header
Header.
Definition: ena.h:211
uint16_t id
Completion queue identifier.
Definition: ena.h:538
unsigned char uint8_t
Definition: stdint.h:10
uint8_t reserved_b[2]
Reserved.
Definition: ena.h:309
uint8_t actual
Actual number of entries.
Definition: ena.h:544
Destroy submission queue request.
Definition: ena.h:197
struct ena_create_cq_rsp create_cq
Create completion queue.
Definition: ena.h:370
#define ETH_ALEN
Definition: if_ether.h:8
uint16_t queue
Queue ID.
Definition: ena.h:311
ena_sq_direction
Submission queue direction.
Definition: ena.h:137
uint32_t node
NUMA node register offset.
Definition: ena.h:242
unsigned int uint32_t
Definition: stdint.h:12
uint8_t requested
Requested number of entries.
Definition: ena.h:542
struct ena_acq acq
Admin completion queue.
Definition: ena.h:579
struct ena_create_sq_rsp create_sq
Create submission queue.
Definition: ena.h:366
uint8_t reserved_b[3]
Reserved.
Definition: ena.h:408
uint16_t id
Submission queue identifier.
Definition: ena.h:201
struct io_buffer * rx_iobuf[ENA_RX_COUNT]
Receive I/O buffers.
Definition: ena.h:585
uint8_t reserved_a
Reserved.
Definition: ena.h:420
uint8_t reserved_b[8]
Reserved.
Definition: ena.h:468
Use host memory.
Definition: ena.h:172
union ena_cq::@39 cqe
Entries.
uint8_t reserved
Reserved.
Definition: ena.h:76
Memory is contiguous.
Definition: ena.h:174
uint8_t intr
Interrupts enabled.
Definition: ena.h:222
struct ena_acq_header header
Header.
Definition: ena.h:236
A named feature.
Definition: features.h:78
struct ena_get_feature_req get_feature
Get feature.
Definition: ena.h:354
Get statistics response.
Definition: ena.h:326
struct ena_sq sq
Submission queue.
Definition: ena.h:567
uint64_t rx_bytes
Receive byte count.
Definition: ena.h:334
uint32_t version
Device version.
Definition: ena.h:113
uint16_t len
Length.
Definition: ena.h:464
uint16_t id
Request identifier.
Definition: ena.h:466
Receive submission queue entry.
Definition: ena.h:416
uint8_t pad[64]
Padding.
Definition: ena.h:358
uint8_t flags
Flags.
Definition: ena.h:95
uint64_t address
Address.
Definition: ena.h:412
Receive completion queue entry.
Definition: ena.h:458
uint8_t direction
Direction.
Definition: ena.h:203
Admin completion queue response.
Definition: ena.h:362
uint16_t count
Number of entries.
Definition: ena.h:22
uint32_t physical
Physical address width.
Definition: ena.h:119
uint8_t opcode
Opcode.
Definition: ena.h:78
union ena_acq_rsp * rsp
Responses.
Definition: ena.h:392
uint64_t tx_bytes
Transmit byte count.
Definition: ena.h:330
uint16_t id
Submission queue identifier.
Definition: ena.h:182
uint8_t flags
Flags.
Definition: ena.h:422
struct ena_acq_header header
Header.
Definition: ena.h:328
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
uint16_t len
Length.
Definition: ena.h:402
uint16_t id
Submission queue identifier.
Definition: ena.h:494
uint8_t scope
Scope.
Definition: ena.h:307
struct ena_destroy_sq_req destroy_sq
Destroy submission queue.
Definition: ena.h:348
struct ena_rx_sqe * rx
Receive submission queue entries.
Definition: ena.h:481
Get feature request.
Definition: ena.h:272
Device attributes.
Definition: ena.h:109
An ENA network card.
Definition: ena.h:573
uint8_t reserved[2]
Reserved.
Definition: ena.h:284
Admin queue request.
Definition: ena.h:342
Admin queue entry header.
Definition: ena.h:72
uint8_t id
Request identifier.
Definition: ena.h:74
uint8_t status
Status.
Definition: ena.h:448
struct ena_aq_header header
Header.
Definition: ena.h:344
struct ena_aq_header header
Header.
Definition: ena.h:301
unsigned int prod
Producer counter.
Definition: ena.h:386
uint64_t rx_packets
Receive packet count.
Definition: ena.h:336
Admin completion queue entry header.
Definition: ena.h:87
union ena_feature __attribute__
Admin completion queue.
Definition: ena.h:390
Receive.
Definition: ena.h:141
struct ena_destroy_cq_rsp destroy_cq
Destroy completion queue.
Definition: ena.h:372
uint8_t direction
Direction.
Definition: ena.h:496
void * raw
Raw data.
Definition: ena.h:483
struct ena_create_sq_req create_sq
Create submission queue.
Definition: ena.h:346
Get statistics request.
Definition: ena.h:299
unsigned int phase
Phase.
Definition: ena.h:396
uint16_t device
Device ID.
Definition: ena.h:313
uint16_t cons
Consumer index.
Definition: ena.h:99
uint32_t implementation
Implementation.
Definition: ena.h:111
uint8_t id
Request identifier.
Definition: ena.h:89
A persistent I/O buffer.
Definition: iobuf.h:32