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iPXE
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16550-compatible UART More...
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Data Structures | |
| struct | ns16550_uart |
| A 16550-compatible UART. More... | |
Macros | |
| #define | NS16550_LEN 8 |
| Length of register region. | |
| #define | NS16550_THR 0x00 |
| Transmitter holding register. | |
| #define | NS16550_RBR 0x00 |
| Receiver buffer register. | |
| #define | NS16550_IER 0x01 |
| Interrupt enable register. | |
| #define | NS16550_FCR 0x02 |
| FIFO control register. | |
| #define | NS16550_FCR_FE 0x01 |
| FIFO enable. | |
| #define | NS16550_LCR 0x03 |
| Line control register. | |
| #define | NS16550_LCR_WLS0 0x01 |
| Word length select bit 0. | |
| #define | NS16550_LCR_WLS1 0x02 |
| Word length select bit 1. | |
| #define | NS16550_LCR_STB 0x04 |
| Number of stop bits. | |
| #define | NS16550_LCR_PEN 0x08 |
| Parity enable. | |
| #define | NS16550_LCR_EPS 0x10 |
| Even parity select. | |
| #define | NS16550_LCR_DLAB 0x80 |
| Divisor latch access bit. | |
| #define | NS16550_LCR_WORD_LEN(x) |
| Word length. | |
| #define | NS16550_LCR_STOP_BITS(x) |
| Stop bits. | |
| #define | NS16550_LCR_PARITY(x) |
| Parity. | |
| #define | NS16550_LCR_WPS(word_len, parity, stop_bits) |
| Calculate line control register value. | |
| #define | NS16550_LCR_8N1 NS16550_LCR_WPS ( 8, 0, 1 ) |
| Default LCR value: 8 data bits, no parity, one stop bit. | |
| #define | NS16550_MCR 0x04 |
| Modem control register. | |
| #define | NS16550_MCR_DTR 0x01 |
| Data terminal ready. | |
| #define | NS16550_MCR_RTS 0x02 |
| Request to send. | |
| #define | NS16550_LSR 0x05 |
| Line status register. | |
| #define | NS16550_LSR_DR 0x01 |
| Data ready. | |
| #define | NS16550_LSR_THRE 0x20 |
| Transmitter holding reg. | |
| #define | NS16550_LSR_TEMT 0x40 |
| Transmitter empty. | |
| #define | NS16550_SCR 0x07 |
| Scratch register. | |
| #define | NS16550_DLL 0x00 |
| Divisor latch (least significant byte) | |
| #define | NS16550_DLM 0x01 |
| Divisor latch (most significant byte) | |
| #define | NS16550_CLK_BIT 16 |
| Post-division clock cycles per data bit. | |
| #define | NS16550_CLK_DEFAULT 1843200 |
| Default input clock rate (1.8432 MHz) | |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER_OR_UBDL) | |
| void | ns16550_write (struct ns16550_uart *ns16550, unsigned int address, uint8_t data) |
| Dummy COM1 UART for non-x86 platforms. | |
| uint8_t | ns16550_read (struct ns16550_uart *ns16550, unsigned int address) |
Variables | |
| struct uart_operations | ns16550_operations |
| 16550 UART operations | |
16550-compatible UART
Definition in file ns16550.h.
| #define NS16550_LEN 8 |
| #define NS16550_THR 0x00 |
Transmitter holding register.
Definition at line 18 of file ns16550.h.
Referenced by ns16550_transmit().
| #define NS16550_RBR 0x00 |
| #define NS16550_IER 0x01 |
| #define NS16550_FCR 0x02 |
| #define NS16550_FCR_FE 0x01 |
| #define NS16550_LCR 0x03 |
| #define NS16550_LCR_DLAB 0x80 |
| #define NS16550_LCR_STOP_BITS | ( | x | ) |
| #define NS16550_LCR_PARITY | ( | x | ) |
| #define NS16550_LCR_WPS | ( | word_len, | |
| parity, | |||
| stop_bits ) |
Calculate line control register value.
| word_len | Word length (5-8) |
| parity | Parity (0=none, 1=odd, 3=even) |
| stop_bits | Stop bits (1-2) |
| lcr | Line control register value |
Definition at line 51 of file ns16550.h.
| #define NS16550_LCR_8N1 NS16550_LCR_WPS ( 8, 0, 1 ) |
Default LCR value: 8 data bits, no parity, one stop bit.
Definition at line 57 of file ns16550.h.
Referenced by ns16550_init().
| #define NS16550_MCR 0x04 |
| #define NS16550_MCR_DTR 0x01 |
| #define NS16550_MCR_RTS 0x02 |
| #define NS16550_LSR 0x05 |
Line status register.
Definition at line 65 of file ns16550.h.
Referenced by ns16550_data_ready(), ns16550_flush(), and ns16550_transmit().
| #define NS16550_LSR_DR 0x01 |
| #define NS16550_LSR_THRE 0x20 |
Transmitter holding reg.
empty
Definition at line 67 of file ns16550.h.
Referenced by ns16550_transmit().
| #define NS16550_LSR_TEMT 0x40 |
| #define NS16550_SCR 0x07 |
| #define NS16550_DLL 0x00 |
Divisor latch (least significant byte)
Definition at line 74 of file ns16550.h.
Referenced by ns16550_init().
| #define NS16550_DLM 0x01 |
Divisor latch (most significant byte)
Definition at line 77 of file ns16550.h.
Referenced by ns16550_init().
| #define NS16550_CLK_BIT 16 |
Post-division clock cycles per data bit.
Definition at line 92 of file ns16550.h.
Referenced by ns16550_init().
| #define NS16550_CLK_DEFAULT 1843200 |
Default input clock rate (1.8432 MHz)
Definition at line 95 of file ns16550.h.
Referenced by dwuart_probe().
| FILE_LICENCE | ( | GPL2_OR_LATER_OR_UBDL | ) |
| void ns16550_write | ( | struct ns16550_uart * | ns16550, |
| unsigned int | address, | ||
| uint8_t | data ) |
Dummy COM1 UART for non-x86 platforms.
The architecture-independent config/serial.h header has long included the line
#define COMCONSOLE COM1
which is meaningless on non-x86 platforms where there is no COM1 port. Allow COM1 to be treated as equivalent to "no UART" on non-x86 platforms, to avoid breaking existing build configurations.
Referenced by ns16550_init(), and ns16550_transmit().
| uint8_t ns16550_read | ( | struct ns16550_uart * | ns16550, |
| unsigned int | address ) |
References address, and ns16550_operations.
Referenced by ns16550_data_ready(), ns16550_flush(), ns16550_init(), ns16550_receive(), and ns16550_transmit().
|
extern |
16550 UART operations
Definition at line 171 of file ns16550.c.
Referenced by dwuart_probe(), ns16550_read(), and spcr_16550().