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iPXE
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Intel 10 Gigabit Ethernet virtual function network card driver. More...
#include "intelvf.h"Go to the source code of this file.
Macros | |
| #define | INTELXVF_CTRL 0x0000UL |
| Control Register. | |
| #define | INTELXVF_CTRL_RST 0x04000000UL |
| Function-level reset. | |
| #define | INTELXVF_LINKS 0x0010UL |
| Link Status Register. | |
| #define | INTELXVF_LINKS_UP 0x40000000UL |
| Link up. | |
| #define | INTELXVF_EICR 0x0100UL |
| Extended Interrupt Cause Read Register. | |
| #define | INTELXVF_EIRQ_RX0 0x00000001UL |
| RX queue 0 (via IVAR) | |
| #define | INTELXVF_EIRQ_TX0 0x00000002UL |
| TX queue 0 (via IVAR) | |
| #define | INTELXVF_EIRQ_MBOX 0x00000004UL |
| Mailbox (via IVARM) | |
| #define | INTELXVF_EIMS 0x0108UL |
| Extended Interrupt Mask Set/Read Register. | |
| #define | INTELXVF_EIMC 0x010cUL |
| Extended Interrupt Mask Clear Register. | |
| #define | INTELXVF_IVAR 0x0120UL |
| Interrupt Vector Allocation Register. | |
| #define | INTELXVF_IVAR_RX0(bit) |
| RX queue 0 allocation. | |
| #define | INTELXVF_IVAR_RX0_DEFAULT INTELXVF_IVAR_RX0 ( 0x00 ) |
| #define | INTELXVF_IVAR_RX0_MASK INTELXVF_IVAR_RX0 ( 0x01 ) |
| #define | INTELXVF_IVAR_RX0_VALID 0x00000080UL |
| RX queue 0 valid. | |
| #define | INTELXVF_IVAR_TX0(bit) |
| TX queue 0 allocation. | |
| #define | INTELXVF_IVAR_TX0_DEFAULT INTELXVF_IVAR_TX0 ( 0x01 ) |
| #define | INTELXVF_IVAR_TX0_MASK INTELXVF_IVAR_TX0 ( 0x01 ) |
| #define | INTELXVF_IVAR_TX0_VALID 0x00008000UL |
| TX queue 0 valid. | |
| #define | INTELXVF_IVARM 0x0140UL |
| Interrupt Vector Allocation Miscellaneous Register. | |
| #define | INTELXVF_IVARM_MBOX(bit) |
| Mailbox allocation. | |
| #define | INTELXVF_IVARM_MBOX_DEFAULT INTELXVF_IVARM_MBOX ( 0x02 ) |
| #define | INTELXVF_IVARM_MBOX_MASK INTELXVF_IVARM_MBOX ( 0x03 ) |
| #define | INTELXVF_IVARM_MBOX_VALID 0x00000080UL |
| Mailbox valid. | |
| #define | INTELXVF_MBMEM 0x0200UL |
| Mailbox Memory Register Base. | |
| #define | INTELXVF_MBCTRL 0x02fcUL |
| Mailbox Control Register. | |
| #define | INTELXVF_PSRTYPE 0x0300UL |
| Packet Split Receive Type. | |
| #define | INTELXVF_RD(n) |
| Receive Descriptor register block. | |
| #define | INTELXVF_DCA_RXCTRL 0x100cUL |
| RX DCA Control Register. | |
| #define | INTELXVF_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL |
| Must be zero. | |
| #define | INTELXVF_SRRCTL 0x1014UL |
| Split Receive Control Register. | |
| #define | INTELXVF_SRRCTL_BSIZE(kb) |
| Receive buffer size. | |
| #define | INTELXVF_SRRCTL_BSIZE_DEFAULT INTELXVF_SRRCTL_BSIZE ( 0x02 ) |
| #define | INTELXVF_SRRCTL_BSIZE_MASK INTELXVF_SRRCTL_BSIZE ( 0x1f ) |
| #define | INTELXVF_SRRCTL_BHDRSIZE(kb) |
| Header size. | |
| #define | INTELXVF_SRRCTL_BHDRSIZE_DEFAULT INTELXVF_SRRCTL_BHDRSIZE ( 0x04 ) |
| #define | INTELXVF_SRRCTL_BHDRSIZE_MASK INTELXVF_SRRCTL_BHDRSIZE ( 0x0f ) |
| #define | INTELXVF_SRRCTL_DESCTYPE(typ) |
| Descriptor type. | |
| #define | INTELXVF_SRRCTL_DESCTYPE_DEFAULT INTELXVF_SRRCTL_DESCTYPE ( 0x00 ) |
| #define | INTELXVF_SRRCTL_DESCTYPE_MASK INTELXVF_SRRCTL_DESCTYPE ( 0x07 ) |
| #define | INTELXVF_SRRCTL_DROP_EN 0x10000000UL |
| #define | INTELXVF_GPRC 0x101c |
| Good Packets Received Count. | |
| #define | INTELXVF_GORCL 0x1020 |
| Good Packets Received Count Low. | |
| #define | INTELXVF_GORCH 0x1024 |
| Good Packets Received Count High. | |
| #define | INTELXVF_MPRC 0x1034 |
| #define | INTELXVF_TD(n) |
| Transmit Descriptor register block. | |
| #define | INTELXVF_GPTC 0x201c |
| Good Packets Transmitted Count. | |
| #define | INTELXVF_GOTCL 0x2020 |
| Good Packets Transmitted Count Low. | |
| #define | INTELXVF_GOTCH 0x2024 |
| Good Packets Transmitted Count High. | |
| #define | INTELXVF_MSG_TYPE_VERSION 0x00000008UL |
| Negotiate API version mailbox message. | |
| #define | INTELXVF_MSG_VERSION_1_1 0x00000002UL |
| API version 1.1. | |
| #define | INTELXVF_NUM_RINGS 8 |
| Number of queues. | |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER_OR_UBDL) | |
| FILE_SECBOOT (PERMITTED) | |
Intel 10 Gigabit Ethernet virtual function network card driver.
Definition in file intelxvf.h.
| #define INTELXVF_CTRL 0x0000UL |
| #define INTELXVF_CTRL_RST 0x04000000UL |
| #define INTELXVF_LINKS 0x0010UL |
Link Status Register.
Definition at line 20 of file intelxvf.h.
Referenced by intelxvf_check_link().
| #define INTELXVF_LINKS_UP 0x40000000UL |
| #define INTELXVF_EICR 0x0100UL |
Extended Interrupt Cause Read Register.
Definition at line 24 of file intelxvf.h.
Referenced by intelxvf_poll().
| #define INTELXVF_EIRQ_RX0 0x00000001UL |
RX queue 0 (via IVAR)
Definition at line 25 of file intelxvf.h.
Referenced by intelxvf_irq(), and intelxvf_poll().
| #define INTELXVF_EIRQ_TX0 0x00000002UL |
TX queue 0 (via IVAR)
Definition at line 26 of file intelxvf.h.
Referenced by intelxvf_irq(), and intelxvf_poll().
| #define INTELXVF_EIRQ_MBOX 0x00000004UL |
Mailbox (via IVARM)
Definition at line 27 of file intelxvf.h.
Referenced by intelxvf_irq(), and intelxvf_poll().
| #define INTELXVF_EIMS 0x0108UL |
Extended Interrupt Mask Set/Read Register.
Definition at line 30 of file intelxvf.h.
Referenced by intelxvf_irq().
| #define INTELXVF_EIMC 0x010cUL |
Extended Interrupt Mask Clear Register.
Definition at line 33 of file intelxvf.h.
Referenced by intelxvf_irq().
| #define INTELXVF_IVAR 0x0120UL |
Interrupt Vector Allocation Register.
Definition at line 36 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_IVAR_RX0 | ( | bit | ) |
| #define INTELXVF_IVAR_RX0_DEFAULT INTELXVF_IVAR_RX0 ( 0x00 ) |
Definition at line 38 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_IVAR_RX0_MASK INTELXVF_IVAR_RX0 ( 0x01 ) |
Definition at line 39 of file intelxvf.h.
| #define INTELXVF_IVAR_RX0_VALID 0x00000080UL |
| #define INTELXVF_IVAR_TX0 | ( | bit | ) |
| #define INTELXVF_IVAR_TX0_DEFAULT INTELXVF_IVAR_TX0 ( 0x01 ) |
Definition at line 42 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_IVAR_TX0_MASK INTELXVF_IVAR_TX0 ( 0x01 ) |
Definition at line 43 of file intelxvf.h.
| #define INTELXVF_IVAR_TX0_VALID 0x00008000UL |
| #define INTELXVF_IVARM 0x0140UL |
Interrupt Vector Allocation Miscellaneous Register.
Definition at line 47 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_IVARM_MBOX | ( | bit | ) |
| #define INTELXVF_IVARM_MBOX_DEFAULT INTELXVF_IVARM_MBOX ( 0x02 ) |
Definition at line 49 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_IVARM_MBOX_MASK INTELXVF_IVARM_MBOX ( 0x03 ) |
Definition at line 50 of file intelxvf.h.
| #define INTELXVF_IVARM_MBOX_VALID 0x00000080UL |
| #define INTELXVF_MBMEM 0x0200UL |
Mailbox Memory Register Base.
Definition at line 54 of file intelxvf.h.
Referenced by intelxvf_probe().
| #define INTELXVF_MBCTRL 0x02fcUL |
| #define INTELXVF_PSRTYPE 0x0300UL |
| #define INTELXVF_RD | ( | n | ) |
Receive Descriptor register block.
Definition at line 63 of file intelxvf.h.
Referenced by intelxvf_open(), and intelxvf_probe().
| #define INTELXVF_DCA_RXCTRL 0x100cUL |
| #define INTELXVF_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL |
| #define INTELXVF_SRRCTL 0x1014UL |
Split Receive Control Register.
Definition at line 70 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_SRRCTL_BSIZE | ( | kb | ) |
| #define INTELXVF_SRRCTL_BSIZE_DEFAULT INTELXVF_SRRCTL_BSIZE ( 0x02 ) |
Definition at line 72 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_SRRCTL_BSIZE_MASK INTELXVF_SRRCTL_BSIZE ( 0x1f ) |
Definition at line 73 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_SRRCTL_BHDRSIZE | ( | kb | ) |
| #define INTELXVF_SRRCTL_BHDRSIZE_DEFAULT INTELXVF_SRRCTL_BHDRSIZE ( 0x04 ) |
Definition at line 75 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_SRRCTL_BHDRSIZE_MASK INTELXVF_SRRCTL_BHDRSIZE ( 0x0f ) |
Definition at line 76 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_SRRCTL_DESCTYPE | ( | typ | ) |
| #define INTELXVF_SRRCTL_DESCTYPE_DEFAULT INTELXVF_SRRCTL_DESCTYPE ( 0x00 ) |
Definition at line 78 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_SRRCTL_DESCTYPE_MASK INTELXVF_SRRCTL_DESCTYPE ( 0x07 ) |
Definition at line 79 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_SRRCTL_DROP_EN 0x10000000UL |
Definition at line 80 of file intelxvf.h.
Referenced by intelxvf_open().
| #define INTELXVF_GPRC 0x101c |
Good Packets Received Count.
Definition at line 83 of file intelxvf.h.
Referenced by intelxvf_stats().
| #define INTELXVF_GORCL 0x1020 |
Good Packets Received Count Low.
Definition at line 86 of file intelxvf.h.
Referenced by intelxvf_stats().
| #define INTELXVF_GORCH 0x1024 |
Good Packets Received Count High.
Definition at line 89 of file intelxvf.h.
Referenced by intelxvf_stats().
| #define INTELXVF_MPRC 0x1034 |
Definition at line 92 of file intelxvf.h.
Referenced by intelxvf_stats().
| #define INTELXVF_TD | ( | n | ) |
Transmit Descriptor register block.
Definition at line 95 of file intelxvf.h.
Referenced by intelxvf_open(), and intelxvf_probe().
| #define INTELXVF_GPTC 0x201c |
Good Packets Transmitted Count.
Definition at line 98 of file intelxvf.h.
Referenced by intelxvf_stats().
| #define INTELXVF_GOTCL 0x2020 |
Good Packets Transmitted Count Low.
Definition at line 101 of file intelxvf.h.
Referenced by intelxvf_stats().
| #define INTELXVF_GOTCH 0x2024 |
Good Packets Transmitted Count High.
Definition at line 104 of file intelxvf.h.
Referenced by intelxvf_stats().
| #define INTELXVF_MSG_TYPE_VERSION 0x00000008UL |
Negotiate API version mailbox message.
Definition at line 107 of file intelxvf.h.
Referenced by intelxvf_mbox_version().
| #define INTELXVF_MSG_VERSION_1_1 0x00000002UL |
| #define INTELXVF_NUM_RINGS 8 |
| FILE_LICENCE | ( | GPL2_OR_LATER_OR_UBDL | ) |
| FILE_SECBOOT | ( | PERMITTED | ) |