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iPXE
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Intel 10 Gigabit Ethernet virtual function network card driver. More...
#include "intelvf.h"Go to the source code of this file.
Macros | |
| #define | INTELXVF_CTRL 0x0000UL |
| Control Register. More... | |
| #define | INTELXVF_CTRL_RST 0x04000000UL |
| Function-level reset. More... | |
| #define | INTELXVF_LINKS 0x0010UL |
| Link Status Register. More... | |
| #define | INTELXVF_LINKS_UP 0x40000000UL |
| Link up. More... | |
| #define | INTELXVF_EICR 0x0100UL |
| Extended Interrupt Cause Read Register. More... | |
| #define | INTELXVF_EIRQ_RX0 0x00000001UL |
| RX queue 0 (via IVAR) More... | |
| #define | INTELXVF_EIRQ_TX0 0x00000002UL |
| TX queue 0 (via IVAR) More... | |
| #define | INTELXVF_EIRQ_MBOX 0x00000004UL |
| Mailbox (via IVARM) More... | |
| #define | INTELXVF_EIMS 0x0108UL |
| Extended Interrupt Mask Set/Read Register. More... | |
| #define | INTELXVF_EIMC 0x010cUL |
| Extended Interrupt Mask Clear Register. More... | |
| #define | INTELXVF_IVAR 0x0120UL |
| Interrupt Vector Allocation Register. More... | |
| #define | INTELXVF_IVAR_RX0(bit) ( (bit) << 0 ) |
| RX queue 0 allocation. More... | |
| #define | INTELXVF_IVAR_RX0_DEFAULT INTELXVF_IVAR_RX0 ( 0x00 ) |
| #define | INTELXVF_IVAR_RX0_MASK INTELXVF_IVAR_RX0 ( 0x01 ) |
| #define | INTELXVF_IVAR_RX0_VALID 0x00000080UL |
| RX queue 0 valid. More... | |
| #define | INTELXVF_IVAR_TX0(bit) ( (bit) << 8 ) |
| TX queue 0 allocation. More... | |
| #define | INTELXVF_IVAR_TX0_DEFAULT INTELXVF_IVAR_TX0 ( 0x01 ) |
| #define | INTELXVF_IVAR_TX0_MASK INTELXVF_IVAR_TX0 ( 0x01 ) |
| #define | INTELXVF_IVAR_TX0_VALID 0x00008000UL |
| TX queue 0 valid. More... | |
| #define | INTELXVF_IVARM 0x0140UL |
| Interrupt Vector Allocation Miscellaneous Register. More... | |
| #define | INTELXVF_IVARM_MBOX(bit) ( (bit) << 0 ) |
| Mailbox allocation. More... | |
| #define | INTELXVF_IVARM_MBOX_DEFAULT INTELXVF_IVARM_MBOX ( 0x02 ) |
| #define | INTELXVF_IVARM_MBOX_MASK INTELXVF_IVARM_MBOX ( 0x03 ) |
| #define | INTELXVF_IVARM_MBOX_VALID 0x00000080UL |
| Mailbox valid. More... | |
| #define | INTELXVF_MBMEM 0x0200UL |
| Mailbox Memory Register Base. More... | |
| #define | INTELXVF_MBCTRL 0x02fcUL |
| Mailbox Control Register. More... | |
| #define | INTELXVF_PSRTYPE 0x0300UL |
| Packet Split Receive Type. More... | |
| #define | INTELXVF_RD(n) ( 0x1000UL + ( 0x40 * (n) ) ) |
| Receive Descriptor register block. More... | |
| #define | INTELXVF_DCA_RXCTRL 0x100cUL |
| RX DCA Control Register. More... | |
| #define | INTELXVF_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL |
| Must be zero. More... | |
| #define | INTELXVF_SRRCTL 0x1014UL |
| Split Receive Control Register. More... | |
| #define | INTELXVF_SRRCTL_BSIZE(kb) ( (kb) << 0 ) |
| Receive buffer size. More... | |
| #define | INTELXVF_SRRCTL_BSIZE_DEFAULT INTELXVF_SRRCTL_BSIZE ( 0x02 ) |
| #define | INTELXVF_SRRCTL_BSIZE_MASK INTELXVF_SRRCTL_BSIZE ( 0x1f ) |
| #define | INTELXVF_SRRCTL_BHDRSIZE(kb) ( (kb) << 8 ) |
| Header size. More... | |
| #define | INTELXVF_SRRCTL_BHDRSIZE_DEFAULT INTELXVF_SRRCTL_BHDRSIZE ( 0x04 ) |
| #define | INTELXVF_SRRCTL_BHDRSIZE_MASK INTELXVF_SRRCTL_BHDRSIZE ( 0x0f ) |
| #define | INTELXVF_SRRCTL_DESCTYPE(typ) ( (typ) << 25 ) |
| Descriptor type. More... | |
| #define | INTELXVF_SRRCTL_DESCTYPE_DEFAULT INTELXVF_SRRCTL_DESCTYPE ( 0x00 ) |
| #define | INTELXVF_SRRCTL_DESCTYPE_MASK INTELXVF_SRRCTL_DESCTYPE ( 0x07 ) |
| #define | INTELXVF_SRRCTL_DROP_EN 0x10000000UL |
| #define | INTELXVF_GPRC 0x101c |
| Good Packets Received Count. More... | |
| #define | INTELXVF_GORCL 0x1020 |
| Good Packets Received Count Low. More... | |
| #define | INTELXVF_GORCH 0x1024 |
| Good Packets Received Count High. More... | |
| #define | INTELXVF_MPRC 0x1034 |
| #define | INTELXVF_TD(n) ( 0x2000UL + ( 0x40 * (n) ) ) |
| Transmit Descriptor register block. More... | |
| #define | INTELXVF_GPTC 0x201c |
| Good Packets Transmitted Count. More... | |
| #define | INTELXVF_GOTCL 0x2020 |
| Good Packets Transmitted Count Low. More... | |
| #define | INTELXVF_GOTCH 0x2024 |
| Good Packets Transmitted Count High. More... | |
| #define | INTELXVF_MSG_TYPE_VERSION 0x00000008UL |
| Negotiate API version mailbox message. More... | |
| #define | INTELXVF_MSG_VERSION_1_1 0x00000002UL |
| API version 1.1. More... | |
| #define | INTELXVF_NUM_RINGS 8 |
| Number of queues. More... | |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER_OR_UBDL) | |
Intel 10 Gigabit Ethernet virtual function network card driver.
Definition in file intelxvf.h.
| #define INTELXVF_CTRL 0x0000UL |
Control Register.
Definition at line 15 of file intelxvf.h.
| #define INTELXVF_CTRL_RST 0x04000000UL |
Function-level reset.
Definition at line 16 of file intelxvf.h.
| #define INTELXVF_LINKS 0x0010UL |
Link Status Register.
Definition at line 19 of file intelxvf.h.
| #define INTELXVF_LINKS_UP 0x40000000UL |
Link up.
Definition at line 20 of file intelxvf.h.
| #define INTELXVF_EICR 0x0100UL |
Extended Interrupt Cause Read Register.
Definition at line 23 of file intelxvf.h.
| #define INTELXVF_EIRQ_RX0 0x00000001UL |
RX queue 0 (via IVAR)
Definition at line 24 of file intelxvf.h.
| #define INTELXVF_EIRQ_TX0 0x00000002UL |
TX queue 0 (via IVAR)
Definition at line 25 of file intelxvf.h.
| #define INTELXVF_EIRQ_MBOX 0x00000004UL |
Mailbox (via IVARM)
Definition at line 26 of file intelxvf.h.
| #define INTELXVF_EIMS 0x0108UL |
Extended Interrupt Mask Set/Read Register.
Definition at line 29 of file intelxvf.h.
| #define INTELXVF_EIMC 0x010cUL |
Extended Interrupt Mask Clear Register.
Definition at line 32 of file intelxvf.h.
| #define INTELXVF_IVAR 0x0120UL |
Interrupt Vector Allocation Register.
Definition at line 35 of file intelxvf.h.
RX queue 0 allocation.
Definition at line 36 of file intelxvf.h.
| #define INTELXVF_IVAR_RX0_DEFAULT INTELXVF_IVAR_RX0 ( 0x00 ) |
Definition at line 37 of file intelxvf.h.
| #define INTELXVF_IVAR_RX0_MASK INTELXVF_IVAR_RX0 ( 0x01 ) |
Definition at line 38 of file intelxvf.h.
| #define INTELXVF_IVAR_RX0_VALID 0x00000080UL |
RX queue 0 valid.
Definition at line 39 of file intelxvf.h.
TX queue 0 allocation.
Definition at line 40 of file intelxvf.h.
| #define INTELXVF_IVAR_TX0_DEFAULT INTELXVF_IVAR_TX0 ( 0x01 ) |
Definition at line 41 of file intelxvf.h.
| #define INTELXVF_IVAR_TX0_MASK INTELXVF_IVAR_TX0 ( 0x01 ) |
Definition at line 42 of file intelxvf.h.
| #define INTELXVF_IVAR_TX0_VALID 0x00008000UL |
TX queue 0 valid.
Definition at line 43 of file intelxvf.h.
| #define INTELXVF_IVARM 0x0140UL |
Interrupt Vector Allocation Miscellaneous Register.
Definition at line 46 of file intelxvf.h.
Mailbox allocation.
Definition at line 47 of file intelxvf.h.
| #define INTELXVF_IVARM_MBOX_DEFAULT INTELXVF_IVARM_MBOX ( 0x02 ) |
Definition at line 48 of file intelxvf.h.
| #define INTELXVF_IVARM_MBOX_MASK INTELXVF_IVARM_MBOX ( 0x03 ) |
Definition at line 49 of file intelxvf.h.
| #define INTELXVF_IVARM_MBOX_VALID 0x00000080UL |
Mailbox valid.
Definition at line 50 of file intelxvf.h.
| #define INTELXVF_MBMEM 0x0200UL |
Mailbox Memory Register Base.
Definition at line 53 of file intelxvf.h.
| #define INTELXVF_MBCTRL 0x02fcUL |
Mailbox Control Register.
Definition at line 56 of file intelxvf.h.
| #define INTELXVF_PSRTYPE 0x0300UL |
Packet Split Receive Type.
Definition at line 59 of file intelxvf.h.
| #define INTELXVF_RD | ( | n | ) | ( 0x1000UL + ( 0x40 * (n) ) ) |
Receive Descriptor register block.
Definition at line 62 of file intelxvf.h.
| #define INTELXVF_DCA_RXCTRL 0x100cUL |
RX DCA Control Register.
Definition at line 65 of file intelxvf.h.
| #define INTELXVF_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL |
Must be zero.
Definition at line 66 of file intelxvf.h.
| #define INTELXVF_SRRCTL 0x1014UL |
Split Receive Control Register.
Definition at line 69 of file intelxvf.h.
| #define INTELXVF_SRRCTL_BSIZE | ( | kb | ) | ( (kb) << 0 ) |
Receive buffer size.
Definition at line 70 of file intelxvf.h.
| #define INTELXVF_SRRCTL_BSIZE_DEFAULT INTELXVF_SRRCTL_BSIZE ( 0x02 ) |
Definition at line 71 of file intelxvf.h.
| #define INTELXVF_SRRCTL_BSIZE_MASK INTELXVF_SRRCTL_BSIZE ( 0x1f ) |
Definition at line 72 of file intelxvf.h.
| #define INTELXVF_SRRCTL_BHDRSIZE | ( | kb | ) | ( (kb) << 8 ) |
Header size.
Definition at line 73 of file intelxvf.h.
| #define INTELXVF_SRRCTL_BHDRSIZE_DEFAULT INTELXVF_SRRCTL_BHDRSIZE ( 0x04 ) |
Definition at line 74 of file intelxvf.h.
| #define INTELXVF_SRRCTL_BHDRSIZE_MASK INTELXVF_SRRCTL_BHDRSIZE ( 0x0f ) |
Definition at line 75 of file intelxvf.h.
| #define INTELXVF_SRRCTL_DESCTYPE | ( | typ | ) | ( (typ) << 25 ) |
Descriptor type.
Definition at line 76 of file intelxvf.h.
| #define INTELXVF_SRRCTL_DESCTYPE_DEFAULT INTELXVF_SRRCTL_DESCTYPE ( 0x00 ) |
Definition at line 77 of file intelxvf.h.
| #define INTELXVF_SRRCTL_DESCTYPE_MASK INTELXVF_SRRCTL_DESCTYPE ( 0x07 ) |
Definition at line 78 of file intelxvf.h.
| #define INTELXVF_SRRCTL_DROP_EN 0x10000000UL |
Definition at line 79 of file intelxvf.h.
| #define INTELXVF_GPRC 0x101c |
Good Packets Received Count.
Definition at line 82 of file intelxvf.h.
| #define INTELXVF_GORCL 0x1020 |
Good Packets Received Count Low.
Definition at line 85 of file intelxvf.h.
| #define INTELXVF_GORCH 0x1024 |
Good Packets Received Count High.
Definition at line 88 of file intelxvf.h.
| #define INTELXVF_MPRC 0x1034 |
Definition at line 91 of file intelxvf.h.
| #define INTELXVF_TD | ( | n | ) | ( 0x2000UL + ( 0x40 * (n) ) ) |
Transmit Descriptor register block.
Definition at line 94 of file intelxvf.h.
| #define INTELXVF_GPTC 0x201c |
Good Packets Transmitted Count.
Definition at line 97 of file intelxvf.h.
| #define INTELXVF_GOTCL 0x2020 |
Good Packets Transmitted Count Low.
Definition at line 100 of file intelxvf.h.
| #define INTELXVF_GOTCH 0x2024 |
Good Packets Transmitted Count High.
Definition at line 103 of file intelxvf.h.
| #define INTELXVF_MSG_TYPE_VERSION 0x00000008UL |
Negotiate API version mailbox message.
Definition at line 106 of file intelxvf.h.
| #define INTELXVF_MSG_VERSION_1_1 0x00000002UL |
API version 1.1.
Definition at line 109 of file intelxvf.h.
| #define INTELXVF_NUM_RINGS 8 |
Number of queues.
Definition at line 112 of file intelxvf.h.
| FILE_LICENCE | ( | GPL2_OR_LATER_OR_UBDL | ) |
1.8.15