52 #define NXHAL_VERSION 1 56 #define UNM_DMA_BUFFER_ALIGN 16 59 #define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) )) 67 #define UNM_128M_CRB_WINDOW 0x6110210UL 68 #define UNM_32M_CRB_WINDOW 0x0110210UL 69 #define UNM_2M_CRB_WINDOW 0x0130060UL 90 #define UNM_CRB_BASE(blk) ( (blk) << 20 ) 91 #define UNM_CRB_BLK(reg) ( (reg) >> 20 ) 92 #define UNM_CRB_OFFSET(reg) ( (reg) & 0x000fffff ) 94 #define UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE ) 95 #define UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 ) 96 #define UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 ) 97 #define UNM_PCIE_IRQ_VECTOR ( UNM_CRB_PCIE + 0x10100 ) 98 #define UNM_PCIE_IRQ_VECTOR_BIT(n) ( 1 << ( (n) + 7 ) ) 99 #define UNM_PCIE_IRQ_STATE ( UNM_CRB_PCIE + 0x1206c ) 100 #define UNM_PCIE_IRQ_STATE_TRIGGERED(state) (( (state) & 0x300 ) == 0x200 ) 101 #define UNM_PCIE_IRQ_MASK_F0 ( UNM_CRB_PCIE + 0x10128 ) 102 #define UNM_PCIE_IRQ_MASK_F1 ( UNM_CRB_PCIE + 0x10170 ) 103 #define UNM_PCIE_IRQ_MASK_F2 ( UNM_CRB_PCIE + 0x10174 ) 104 #define UNM_PCIE_IRQ_MASK_F3 ( UNM_CRB_PCIE + 0x10178 ) 105 #define UNM_PCIE_IRQ_MASK_F4 ( UNM_CRB_PCIE + 0x10370 ) 106 #define UNM_PCIE_IRQ_MASK_F5 ( UNM_CRB_PCIE + 0x10374 ) 107 #define UNM_PCIE_IRQ_MASK_F6 ( UNM_CRB_PCIE + 0x10378 ) 108 #define UNM_PCIE_IRQ_MASK_F7 ( UNM_CRB_PCIE + 0x1037c ) 109 #define UNM_PCIE_IRQ_MASK_MAGIC 0x0000fbffUL 110 #define UNM_PCIE_IRQ_STATUS_F0 ( UNM_CRB_PCIE + 0x10118 ) 111 #define UNM_PCIE_IRQ_STATUS_F1 ( UNM_CRB_PCIE + 0x10160 ) 112 #define UNM_PCIE_IRQ_STATUS_F2 ( UNM_CRB_PCIE + 0x10164 ) 113 #define UNM_PCIE_IRQ_STATUS_F3 ( UNM_CRB_PCIE + 0x10168 ) 114 #define UNM_PCIE_IRQ_STATUS_F4 ( UNM_CRB_PCIE + 0x10360 ) 115 #define UNM_PCIE_IRQ_STATUS_F5 ( UNM_CRB_PCIE + 0x10364 ) 116 #define UNM_PCIE_IRQ_STATUS_F6 ( UNM_CRB_PCIE + 0x10368 ) 117 #define UNM_PCIE_IRQ_STATUS_F7 ( UNM_CRB_PCIE + 0x1036c ) 118 #define UNM_PCIE_IRQ_STATUS_MAGIC 0xffffffffUL 120 #define UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM ) 122 #define UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 ) 123 #define UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 ) 124 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4 125 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5 126 #define UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 ) 127 #define UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 ) 128 #define UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 ) 129 #define UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 ) 130 #define UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL 131 #define UNM_CAM_RAM_NUM_DMESG_BUFFERS 5 132 #define UNM_CAM_RAM_CLP_COMMAND ( UNM_CAM_RAM + 0x000c0 ) 133 #define UNM_CAM_RAM_CLP_COMMAND_LAST 0x00000080UL 134 #define UNM_CAM_RAM_CLP_DATA_LO ( UNM_CAM_RAM + 0x000c4 ) 135 #define UNM_CAM_RAM_CLP_DATA_HI ( UNM_CAM_RAM + 0x000c8 ) 136 #define UNM_CAM_RAM_CLP_STATUS ( UNM_CAM_RAM + 0x000cc ) 137 #define UNM_CAM_RAM_CLP_STATUS_START 0x00000001UL 138 #define UNM_CAM_RAM_CLP_STATUS_DONE 0x00000002UL 139 #define UNM_CAM_RAM_CLP_STATUS_ERROR 0x0000ff00UL 140 #define UNM_CAM_RAM_CLP_STATUS_UNINITIALISED 0xffffffffUL 141 #define UNM_CAM_RAM_BOOT_ENABLE ( UNM_CAM_RAM + 0x000fc ) 142 #define UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 ) 143 #define UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 ) 144 #define UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc ) 145 #define UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL 147 #define UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 ) 148 #define UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 ) 149 #define UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c ) 150 #define UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 ) 151 #define UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 ) 152 #define UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 ) 153 #define UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c ) 154 #define UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 ) 155 #define UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 ) 156 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01 157 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f 158 #define UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc ) 159 #define UNM_NIC_REG_DUMMY_BUF_INIT 0 160 #define UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 ) 161 #define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \ 162 ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f ) 163 #define UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01 164 #define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02 165 #define UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c ) 166 #define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01 168 #define UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB ) 170 #define UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 ) 171 #define UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 ) 172 #define UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 ) 173 #define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 ) 174 #define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL 175 #define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c ) 176 #define UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC 0x31 178 #define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 ) 179 #define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 ) 180 #define UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 ) 181 #define UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c ) 182 #define UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 ) 183 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 ) 184 #define UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 ) 186 #define UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST ) 188 #define UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 ) 189 #define UNM_TEST_CONTROL_START 0x01 190 #define UNM_TEST_CONTROL_ENABLE 0x02 191 #define UNM_TEST_CONTROL_BUSY 0x08 192 #define UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 ) 193 #define UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 ) 194 #define UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 ) 195 #define UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac ) 197 #define UNM_CRB_PEG_0 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 ) 198 #define UNM_PEG_0_HALT_STATUS ( UNM_CRB_PEG_0 + 0x00030 ) 199 #define UNM_PEG_0_HALT ( UNM_CRB_PEG_0 + 0x0003c ) 201 #define UNM_CRB_PEG_1 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 ) 202 #define UNM_PEG_1_HALT_STATUS ( UNM_CRB_PEG_1 + 0x00030 ) 203 #define UNM_PEG_1_HALT ( UNM_CRB_PEG_1 + 0x0003c ) 205 #define UNM_CRB_PEG_2 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 ) 206 #define UNM_PEG_2_HALT_STATUS ( UNM_CRB_PEG_2 + 0x00030 ) 207 #define UNM_PEG_2_HALT ( UNM_CRB_PEG_2 + 0x0003c ) 209 #define UNM_CRB_PEG_3 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 ) 210 #define UNM_PEG_3_HALT_STATUS ( UNM_CRB_PEG_3 + 0x00030 ) 211 #define UNM_PEG_3_HALT ( UNM_CRB_PEG_3 + 0x0003c ) 213 #define UNM_CRB_PEG_4 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 ) 214 #define UNM_PEG_4_HALT_STATUS ( UNM_CRB_PEG_4 + 0x00030 ) 215 #define UNM_PEG_4_HALT ( UNM_CRB_PEG_4 + 0x0003c )
Phantom hardware definitions.
unsigned long long uint64_t
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
A Phantom RX status descriptor.
A Phantom command descriptor.
#define NX_PSEUDO_BIT_STRUCT(_structure)
Wrapper structure for pseudo_bit_t structures.
unm_reg_blocks
Phantom register blocks.