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| #define | NXHAL_VERSION 1 |
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| #define | UNM_DMA_BUFFER_ALIGN 16 |
| | DMA buffer alignment. More...
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| #define | __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) )) |
| | Mark structure as DMA-aligned. More...
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| #define | UNM_128M_CRB_WINDOW 0x6110210UL |
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| #define | UNM_32M_CRB_WINDOW 0x0110210UL |
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| #define | UNM_2M_CRB_WINDOW 0x0130060UL |
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| #define | UNM_CRB_BASE(blk) ( (blk) << 20 ) |
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| #define | UNM_CRB_BLK(reg) ( (reg) >> 20 ) |
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| #define | UNM_CRB_OFFSET(reg) ( (reg) & 0x000fffff ) |
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| #define | UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE ) |
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| #define | UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 ) |
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| #define | UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 ) |
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| #define | UNM_PCIE_IRQ_VECTOR ( UNM_CRB_PCIE + 0x10100 ) |
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| #define | UNM_PCIE_IRQ_VECTOR_BIT(n) ( 1 << ( (n) + 7 ) ) |
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| #define | UNM_PCIE_IRQ_STATE ( UNM_CRB_PCIE + 0x1206c ) |
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| #define | UNM_PCIE_IRQ_STATE_TRIGGERED(state) (( (state) & 0x300 ) == 0x200 ) |
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| #define | UNM_PCIE_IRQ_MASK_F0 ( UNM_CRB_PCIE + 0x10128 ) |
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| #define | UNM_PCIE_IRQ_MASK_F1 ( UNM_CRB_PCIE + 0x10170 ) |
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| #define | UNM_PCIE_IRQ_MASK_F2 ( UNM_CRB_PCIE + 0x10174 ) |
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| #define | UNM_PCIE_IRQ_MASK_F3 ( UNM_CRB_PCIE + 0x10178 ) |
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| #define | UNM_PCIE_IRQ_MASK_F4 ( UNM_CRB_PCIE + 0x10370 ) |
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| #define | UNM_PCIE_IRQ_MASK_F5 ( UNM_CRB_PCIE + 0x10374 ) |
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| #define | UNM_PCIE_IRQ_MASK_F6 ( UNM_CRB_PCIE + 0x10378 ) |
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| #define | UNM_PCIE_IRQ_MASK_F7 ( UNM_CRB_PCIE + 0x1037c ) |
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| #define | UNM_PCIE_IRQ_MASK_MAGIC 0x0000fbffUL |
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| #define | UNM_PCIE_IRQ_STATUS_F0 ( UNM_CRB_PCIE + 0x10118 ) |
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| #define | UNM_PCIE_IRQ_STATUS_F1 ( UNM_CRB_PCIE + 0x10160 ) |
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| #define | UNM_PCIE_IRQ_STATUS_F2 ( UNM_CRB_PCIE + 0x10164 ) |
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| #define | UNM_PCIE_IRQ_STATUS_F3 ( UNM_CRB_PCIE + 0x10168 ) |
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| #define | UNM_PCIE_IRQ_STATUS_F4 ( UNM_CRB_PCIE + 0x10360 ) |
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| #define | UNM_PCIE_IRQ_STATUS_F5 ( UNM_CRB_PCIE + 0x10364 ) |
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| #define | UNM_PCIE_IRQ_STATUS_F6 ( UNM_CRB_PCIE + 0x10368 ) |
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| #define | UNM_PCIE_IRQ_STATUS_F7 ( UNM_CRB_PCIE + 0x1036c ) |
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| #define | UNM_PCIE_IRQ_STATUS_MAGIC 0xffffffffUL |
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| #define | UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM ) |
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| #define | UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 ) |
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| #define | UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 ) |
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| #define | UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4 |
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| #define | UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5 |
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| #define | UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 ) |
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| #define | UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 ) |
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| #define | UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 ) |
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| #define | UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 ) |
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| #define | UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL |
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| #define | UNM_CAM_RAM_NUM_DMESG_BUFFERS 5 |
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| #define | UNM_CAM_RAM_CLP_COMMAND ( UNM_CAM_RAM + 0x000c0 ) |
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| #define | UNM_CAM_RAM_CLP_COMMAND_LAST 0x00000080UL |
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| #define | UNM_CAM_RAM_CLP_DATA_LO ( UNM_CAM_RAM + 0x000c4 ) |
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| #define | UNM_CAM_RAM_CLP_DATA_HI ( UNM_CAM_RAM + 0x000c8 ) |
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| #define | UNM_CAM_RAM_CLP_STATUS ( UNM_CAM_RAM + 0x000cc ) |
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| #define | UNM_CAM_RAM_CLP_STATUS_START 0x00000001UL |
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| #define | UNM_CAM_RAM_CLP_STATUS_DONE 0x00000002UL |
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| #define | UNM_CAM_RAM_CLP_STATUS_ERROR 0x0000ff00UL |
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| #define | UNM_CAM_RAM_CLP_STATUS_UNINITIALISED 0xffffffffUL |
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| #define | UNM_CAM_RAM_BOOT_ENABLE ( UNM_CAM_RAM + 0x000fc ) |
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| #define | UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 ) |
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| #define | UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 ) |
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| #define | UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc ) |
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| #define | UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL |
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| #define | UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 ) |
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| #define | UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 ) |
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| #define | UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c ) |
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| #define | UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 ) |
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| #define | UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 ) |
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| #define | UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 ) |
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| #define | UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c ) |
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| #define | UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 ) |
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| #define | UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 ) |
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| #define | UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01 |
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| #define | UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f |
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| #define | UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc ) |
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| #define | UNM_NIC_REG_DUMMY_BUF_INIT 0 |
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| #define | UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 ) |
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| #define | UNM_NIC_REG_XG_STATE_P3_LINK(port, state_p3) ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f ) |
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| #define | UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01 |
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| #define | UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02 |
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| #define | UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c ) |
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| #define | UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01 |
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| #define | UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB ) |
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| #define | UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 ) |
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| #define | UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 ) |
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| #define | UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 ) |
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| #define | UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 ) |
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| #define | UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL |
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| #define | UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c ) |
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| #define | UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC 0x31 |
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| #define | UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 ) |
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| #define | UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 ) |
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| #define | UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 ) |
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| #define | UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c ) |
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| #define | UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 ) |
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| #define | UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 ) |
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| #define | UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 ) |
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| #define | UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST ) |
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| #define | UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 ) |
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| #define | UNM_TEST_CONTROL_START 0x01 |
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| #define | UNM_TEST_CONTROL_ENABLE 0x02 |
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| #define | UNM_TEST_CONTROL_BUSY 0x08 |
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| #define | UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 ) |
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| #define | UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 ) |
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| #define | UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 ) |
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| #define | UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac ) |
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| #define | UNM_CRB_PEG_0 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 ) |
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| #define | UNM_PEG_0_HALT_STATUS ( UNM_CRB_PEG_0 + 0x00030 ) |
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| #define | UNM_PEG_0_HALT ( UNM_CRB_PEG_0 + 0x0003c ) |
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| #define | UNM_CRB_PEG_1 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 ) |
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| #define | UNM_PEG_1_HALT_STATUS ( UNM_CRB_PEG_1 + 0x00030 ) |
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| #define | UNM_PEG_1_HALT ( UNM_CRB_PEG_1 + 0x0003c ) |
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| #define | UNM_CRB_PEG_2 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 ) |
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| #define | UNM_PEG_2_HALT_STATUS ( UNM_CRB_PEG_2 + 0x00030 ) |
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| #define | UNM_PEG_2_HALT ( UNM_CRB_PEG_2 + 0x0003c ) |
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| #define | UNM_CRB_PEG_3 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 ) |
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| #define | UNM_PEG_3_HALT_STATUS ( UNM_CRB_PEG_3 + 0x00030 ) |
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| #define | UNM_PEG_3_HALT ( UNM_CRB_PEG_3 + 0x0003c ) |
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| #define | UNM_CRB_PEG_4 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 ) |
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| #define | UNM_PEG_4_HALT_STATUS ( UNM_CRB_PEG_4 + 0x00030 ) |
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| #define | UNM_PEG_4_HALT ( UNM_CRB_PEG_4 + 0x0003c ) |
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