18 #define SIS900_TOTAL_SIZE 0x100 112 #define MAX_DMA_RANGE 7 113 #define TxMXDMA_shift 20 114 #define RxMXDMA_shift 20 115 #define TX_DMA_BURST 0 116 #define RX_DMA_BURST 0 123 #define TX_FILL_THRESH 16 124 #define TxFILLT_shift 8 125 #define TxDRNT_shift 0 126 #define TxDRNT_100 48 140 #define RxDRNT_shift 1 141 #define RxDRNT_100 16 152 #define RFAA_shift 28 153 #define RFADDR_shift 16 194 #define MIIread 0x6000 195 #define MIIwrite 0x5002 196 #define MIIpmdShift 7 197 #define MIIregShift 2 199 #define MIIcmdShift 16 299 #define MII_ID1_OUI_LO 0xFC00 300 #define MII_ID1_MODEL 0x03F0 301 #define MII_ID1_REV 0x000F 350 #define FDX_CAPABLE_DUPLEX_UNKNOWN 0 351 #define FDX_CAPABLE_HALF_SELECTED 1 352 #define FDX_CAPABLE_FULL_SELECTED 2 354 #define HW_SPEED_UNCONFIG 0 355 #define HW_SPEED_HOME 1 356 #define HW_SPEED_10_MBPS 10 357 #define HW_SPEED_100_MBPS 100 358 #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS) 361 #define MAC_HEADER_SIZE 14 363 #define TX_BUF_SIZE 1536 364 #define RX_BUF_SIZE 1536 366 #define NUM_RX_DESC 4 369 #define TX_TIMEOUT (4*TICKS_PER_SEC) sis900_transmit_config_register_bits
struct _BufferDesc BufferDesc
sis900_receive_filter_control_register_bits
sis900_reveive_config_register_bits
mii_control_register_bits
sis900_eeprom_access_reigster_bits
sis900_command_register_bits
sis900_interrupt_register_bits
sis900_configuration_register_bits
sis900_interrupt_enable_reigster_bits
sis900_reveive_filter_data_mask