iPXE
Data Fields
PCI_BRIDGE_CONTROL_REGISTER Struct Reference

PCI-PCI Bridge header region in PCI Configuration Space Section 3.2, PCI-PCI Bridge Architecture, Version 1.2. More...

#include <Pci22.h>

Data Fields

UINT32 Bar [2]
 
UINT8 PrimaryBus
 
UINT8 SecondaryBus
 
UINT8 SubordinateBus
 
UINT8 SecondaryLatencyTimer
 
UINT8 IoBase
 
UINT8 IoLimit
 
UINT16 SecondaryStatus
 
UINT16 MemoryBase
 
UINT16 MemoryLimit
 
UINT16 PrefetchableMemoryBase
 
UINT16 PrefetchableMemoryLimit
 
UINT32 PrefetchableBaseUpper32
 
UINT32 PrefetchableLimitUpper32
 
UINT16 IoBaseUpper16
 
UINT16 IoLimitUpper16
 
UINT8 CapabilityPtr
 
UINT8 Reserved [3]
 
UINT32 ExpansionRomBAR
 
UINT8 InterruptLine
 
UINT8 InterruptPin
 
UINT16 BridgeControl
 

Detailed Description

PCI-PCI Bridge header region in PCI Configuration Space Section 3.2, PCI-PCI Bridge Architecture, Version 1.2.

Definition at line 82 of file Pci22.h.

Field Documentation

◆ Bar

UINT32 PCI_BRIDGE_CONTROL_REGISTER::Bar[2]

Definition at line 83 of file Pci22.h.

◆ PrimaryBus

UINT8 PCI_BRIDGE_CONTROL_REGISTER::PrimaryBus

Definition at line 84 of file Pci22.h.

◆ SecondaryBus

UINT8 PCI_BRIDGE_CONTROL_REGISTER::SecondaryBus

Definition at line 85 of file Pci22.h.

◆ SubordinateBus

UINT8 PCI_BRIDGE_CONTROL_REGISTER::SubordinateBus

Definition at line 86 of file Pci22.h.

◆ SecondaryLatencyTimer

UINT8 PCI_BRIDGE_CONTROL_REGISTER::SecondaryLatencyTimer

Definition at line 87 of file Pci22.h.

◆ IoBase

UINT8 PCI_BRIDGE_CONTROL_REGISTER::IoBase

Definition at line 88 of file Pci22.h.

◆ IoLimit

UINT8 PCI_BRIDGE_CONTROL_REGISTER::IoLimit

Definition at line 89 of file Pci22.h.

◆ SecondaryStatus

UINT16 PCI_BRIDGE_CONTROL_REGISTER::SecondaryStatus

Definition at line 90 of file Pci22.h.

◆ MemoryBase

UINT16 PCI_BRIDGE_CONTROL_REGISTER::MemoryBase

Definition at line 91 of file Pci22.h.

◆ MemoryLimit

UINT16 PCI_BRIDGE_CONTROL_REGISTER::MemoryLimit

Definition at line 92 of file Pci22.h.

◆ PrefetchableMemoryBase

UINT16 PCI_BRIDGE_CONTROL_REGISTER::PrefetchableMemoryBase

Definition at line 93 of file Pci22.h.

◆ PrefetchableMemoryLimit

UINT16 PCI_BRIDGE_CONTROL_REGISTER::PrefetchableMemoryLimit

Definition at line 94 of file Pci22.h.

◆ PrefetchableBaseUpper32

UINT32 PCI_BRIDGE_CONTROL_REGISTER::PrefetchableBaseUpper32

Definition at line 95 of file Pci22.h.

◆ PrefetchableLimitUpper32

UINT32 PCI_BRIDGE_CONTROL_REGISTER::PrefetchableLimitUpper32

Definition at line 96 of file Pci22.h.

◆ IoBaseUpper16

UINT16 PCI_BRIDGE_CONTROL_REGISTER::IoBaseUpper16

Definition at line 97 of file Pci22.h.

◆ IoLimitUpper16

UINT16 PCI_BRIDGE_CONTROL_REGISTER::IoLimitUpper16

Definition at line 98 of file Pci22.h.

◆ CapabilityPtr

UINT8 PCI_BRIDGE_CONTROL_REGISTER::CapabilityPtr

Definition at line 99 of file Pci22.h.

◆ Reserved

UINT8 PCI_BRIDGE_CONTROL_REGISTER::Reserved[3]

Definition at line 100 of file Pci22.h.

◆ ExpansionRomBAR

UINT32 PCI_BRIDGE_CONTROL_REGISTER::ExpansionRomBAR

Definition at line 101 of file Pci22.h.

◆ InterruptLine

UINT8 PCI_BRIDGE_CONTROL_REGISTER::InterruptLine

Definition at line 102 of file Pci22.h.

◆ InterruptPin

UINT8 PCI_BRIDGE_CONTROL_REGISTER::InterruptPin

Definition at line 103 of file Pci22.h.

◆ BridgeControl

UINT16 PCI_BRIDGE_CONTROL_REGISTER::BridgeControl

Definition at line 104 of file Pci22.h.


The documentation for this struct was generated from the following file: