iPXE
Pci22.h
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1 /** @file
2  Support for PCI 2.2 standard.
3 
4  This file includes the definitions in the following specifications,
5  PCI Local Bus Specification, 2.2
6  PCI-to-PCI Bridge Architecture Specification, Revision 1.2
7  PC Card Standard, 8.0
8  PCI Power Management Interface Specifiction, Revision 1.2
9 
10  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
11  Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
12  This program and the accompanying materials
13  are licensed and made available under the terms and conditions of the BSD License
14  which accompanies this distribution. The full text of the license may be found at
15  http://opensource.org/licenses/bsd-license.php
16 
17  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
18  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 
20 **/
21 
22 #ifndef _PCI22_H_
23 #define _PCI22_H_
24 
25 FILE_LICENCE ( BSD3 );
26 
27 #define PCI_MAX_BUS 255
28 #define PCI_MAX_DEVICE 31
29 #define PCI_MAX_FUNC 7
30 
31 #pragma pack(1)
32 
33 ///
34 /// Common header region in PCI Configuration Space
35 /// Section 6.1, PCI Local Bus Specification, 2.2
36 ///
37 typedef struct {
43  UINT8 ClassCode[3];
49 
50 ///
51 /// PCI Device header region in PCI Configuration Space
52 /// Section 6.1, PCI Local Bus Specification, 2.2
53 ///
54 typedef struct {
55  UINT32 Bar[6];
61  UINT8 Reserved1[3];
68 
69 ///
70 /// PCI Device Configuration Space
71 /// Section 6.1, PCI Local Bus Specification, 2.2
72 ///
73 typedef struct {
76 } PCI_TYPE00;
77 
78 ///
79 /// PCI-PCI Bridge header region in PCI Configuration Space
80 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
81 ///
82 typedef struct {
83  UINT32 Bar[2];
106 
107 ///
108 /// PCI-to-PCI Bridge Configuration Space
109 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
110 ///
111 typedef struct {
114 } PCI_TYPE01;
115 
116 typedef union {
120 
121 ///
122 /// CardBus Conroller Configuration Space,
123 /// Section 4.5.1, PC Card Standard. 8.0
124 ///
125 typedef struct {
126  UINT32 CardBusSocketReg; ///< Cardus Socket/ExCA Base
129  UINT16 SecondaryStatus; ///< Secondary Status
130  UINT8 PciBusNumber; ///< PCI Bus Number
131  UINT8 CardBusBusNumber; ///< CardBus Bus Number
132  UINT8 SubordinateBusNumber; ///< Subordinate Bus Number
133  UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer
134  UINT32 MemoryBase0; ///< Memory Base Register 0
135  UINT32 MemoryLimit0; ///< Memory Limit Register 0
139  UINT32 IoLimit0; ///< I/O Base Register 0
140  UINT32 IoBase1; ///< I/O Limit Register 0
142  UINT8 InterruptLine; ///< Interrupt Line
143  UINT8 InterruptPin; ///< Interrupt Pin
144  UINT16 BridgeControl; ///< Bridge Control
146 
147 //
148 // Definitions of PCI class bytes and manipulation macros.
149 //
150 #define PCI_CLASS_OLD 0x00
151 #define PCI_CLASS_OLD_OTHER 0x00
152 #define PCI_CLASS_OLD_VGA 0x01
153 
154 #define PCI_CLASS_MASS_STORAGE 0x01
155 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
156 #define PCI_CLASS_MASS_STORAGE_IDE 0x01
157 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
158 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
159 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
160 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
161 
162 #define PCI_CLASS_NETWORK 0x02
163 #define PCI_CLASS_NETWORK_ETHERNET 0x00
164 #define PCI_CLASS_NETWORK_TOKENRING 0x01
165 #define PCI_CLASS_NETWORK_FDDI 0x02
166 #define PCI_CLASS_NETWORK_ATM 0x03
167 #define PCI_CLASS_NETWORK_ISDN 0x04
168 #define PCI_CLASS_NETWORK_OTHER 0x80
169 
170 #define PCI_CLASS_DISPLAY 0x03
171 #define PCI_CLASS_DISPLAY_VGA 0x00
172 #define PCI_IF_VGA_VGA 0x00
173 #define PCI_IF_VGA_8514 0x01
174 #define PCI_CLASS_DISPLAY_XGA 0x01
175 #define PCI_CLASS_DISPLAY_3D 0x02
176 #define PCI_CLASS_DISPLAY_OTHER 0x80
177 
178 #define PCI_CLASS_MEDIA 0x04
179 #define PCI_CLASS_MEDIA_VIDEO 0x00
180 #define PCI_CLASS_MEDIA_AUDIO 0x01
181 #define PCI_CLASS_MEDIA_TELEPHONE 0x02
182 #define PCI_CLASS_MEDIA_OTHER 0x80
183 
184 #define PCI_CLASS_MEMORY_CONTROLLER 0x05
185 #define PCI_CLASS_MEMORY_RAM 0x00
186 #define PCI_CLASS_MEMORY_FLASH 0x01
187 #define PCI_CLASS_MEMORY_OTHER 0x80
188 
189 #define PCI_CLASS_BRIDGE 0x06
190 #define PCI_CLASS_BRIDGE_HOST 0x00
191 #define PCI_CLASS_BRIDGE_ISA 0x01
192 #define PCI_CLASS_BRIDGE_EISA 0x02
193 #define PCI_CLASS_BRIDGE_MCA 0x03
194 #define PCI_CLASS_BRIDGE_P2P 0x04
195 #define PCI_IF_BRIDGE_P2P 0x00
196 #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
197 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
198 #define PCI_CLASS_BRIDGE_NUBUS 0x06
199 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
200 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
201 #define PCI_CLASS_BRIDGE_OTHER 0x80
202 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
203 
204 #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers
205 #define PCI_SUBCLASS_SERIAL 0x00
206 #define PCI_IF_GENERIC_XT 0x00
207 #define PCI_IF_16450 0x01
208 #define PCI_IF_16550 0x02
209 #define PCI_IF_16650 0x03
210 #define PCI_IF_16750 0x04
211 #define PCI_IF_16850 0x05
212 #define PCI_IF_16950 0x06
213 #define PCI_SUBCLASS_PARALLEL 0x01
214 #define PCI_IF_PARALLEL_PORT 0x00
215 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
216 #define PCI_IF_ECP_PARALLEL_PORT 0x02
217 #define PCI_IF_1284_CONTROLLER 0x03
218 #define PCI_IF_1284_DEVICE 0xFE
219 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
220 #define PCI_SUBCLASS_MODEM 0x03
221 #define PCI_IF_GENERIC_MODEM 0x00
222 #define PCI_IF_16450_MODEM 0x01
223 #define PCI_IF_16550_MODEM 0x02
224 #define PCI_IF_16650_MODEM 0x03
225 #define PCI_IF_16750_MODEM 0x04
226 #define PCI_SUBCLASS_SCC_OTHER 0x80
227 
228 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
229 #define PCI_SUBCLASS_PIC 0x00
230 #define PCI_IF_8259_PIC 0x00
231 #define PCI_IF_ISA_PIC 0x01
232 #define PCI_IF_EISA_PIC 0x02
233 #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
234 #define PCI_IF_APIC_CONTROLLER2 0x20
235 #define PCI_SUBCLASS_DMA 0x01
236 #define PCI_IF_8237_DMA 0x00
237 #define PCI_IF_ISA_DMA 0x01
238 #define PCI_IF_EISA_DMA 0x02
239 #define PCI_SUBCLASS_TIMER 0x02
240 #define PCI_IF_8254_TIMER 0x00
241 #define PCI_IF_ISA_TIMER 0x01
242 #define PCI_IF_EISA_TIMER 0x02
243 #define PCI_SUBCLASS_RTC 0x03
244 #define PCI_IF_GENERIC_RTC 0x00
245 #define PCI_IF_ISA_RTC 0x01
246 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
247 #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
248 
249 #define PCI_CLASS_INPUT_DEVICE 0x09
250 #define PCI_SUBCLASS_KEYBOARD 0x00
251 #define PCI_SUBCLASS_PEN 0x01
252 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
253 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
254 #define PCI_SUBCLASS_GAMEPORT 0x04
255 #define PCI_IF_GAMEPORT 0x00
256 #define PCI_IF_GAMEPORT1 0x10
257 #define PCI_SUBCLASS_INPUT_OTHER 0x80
258 
259 #define PCI_CLASS_DOCKING_STATION 0x0A
260 #define PCI_SUBCLASS_DOCKING_GENERIC 0x00
261 #define PCI_SUBCLASS_DOCKING_OTHER 0x80
262 
263 #define PCI_CLASS_PROCESSOR 0x0B
264 #define PCI_SUBCLASS_PROC_386 0x00
265 #define PCI_SUBCLASS_PROC_486 0x01
266 #define PCI_SUBCLASS_PROC_PENTIUM 0x02
267 #define PCI_SUBCLASS_PROC_ALPHA 0x10
268 #define PCI_SUBCLASS_PROC_POWERPC 0x20
269 #define PCI_SUBCLASS_PROC_MIPS 0x30
270 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
271 
272 #define PCI_CLASS_SERIAL 0x0C
273 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
274 #define PCI_IF_1394 0x00
275 #define PCI_IF_1394_OPEN_HCI 0x10
276 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
277 #define PCI_CLASS_SERIAL_SSA 0x02
278 #define PCI_CLASS_SERIAL_USB 0x03
279 #define PCI_IF_UHCI 0x00
280 #define PCI_IF_OHCI 0x10
281 #define PCI_IF_USB_OTHER 0x80
282 #define PCI_IF_USB_DEVICE 0xFE
283 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
284 #define PCI_CLASS_SERIAL_SMB 0x05
285 
286 #define PCI_CLASS_WIRELESS 0x0D
287 #define PCI_SUBCLASS_IRDA 0x00
288 #define PCI_SUBCLASS_IR 0x01
289 #define PCI_SUBCLASS_RF 0x10
290 #define PCI_SUBCLASS_WIRELESS_OTHER 0x80
291 
292 #define PCI_CLASS_INTELLIGENT_IO 0x0E
293 
294 #define PCI_CLASS_SATELLITE 0x0F
295 #define PCI_SUBCLASS_TV 0x01
296 #define PCI_SUBCLASS_AUDIO 0x02
297 #define PCI_SUBCLASS_VOICE 0x03
298 #define PCI_SUBCLASS_DATA 0x04
299 
300 #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
301 #define PCI_SUBCLASS_NET_COMPUT 0x00
302 #define PCI_SUBCLASS_ENTERTAINMENT 0x10
303 #define PCI_SUBCLASS_SECURITY_OTHER 0x80
304 
305 #define PCI_CLASS_DPIO 0x11
306 #define PCI_SUBCLASS_DPIO 0x00
307 #define PCI_SUBCLASS_DPIO_OTHER 0x80
308 
309 /**
310  Macro that checks whether the Base Class code of device matched.
311 
312  @param _p Specified device.
313  @param c Base Class code needs matching.
314 
315  @retval TRUE Base Class code matches the specified device.
316  @retval FALSE Base Class code doesn't match the specified device.
317 
318 **/
319 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
320 /**
321  Macro that checks whether the Base Class code and Sub-Class code of device matched.
322 
323  @param _p Specified device.
324  @param c Base Class code needs matching.
325  @param s Sub-Class code needs matching.
326 
327  @retval TRUE Base Class code and Sub-Class code match the specified device.
328  @retval FALSE Base Class code and Sub-Class code don't match the specified device.
329 
330 **/
331 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
332 /**
333  Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
334 
335  @param _p Specified device.
336  @param c Base Class code needs matching.
337  @param s Sub-Class code needs matching.
338  @param p Interface code needs matching.
339 
340  @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
341  @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
342 
343 **/
344 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
345 
346 /**
347  Macro that checks whether device is a display controller.
348 
349  @param _p Specified device.
350 
351  @retval TRUE Device is a display controller.
352  @retval FALSE Device is not a display controller.
353 
354 **/
355 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
356 /**
357  Macro that checks whether device is a VGA-compatible controller.
358 
359  @param _p Specified device.
360 
361  @retval TRUE Device is a VGA-compatible controller.
362  @retval FALSE Device is not a VGA-compatible controller.
363 
364 **/
365 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
366 /**
367  Macro that checks whether device is an 8514-compatible controller.
368 
369  @param _p Specified device.
370 
371  @retval TRUE Device is an 8514-compatible controller.
372  @retval FALSE Device is not an 8514-compatible controller.
373 
374 **/
375 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
376 /**
377  Macro that checks whether device is built before the Class Code field was defined.
378 
379  @param _p Specified device.
380 
381  @retval TRUE Device is an old device.
382  @retval FALSE Device is not an old device.
383 
384 **/
385 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
386 /**
387  Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
388 
389  @param _p Specified device.
390 
391  @retval TRUE Device is an old VGA-compatible device.
392  @retval FALSE Device is not an old VGA-compatible device.
393 
394 **/
395 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
396 /**
397  Macro that checks whether device is an IDE controller.
398 
399  @param _p Specified device.
400 
401  @retval TRUE Device is an IDE controller.
402  @retval FALSE Device is not an IDE controller.
403 
404 **/
405 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
406 /**
407  Macro that checks whether device is a SCSI bus controller.
408 
409  @param _p Specified device.
410 
411  @retval TRUE Device is a SCSI bus controller.
412  @retval FALSE Device is not a SCSI bus controller.
413 
414 **/
415 #define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
416 /**
417  Macro that checks whether device is a RAID controller.
418 
419  @param _p Specified device.
420 
421  @retval TRUE Device is a RAID controller.
422  @retval FALSE Device is not a RAID controller.
423 
424 **/
425 #define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
426 /**
427  Macro that checks whether device is an ISA bridge.
428 
429  @param _p Specified device.
430 
431  @retval TRUE Device is an ISA bridge.
432  @retval FALSE Device is not an ISA bridge.
433 
434 **/
435 #define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
436 /**
437  Macro that checks whether device is a PCI-to-PCI bridge.
438 
439  @param _p Specified device.
440 
441  @retval TRUE Device is a PCI-to-PCI bridge.
442  @retval FALSE Device is not a PCI-to-PCI bridge.
443 
444 **/
445 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
446 /**
447  Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
448 
449  @param _p Specified device.
450 
451  @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
452  @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
453 
454 **/
455 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
456 /**
457  Macro that checks whether device is a 16550-compatible serial controller.
458 
459  @param _p Specified device.
460 
461  @retval TRUE Device is a 16550-compatible serial controller.
462  @retval FALSE Device is not a 16550-compatible serial controller.
463 
464 **/
465 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
466 /**
467  Macro that checks whether device is a Universal Serial Bus controller.
468 
469  @param _p Specified device.
470 
471  @retval TRUE Device is a Universal Serial Bus controller.
472  @retval FALSE Device is not a Universal Serial Bus controller.
473 
474 **/
475 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
476 
477 //
478 // the definition of Header Type
479 //
480 #define HEADER_TYPE_DEVICE 0x00
481 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
482 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
483 #define HEADER_TYPE_MULTI_FUNCTION 0x80
484 //
485 // Mask of Header type
486 //
487 #define HEADER_LAYOUT_CODE 0x7f
488 /**
489  Macro that checks whether device is a PCI-PCI bridge.
490 
491  @param _p Specified device.
492 
493  @retval TRUE Device is a PCI-PCI bridge.
494  @retval FALSE Device is not a PCI-PCI bridge.
495 
496 **/
497 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
498 /**
499  Macro that checks whether device is a CardBus bridge.
500 
501  @param _p Specified device.
502 
503  @retval TRUE Device is a CardBus bridge.
504  @retval FALSE Device is not a CardBus bridge.
505 
506 **/
507 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
508 /**
509  Macro that checks whether device is a multiple functions device.
510 
511  @param _p Specified device.
512 
513  @retval TRUE Device is a multiple functions device.
514  @retval FALSE Device is not a multiple functions device.
515 
516 **/
517 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
518 
519 ///
520 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
521 ///
522 #define PCI_BRIDGE_ROMBAR 0x38
523 
524 #define PCI_MAX_BAR 0x0006
525 #define PCI_MAX_CONFIG_OFFSET 0x0100
526 
527 #define PCI_VENDOR_ID_OFFSET 0x00
528 #define PCI_DEVICE_ID_OFFSET 0x02
529 #define PCI_COMMAND_OFFSET 0x04
530 #define PCI_PRIMARY_STATUS_OFFSET 0x06
531 #define PCI_REVISION_ID_OFFSET 0x08
532 #define PCI_CLASSCODE_OFFSET 0x09
533 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
534 #define PCI_LATENCY_TIMER_OFFSET 0x0D
535 #define PCI_HEADER_TYPE_OFFSET 0x0E
536 #define PCI_BIST_OFFSET 0x0F
537 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
538 #define PCI_CARDBUS_CIS_OFFSET 0x28
539 #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
540 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
541 #define PCI_SID_OFFSET 0x2E ///< SubSystem ID
542 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
543 #define PCI_EXPANSION_ROM_BASE 0x30
544 #define PCI_CAPBILITY_POINTER_OFFSET 0x34
545 #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
546 #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
547 #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
548 #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
549 
550 //
551 // defined in PCI-to-PCI Bridge Architecture Specification
552 //
553 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
554 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
555 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
556 #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
557 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
558 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
559 
560 ///
561 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
562 ///
563 #define PCI_INT_LINE_UNKNOWN 0xFF
564 
565 ///
566 /// PCI Access Data Format
567 ///
568 typedef union {
569  struct {
570  UINT32 Reg : 8;
572  UINT32 Dev : 5;
573  UINT32 Bus : 8;
576  } Bits;
579 
580 #pragma pack()
581 
582 #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
583 #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
584 #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
585 #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
586 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
587 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
588 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
589 #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
590 #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
591 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
592 
593 //
594 // defined in PCI-to-PCI Bridge Architecture Specification
595 //
596 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
597 #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
598 #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
599 #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008
600 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010
601 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020
602 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040
603 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
604 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100
605 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
606 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
607 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
608 
609 //
610 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
611 //
612 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
613 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
614 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
615 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
616 
617 //
618 // Following are the PCI status control bit
619 //
620 #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
621 #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
622 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
623 #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
624 
625 ///
626 /// defined in PC Card Standard
627 ///
628 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
629 
630 #pragma pack(1)
631 //
632 // PCI Capability List IDs and records
633 //
634 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
635 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
636 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
637 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
638 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
639 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
640 #define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
641 
642 ///
643 /// Capabilities List Header
644 /// Section 6.7, PCI Local Bus Specification, 2.2
645 ///
646 typedef struct {
650 
651 ///
652 /// PMC - Power Management Capabilities
653 /// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
654 ///
655 typedef union {
656  struct {
665  } Bits;
667 } EFI_PCI_PMC;
668 
669 #define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
670 
671 ///
672 /// PMCSR - Power Management Control/Status
673 /// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2
674 ///
675 typedef union {
676  struct {
685  } Bits;
687 } EFI_PCI_PMCSR;
688 
689 #define PCI_POWER_STATE_D0 0
690 #define PCI_POWER_STATE_D1 1
691 #define PCI_POWER_STATE_D2 2
692 #define PCI_POWER_STATE_D3_HOT 3
693 
694 ///
695 /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
696 /// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
697 ///
698 typedef union {
699  struct {
701  UINT8 B2B3 : 1;
703  } Bits;
706 
707 ///
708 /// Power Management Register Block Definition
709 /// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
710 ///
711 typedef struct {
718 
719 ///
720 /// A.G.P Capability
721 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
722 ///
723 typedef struct {
730 
731 ///
732 /// VPD Capability Structure
733 /// Appendix I, PCI Local Bus Specification, 2.2
734 ///
735 typedef struct {
740 
741 ///
742 /// Slot Numbering Capabilities Register
743 /// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
744 ///
745 typedef struct {
750 
751 ///
752 /// Message Capability Structure for 32-bit Message Address
753 /// Section 6.8.1, PCI Local Bus Specification, 2.2
754 ///
755 typedef struct {
761 
762 ///
763 /// Message Capability Structure for 64-bit Message Address
764 /// Section 6.8.1, PCI Local Bus Specification, 2.2
765 ///
766 typedef struct {
773 
774 ///
775 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
776 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
777 ///
778 typedef struct {
780  ///
781  /// not finished - fields need to go here
782  ///
784 
785 #define PCI_BAR_IDX0 0x00
786 #define PCI_BAR_IDX1 0x01
787 #define PCI_BAR_IDX2 0x02
788 #define PCI_BAR_IDX3 0x03
789 #define PCI_BAR_IDX4 0x04
790 #define PCI_BAR_IDX5 0x05
791 
792 ///
793 /// EFI PCI Option ROM definitions
794 ///
795 #define EFI_ROOT_BRIDGE_LIST 'eprb'
796 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
797 
798 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
799 #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
800 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
801 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
802 
803 ///
804 /// Standard PCI Expansion ROM Header
805 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
806 ///
807 typedef struct {
808  UINT16 Signature; ///< 0xaa55
812 
813 ///
814 /// Legacy ROM Header Extensions
815 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
816 ///
817 typedef struct {
818  UINT16 Signature; ///< 0xaa55
820  UINT8 InitEntryPoint[3];
824 
825 ///
826 /// PCI Data Structure Format
827 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
828 ///
829 typedef struct {
830  UINT32 Signature; ///< "PCIR"
836  UINT8 ClassCode[3];
843 
844 ///
845 /// EFI PCI Expansion ROM Header
846 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
847 ///
848 typedef struct {
849  UINT16 Signature; ///< 0xaa55
851  UINT32 EfiSignature; ///< 0x0EF1
859 
860 typedef union {
866 
867 #pragma pack()
868 
869 #endif
PCI_EXPANSION_ROM_HEADER * Generic
Definition: Pci22.h:862
UINT16 Reserved0
Definition: Pci22.h:833
UINT8 PciBusNumber
PCI Bus Number.
Definition: Pci22.h:130
PCI-to-PCI Bridge Configuration Space Section 3.2, PCI-PCI Bridge Architecture, Version 1....
Definition: Pci22.h:111
UINT16 Reserved
Definition: Pci22.h:659
UINT16 Length
Definition: Pci22.h:834
UINT8 CardBusBusNumber
CardBus Bus Number.
Definition: Pci22.h:131
UINT32 IoLimit0
I/O Base Register 0.
Definition: Pci22.h:139
UINT16 D2Support
Definition: Pci22.h:663
UINT16 CodeRevision
Definition: Pci22.h:838
Message Capability Structure for 64-bit Message Address Section 6.8.1, PCI Local Bus Specification,...
Definition: Pci22.h:766
UINT32 Signature
"PCIR"
Definition: Pci22.h:830
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:779
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:736
PCI Device header region in PCI Configuration Space Section 6.1, PCI Local Bus Specification,...
Definition: Pci22.h:54
PMCSR - Power Management Control/Status Section 3.2.4, PCI Power Management Interface Specifiction,...
Definition: Pci22.h:675
UINT16 NoSoftReset
Definition: Pci22.h:679
A.G.P Capability Section 6.1.4, Accelerated Graphics Port Interface Specification,...
Definition: Pci22.h:723
UINT16 Data
Definition: Pci22.h:686
UINT32 IoBase1
I/O Limit Register 0.
Definition: Pci22.h:140
PCI_TYPE01 Bridge
Definition: Pci22.h:118
unsigned int UINT32
Definition: ProcessorBind.h:56
UINT8 Indicator
Definition: Pci22.h:840
VPD Capability Structure Appendix I, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:735
UINT16 Version
Definition: Pci22.h:657
UINT16 SecondaryStatus
Secondary Status.
Definition: Pci22.h:129
UINT8 SubordinateBusNumber
Subordinate Bus Number.
Definition: Pci22.h:132
UINT32 CardBusSocketReg
Cardus Socket/ExCA Base.
Definition: Pci22.h:126
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions Section 3.2.5, PCI Power Management Interface ...
Definition: Pci22.h:698
UINT8 BusPowerClockControl
Definition: Pci22.h:702
unsigned char UINT8
Definition: ProcessorBind.h:62
UINT16 PrefetchableMemoryBase
Definition: Pci22.h:93
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:767
UINT16 ImageLength
Definition: Pci22.h:837
Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, CompactPCI Hot Swap Specification PICMG 2....
Definition: Pci22.h:778
PCI_BRIDGE_CONTROL_REGISTER Bridge
Definition: Pci22.h:113
UINT16 DataSelect
Definition: Pci22.h:682
PCI Device Configuration Space Section 6.1, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:73
PCI_DEVICE_INDEPENDENT_REGION Hdr
Definition: Pci22.h:74
UINT16 VendorId
Definition: Pci22.h:831
PCI_DEVICE_INDEPENDENT_REGION Hdr
Definition: Pci22.h:112
UINT16 Data
Definition: Pci22.h:666
UINT16 ReservedForPciExpress
Definition: Pci22.h:678
Standard PCI Expansion ROM Header Section 13.4.2, Unified Extensible Firmware Interface Specification...
Definition: Pci22.h:807
PCI-PCI Bridge header region in PCI Configuration Space Section 3.2, PCI-PCI Bridge Architecture,...
Definition: Pci22.h:82
UINT8 * Raw
Definition: Pci22.h:861
Power Management Register Block Definition Section 3.2, PCI Power Management Interface Specifiction,...
Definition: Pci22.h:711
CardBus Conroller Configuration Space, Section 4.5.1, PC Card Standard.
Definition: Pci22.h:125
UINT16 AuxCurrent
Definition: Pci22.h:661
EFI_PCI_PMCSR_BSE BridgeExtention
Definition: Pci22.h:715
UINT32 MemoryBase0
Memory Base Register 0.
Definition: Pci22.h:134
EFI_LEGACY_EXPANSION_ROM_HEADER * PcAt
Definition: Pci22.h:864
EFI_PCI_EXPANSION_ROM_HEADER * Efi
Definition: Pci22.h:863
UINT8 Reserved
Definition: Pci22.h:700
UINT16 PrefetchableMemoryLimit
Definition: Pci22.h:94
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:756
PCI_TYPE00 Device
Definition: Pci22.h:117
UINT16 PmeSupport
Definition: Pci22.h:664
unsigned short UINT16
Definition: ProcessorBind.h:58
UINT8 Reserved
Must be zero.
Definition: Acpi30.h:42
UINT16 PmeStatus
Definition: Pci22.h:684
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:746
Message Capability Structure for 32-bit Message Address Section 6.8.1, PCI Local Bus Specification,...
Definition: Pci22.h:755
UINT16 Signature
0xaa55
Definition: Pci22.h:849
Slot Numbering Capabilities Register Section 3.2.6, PCI-to-PCI Bridge Architeture Specification,...
Definition: Pci22.h:745
UINT32 MemoryLimit0
Memory Limit Register 0.
Definition: Pci22.h:135
UINT8 InterruptLine
Interrupt Line.
Definition: Pci22.h:142
UINT32 EfiSignature
0x0EF1
Definition: Pci22.h:851
UINT16 BridgeControl
Bridge Control.
Definition: Pci22.h:144
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:724
UINT16 D1Support
Definition: Pci22.h:662
UINT16 DataScale
Definition: Pci22.h:683
EFI PCI Expansion ROM Header Section 13.4.2, Unified Extensible Firmware Interface Specification,...
Definition: Pci22.h:848
UINT8 CardBusLatencyTimer
CardBus Latency Timer.
Definition: Pci22.h:133
PCI Access Data Format.
Definition: Pci22.h:568
EFI_PCI_PMCSR PMCSR
Definition: Pci22.h:714
UINT8 CodeType
Definition: Pci22.h:839
UINT16 Reserved1
Definition: Pci22.h:841
UINT16 PmeClock
Definition: Pci22.h:658
UINT16 PmeEnable
Definition: Pci22.h:681
UINT16 Reserved
Definition: Pci22.h:680
PCI Data Structure Format Section 6.3.1.2, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:829
PCI_DEVICE_HEADER_TYPE_REGION Device
Definition: Pci22.h:75
Common header region in PCI Configuration Space Section 6.1, PCI Local Bus Specification,...
Definition: Pci22.h:37
PACKED struct @458::@472 Bits
UINT16 DeviceId
Definition: Pci22.h:832
PMC - Power Management Capabilities Section 3.2.3, PCI Power Management Interface Specifiction,...
Definition: Pci22.h:655
UINT32 PrefetchableLimitUpper32
Definition: Pci22.h:96
UINT32 PrefetchableBaseUpper32
Definition: Pci22.h:95
UINT16 PowerState
Definition: Pci22.h:677
FILE_LICENCE(BSD3)
Legacy ROM Header Extensions Section 6.3.3.1, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:817
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:712
EFI_PCI_PMC PMC
Definition: Pci22.h:713
UINT8 Revision
Definition: Pci22.h:835
UINT8 InterruptPin
Interrupt Pin.
Definition: Pci22.h:143
Capabilities List Header Section 6.7, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:646
UINT16 Signature
0xaa55
Definition: Pci22.h:808
UINT16 DeviceSpecificInitialization
Definition: Pci22.h:660