iPXE
Pci22.h
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1 /** @file
2  Support for PCI 2.2 standard.
3 
4  This file includes the definitions in the following specifications,
5  PCI Local Bus Specification, 2.2
6  PCI-to-PCI Bridge Architecture Specification, Revision 1.2
7  PC Card Standard, 8.0
8  PCI Power Management Interface Specification, Revision 1.2
9 
10  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
11  Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
12  SPDX-License-Identifier: BSD-2-Clause-Patent
13 
14 **/
15 
16 #ifndef _PCI22_H_
17 #define _PCI22_H_
18 
19 FILE_LICENCE ( BSD2_PATENT );
20 
21 #define PCI_MAX_BUS 255
22 #define PCI_MAX_DEVICE 31
23 #define PCI_MAX_FUNC 7
24 
25 #pragma pack(1)
26 
27 ///
28 /// Common header region in PCI Configuration Space
29 /// Section 6.1, PCI Local Bus Specification, 2.2
30 ///
31 typedef struct {
37  UINT8 ClassCode[3];
43 
44 ///
45 /// PCI Device header region in PCI Configuration Space
46 /// Section 6.1, PCI Local Bus Specification, 2.2
47 ///
48 typedef struct {
49  UINT32 Bar[6];
55  UINT8 Reserved1[3];
62 
63 ///
64 /// PCI Device Configuration Space
65 /// Section 6.1, PCI Local Bus Specification, 2.2
66 ///
67 typedef struct {
70 } PCI_TYPE00;
71 
72 ///
73 /// PCI-PCI Bridge header region in PCI Configuration Space
74 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
75 ///
76 typedef struct {
77  UINT32 Bar[2];
100 
101 ///
102 /// PCI-to-PCI Bridge Configuration Space
103 /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2
104 ///
105 typedef struct {
108 } PCI_TYPE01;
109 
110 typedef union {
114 
115 ///
116 /// CardBus Controller Configuration Space,
117 /// Section 4.5.1, PC Card Standard. 8.0
118 ///
119 typedef struct {
120  UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base
123  UINT16 SecondaryStatus; ///< Secondary Status
124  UINT8 PciBusNumber; ///< PCI Bus Number
125  UINT8 CardBusBusNumber; ///< CardBus Bus Number
126  UINT8 SubordinateBusNumber; ///< Subordinate Bus Number
127  UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer
128  UINT32 MemoryBase0; ///< Memory Base Register 0
129  UINT32 MemoryLimit0; ///< Memory Limit Register 0
133  UINT32 IoLimit0; ///< I/O Base Register 0
134  UINT32 IoBase1; ///< I/O Limit Register 0
136  UINT8 InterruptLine; ///< Interrupt Line
137  UINT8 InterruptPin; ///< Interrupt Pin
138  UINT16 BridgeControl; ///< Bridge Control
140 
141 //
142 // Definitions of PCI class bytes and manipulation macros.
143 //
144 #define PCI_CLASS_OLD 0x00
145 #define PCI_CLASS_OLD_OTHER 0x00
146 #define PCI_CLASS_OLD_VGA 0x01
147 
148 #define PCI_CLASS_MASS_STORAGE 0x01
149 #define PCI_CLASS_MASS_STORAGE_SCSI 0x00
150 #define PCI_CLASS_MASS_STORAGE_IDE 0x01
151 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
152 #define PCI_CLASS_MASS_STORAGE_IPI 0x03
153 #define PCI_CLASS_MASS_STORAGE_RAID 0x04
154 #define PCI_CLASS_MASS_STORAGE_OTHER 0x80
155 
156 #define PCI_CLASS_NETWORK 0x02
157 #define PCI_CLASS_NETWORK_ETHERNET 0x00
158 #define PCI_CLASS_NETWORK_TOKENRING 0x01
159 #define PCI_CLASS_NETWORK_FDDI 0x02
160 #define PCI_CLASS_NETWORK_ATM 0x03
161 #define PCI_CLASS_NETWORK_ISDN 0x04
162 #define PCI_CLASS_NETWORK_OTHER 0x80
163 
164 #define PCI_CLASS_DISPLAY 0x03
165 #define PCI_CLASS_DISPLAY_VGA 0x00
166 #define PCI_IF_VGA_VGA 0x00
167 #define PCI_IF_VGA_8514 0x01
168 #define PCI_CLASS_DISPLAY_XGA 0x01
169 #define PCI_CLASS_DISPLAY_3D 0x02
170 #define PCI_CLASS_DISPLAY_OTHER 0x80
171 
172 #define PCI_CLASS_MEDIA 0x04
173 #define PCI_CLASS_MEDIA_VIDEO 0x00
174 #define PCI_CLASS_MEDIA_AUDIO 0x01
175 #define PCI_CLASS_MEDIA_TELEPHONE 0x02
176 #define PCI_CLASS_MEDIA_OTHER 0x80
177 
178 #define PCI_CLASS_MEMORY_CONTROLLER 0x05
179 #define PCI_CLASS_MEMORY_RAM 0x00
180 #define PCI_CLASS_MEMORY_FLASH 0x01
181 #define PCI_CLASS_MEMORY_OTHER 0x80
182 
183 #define PCI_CLASS_BRIDGE 0x06
184 #define PCI_CLASS_BRIDGE_HOST 0x00
185 #define PCI_CLASS_BRIDGE_ISA 0x01
186 #define PCI_CLASS_BRIDGE_EISA 0x02
187 #define PCI_CLASS_BRIDGE_MCA 0x03
188 #define PCI_CLASS_BRIDGE_P2P 0x04
189 #define PCI_IF_BRIDGE_P2P 0x00
190 #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
191 #define PCI_CLASS_BRIDGE_PCMCIA 0x05
192 #define PCI_CLASS_BRIDGE_NUBUS 0x06
193 #define PCI_CLASS_BRIDGE_CARDBUS 0x07
194 #define PCI_CLASS_BRIDGE_RACEWAY 0x08
195 #define PCI_CLASS_BRIDGE_OTHER 0x80
196 #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
197 
198 #define PCI_CLASS_SCC 0x07///< Simple communications controllers
199 #define PCI_SUBCLASS_SERIAL 0x00
200 #define PCI_IF_GENERIC_XT 0x00
201 #define PCI_IF_16450 0x01
202 #define PCI_IF_16550 0x02
203 #define PCI_IF_16650 0x03
204 #define PCI_IF_16750 0x04
205 #define PCI_IF_16850 0x05
206 #define PCI_IF_16950 0x06
207 #define PCI_SUBCLASS_PARALLEL 0x01
208 #define PCI_IF_PARALLEL_PORT 0x00
209 #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
210 #define PCI_IF_ECP_PARALLEL_PORT 0x02
211 #define PCI_IF_1284_CONTROLLER 0x03
212 #define PCI_IF_1284_DEVICE 0xFE
213 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
214 #define PCI_SUBCLASS_MODEM 0x03
215 #define PCI_IF_GENERIC_MODEM 0x00
216 #define PCI_IF_16450_MODEM 0x01
217 #define PCI_IF_16550_MODEM 0x02
218 #define PCI_IF_16650_MODEM 0x03
219 #define PCI_IF_16750_MODEM 0x04
220 #define PCI_SUBCLASS_SCC_OTHER 0x80
221 
222 #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
223 #define PCI_SUBCLASS_PIC 0x00
224 #define PCI_IF_8259_PIC 0x00
225 #define PCI_IF_ISA_PIC 0x01
226 #define PCI_IF_EISA_PIC 0x02
227 #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.
228 #define PCI_IF_APIC_CONTROLLER2 0x20
229 #define PCI_SUBCLASS_DMA 0x01
230 #define PCI_IF_8237_DMA 0x00
231 #define PCI_IF_ISA_DMA 0x01
232 #define PCI_IF_EISA_DMA 0x02
233 #define PCI_SUBCLASS_TIMER 0x02
234 #define PCI_IF_8254_TIMER 0x00
235 #define PCI_IF_ISA_TIMER 0x01
236 #define PCI_IF_EISA_TIMER 0x02
237 #define PCI_SUBCLASS_RTC 0x03
238 #define PCI_IF_GENERIC_RTC 0x00
239 #define PCI_IF_ISA_RTC 0x01
240 #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller
241 #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
242 
243 #define PCI_CLASS_INPUT_DEVICE 0x09
244 #define PCI_SUBCLASS_KEYBOARD 0x00
245 #define PCI_SUBCLASS_PEN 0x01
246 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
247 #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
248 #define PCI_SUBCLASS_GAMEPORT 0x04
249 #define PCI_IF_GAMEPORT 0x00
250 #define PCI_IF_GAMEPORT1 0x10
251 #define PCI_SUBCLASS_INPUT_OTHER 0x80
252 
253 #define PCI_CLASS_DOCKING_STATION 0x0A
254 #define PCI_SUBCLASS_DOCKING_GENERIC 0x00
255 #define PCI_SUBCLASS_DOCKING_OTHER 0x80
256 
257 #define PCI_CLASS_PROCESSOR 0x0B
258 #define PCI_SUBCLASS_PROC_386 0x00
259 #define PCI_SUBCLASS_PROC_486 0x01
260 #define PCI_SUBCLASS_PROC_PENTIUM 0x02
261 #define PCI_SUBCLASS_PROC_ALPHA 0x10
262 #define PCI_SUBCLASS_PROC_POWERPC 0x20
263 #define PCI_SUBCLASS_PROC_MIPS 0x30
264 #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor
265 
266 #define PCI_CLASS_SERIAL 0x0C
267 #define PCI_CLASS_SERIAL_FIREWIRE 0x00
268 #define PCI_IF_1394 0x00
269 #define PCI_IF_1394_OPEN_HCI 0x10
270 #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
271 #define PCI_CLASS_SERIAL_SSA 0x02
272 #define PCI_CLASS_SERIAL_USB 0x03
273 #define PCI_IF_UHCI 0x00
274 #define PCI_IF_OHCI 0x10
275 #define PCI_IF_USB_OTHER 0x80
276 #define PCI_IF_USB_DEVICE 0xFE
277 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
278 #define PCI_CLASS_SERIAL_SMB 0x05
279 
280 #define PCI_CLASS_WIRELESS 0x0D
281 #define PCI_SUBCLASS_IRDA 0x00
282 #define PCI_SUBCLASS_IR 0x01
283 #define PCI_SUBCLASS_RF 0x10
284 #define PCI_SUBCLASS_WIRELESS_OTHER 0x80
285 
286 #define PCI_CLASS_INTELLIGENT_IO 0x0E
287 
288 #define PCI_CLASS_SATELLITE 0x0F
289 #define PCI_SUBCLASS_TV 0x01
290 #define PCI_SUBCLASS_AUDIO 0x02
291 #define PCI_SUBCLASS_VOICE 0x03
292 #define PCI_SUBCLASS_DATA 0x04
293 
294 #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller
295 #define PCI_SUBCLASS_NET_COMPUT 0x00
296 #define PCI_SUBCLASS_ENTERTAINMENT 0x10
297 #define PCI_SUBCLASS_SECURITY_OTHER 0x80
298 
299 #define PCI_CLASS_DPIO 0x11
300 #define PCI_SUBCLASS_DPIO 0x00
301 #define PCI_SUBCLASS_DPIO_OTHER 0x80
302 
303 /**
304  Macro that checks whether the Base Class code of device matched.
305 
306  @param _p Specified device.
307  @param c Base Class code needs matching.
308 
309  @retval TRUE Base Class code matches the specified device.
310  @retval FALSE Base Class code doesn't match the specified device.
311 
312 **/
313 #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
314 
315 /**
316  Macro that checks whether the Base Class code and Sub-Class code of device matched.
317 
318  @param _p Specified device.
319  @param c Base Class code needs matching.
320  @param s Sub-Class code needs matching.
321 
322  @retval TRUE Base Class code and Sub-Class code match the specified device.
323  @retval FALSE Base Class code and Sub-Class code don't match the specified device.
324 
325 **/
326 #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
327 
328 /**
329  Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
330 
331  @param _p Specified device.
332  @param c Base Class code needs matching.
333  @param s Sub-Class code needs matching.
334  @param p Interface code needs matching.
335 
336  @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.
337  @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.
338 
339 **/
340 #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
341 
342 /**
343  Macro that checks whether device is a display controller.
344 
345  @param _p Specified device.
346 
347  @retval TRUE Device is a display controller.
348  @retval FALSE Device is not a display controller.
349 
350 **/
351 #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
352 
353 /**
354  Macro that checks whether device is a VGA-compatible controller.
355 
356  @param _p Specified device.
357 
358  @retval TRUE Device is a VGA-compatible controller.
359  @retval FALSE Device is not a VGA-compatible controller.
360 
361 **/
362 #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
363 
364 /**
365  Macro that checks whether device is an 8514-compatible controller.
366 
367  @param _p Specified device.
368 
369  @retval TRUE Device is an 8514-compatible controller.
370  @retval FALSE Device is not an 8514-compatible controller.
371 
372 **/
373 #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
374 
375 /**
376  Macro that checks whether device is built before the Class Code field was defined.
377 
378  @param _p Specified device.
379 
380  @retval TRUE Device is an old device.
381  @retval FALSE Device is not an old device.
382 
383 **/
384 #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)
385 
386 /**
387  Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
388 
389  @param _p Specified device.
390 
391  @retval TRUE Device is an old VGA-compatible device.
392  @retval FALSE Device is not an old VGA-compatible device.
393 
394 **/
395 #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
396 
397 /**
398  Macro that checks whether device is an IDE controller.
399 
400  @param _p Specified device.
401 
402  @retval TRUE Device is an IDE controller.
403  @retval FALSE Device is not an IDE controller.
404 
405 **/
406 #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
407 
408 /**
409  Macro that checks whether device is a SCSI bus controller.
410 
411  @param _p Specified device.
412 
413  @retval TRUE Device is a SCSI bus controller.
414  @retval FALSE Device is not a SCSI bus controller.
415 
416 **/
417 #define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
418 
419 /**
420  Macro that checks whether device is a RAID controller.
421 
422  @param _p Specified device.
423 
424  @retval TRUE Device is a RAID controller.
425  @retval FALSE Device is not a RAID controller.
426 
427 **/
428 #define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
429 
430 /**
431  Macro that checks whether device is an ISA bridge.
432 
433  @param _p Specified device.
434 
435  @retval TRUE Device is an ISA bridge.
436  @retval FALSE Device is not an ISA bridge.
437 
438 **/
439 #define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
440 
441 /**
442  Macro that checks whether device is a PCI-to-PCI bridge.
443 
444  @param _p Specified device.
445 
446  @retval TRUE Device is a PCI-to-PCI bridge.
447  @retval FALSE Device is not a PCI-to-PCI bridge.
448 
449 **/
450 #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
451 
452 /**
453  Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
454 
455  @param _p Specified device.
456 
457  @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.
458  @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.
459 
460 **/
461 #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
462 
463 /**
464  Macro that checks whether device is a 16550-compatible serial controller.
465 
466  @param _p Specified device.
467 
468  @retval TRUE Device is a 16550-compatible serial controller.
469  @retval FALSE Device is not a 16550-compatible serial controller.
470 
471 **/
472 #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
473 
474 /**
475  Macro that checks whether device is a Universal Serial Bus controller.
476 
477  @param _p Specified device.
478 
479  @retval TRUE Device is a Universal Serial Bus controller.
480  @retval FALSE Device is not a Universal Serial Bus controller.
481 
482 **/
483 #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
484 
485 //
486 // the definition of Header Type
487 //
488 #define HEADER_TYPE_DEVICE 0x00
489 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
490 #define HEADER_TYPE_CARDBUS_BRIDGE 0x02
491 #define HEADER_TYPE_MULTI_FUNCTION 0x80
492 //
493 // Mask of Header type
494 //
495 #define HEADER_LAYOUT_CODE 0x7f
496 
497 /**
498  Macro that checks whether device is a PCI-PCI bridge.
499 
500  @param _p Specified device.
501 
502  @retval TRUE Device is a PCI-PCI bridge.
503  @retval FALSE Device is not a PCI-PCI bridge.
504 
505 **/
506 #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
507 
508 /**
509  Macro that checks whether device is a CardBus bridge.
510 
511  @param _p Specified device.
512 
513  @retval TRUE Device is a CardBus bridge.
514  @retval FALSE Device is not a CardBus bridge.
515 
516 **/
517 #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
518 
519 /**
520  Macro that checks whether device is a multiple functions device.
521 
522  @param _p Specified device.
523 
524  @retval TRUE Device is a multiple functions device.
525  @retval FALSE Device is not a multiple functions device.
526 
527 **/
528 #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
529 
530 ///
531 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,
532 ///
533 #define PCI_BRIDGE_ROMBAR 0x38
534 
535 #define PCI_MAX_BAR 0x0006
536 #define PCI_MAX_CONFIG_OFFSET 0x0100
537 
538 #define PCI_VENDOR_ID_OFFSET 0x00
539 #define PCI_DEVICE_ID_OFFSET 0x02
540 #define PCI_COMMAND_OFFSET 0x04
541 #define PCI_PRIMARY_STATUS_OFFSET 0x06
542 #define PCI_REVISION_ID_OFFSET 0x08
543 #define PCI_CLASSCODE_OFFSET 0x09
544 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
545 #define PCI_LATENCY_TIMER_OFFSET 0x0D
546 #define PCI_HEADER_TYPE_OFFSET 0x0E
547 #define PCI_BIST_OFFSET 0x0F
548 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
549 #define PCI_CARDBUS_CIS_OFFSET 0x28
550 #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id
551 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
552 #define PCI_SID_OFFSET 0x2E ///< SubSystem ID
553 #define PCI_SUBSYSTEM_ID_OFFSET 0x2E
554 #define PCI_EXPANSION_ROM_BASE 0x30
555 #define PCI_CAPBILITY_POINTER_OFFSET 0x34
556 #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register
557 #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register
558 #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register
559 #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register
560 
561 //
562 // defined in PCI-to-PCI Bridge Architecture Specification
563 //
564 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18
565 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19
566 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a
567 #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b
568 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
569 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
570 
571 ///
572 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
573 ///
574 #define PCI_INT_LINE_UNKNOWN 0xFF
575 
576 ///
577 /// PCI Access Data Format
578 ///
579 typedef union {
580  struct {
581  UINT32 Reg : 8;
583  UINT32 Dev : 5;
584  UINT32 Bus : 8;
587  } Bits;
590 
591 #pragma pack()
592 
593 #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001
594 #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002
595 #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004
596 #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008
597 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010
598 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020
599 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040
600 #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080
601 #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100
602 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
603 
604 //
605 // defined in PCI-to-PCI Bridge Architecture Specification
606 //
607 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001
608 #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002
609 #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004
610 #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008
611 #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010
612 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020
613 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040
614 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080
615 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100
616 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
617 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400
618 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800
619 
620 //
621 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
622 //
623 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080
624 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100
625 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
626 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400
627 
628 //
629 // Following are the PCI status control bit
630 //
631 #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010
632 #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020
633 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080
634 #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100
635 
636 ///
637 /// defined in PC Card Standard
638 ///
639 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
640 
641 #pragma pack(1)
642 //
643 // PCI Capability List IDs and records
644 //
645 #define EFI_PCI_CAPABILITY_ID_PMI 0x01
646 #define EFI_PCI_CAPABILITY_ID_AGP 0x02
647 #define EFI_PCI_CAPABILITY_ID_VPD 0x03
648 #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
649 #define EFI_PCI_CAPABILITY_ID_MSI 0x05
650 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
651 #define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
652 
653 ///
654 /// Capabilities List Header
655 /// Section 6.7, PCI Local Bus Specification, 2.2
656 ///
657 typedef struct {
661 
662 ///
663 /// PMC - Power Management Capabilities
664 /// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2
665 ///
666 typedef union {
667  struct {
676  } Bits;
678 } EFI_PCI_PMC;
679 
680 #define EFI_PCI_PMC_D3_COLD_MASK (BIT15)
681 
682 ///
683 /// PMCSR - Power Management Control/Status
684 /// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2
685 ///
686 typedef union {
687  struct {
696  } Bits;
698 } EFI_PCI_PMCSR;
699 
700 #define PCI_POWER_STATE_D0 0
701 #define PCI_POWER_STATE_D1 1
702 #define PCI_POWER_STATE_D2 2
703 #define PCI_POWER_STATE_D3_HOT 3
704 
705 ///
706 /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
707 /// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2
708 ///
709 typedef union {
710  struct {
712  UINT8 B2B3 : 1;
714  } Bits;
717 
718 ///
719 /// Power Management Register Block Definition
720 /// Section 3.2, PCI Power Management Interface Specification, Revision 1.2
721 ///
722 typedef struct {
729 
730 ///
731 /// A.G.P Capability
732 /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
733 ///
734 typedef struct {
741 
742 ///
743 /// VPD Capability Structure
744 /// Appendix I, PCI Local Bus Specification, 2.2
745 ///
746 typedef struct {
751 
752 ///
753 /// Slot Numbering Capabilities Register
754 /// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2
755 ///
756 typedef struct {
761 
762 ///
763 /// Message Capability Structure for 32-bit Message Address
764 /// Section 6.8.1, PCI Local Bus Specification, 2.2
765 ///
766 typedef struct {
772 
773 ///
774 /// Message Capability Structure for 64-bit Message Address
775 /// Section 6.8.1, PCI Local Bus Specification, 2.2
776 ///
777 typedef struct {
784 
785 ///
786 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
787 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
788 ///
789 typedef struct {
791  ///
792  /// not finished - fields need to go here
793  ///
795 
796 #define PCI_BAR_IDX0 0x00
797 #define PCI_BAR_IDX1 0x01
798 #define PCI_BAR_IDX2 0x02
799 #define PCI_BAR_IDX3 0x03
800 #define PCI_BAR_IDX4 0x04
801 #define PCI_BAR_IDX5 0x05
802 
803 ///
804 /// EFI PCI Option ROM definitions
805 ///
806 #define EFI_ROOT_BRIDGE_LIST 'eprb'
807 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.
808 
809 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
810 #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')
811 #define PCI_CODE_TYPE_PCAT_IMAGE 0x00
812 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.
813 
814 ///
815 /// Standard PCI Expansion ROM Header
816 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
817 ///
818 typedef struct {
819  UINT16 Signature; ///< 0xaa55
823 
824 ///
825 /// Legacy ROM Header Extensions
826 /// Section 6.3.3.1, PCI Local Bus Specification, 2.2
827 ///
828 typedef struct {
829  UINT16 Signature; ///< 0xaa55
831  UINT8 InitEntryPoint[3];
835 
836 ///
837 /// PCI Data Structure Format
838 /// Section 6.3.1.2, PCI Local Bus Specification, 2.2
839 ///
840 typedef struct {
841  UINT32 Signature; ///< "PCIR"
847  UINT8 ClassCode[3];
854 
855 ///
856 /// EFI PCI Expansion ROM Header
857 /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1
858 ///
859 typedef struct {
860  UINT16 Signature; ///< 0xaa55
862  UINT32 EfiSignature; ///< 0x0EF1
870 
871 typedef union {
877 
878 #pragma pack()
879 
880 #endif
PCI_EXPANSION_ROM_HEADER * Generic
Definition: Pci22.h:873
UINT16 Reserved0
Definition: Pci22.h:844
UINT8 PciBusNumber
PCI Bus Number.
Definition: Pci22.h:124
PCI-to-PCI Bridge Configuration Space Section 3.2, PCI-PCI Bridge Architecture, Version 1....
Definition: Pci22.h:105
UINT16 Reserved
Definition: Pci22.h:670
UINT16 Length
Definition: Pci22.h:845
UINT8 CardBusBusNumber
CardBus Bus Number.
Definition: Pci22.h:125
UINT32 IoLimit0
I/O Base Register 0.
Definition: Pci22.h:133
UINT16 D2Support
Definition: Pci22.h:674
UINT16 CodeRevision
Definition: Pci22.h:849
Message Capability Structure for 64-bit Message Address Section 6.8.1, PCI Local Bus Specification,...
Definition: Pci22.h:777
UINT32 Signature
"PCIR"
Definition: Pci22.h:841
PACKED struct @467::@481 Bits
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:790
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:747
PCI Device header region in PCI Configuration Space Section 6.1, PCI Local Bus Specification,...
Definition: Pci22.h:48
PMCSR - Power Management Control/Status Section 3.2.4, PCI Power Management Interface Specification,...
Definition: Pci22.h:686
UINT16 NoSoftReset
Definition: Pci22.h:690
A.G.P Capability Section 6.1.4, Accelerated Graphics Port Interface Specification,...
Definition: Pci22.h:734
UINT16 Data
Definition: Pci22.h:697
UINT32 IoBase1
I/O Limit Register 0.
Definition: Pci22.h:134
PCI_TYPE01 Bridge
Definition: Pci22.h:112
unsigned int UINT32
Definition: ProcessorBind.h:98
UINT8 Indicator
Definition: Pci22.h:851
VPD Capability Structure Appendix I, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:746
UINT16 Version
Definition: Pci22.h:668
UINT16 SecondaryStatus
Secondary Status.
Definition: Pci22.h:123
UINT8 SubordinateBusNumber
Subordinate Bus Number.
Definition: Pci22.h:126
UINT32 CardBusSocketReg
Cardbus Socket/ExCA Base.
Definition: Pci22.h:120
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions Section 3.2.5, PCI Power Management Interface ...
Definition: Pci22.h:709
FILE_LICENCE(BSD2_PATENT)
UINT8 BusPowerClockControl
Definition: Pci22.h:713
unsigned char UINT8
UINT16 PrefetchableMemoryBase
Definition: Pci22.h:87
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:778
UINT16 ImageLength
Definition: Pci22.h:848
Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, CompactPCI Hot Swap Specification PICMG 2....
Definition: Pci22.h:789
PCI_BRIDGE_CONTROL_REGISTER Bridge
Definition: Pci22.h:107
UINT16 DataSelect
Definition: Pci22.h:693
PCI Device Configuration Space Section 6.1, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:67
PCI_DEVICE_INDEPENDENT_REGION Hdr
Definition: Pci22.h:68
UINT16 VendorId
Definition: Pci22.h:842
PCI_DEVICE_INDEPENDENT_REGION Hdr
Definition: Pci22.h:106
UINT16 Data
Definition: Pci22.h:677
UINT16 ReservedForPciExpress
Definition: Pci22.h:689
Standard PCI Expansion ROM Header Section 13.4.2, Unified Extensible Firmware Interface Specification...
Definition: Pci22.h:818
PCI-PCI Bridge header region in PCI Configuration Space Section 3.2, PCI-PCI Bridge Architecture,...
Definition: Pci22.h:76
UINT8 * Raw
Definition: Pci22.h:872
Power Management Register Block Definition Section 3.2, PCI Power Management Interface Specification,...
Definition: Pci22.h:722
CardBus Controller Configuration Space, Section 4.5.1, PC Card Standard.
Definition: Pci22.h:119
UINT16 AuxCurrent
Definition: Pci22.h:672
EFI_PCI_PMCSR_BSE BridgeExtention
Definition: Pci22.h:726
UINT32 MemoryBase0
Memory Base Register 0.
Definition: Pci22.h:128
EFI_LEGACY_EXPANSION_ROM_HEADER * PcAt
Definition: Pci22.h:875
EFI_PCI_EXPANSION_ROM_HEADER * Efi
Definition: Pci22.h:874
UINT8 Reserved
Definition: Pci22.h:711
UINT16 PrefetchableMemoryLimit
Definition: Pci22.h:88
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:767
PCI_TYPE00 Device
Definition: Pci22.h:111
UINT16 PmeSupport
Definition: Pci22.h:675
unsigned short UINT16
UINT8 Reserved
Must be zero.
Definition: Acpi30.h:36
UINT16 PmeStatus
Definition: Pci22.h:695
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:757
Message Capability Structure for 32-bit Message Address Section 6.8.1, PCI Local Bus Specification,...
Definition: Pci22.h:766
UINT16 Signature
0xaa55
Definition: Pci22.h:860
Slot Numbering Capabilities Register Section 3.2.6, PCI-to-PCI Bridge Architecture Specification,...
Definition: Pci22.h:756
UINT32 MemoryLimit0
Memory Limit Register 0.
Definition: Pci22.h:129
UINT8 InterruptLine
Interrupt Line.
Definition: Pci22.h:136
UINT32 EfiSignature
0x0EF1
Definition: Pci22.h:862
UINT16 BridgeControl
Bridge Control.
Definition: Pci22.h:138
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:735
UINT16 D1Support
Definition: Pci22.h:673
UINT16 DataScale
Definition: Pci22.h:694
EFI PCI Expansion ROM Header Section 13.4.2, Unified Extensible Firmware Interface Specification,...
Definition: Pci22.h:859
UINT8 CardBusLatencyTimer
CardBus Latency Timer.
Definition: Pci22.h:127
PCI Access Data Format.
Definition: Pci22.h:579
EFI_PCI_PMCSR PMCSR
Definition: Pci22.h:725
UINT8 CodeType
Definition: Pci22.h:850
UINT16 Reserved1
Definition: Pci22.h:852
UINT16 PmeClock
Definition: Pci22.h:669
UINT16 PmeEnable
Definition: Pci22.h:692
UINT16 Reserved
Definition: Pci22.h:691
PCI Data Structure Format Section 6.3.1.2, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:840
PCI_DEVICE_HEADER_TYPE_REGION Device
Definition: Pci22.h:69
Common header region in PCI Configuration Space Section 6.1, PCI Local Bus Specification,...
Definition: Pci22.h:31
UINT16 DeviceId
Definition: Pci22.h:843
PMC - Power Management Capabilities Section 3.2.3, PCI Power Management Interface Specification,...
Definition: Pci22.h:666
UINT32 PrefetchableLimitUpper32
Definition: Pci22.h:90
UINT32 PrefetchableBaseUpper32
Definition: Pci22.h:89
UINT16 PowerState
Definition: Pci22.h:688
Legacy ROM Header Extensions Section 6.3.3.1, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:828
EFI_PCI_CAPABILITY_HDR Hdr
Definition: Pci22.h:723
EFI_PCI_PMC PMC
Definition: Pci22.h:724
UINT8 Revision
Definition: Pci22.h:846
UINT8 InterruptPin
Interrupt Pin.
Definition: Pci22.h:137
Capabilities List Header Section 6.7, PCI Local Bus Specification, 2.2.
Definition: Pci22.h:657
UINT16 Signature
0xaa55
Definition: Pci22.h:819
UINT16 DeviceSpecificInitialization
Definition: Pci22.h:671