iPXE
axge.h
Go to the documentation of this file.
00001 #ifndef _AXGE_H
00002 #define _AXGE_H
00003 
00004 /** @file
00005  *
00006  * Asix 10/100/1000 USB Ethernet driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <ipxe/usb.h>
00013 #include <ipxe/usbnet.h>
00014 
00015 /** Read MAC register */
00016 #define AXGE_READ_MAC_REGISTER                                          \
00017         ( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE |             \
00018           USB_REQUEST_TYPE ( 0x01 ) )
00019 
00020 /** Write MAC register */
00021 #define AXGE_WRITE_MAC_REGISTER                                         \
00022         ( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE |            \
00023           USB_REQUEST_TYPE ( 0x01 ) )
00024 
00025 /** Physical Link Status Register */
00026 #define AXGE_PLSR 0x02
00027 #define AXGE_PLSR_EPHY_10               0x10    /**< Ethernet at 10Mbps */
00028 #define AXGE_PLSR_EPHY_100              0x20    /**< Ethernet at 100Mbps */
00029 #define AXGE_PLSR_EPHY_1000             0x40    /**< Ethernet at 1000Mbps */
00030 #define AXGE_PLSR_EPHY_ANY                                              \
00031         ( AXGE_PLSR_EPHY_10 |                                           \
00032           AXGE_PLSR_EPHY_100 |                                          \
00033           AXGE_PLSR_EPHY_1000 )
00034 
00035 /** RX Control Register */
00036 #define AXGE_RCR 0x0b
00037 #define AXGE_RCR_PRO                    0x0001  /**< Promiscuous mode */
00038 #define AXGE_RCR_AMALL                  0x0002  /**< Accept all multicasts */
00039 #define AXGE_RCR_AB                     0x0008  /**< Accept broadcasts */
00040 #define AXGE_RCR_SO                     0x0080  /**< Start operation */
00041 
00042 /** Node ID Register */
00043 #define AXGE_NIDR 0x10
00044 
00045 /** Medium Status Register */
00046 #define AXGE_MSR 0x22
00047 #define AXGE_MSR_GM                     0x0001  /**< Gigabit mode */
00048 #define AXGE_MSR_FD                     0x0002  /**< Full duplex */
00049 #define AXGE_MSR_RFC                    0x0010  /**< RX flow control enable */
00050 #define AXGE_MSR_TFC                    0x0020  /**< TX flow control enable */
00051 #define AXGE_MSR_RE                     0x0100  /**< Receive enable */
00052 
00053 /** Ethernet PHY Power and Reset Control Register */
00054 #define AXGE_EPPRCR 0x26
00055 #define AXGE_EPPRCR_IPRL                0x0020  /**< Undocumented */
00056 
00057 /** Delay after initialising EPPRCR */
00058 #define AXGE_EPPRCR_DELAY_MS 200
00059 
00060 /** Bulk IN Control Register (undocumented) */
00061 #define AXGE_BICR 0x2e
00062 
00063 /** Bulk IN Control (undocumented) */
00064 struct axge_bulk_in_control {
00065         /** Control */
00066         uint8_t ctrl;
00067         /** Timer */
00068         uint16_t timer;
00069         /** Size */
00070         uint8_t size;
00071         /** Inter-frame gap */
00072         uint8_t ifg;
00073 } __attribute__ (( packed ));
00074 
00075 /** Clock Select Register (undocumented) */
00076 #define AXGE_CSR 0x33
00077 #define AXGE_CSR_BCS                    0x01    /**< Undocumented */
00078 #define AXGE_CSR_ACS                    0x02    /**< Undocumented */
00079 
00080 /** Delay after initialising CSR */
00081 #define AXGE_CSR_DELAY_MS 100
00082 
00083 /** Transmit packet header */
00084 struct axge_tx_header {
00085         /** Packet length */
00086         uint32_t len;
00087         /** Answers on a postcard, please */
00088         uint32_t wtf;
00089 } __attribute__ (( packed ));
00090 
00091 /** Receive packet footer */
00092 struct axge_rx_footer {
00093         /** Packet count */
00094         uint16_t count;
00095         /** Header offset */
00096         uint16_t offset;
00097 } __attribute__ (( packed ));
00098 
00099 /** Receive packet descriptor */
00100 struct axge_rx_descriptor {
00101         /** Checksum information */
00102         uint16_t check;
00103         /** Length and error flags */
00104         uint16_t len_flags;
00105 } __attribute__ (( packed ));
00106 
00107 /** Receive packet length mask */
00108 #define AXGE_RX_LEN_MASK 0x1fff
00109 
00110 /** Receive packet length alignment */
00111 #define AXGE_RX_LEN_PAD_ALIGN 8
00112 
00113 /** Receive packet CRC error */
00114 #define AXGE_RX_CRC_ERROR 0x2000
00115 
00116 /** Receive packet dropped error */
00117 #define AXGE_RX_DROP_ERROR 0x8000
00118 
00119 /** Interrupt data */
00120 struct axge_interrupt {
00121         /** Magic signature */
00122         uint16_t magic;
00123         /** Link state */
00124         uint16_t link;
00125         /** PHY register MR01 */
00126         uint16_t mr01;
00127         /** PHY register MR05 */
00128         uint16_t mr05;
00129 } __attribute__ (( packed ));
00130 
00131 /** Interrupt magic signature */
00132 #define AXGE_INTR_MAGIC 0x00a1
00133 
00134 /** Link is up */
00135 #define AXGE_INTR_LINK_PPLS 0x0001
00136 
00137 /** An AXGE network device */
00138 struct axge_device {
00139         /** USB device */
00140         struct usb_device *usb;
00141         /** USB bus */
00142         struct usb_bus *bus;
00143         /** Network device */
00144         struct net_device *netdev;
00145         /** USB network device */
00146         struct usbnet_device usbnet;
00147 };
00148 
00149 /** Interrupt maximum fill level
00150  *
00151  * This is a policy decision.
00152  */
00153 #define AXGE_INTR_MAX_FILL 2
00154 
00155 /** Bulk IN maximum fill level
00156  *
00157  * This is a policy decision.
00158  */
00159 #define AXGE_IN_MAX_FILL 8
00160 
00161 /** Bulk IN buffer size
00162  *
00163  * This is a policy decision.
00164  */
00165 #define AXGE_IN_MTU 2048
00166 
00167 /** Amount of space to reserve at start of bulk IN buffers
00168  *
00169  * This is required to allow for protocols such as ARP which may reuse
00170  * a received I/O buffer for transmission.
00171  */
00172 #define AXGE_IN_RESERVE sizeof ( struct axge_tx_header )
00173 
00174 #endif /* _AXGE_H */