Defines | Enumerations | Functions
epic100.h File Reference

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#define CR_STOP_RX   (0x00000001)
#define CR_START_RX   (0x00000002)
#define CR_QUEUE_TX   (0x00000004)
#define CR_QUEUE_RX   (0x00000008)
#define CR_NEXTFRAME   (0x00000010)
#define CR_STOP_TX_DMA   (0x00000020)
#define CR_STOP_RX_DMA   (0x00000040)
#define CR_TX_UGO   (0x00000080)
#define INTR_RX_THR_STA   (0x00400000) /* rx copy threshold status NI */
#define INTR_RX_BUFF_EMPTY   (0x00200000) /* rx buffers empty. NI */
#define INTR_TX_IN_PROG   (0x00100000) /* tx copy in progess. NI */
#define INTR_RX_IN_PROG   (0x00080000) /* rx copy in progress. NI */
#define INTR_TXIDLE   (0x00040000) /* tx idle. NI */
#define INTR_RXIDLE   (0x00020000) /* rx idle. NI */
#define INTR_INTR_ACTIVE   (0x00010000) /* Interrupt active. NI */
#define INTR_RX_STATUS_OK   (0x00008000) /* rx status valid. NI */
#define INTR_PCI_TGT_ABT   (0x00004000) /* PCI Target abort */
#define INTR_PCI_MASTER_ABT   (0x00002000) /* PCI Master abort */
#define INTR_PCI_PARITY_ERR   (0x00001000) /* PCI address parity error */
#define INTR_PCI_DATA_ERR   (0x00000800) /* PCI data parity error */
#define INTR_RX_THR_CROSSED   (0x00000400) /* rx copy threshold crossed */
#define INTR_CNTFULL   (0x00000200) /* Counter overflow */
#define INTR_TXUNDERRUN   (0x00000100) /* tx underrun. */
#define INTR_TXEMPTY   (0x00000080) /* tx queue empty */
#define INTR_TX_CH_COMPLETE   (0x00000040) /* tx chain complete */
#define INTR_TXDONE   (0x00000020) /* tx complete (w or w/o err) */
#define INTR_RXERROR   (0x00000010) /* rx error (CRC) */
#define INTR_RXOVERFLOW   (0x00000008) /* rx buffer overflow */
#define INTR_RX_QUEUE_EMPTY   (0x00000004) /* rx queue empty. */
#define INTR_RXHEADER   (0x00000002) /* header copy complete */
#define INTR_RXDONE   (0x00000001) /* Receive copy complete */
#define INTR_CLEARINTR   (0x00007FFF)
#define INTR_VALIDBITS   (0x007FFFFF)
#define INTR_DISABLE   (0x00000000)
#define INTR_CLEARERRS   (0x00007F18)
#define GC_SOFT_RESET   (0x00000001)
#define GC_INTR_ENABLE   (0x00000002)
#define GC_SOFT_INTR   (0x00000004)
#define GC_POWER_DOWN   (0x00000008)
#define GC_ONE_COPY   (0x00000010)
#define GC_BIG_ENDIAN   (0x00000020)
#define GC_RX_PREEMPT_TX   (0x00000040)
#define GC_TX_PREEMPT_RX   (0x00000080)
#define GC_RX_FIFO_THR_32   (0x00000000)
#define GC_RX_FIFO_THR_64   (0x00000100)
#define GC_RX_FIFO_THR_96   (0x00000200)
#define GC_RX_FIFO_THR_128   (0x00000300)
#define GC_MRC_MEM_READ   (0x00000000)
#define GC_MRC_READ_MULT   (0x00000400)
#define GC_MRC_READ_LINE   (0x00000800)
#define GC_SOFTBIT0   (0x00001000)
#define GC_SOFTBIT1   (0x00002000)
#define GC_RESET_PHY   (0x00004000)
#define RC_SAVE_ERRORED_PKT   (0x00000001)
#define RC_SAVE_RUNT_FRAMES   (0x00000002)
#define RC_RCV_BROADCAST   (0x00000004)
#define RC_RCV_MULTICAST   (0x00000008)
#define RC_RCV_INVERSE_PKT   (0x00000010)
#define RC_PROMISCUOUS_MODE   (0x00000020)
#define RC_MONITOR_MODE   (0x00000040)
#define RC_EARLY_RCV_ENABLE   (0x00000080)
#define RD_FRAGLIST   (0x0001) /* Desc points to a fragment list */
#define RD_LLFORM   (0x0002) /* Frag list format */
#define RD_HDR_CPY   (0x0004) /* Desc used for header copy */
#define TC_EARLY_TX_ENABLE   (0x00000001)
#define TC_LM_NORMAL   (0x00000000)
#define TC_LM_INTERNAL   (0x00000002)
#define TC_LM_EXTERNAL   (0x00000004)
#define TC_LM_FULL_DPX   (0x00000006)
#define TX_SLOT_TIME   (0x00000078)
#define TX_FIFO_THRESH   128 /* Rounded down to 4 byte units. */
#define RRING_PKT_INTACT   (0x0001)
#define RRING_ALIGN_ERR   (0x0002)
#define RRING_CRC_ERR   (0x0004)
#define RRING_MISSED_PKT   (0x0008)
#define RRING_MULTICAST   (0x0010)
#define RRING_BROADCAST   (0x0020)
#define RRING_RECEIVER_DISABLE   (0x0040)
#define RRING_STATUS_VALID   (0x1000)
#define RRING_FRAGLIST_ERR   (0x2000)
#define RRING_HDR_COPIED   (0x4000)
#define RRING_OWN   (0x8000)
#define TRING_PKT_INTACT   (0x0001) /* pkt transmitted. */
#define TRING_PKT_NONDEFER   (0x0002) /* pkt xmitted w/o deferring */
#define TRING_COLL   (0x0004) /* pkt xmitted w collisions */
#define TRING_CARR   (0x0008) /* carrier sense lost */
#define TRING_UNDERRUN   (0x0010) /* DMA underrun */
#define TRING_HB_COLL   (0x0020) /* Collision detect Heartbeat */
#define TRING_WIN_COLL   (0x0040) /* out of window collision */
#define TRING_DEFERRED   (0x0080) /* Deferring */
#define TRING_COLL_COUNT   (0x0F00) /* collision counter (mask) */
#define TRING_COLL_EXCESS   (0x1000) /* tx aborted: excessive colls */
#define TRING_OWN   (0x8000) /* desc ownership bit */
#define TD_FRAGLIST   (0x0001) /* Desc points to a fragment list */
#define TD_LLFORM   (0x0002) /* Frag list format */
#define TD_IAF   (0x0004) /* Generate Interrupt after tx */
#define TD_NOCRC   (0x0008) /* No CRC generated */
#define TD_LASTDESC   (0x0010) /* Last desc for this frame */


enum  epic100_registers {
  NVCTL = 0x10, EECTL = 0x14, TEST = 0x1C, CRCCNT = 0x20,
  ALICNT = 0x24, MPCNT = 0x28, MMCTL = 0x30, MMDATA = 0x34,
  MIICFG = 0x38, IPG = 0x3C, LAN0 = 0x40, IDCHK = 0x4C,
  MC0 = 0x50, RXCON = 0x60, TXCON = 0x70, TXSTAT = 0x74,
  PRCDAR = 0x84, PRSTAT = 0xA4, PRCPTHR = 0xB0, PTCDAR = 0xC4,



Define Documentation


Definition at line 14 of file epic100.h.

#define CR_STOP_RX   (0x00000001)

Definition at line 46 of file epic100.h.

#define CR_START_RX   (0x00000002)

Definition at line 47 of file epic100.h.

Referenced by epic100_open(), and epic100_poll().

#define CR_QUEUE_TX   (0x00000004)

Definition at line 48 of file epic100.h.

Referenced by epic100_transmit().

#define CR_QUEUE_RX   (0x00000008)

Definition at line 49 of file epic100.h.

Referenced by epic100_open(), and epic100_poll().

#define CR_NEXTFRAME   (0x00000010)

Definition at line 50 of file epic100.h.

#define CR_STOP_TX_DMA   (0x00000020)

Definition at line 51 of file epic100.h.

#define CR_STOP_RX_DMA   (0x00000040)

Definition at line 52 of file epic100.h.

#define CR_TX_UGO   (0x00000080)

Definition at line 53 of file epic100.h.

#define INTR_RX_THR_STA   (0x00400000) /* rx copy threshold status NI */

Definition at line 57 of file epic100.h.

#define INTR_RX_BUFF_EMPTY   (0x00200000) /* rx buffers empty. NI */

Definition at line 58 of file epic100.h.

#define INTR_TX_IN_PROG   (0x00100000) /* tx copy in progess. NI */

Definition at line 59 of file epic100.h.

#define INTR_RX_IN_PROG   (0x00080000) /* rx copy in progress. NI */

Definition at line 60 of file epic100.h.

#define INTR_TXIDLE   (0x00040000) /* tx idle. NI */

Definition at line 61 of file epic100.h.

#define INTR_RXIDLE   (0x00020000) /* rx idle. NI */

Definition at line 62 of file epic100.h.

#define INTR_INTR_ACTIVE   (0x00010000) /* Interrupt active. NI */

Definition at line 63 of file epic100.h.

#define INTR_RX_STATUS_OK   (0x00008000) /* rx status valid. NI */

Definition at line 64 of file epic100.h.

#define INTR_PCI_TGT_ABT   (0x00004000) /* PCI Target abort */

Definition at line 65 of file epic100.h.

#define INTR_PCI_MASTER_ABT   (0x00002000) /* PCI Master abort */

Definition at line 66 of file epic100.h.

#define INTR_PCI_PARITY_ERR   (0x00001000) /* PCI address parity error */

Definition at line 67 of file epic100.h.

#define INTR_PCI_DATA_ERR   (0x00000800) /* PCI data parity error */

Definition at line 68 of file epic100.h.

#define INTR_RX_THR_CROSSED   (0x00000400) /* rx copy threshold crossed */

Definition at line 69 of file epic100.h.

#define INTR_CNTFULL   (0x00000200) /* Counter overflow */

Definition at line 70 of file epic100.h.

#define INTR_TXUNDERRUN   (0x00000100) /* tx underrun. */

Definition at line 71 of file epic100.h.

#define INTR_TXEMPTY   (0x00000080) /* tx queue empty */

Definition at line 72 of file epic100.h.

#define INTR_TX_CH_COMPLETE   (0x00000040) /* tx chain complete */

Definition at line 73 of file epic100.h.

#define INTR_TXDONE   (0x00000020) /* tx complete (w or w/o err) */

Definition at line 74 of file epic100.h.

#define INTR_RXERROR   (0x00000010) /* rx error (CRC) */

Definition at line 75 of file epic100.h.

#define INTR_RXOVERFLOW   (0x00000008) /* rx buffer overflow */

Definition at line 76 of file epic100.h.

#define INTR_RX_QUEUE_EMPTY   (0x00000004) /* rx queue empty. */

Definition at line 77 of file epic100.h.

#define INTR_RXHEADER   (0x00000002) /* header copy complete */

Definition at line 78 of file epic100.h.

#define INTR_RXDONE   (0x00000001) /* Receive copy complete */

Definition at line 79 of file epic100.h.

#define INTR_CLEARINTR   (0x00007FFF)

Definition at line 81 of file epic100.h.

#define INTR_VALIDBITS   (0x007FFFFF)

Definition at line 82 of file epic100.h.

#define INTR_DISABLE   (0x00000000)

Definition at line 83 of file epic100.h.

Referenced by epic100_probe().

#define INTR_CLEARERRS   (0x00007F18)

Definition at line 84 of file epic100.h.

Referenced by epic100_poll().

Definition at line 85 of file epic100.h.

#define GC_SOFT_RESET   (0x00000001)

Definition at line 89 of file epic100.h.

Referenced by epic100_disable(), and epic100_probe().

#define GC_INTR_ENABLE   (0x00000002)

Definition at line 90 of file epic100.h.

#define GC_SOFT_INTR   (0x00000004)

Definition at line 91 of file epic100.h.

#define GC_POWER_DOWN   (0x00000008)

Definition at line 92 of file epic100.h.

#define GC_ONE_COPY   (0x00000010)

Definition at line 93 of file epic100.h.

Referenced by epic100_open().

#define GC_BIG_ENDIAN   (0x00000020)

Definition at line 94 of file epic100.h.

#define GC_RX_PREEMPT_TX   (0x00000040)

Definition at line 95 of file epic100.h.

#define GC_TX_PREEMPT_RX   (0x00000080)

Definition at line 96 of file epic100.h.

#define GC_RX_FIFO_THR_32   (0x00000000)

Definition at line 105 of file epic100.h.

#define GC_RX_FIFO_THR_64   (0x00000100)

Definition at line 106 of file epic100.h.

Referenced by epic100_open().

#define GC_RX_FIFO_THR_96   (0x00000200)

Definition at line 107 of file epic100.h.

#define GC_RX_FIFO_THR_128   (0x00000300)

Definition at line 108 of file epic100.h.

#define GC_MRC_MEM_READ   (0x00000000)

Definition at line 111 of file epic100.h.

#define GC_MRC_READ_MULT   (0x00000400)

Definition at line 112 of file epic100.h.

Referenced by epic100_open().

#define GC_MRC_READ_LINE   (0x00000800)

Definition at line 113 of file epic100.h.

#define GC_SOFTBIT0   (0x00001000)

Definition at line 115 of file epic100.h.

#define GC_SOFTBIT1   (0x00002000)

Definition at line 116 of file epic100.h.

#define GC_RESET_PHY   (0x00004000)

Definition at line 117 of file epic100.h.

#define RC_SAVE_ERRORED_PKT   (0x00000001)

Definition at line 121 of file epic100.h.

#define RC_SAVE_RUNT_FRAMES   (0x00000002)

Definition at line 122 of file epic100.h.

#define RC_RCV_BROADCAST   (0x00000004)

Definition at line 123 of file epic100.h.

#define RC_RCV_MULTICAST   (0x00000008)

Definition at line 124 of file epic100.h.

#define RC_RCV_INVERSE_PKT   (0x00000010)

Definition at line 125 of file epic100.h.

#define RC_PROMISCUOUS_MODE   (0x00000020)

Definition at line 126 of file epic100.h.

#define RC_MONITOR_MODE   (0x00000040)

Definition at line 127 of file epic100.h.

#define RC_EARLY_RCV_ENABLE   (0x00000080)

Definition at line 128 of file epic100.h.

#define RD_FRAGLIST   (0x0001) /* Desc points to a fragment list */

Definition at line 131 of file epic100.h.

#define RD_LLFORM   (0x0002) /* Frag list format */

Definition at line 132 of file epic100.h.

#define RD_HDR_CPY   (0x0004) /* Desc used for header copy */

Definition at line 133 of file epic100.h.

#define TC_EARLY_TX_ENABLE   (0x00000001)

Definition at line 137 of file epic100.h.

Referenced by epic100_open().

#define TC_LM_NORMAL   (0x00000000)

Definition at line 140 of file epic100.h.

Referenced by epic100_open().

#define TC_LM_INTERNAL   (0x00000002)

Definition at line 141 of file epic100.h.

#define TC_LM_EXTERNAL   (0x00000004)

Definition at line 142 of file epic100.h.

#define TC_LM_FULL_DPX   (0x00000006)

Definition at line 143 of file epic100.h.

Referenced by epic100_open().

#define TX_SLOT_TIME   (0x00000078)

Definition at line 145 of file epic100.h.

Referenced by epic100_open().

#define TX_FIFO_THRESH   128 /* Rounded down to 4 byte units. */

Definition at line 148 of file epic100.h.

Referenced by epic100_open().

#define RRING_PKT_INTACT   (0x0001)

Definition at line 151 of file epic100.h.

#define RRING_ALIGN_ERR   (0x0002)

Definition at line 152 of file epic100.h.

#define RRING_CRC_ERR   (0x0004)

Definition at line 153 of file epic100.h.

#define RRING_MISSED_PKT   (0x0008)

Definition at line 154 of file epic100.h.

#define RRING_MULTICAST   (0x0010)

Definition at line 155 of file epic100.h.

#define RRING_BROADCAST   (0x0020)

Definition at line 156 of file epic100.h.

#define RRING_RECEIVER_DISABLE   (0x0040)

Definition at line 157 of file epic100.h.

#define RRING_STATUS_VALID   (0x1000)

Definition at line 158 of file epic100.h.

#define RRING_FRAGLIST_ERR   (0x2000)

Definition at line 159 of file epic100.h.

#define RRING_HDR_COPIED   (0x4000)

Definition at line 160 of file epic100.h.

#define RRING_OWN   (0x8000)

Definition at line 161 of file epic100.h.

Referenced by epic100_init_ring(), and epic100_poll().

Definition at line 164 of file epic100.h.

#define TRING_PKT_INTACT   (0x0001) /* pkt transmitted. */

Definition at line 167 of file epic100.h.

#define TRING_PKT_NONDEFER   (0x0002) /* pkt xmitted w/o deferring */

Definition at line 168 of file epic100.h.

#define TRING_COLL   (0x0004) /* pkt xmitted w collisions */

Definition at line 169 of file epic100.h.

#define TRING_CARR   (0x0008) /* carrier sense lost */

Definition at line 170 of file epic100.h.

#define TRING_UNDERRUN   (0x0010) /* DMA underrun */

Definition at line 171 of file epic100.h.

#define TRING_HB_COLL   (0x0020) /* Collision detect Heartbeat */

Definition at line 172 of file epic100.h.

#define TRING_WIN_COLL   (0x0040) /* out of window collision */

Definition at line 173 of file epic100.h.

#define TRING_DEFERRED   (0x0080) /* Deferring */

Definition at line 174 of file epic100.h.

#define TRING_COLL_COUNT   (0x0F00) /* collision counter (mask) */

Definition at line 175 of file epic100.h.

#define TRING_COLL_EXCESS   (0x1000) /* tx aborted: excessive colls */

Definition at line 176 of file epic100.h.

#define TRING_OWN   (0x8000) /* desc ownership bit */

Definition at line 177 of file epic100.h.

Referenced by epic100_transmit().

Definition at line 180 of file epic100.h.

Definition at line 181 of file epic100.h.

#define TD_FRAGLIST   (0x0001) /* Desc points to a fragment list */

Definition at line 184 of file epic100.h.

#define TD_LLFORM   (0x0002) /* Frag list format */

Definition at line 185 of file epic100.h.

#define TD_IAF   (0x0004) /* Generate Interrupt after tx */

Definition at line 186 of file epic100.h.

#define TD_NOCRC   (0x0008) /* No CRC generated */

Definition at line 187 of file epic100.h.

#define TD_LASTDESC   (0x0010) /* Last desc for this frame */

Definition at line 188 of file epic100.h.

Enumeration Type Documentation


Definition at line 17 of file epic100.h.

    COMMAND= 0,         /* Control Register */
    INTSTAT= 4,         /* Interrupt Status */
    INTMASK= 8,         /* Interrupt Mask */
    GENCTL = 0x0C,      /* General Control */
    NVCTL  = 0x10,      /* Non Volatile Control */
    EECTL  = 0x14,      /* EEPROM Control  */
    TEST   = 0x1C,      /* Test register: marked as reserved (see in source code) */
    CRCCNT = 0x20,      /* CRC Error Counter */
    ALICNT = 0x24,      /* Frame Alignment Error Counter */
    MPCNT  = 0x28,      /* Missed Packet Counter */
    MMCTL  = 0x30,      /* MII Management Interface Control */
    MMDATA = 0x34,      /* MII Management Interface Data */
    MIICFG = 0x38,      /* MII Configuration */
    IPG    = 0x3C,      /* InterPacket Gap */
    LAN0   = 0x40,      /* MAC address. (0x40-0x48) */
    IDCHK  = 0x4C,      /* BoardID/ Checksum */
    MC0    = 0x50,      /* Multicast filter table. (0x50-0x5c) */
    RXCON  = 0x60,      /* Receive Control */
    TXCON  = 0x70,      /* Transmit Control */
    TXSTAT = 0x74,      /* Transmit Status */
    PRCDAR = 0x84,      /* PCI Receive Current Descriptor Address */
    PRSTAT = 0xA4,      /* PCI Receive DMA Status */
    PRCPTHR= 0xB0,      /* PCI Receive Copy Threshold */
    PTCDAR = 0xC4,      /* PCI Transmit Current Descriptor Address */
    ETHTHR = 0xDC       /* Early Transmit Threshold */

Function Documentation