iPXE
epic100.h
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00001 #ifndef _EPIC100_H_
00002 # define _EPIC100_H_
00003 
00004 FILE_LICENCE ( GPL2_OR_LATER );
00005 
00006 #ifndef PCI_VENDOR_SMC
00007 # define PCI_VENDOR_SMC         0x10B8
00008 #endif
00009 
00010 #ifndef PCI_DEVICE_SMC_EPIC100
00011 # define PCI_DEVICE_SMC_EPIC100 0x0005
00012 #endif
00013 
00014 #define PCI_DEVICE_ID_NONE      0xFFFF
00015 
00016 /* Offsets to registers (using SMC names). */
00017 enum epic100_registers {
00018     COMMAND= 0,         /* Control Register */
00019     INTSTAT= 4,         /* Interrupt Status */
00020     INTMASK= 8,         /* Interrupt Mask */
00021     GENCTL = 0x0C,      /* General Control */
00022     NVCTL  = 0x10,      /* Non Volatile Control */
00023     EECTL  = 0x14,      /* EEPROM Control  */
00024     TEST   = 0x1C,      /* Test register: marked as reserved (see in source code) */
00025     CRCCNT = 0x20,      /* CRC Error Counter */
00026     ALICNT = 0x24,      /* Frame Alignment Error Counter */
00027     MPCNT  = 0x28,      /* Missed Packet Counter */
00028     MMCTL  = 0x30,      /* MII Management Interface Control */
00029     MMDATA = 0x34,      /* MII Management Interface Data */
00030     MIICFG = 0x38,      /* MII Configuration */
00031     IPG    = 0x3C,      /* InterPacket Gap */
00032     LAN0   = 0x40,      /* MAC address. (0x40-0x48) */
00033     IDCHK  = 0x4C,      /* BoardID/ Checksum */
00034     MC0    = 0x50,      /* Multicast filter table. (0x50-0x5c) */
00035     RXCON  = 0x60,      /* Receive Control */
00036     TXCON  = 0x70,      /* Transmit Control */
00037     TXSTAT = 0x74,      /* Transmit Status */
00038     PRCDAR = 0x84,      /* PCI Receive Current Descriptor Address */
00039     PRSTAT = 0xA4,      /* PCI Receive DMA Status */
00040     PRCPTHR= 0xB0,      /* PCI Receive Copy Threshold */
00041     PTCDAR = 0xC4,      /* PCI Transmit Current Descriptor Address */
00042     ETHTHR = 0xDC       /* Early Transmit Threshold */
00043 };
00044 
00045 /* Command register (CR_) bits */
00046 #define CR_STOP_RX              (0x00000001)
00047 #define CR_START_RX             (0x00000002)
00048 #define CR_QUEUE_TX             (0x00000004)
00049 #define CR_QUEUE_RX             (0x00000008)
00050 #define CR_NEXTFRAME            (0x00000010)
00051 #define CR_STOP_TX_DMA          (0x00000020)
00052 #define CR_STOP_RX_DMA          (0x00000040)
00053 #define CR_TX_UGO               (0x00000080)
00054 
00055 /* Interrupt register bits. NI means No Interrupt generated */
00056 
00057 #define INTR_RX_THR_STA         (0x00400000)    /* rx copy threshold status NI */
00058 #define INTR_RX_BUFF_EMPTY      (0x00200000)    /* rx buffers empty. NI */
00059 #define INTR_TX_IN_PROG         (0x00100000)    /* tx copy in progess. NI */
00060 #define INTR_RX_IN_PROG         (0x00080000)    /* rx copy in progress. NI */
00061 #define INTR_TXIDLE             (0x00040000)    /* tx idle. NI */
00062 #define INTR_RXIDLE             (0x00020000)    /* rx idle. NI */
00063 #define INTR_INTR_ACTIVE        (0x00010000)    /* Interrupt active. NI */
00064 #define INTR_RX_STATUS_OK       (0x00008000)    /* rx status valid. NI */
00065 #define INTR_PCI_TGT_ABT        (0x00004000)    /* PCI Target abort */
00066 #define INTR_PCI_MASTER_ABT     (0x00002000)    /* PCI Master abort */
00067 #define INTR_PCI_PARITY_ERR     (0x00001000)    /* PCI address parity error */
00068 #define INTR_PCI_DATA_ERR       (0x00000800)    /* PCI data parity error */
00069 #define INTR_RX_THR_CROSSED     (0x00000400)    /* rx copy threshold crossed */
00070 #define INTR_CNTFULL            (0x00000200)    /* Counter overflow */
00071 #define INTR_TXUNDERRUN         (0x00000100)    /* tx underrun. */
00072 #define INTR_TXEMPTY            (0x00000080)    /* tx queue empty */
00073 #define INTR_TX_CH_COMPLETE     (0x00000040)    /* tx chain complete */
00074 #define INTR_TXDONE             (0x00000020)    /* tx complete (w or w/o err) */
00075 #define INTR_RXERROR            (0x00000010)    /* rx error (CRC) */
00076 #define INTR_RXOVERFLOW         (0x00000008)    /* rx buffer overflow */
00077 #define INTR_RX_QUEUE_EMPTY     (0x00000004)    /* rx queue empty. */
00078 #define INTR_RXHEADER           (0x00000002)    /* header copy complete */
00079 #define INTR_RXDONE             (0x00000001)    /* Receive copy complete */
00080 
00081 #define INTR_CLEARINTR          (0x00007FFF)
00082 #define INTR_VALIDBITS          (0x007FFFFF)
00083 #define INTR_DISABLE            (0x00000000)
00084 #define INTR_CLEARERRS          (0x00007F18)
00085 #define INTR_ABNINTR            (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW)
00086 
00087 /* General Control (GC_) bits */
00088 
00089 #define GC_SOFT_RESET           (0x00000001)
00090 #define GC_INTR_ENABLE          (0x00000002)
00091 #define GC_SOFT_INTR            (0x00000004)
00092 #define GC_POWER_DOWN           (0x00000008)
00093 #define GC_ONE_COPY             (0x00000010)
00094 #define GC_BIG_ENDIAN           (0x00000020)
00095 #define GC_RX_PREEMPT_TX        (0x00000040)
00096 #define GC_TX_PREEMPT_RX        (0x00000080)
00097 
00098 /*
00099  * Receive FIFO Threshold values
00100  * Control the level at which the  PCI burst state machine
00101  * begins to empty the receive FIFO. Possible values: 0-3
00102  *
00103  * 0 => 32, 1 => 64, 2 => 96 3 => 128 bytes.
00104  */
00105 #define GC_RX_FIFO_THR_32       (0x00000000)
00106 #define GC_RX_FIFO_THR_64       (0x00000100)
00107 #define GC_RX_FIFO_THR_96       (0x00000200)
00108 #define GC_RX_FIFO_THR_128      (0x00000300)
00109 
00110 /* Memory Read Control (MRC_) values */
00111 #define GC_MRC_MEM_READ         (0x00000000)
00112 #define GC_MRC_READ_MULT        (0x00000400)
00113 #define GC_MRC_READ_LINE        (0x00000800)
00114 
00115 #define GC_SOFTBIT0             (0x00001000)
00116 #define GC_SOFTBIT1             (0x00002000)
00117 #define GC_RESET_PHY            (0x00004000)
00118 
00119 /* Definitions of the Receive Control (RC_) register bits */
00120 
00121 #define RC_SAVE_ERRORED_PKT     (0x00000001)
00122 #define RC_SAVE_RUNT_FRAMES     (0x00000002)
00123 #define RC_RCV_BROADCAST        (0x00000004)
00124 #define RC_RCV_MULTICAST        (0x00000008)
00125 #define RC_RCV_INVERSE_PKT      (0x00000010)
00126 #define RC_PROMISCUOUS_MODE     (0x00000020)
00127 #define RC_MONITOR_MODE         (0x00000040)
00128 #define RC_EARLY_RCV_ENABLE     (0x00000080)
00129 
00130 /* description of the rx descriptors control bits */
00131 #define RD_FRAGLIST             (0x0001)        /* Desc points to a fragment list */
00132 #define RD_LLFORM               (0x0002)        /* Frag list format */
00133 #define RD_HDR_CPY              (0x0004)        /* Desc used for header copy */
00134 
00135 /* Definition of the Transmit CONTROL (TC) register bits */
00136 
00137 #define TC_EARLY_TX_ENABLE      (0x00000001)
00138 
00139 /* Loopback Mode (LM_) Select valuesbits */
00140 #define TC_LM_NORMAL            (0x00000000)
00141 #define TC_LM_INTERNAL          (0x00000002)
00142 #define TC_LM_EXTERNAL          (0x00000004)
00143 #define TC_LM_FULL_DPX          (0x00000006)
00144 
00145 #define TX_SLOT_TIME            (0x00000078)
00146 
00147 /* Bytes transferred to chip before transmission starts. */
00148 #define TX_FIFO_THRESH          128     /* Rounded down to 4 byte units. */
00149 
00150 /* description of rx descriptors status bits */
00151 #define RRING_PKT_INTACT        (0x0001)
00152 #define RRING_ALIGN_ERR         (0x0002)
00153 #define RRING_CRC_ERR           (0x0004)
00154 #define RRING_MISSED_PKT        (0x0008)
00155 #define RRING_MULTICAST         (0x0010)
00156 #define RRING_BROADCAST         (0x0020)
00157 #define RRING_RECEIVER_DISABLE  (0x0040)
00158 #define RRING_STATUS_VALID      (0x1000)
00159 #define RRING_FRAGLIST_ERR      (0x2000)
00160 #define RRING_HDR_COPIED        (0x4000)
00161 #define RRING_OWN               (0x8000)
00162 
00163 /* error summary */
00164 #define RRING_ERROR             (RRING_ALIGN_ERR|RRING_CRC_ERR)
00165 
00166 /* description of tx descriptors status bits */
00167 #define TRING_PKT_INTACT        (0x0001)        /* pkt transmitted. */
00168 #define TRING_PKT_NONDEFER      (0x0002)        /* pkt xmitted w/o deferring */
00169 #define TRING_COLL              (0x0004)        /* pkt xmitted w collisions */
00170 #define TRING_CARR              (0x0008)        /* carrier sense lost */
00171 #define TRING_UNDERRUN          (0x0010)        /* DMA underrun */
00172 #define TRING_HB_COLL           (0x0020)        /* Collision detect Heartbeat */
00173 #define TRING_WIN_COLL          (0x0040)        /* out of window collision */
00174 #define TRING_DEFERRED          (0x0080)        /* Deferring */
00175 #define TRING_COLL_COUNT        (0x0F00)        /* collision counter (mask) */
00176 #define TRING_COLL_EXCESS       (0x1000)        /* tx aborted: excessive colls */
00177 #define TRING_OWN               (0x8000)        /* desc ownership bit */
00178 
00179 /* error summary */
00180 #define TRING_ABORT     (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN)
00181 #define TRING_ERROR     (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR/*|TRING_COLL*/ )
00182 
00183 /* description of the tx descriptors control bits */
00184 #define TD_FRAGLIST             (0x0001)        /* Desc points to a fragment list */
00185 #define TD_LLFORM               (0x0002)        /* Frag list format */
00186 #define TD_IAF                  (0x0004)        /* Generate Interrupt after tx */
00187 #define TD_NOCRC                (0x0008)        /* No CRC generated */
00188 #define TD_LASTDESC             (0x0010)        /* Last desc for this frame */
00189 
00190 #endif  /* _EPIC100_H_ */