iPXE
forcedeth.h
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00001 /*
00002  *    forcedeth.h -- Driver for NVIDIA nForce media access controllers for iPXE
00003  *    Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
00004  *
00005  *    This program is free software; you can redistribute it and/or
00006  *    modify it under the terms of the GNU General Public License as
00007  *    published by the Free Software Foundation; either version 2 of the
00008  *    License, or any later version.
00009  *
00010  *    This program is distributed in the hope that it will be useful, but
00011  *    WITHOUT ANY WARRANTY; without even the implied warranty of
00012  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013  *    General Public License for more details.
00014  *
00015  *    You should have received a copy of the GNU General Public License
00016  *    along with this program; if not, write to the Free Software
00017  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00018  *    02110-1301, USA.
00019  *
00020  * Portions of this code are taken from the Linux forcedeth driver that was
00021  * based on a cleanroom reimplementation which was based on reverse engineered
00022  * documentation written by Carl-Daniel Hailfinger and Andrew de Quincey:
00023  * Copyright (C) 2003,4,5 Manfred Spraul
00024  * Copyright (C) 2004 Andrew de Quincey (wol support)
00025  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
00026  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
00027  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
00028  *
00029  * This header is a direct copy of #define lines and structs found in the
00030  * above mentioned driver, modified where necessary to make them work for iPXE.
00031  *
00032  */
00033 
00034 FILE_LICENCE ( GPL2_OR_LATER );
00035 
00036 #ifndef _FORCEDETH_H_
00037 #define _FORCEDETH_H_
00038 
00039 struct ring_desc {
00040         u32 buf;
00041         u32 flaglen;
00042 };
00043 
00044 struct ring_desc_ex {
00045         u32 bufhigh;
00046         u32 buflow;
00047         u32 txvlan;
00048         u32 flaglen;
00049 };
00050 
00051 #define DESC_VER_1      1
00052 #define DESC_VER_2      2
00053 #define DESC_VER_3      3
00054 
00055 #define RX_RING_SIZE            16
00056 #define TX_RING_SIZE            32
00057 #define RXTX_RING_SIZE          ( ( RX_RING_SIZE ) + ( TX_RING_SIZE ) )
00058 #define RX_RING_MIN             128
00059 #define TX_RING_MIN             64
00060 #define RING_MAX_DESC_VER_1     1024
00061 #define RING_MAX_DESC_VER_2_3   16384
00062 
00063 #define NV_RX_ALLOC_PAD (64)
00064 
00065 #define NV_RX_HEADERS   (64)
00066 
00067 #define RX_BUF_SZ               ( ( ETH_FRAME_LEN ) + ( NV_RX_HEADERS ) )
00068 
00069 #define NV_PKTLIMIT_1   1500
00070 #define NV_PKTLIMIT_2   9100
00071 
00072 #define NV_LINK_POLL_FREQUENCY  128
00073 
00074 /* PHY defines */
00075 #define PHY_OUI_MARVELL         0x5043
00076 #define PHY_OUI_CICADA          0x03f1
00077 #define PHY_OUI_VITESSE         0x01c1
00078 #define PHY_OUI_REALTEK         0x0732
00079 #define PHY_OUI_REALTEK2        0x0020
00080 #define PHYID1_OUI_MASK 0x03ff
00081 #define PHYID1_OUI_SHFT 6
00082 #define PHYID2_OUI_MASK 0xfc00
00083 #define PHYID2_OUI_SHFT 10
00084 #define PHYID2_MODEL_MASK               0x03f0
00085 #define PHY_MODEL_REALTEK_8211          0x0110
00086 #define PHY_REV_MASK                    0x0001
00087 #define PHY_REV_REALTEK_8211B           0x0000
00088 #define PHY_REV_REALTEK_8211C           0x0001
00089 #define PHY_MODEL_REALTEK_8201          0x0200
00090 #define PHY_MODEL_MARVELL_E3016         0x0220
00091 #define PHY_MARVELL_E3016_INITMASK      0x0300
00092 #define PHY_CICADA_INIT1        0x0f000
00093 #define PHY_CICADA_INIT2        0x0e00
00094 #define PHY_CICADA_INIT3        0x01000
00095 #define PHY_CICADA_INIT4        0x0200
00096 #define PHY_CICADA_INIT5        0x0004
00097 #define PHY_CICADA_INIT6        0x02000
00098 #define PHY_VITESSE_INIT_REG1   0x1f
00099 #define PHY_VITESSE_INIT_REG2   0x10
00100 #define PHY_VITESSE_INIT_REG3   0x11
00101 #define PHY_VITESSE_INIT_REG4   0x12
00102 #define PHY_VITESSE_INIT_MSK1   0xc
00103 #define PHY_VITESSE_INIT_MSK2   0x0180
00104 #define PHY_VITESSE_INIT1       0x52b5
00105 #define PHY_VITESSE_INIT2       0xaf8a
00106 #define PHY_VITESSE_INIT3       0x8
00107 #define PHY_VITESSE_INIT4       0x8f8a
00108 #define PHY_VITESSE_INIT5       0xaf86
00109 #define PHY_VITESSE_INIT6       0x8f86
00110 #define PHY_VITESSE_INIT7       0xaf82
00111 #define PHY_VITESSE_INIT8       0x0100
00112 #define PHY_VITESSE_INIT9       0x8f82
00113 #define PHY_VITESSE_INIT10      0x0
00114 #define PHY_REALTEK_INIT_REG1   0x1f
00115 #define PHY_REALTEK_INIT_REG2   0x19
00116 #define PHY_REALTEK_INIT_REG3   0x13
00117 #define PHY_REALTEK_INIT_REG4   0x14
00118 #define PHY_REALTEK_INIT_REG5   0x18
00119 #define PHY_REALTEK_INIT_REG6   0x11
00120 #define PHY_REALTEK_INIT_REG7   0x01
00121 #define PHY_REALTEK_INIT1       0x0000
00122 #define PHY_REALTEK_INIT2       0x8e00
00123 #define PHY_REALTEK_INIT3       0x0001
00124 #define PHY_REALTEK_INIT4       0xad17
00125 #define PHY_REALTEK_INIT5       0xfb54
00126 #define PHY_REALTEK_INIT6       0xf5c7
00127 #define PHY_REALTEK_INIT7       0x1000
00128 #define PHY_REALTEK_INIT8       0x0003
00129 #define PHY_REALTEK_INIT9       0x0008
00130 #define PHY_REALTEK_INIT10      0x0005
00131 #define PHY_REALTEK_INIT11      0x0200
00132 #define PHY_REALTEK_INIT_MSK1   0x0003
00133 
00134 #define PHY_GIGABIT     0x0100
00135 
00136 #define PHY_TIMEOUT     0x1
00137 #define PHY_ERROR       0x2
00138 
00139 #define PHY_100 0x1
00140 #define PHY_1000        0x2
00141 #define PHY_HALF        0x100
00142 
00143 
00144 #define NV_PAUSEFRAME_RX_CAPABLE        0x0001
00145 #define NV_PAUSEFRAME_TX_CAPABLE        0x0002
00146 #define NV_PAUSEFRAME_RX_ENABLE         0x0004
00147 #define NV_PAUSEFRAME_TX_ENABLE         0x0008
00148 #define NV_PAUSEFRAME_RX_REQ            0x0010
00149 #define NV_PAUSEFRAME_TX_REQ            0x0020
00150 #define NV_PAUSEFRAME_AUTONEG           0x0040
00151 
00152 /* MSI/MSI-X defines */
00153 #define NV_MSI_X_MAX_VECTORS  8
00154 #define NV_MSI_X_VECTORS_MASK 0x000f
00155 #define NV_MSI_CAPABLE        0x0010
00156 #define NV_MSI_X_CAPABLE      0x0020
00157 #define NV_MSI_ENABLED        0x0040
00158 #define NV_MSI_X_ENABLED      0x0080
00159 
00160 #define NV_MSI_X_VECTOR_ALL   0x0
00161 #define NV_MSI_X_VECTOR_RX    0x0
00162 #define NV_MSI_X_VECTOR_TX    0x1
00163 #define NV_MSI_X_VECTOR_OTHER 0x2
00164 
00165 #define NV_MSI_PRIV_OFFSET 0x68
00166 #define NV_MSI_PRIV_VALUE  0xffffffff
00167 
00168 
00169 #define NV_MIIBUSY_DELAY        50
00170 #define NV_MIIPHY_DELAY         10
00171 #define NV_MIIPHY_DELAYMAX      10000
00172 
00173 /* Hardware access */
00174 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
00175 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
00176 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
00177 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
00178 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
00179 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
00180 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
00181 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
00182 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
00183 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
00184 #define DEV_HAS_STATISTICS_V2      0x0000600  /* device supports hw statistics version 2 */
00185 #define DEV_HAS_STATISTICS_V3      0x0000e00  /* device supports hw statistics version 3 */
00186 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
00187 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
00188 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
00189 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
00190 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
00191 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
00192 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
00193 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
00194 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
00195 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
00196 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
00197 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
00198 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
00199 
00200 #define FLAG_MASK_V1 0xffff0000
00201 #define FLAG_MASK_V2 0xffffc000
00202 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
00203 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
00204 
00205 #define NV_TX_LASTPACKET        (1<<16)
00206 #define NV_TX_RETRYERROR        (1<<19)
00207 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
00208 #define NV_TX_FORCED_INTERRUPT  (1<<24)
00209 #define NV_TX_DEFERRED          (1<<26)
00210 #define NV_TX_CARRIERLOST       (1<<27)
00211 #define NV_TX_LATECOLLISION     (1<<28)
00212 #define NV_TX_UNDERFLOW         (1<<29)
00213 #define NV_TX_ERROR             (1<<30)
00214 #define NV_TX_VALID             (1<<31)
00215 
00216 #define NV_TX2_LASTPACKET       (1<<29)
00217 #define NV_TX2_RETRYERROR       (1<<18)
00218 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
00219 #define NV_TX2_FORCED_INTERRUPT (1<<30)
00220 #define NV_TX2_DEFERRED         (1<<25)
00221 #define NV_TX2_CARRIERLOST      (1<<26)
00222 #define NV_TX2_LATECOLLISION    (1<<27)
00223 #define NV_TX2_UNDERFLOW        (1<<28)
00224 /* error and valid are the same for both */
00225 #define NV_TX2_ERROR            (1<<30)
00226 #define NV_TX2_VALID            (1<<31)
00227 #define NV_TX2_TSO              (1<<28)
00228 #define NV_TX2_TSO_SHIFT        14
00229 #define NV_TX2_TSO_MAX_SHIFT    14
00230 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
00231 #define NV_TX2_CHECKSUM_L3      (1<<27)
00232 #define NV_TX2_CHECKSUM_L4      (1<<26)
00233 
00234 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
00235 
00236 #define NV_RX_DESCRIPTORVALID   (1<<16)
00237 #define NV_RX_MISSEDFRAME       (1<<17)
00238 #define NV_RX_SUBSTRACT1        (1<<18)
00239 #define NV_RX_ERROR1            (1<<23)
00240 #define NV_RX_ERROR2            (1<<24)
00241 #define NV_RX_ERROR3            (1<<25)
00242 #define NV_RX_ERROR4            (1<<26)
00243 #define NV_RX_CRCERR            (1<<27)
00244 #define NV_RX_OVERFLOW          (1<<28)
00245 #define NV_RX_FRAMINGERR        (1<<29)
00246 #define NV_RX_ERROR             (1<<30)
00247 #define NV_RX_AVAIL             (1<<31)
00248 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
00249 
00250 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
00251 #define NV_RX2_CHECKSUM_IP      (0x10000000)
00252 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
00253 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
00254 #define NV_RX2_DESCRIPTORVALID  (1<<29)
00255 #define NV_RX2_SUBSTRACT1       (1<<25)
00256 #define NV_RX2_ERROR1           (1<<18)
00257 #define NV_RX2_ERROR2           (1<<19)
00258 #define NV_RX2_ERROR3           (1<<20)
00259 #define NV_RX2_ERROR4           (1<<21)
00260 #define NV_RX2_CRCERR           (1<<22)
00261 #define NV_RX2_OVERFLOW         (1<<23)
00262 #define NV_RX2_FRAMINGERR       (1<<24)
00263 /* error and avail are the same for both */
00264 #define NV_RX2_ERROR            (1<<30)
00265 #define NV_RX2_AVAIL            (1<<31)
00266 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
00267 
00268 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
00269 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
00270 
00271 /* Miscellaneous hardware related defines */
00272 #define NV_PCI_REGSZ_VER1       0x270
00273 #define NV_PCI_REGSZ_VER2       0x2d4
00274 #define NV_PCI_REGSZ_VER3       0x604
00275 #define NV_PCI_REGSZ_MAX        0x604
00276 
00277 /* various timeout delays: all in usec */
00278 #define NV_TXRX_RESET_DELAY     4
00279 #define NV_TXSTOP_DELAY1        10
00280 #define NV_TXSTOP_DELAY1MAX     500000
00281 #define NV_TXSTOP_DELAY2        100
00282 #define NV_RXSTOP_DELAY1        10
00283 #define NV_RXSTOP_DELAY1MAX     500000
00284 #define NV_RXSTOP_DELAY2        100
00285 #define NV_SETUP5_DELAY         5
00286 #define NV_SETUP5_DELAYMAX      50000
00287 #define NV_POWERUP_DELAY        5
00288 #define NV_POWERUP_DELAYMAX     5000
00289 #define NV_MIIBUSY_DELAY        50
00290 #define NV_MIIPHY_DELAY 10
00291 #define NV_MIIPHY_DELAYMAX      10000
00292 #define NV_MAC_RESET_DELAY      64
00293 
00294 #define NV_MSI_X_CAPABLE        0x0020
00295 
00296 #define MII_READ        (-1)
00297 
00298 struct forcedeth_private {
00299         struct pci_device *pci_dev;
00300         struct net_device *netdev;
00301 
00302         void *mmio_addr;
00303 
00304         u32 linkspeed;
00305         int duplex;
00306 
00307         int phyaddr;
00308         unsigned int phy_oui;
00309         unsigned int phy_rev;
00310         unsigned int phy_model;
00311 
00312         u16 gigabit;
00313         u32 mac_in_use;
00314         int mgmt_version;
00315         int mgmt_sema;
00316 
00317         /* rx specific fields */
00318         struct ring_desc *rx_ring;
00319         struct io_buffer *rx_iobuf[RX_RING_SIZE];
00320         int rx_curr;
00321 
00322         /* tx specific fields */
00323         struct ring_desc *tx_ring;
00324         struct io_buffer *tx_iobuf[TX_RING_SIZE];
00325         int tx_fill_ctr;
00326         int tx_curr;
00327         int tx_tail;
00328 
00329         /* flow control */
00330         u32 pause_flags;
00331 
00332         unsigned long driver_data;
00333 };
00334 
00335 enum {
00336         NvRegIrqStatus = 0x000,
00337 #define NVREG_IRQSTAT_MIIEVENT  0x040
00338 #define NVREG_IRQSTAT_MASK              0x83ff
00339         NvRegIrqMask = 0x004,
00340 #define NVREG_IRQ_RX_ERROR              0x0001
00341 #define NVREG_IRQ_RX                    0x0002
00342 #define NVREG_IRQ_RX_NOBUF              0x0004
00343 #define NVREG_IRQ_TX_ERR                0x0008
00344 #define NVREG_IRQ_TX_OK                 0x0010
00345 #define NVREG_IRQ_TIMER                 0x0020
00346 #define NVREG_IRQ_LINK                  0x0040
00347 #define NVREG_IRQ_RX_FORCED             0x0080
00348 #define NVREG_IRQ_TX_FORCED             0x0100
00349 #define NVREG_IRQ_RECOVER_ERROR         0x8200
00350 #define NVREG_IRQMASK_THROUGHPUT        0x00df
00351 #define NVREG_IRQMASK_CPU               0x0060
00352 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
00353 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
00354 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
00355 
00356         NvRegUnknownSetupReg6 = 0x008,
00357 #define NVREG_UNKSETUP6_VAL             3
00358 
00359 /*
00360  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
00361  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
00362  */
00363         NvRegPollingInterval = 0x00c,
00364 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
00365 #define NVREG_POLL_DEFAULT_CPU  13
00366         NvRegMSIMap0 = 0x020,
00367         NvRegMSIMap1 = 0x024,
00368         NvRegMSIIrqMask = 0x030,
00369 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
00370         NvRegMisc1 = 0x080,
00371 #define NVREG_MISC1_PAUSE_TX    0x01
00372 #define NVREG_MISC1_HD          0x02
00373 #define NVREG_MISC1_FORCE       0x3b0f3c
00374 
00375         NvRegMacReset = 0x34,
00376 #define NVREG_MAC_RESET_ASSERT  0x0F3
00377         NvRegTransmitterControl = 0x084,
00378 #define NVREG_XMITCTL_START     0x01
00379 #define NVREG_XMITCTL_MGMT_ST   0x40000000
00380 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
00381 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
00382 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
00383 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
00384 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
00385 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
00386 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
00387 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
00388 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
00389 #define NVREG_XMITCTL_DATA_START        0x00100000
00390 #define NVREG_XMITCTL_DATA_READY        0x00010000
00391 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
00392         NvRegTransmitterStatus = 0x088,
00393 #define NVREG_XMITSTAT_BUSY     0x01
00394 
00395         NvRegPacketFilterFlags = 0x8c,
00396 #define NVREG_PFF_PAUSE_RX      0x08
00397 #define NVREG_PFF_ALWAYS        0x7F0000
00398 #define NVREG_PFF_PROMISC       0x80
00399 #define NVREG_PFF_MYADDR        0x20
00400 #define NVREG_PFF_LOOPBACK      0x10
00401 
00402         NvRegOffloadConfig = 0x90,
00403 #define NVREG_OFFLOAD_HOMEPHY   0x601
00404 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
00405         NvRegReceiverControl = 0x094,
00406 #define NVREG_RCVCTL_START      0x01
00407 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
00408         NvRegReceiverStatus = 0x98,
00409 #define NVREG_RCVSTAT_BUSY      0x01
00410 
00411         NvRegSlotTime = 0x9c,
00412 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
00413 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
00414 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
00415 #define NVREG_SLOTTIME_HALF             0x0000ff00
00416 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
00417 #define NVREG_SLOTTIME_MASK             0x000000ff
00418 
00419         NvRegTxDeferral = 0xA0,
00420 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
00421 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
00422 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
00423 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
00424 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
00425 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
00426         NvRegRxDeferral = 0xA4,
00427 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
00428         NvRegMacAddrA = 0xA8,
00429         NvRegMacAddrB = 0xAC,
00430         NvRegMulticastAddrA = 0xB0,
00431 #define NVREG_MCASTADDRA_FORCE  0x01
00432         NvRegMulticastAddrB = 0xB4,
00433         NvRegMulticastMaskA = 0xB8,
00434 #define NVREG_MCASTMASKA_NONE           0xffffffff
00435         NvRegMulticastMaskB = 0xBC,
00436 #define NVREG_MCASTMASKB_NONE           0xffff
00437 
00438         NvRegPhyInterface = 0xC0,
00439 #define PHY_RGMII               0x10000000
00440         NvRegBackOffControl = 0xC4,
00441 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
00442 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
00443 #define NVREG_BKOFFCTRL_SELECT                  24
00444 #define NVREG_BKOFFCTRL_GEAR                    12
00445 
00446         NvRegTxRingPhysAddr = 0x100,
00447         NvRegRxRingPhysAddr = 0x104,
00448         NvRegRingSizes = 0x108,
00449 #define NVREG_RINGSZ_TXSHIFT 0
00450 #define NVREG_RINGSZ_RXSHIFT 16
00451         NvRegTransmitPoll = 0x10c,
00452 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
00453         NvRegLinkSpeed = 0x110,
00454 #define NVREG_LINKSPEED_FORCE 0x10000
00455 #define NVREG_LINKSPEED_10      1000
00456 #define NVREG_LINKSPEED_100     100
00457 #define NVREG_LINKSPEED_1000    50
00458 #define NVREG_LINKSPEED_MASK    (0xFFF)
00459         NvRegUnknownSetupReg5 = 0x130,
00460 #define NVREG_UNKSETUP5_BIT31   (1<<31)
00461         NvRegTxWatermark = 0x13c,
00462 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
00463 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
00464 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
00465         NvRegTxRxControl = 0x144,
00466 #define NVREG_TXRXCTL_KICK      0x0001
00467 #define NVREG_TXRXCTL_BIT1      0x0002
00468 #define NVREG_TXRXCTL_BIT2      0x0004
00469 #define NVREG_TXRXCTL_IDLE      0x0008
00470 #define NVREG_TXRXCTL_RESET     0x0010
00471 #define NVREG_TXRXCTL_RXCHECK   0x0400
00472 #define NVREG_TXRXCTL_DESC_1    0
00473 #define NVREG_TXRXCTL_DESC_2    0x002100
00474 #define NVREG_TXRXCTL_DESC_3    0xc02200
00475 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
00476 #define NVREG_TXRXCTL_VLANINS   0x00080
00477         NvRegTxRingPhysAddrHigh = 0x148,
00478         NvRegRxRingPhysAddrHigh = 0x14C,
00479         NvRegTxPauseFrame = 0x170,
00480 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
00481 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
00482 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
00483 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
00484         NvRegTxPauseFrameLimit = 0x174,
00485 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
00486         NvRegMIIStatus = 0x180,
00487 #define NVREG_MIISTAT_ERROR             0x0001
00488 #define NVREG_MIISTAT_LINKCHANGE        0x0008
00489 #define NVREG_MIISTAT_MASK_RW           0x0007
00490 #define NVREG_MIISTAT_MASK_ALL          0x000f
00491         NvRegMIIMask = 0x184,
00492 #define NVREG_MII_LINKCHANGE            0x0008
00493 
00494         NvRegAdapterControl = 0x188,
00495 #define NVREG_ADAPTCTL_START    0x02
00496 #define NVREG_ADAPTCTL_LINKUP   0x04
00497 #define NVREG_ADAPTCTL_PHYVALID 0x40000
00498 #define NVREG_ADAPTCTL_RUNNING  0x100000
00499 #define NVREG_ADAPTCTL_PHYSHIFT 24
00500         NvRegMIISpeed = 0x18c,
00501 #define NVREG_MIISPEED_BIT8     (1<<8)
00502 #define NVREG_MIIDELAY  5
00503         NvRegMIIControl = 0x190,
00504 #define NVREG_MIICTL_INUSE      0x08000
00505 #define NVREG_MIICTL_WRITE      0x00400
00506 #define NVREG_MIICTL_ADDRSHIFT  5
00507         NvRegMIIData = 0x194,
00508         NvRegTxUnicast = 0x1a0,
00509         NvRegTxMulticast = 0x1a4,
00510         NvRegTxBroadcast = 0x1a8,
00511         NvRegWakeUpFlags = 0x200,
00512 #define NVREG_WAKEUPFLAGS_VAL           0x7770
00513 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
00514 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
00515 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
00516 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
00517 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
00518 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
00519 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
00520 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
00521 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
00522 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
00523 
00524         NvRegMgmtUnitGetVersion = 0x204,
00525 #define NVREG_MGMTUNITGETVERSION        0x01
00526         NvRegMgmtUnitVersion = 0x208,
00527 #define NVREG_MGMTUNITVERSION           0x08
00528         NvRegPowerCap = 0x268,
00529 #define NVREG_POWERCAP_D3SUPP   (1<<30)
00530 #define NVREG_POWERCAP_D2SUPP   (1<<26)
00531 #define NVREG_POWERCAP_D1SUPP   (1<<25)
00532         NvRegPowerState = 0x26c,
00533 #define NVREG_POWERSTATE_POWEREDUP      0x8000
00534 #define NVREG_POWERSTATE_VALID          0x0100
00535 #define NVREG_POWERSTATE_MASK           0x0003
00536 #define NVREG_POWERSTATE_D0             0x0000
00537 #define NVREG_POWERSTATE_D1             0x0001
00538 #define NVREG_POWERSTATE_D2             0x0002
00539 #define NVREG_POWERSTATE_D3             0x0003
00540         NvRegMgmtUnitControl = 0x278,
00541 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
00542         NvRegTxCnt = 0x280,
00543         NvRegTxZeroReXmt = 0x284,
00544         NvRegTxOneReXmt = 0x288,
00545         NvRegTxManyReXmt = 0x28c,
00546         NvRegTxLateCol = 0x290,
00547         NvRegTxUnderflow = 0x294,
00548         NvRegTxLossCarrier = 0x298,
00549         NvRegTxExcessDef = 0x29c,
00550         NvRegTxRetryErr = 0x2a0,
00551         NvRegRxFrameErr = 0x2a4,
00552         NvRegRxExtraByte = 0x2a8,
00553         NvRegRxLateCol = 0x2ac,
00554         NvRegRxRunt = 0x2b0,
00555         NvRegRxFrameTooLong = 0x2b4,
00556         NvRegRxOverflow = 0x2b8,
00557         NvRegRxFCSErr = 0x2bc,
00558         NvRegRxFrameAlignErr = 0x2c0,
00559         NvRegRxLenErr = 0x2c4,
00560         NvRegRxUnicast = 0x2c8,
00561         NvRegRxMulticast = 0x2cc,
00562         NvRegRxBroadcast = 0x2d0,
00563         NvRegTxDef = 0x2d4,
00564         NvRegTxFrame = 0x2d8,
00565         NvRegRxCnt = 0x2dc,
00566         NvRegTxPause = 0x2e0,
00567         NvRegRxPause = 0x2e4,
00568         NvRegRxDropFrame = 0x2e8,
00569         NvRegVlanControl = 0x300,
00570 #define NVREG_VLANCONTROL_ENABLE        0x2000
00571         NvRegMSIXMap0 = 0x3e0,
00572         NvRegMSIXMap1 = 0x3e4,
00573         NvRegMSIXIrqStatus = 0x3f0,
00574 
00575         NvRegPowerState2 = 0x600,
00576 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
00577 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
00578 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
00579 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
00580 };
00581 
00582 enum {
00583         NV_OPTIMIZATION_MODE_THROUGHPUT,
00584         NV_OPTIMIZATION_MODE_CPU,
00585         NV_OPTIMIZATION_MODE_DYNAMIC
00586 };
00587 
00588 enum {
00589         NV_CROSSOVER_DETECTION_DISABLED,
00590         NV_CROSSOVER_DETECTION_ENABLED
00591 };
00592 
00593 
00594 #define NV_SETUP_RX_RING        0x01
00595 #define NV_SETUP_TX_RING        0x02
00596 
00597 #define NV_RESTART_TX           0x1
00598 #define NV_RESTART_RX           0x2
00599 
00600 #endif /* _FORCEDETH_H_ */