iPXE
icplus.h
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00001 #ifndef _ICPLUS_H
00002 #define _ICPLUS_H
00003 
00004 /** @file
00005  *
00006  * IC+ network driver
00007  *
00008  */
00009 
00010 #include <ipxe/nvs.h>
00011 #include <ipxe/mii_bit.h>
00012 
00013 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00014 
00015 /** BAR size */
00016 #define ICP_BAR_SIZE 0x200
00017 
00018 /** Alignment requirement */
00019 #define ICP_ALIGN 0x8
00020 
00021 /** Base address low register offset */
00022 #define ICP_BASE_LO 0x0
00023 
00024 /** Base address high register offset */
00025 #define ICP_BASE_HI 0x4
00026 
00027 /** ASIC control register (double word) */
00028 #define ICP_ASICCTRL 0x30
00029 #define ICP_ASICCTRL_PHYSPEED1000       0x00000040UL    /**< PHY speed 1000 */
00030 #define ICP_ASICCTRL_GLOBALRESET        0x00010000UL    /**< Global reset */
00031 #define ICP_ASICCTRL_DMA                0x00080000UL    /**< DMA */
00032 #define ICP_ASICCTRL_FIFO               0x00100000UL    /**< FIFO */
00033 #define ICP_ASICCTRL_NETWORK            0x00200000UL    /**< Network */
00034 #define ICP_ASICCTRL_HOST               0x00400000UL    /**< Host */
00035 #define ICP_ASICCTRL_AUTOINIT           0x00800000UL    /**< Auto init */
00036 #define ICP_ASICCTRL_RESETBUSY          0x04000000UL    /**< Reset busy */
00037 
00038 /** Maximum time to wait for reset */
00039 #define ICP_RESET_MAX_WAIT_MS 1000
00040 
00041 /** DMA control register (word/double word) */
00042 #define ICP_DMACTRL 0x00
00043 #define ICP_DMACTRL_RXPOLLNOW           0x0010          /**< Receive poll now */
00044 #define ICP_DMACTRL_TXPOLLNOW           0x1000          /**< Transmit poll now */
00045 
00046 /** EEPROM control register (word) */
00047 #define ICP_EEPROMCTRL 0x4a
00048 #define ICP_EEPROMCTRL_ADDRESS( x )     ( (x) << 0 )    /**< Address */
00049 #define ICP_EEPROMCTRL_OPCODE( x )      ( (x) << 8 )    /**< Opcode */
00050 #define ICP_EEPROMCTRL_OPCODE_READ \
00051         ICP_EEPROMCTRL_OPCODE ( 2 )                     /**< Read register */
00052 #define ICP_EEPROMCTRL_BUSY             0x8000          /**< EEPROM busy */
00053 
00054 /** Maximum time to wait for reading EEPROM */
00055 #define ICP_EEPROM_MAX_WAIT_MS 1000
00056 
00057 /** EEPROM word length */
00058 #define ICP_EEPROM_WORD_LEN_LOG2 1
00059 
00060 /** Minimum EEPROM size, in words */
00061 #define ICP_EEPROM_MIN_SIZE_WORDS 0x20
00062 
00063 /** Address of MAC address within EEPROM */
00064 #define ICP_EEPROM_MAC 0x10
00065 
00066 /** EEPROM data register (word) */
00067 #define ICP_EEPROMDATA 0x48
00068 
00069 /** Interupt status register (word) */
00070 #define ICP_INTSTATUS 0x5e
00071 #define ICP_INTSTATUS_TXCOMPLETE        0x0004          /**< TX complete */
00072 #define ICP_INTSTATUS_LINKEVENT         0x0100          /**< Link event */
00073 #define ICP_INTSTATUS_RXDMACOMPLETE     0x0400          /**< RX DMA complete */
00074 
00075 /** MAC control register (double word) */
00076 #define ICP_MACCTRL 0x6c
00077 #define ICP_MACCTRL_DUPLEX              0x00000020UL    /**< Duplex select */
00078 #define ICP_MACCTRL_TXENABLE            0x01000000UL    /**< TX enable */
00079 #define ICP_MACCTRL_TXDISABLE           0x02000000UL    /**< TX disable */
00080 #define ICP_MACCTRL_RXENABLE            0x08000000UL    /**< RX enable */
00081 #define ICP_MACCTRL_RXDISABLE           0x10000000UL    /**< RX disable */
00082 
00083 /** PHY control register (byte) */
00084 #define ICP_PHYCTRL 0x76
00085 #define ICP_PHYCTRL_MGMTCLK             0x01            /**< Management clock */
00086 #define ICP_PHYCTRL_MGMTDATA            0x02            /**< Management data */
00087 #define ICP_PHYCTRL_MGMTDIR             0x04            /**< Management direction */
00088 #define ICP_PHYCTRL_LINKSPEED           0xc0            /**< Link speed */
00089 
00090 /** Receive mode register (word) */
00091 #define ICP_RXMODE 0x88
00092 #define ICP_RXMODE_UNICAST              0x0001          /**< Receive unicast */
00093 #define ICP_RXMODE_MULTICAST            0x0002          /**< Receice multicast */
00094 #define ICP_RXMODE_BROADCAST            0x0004          /**< Receive broadcast */
00095 #define ICP_RXMODE_ALLFRAMES            0x0008          /**< Receive all frames */
00096 
00097 /** List pointer receive register */
00098 #define ICP_RFDLISTPTR 0x1c
00099 
00100 /** List pointer transmit register */
00101 #define ICP_TFDLISTPTR 0x10
00102 
00103 /** Transmit status register */
00104 #define ICP_TXSTATUS 0x60
00105 #define ICP_TXSTATUS_ERROR              0x00000001UL    /**< TX error */
00106 
00107 /** Data fragment */
00108 union icplus_fragment {
00109         /** Address of data */
00110         uint64_t address;
00111         /** Length */
00112         struct {
00113                 /** Reserved */
00114                 uint8_t reserved[6];
00115                 /** Length of data */
00116                 uint16_t len;
00117         };
00118 };
00119 
00120 /** Transmit or receive descriptor */
00121 struct icplus_descriptor {
00122         /** Address of next descriptor */
00123         uint64_t next;
00124         /** Actual length */
00125         uint16_t len;
00126         /** Flags */
00127         uint8_t flags;
00128         /** Control */
00129         uint8_t control;
00130         /** VLAN */
00131         uint16_t vlan;
00132         /** Reserved */
00133         uint16_t reserved_a;
00134         /** Data buffer */
00135         union icplus_fragment data;
00136         /** Reserved */
00137         uint8_t reserved_b[8];
00138 };
00139 
00140 /** Descriptor complete */
00141 #define ICP_DONE 0x80
00142 
00143 /** Transmit alignment disabled */
00144 #define ICP_TX_UNALIGN 0x01
00145 
00146 /** Request transmit completion */
00147 #define ICP_TX_INDICATE 0x40
00148 
00149 /** Sole transmit fragment */
00150 #define ICP_TX_SOLE_FRAG 0x01
00151 
00152 /** Recieve frame overrun error */
00153 #define ICP_RX_ERR_OVERRUN 0x01
00154 
00155 /** Receive runt frame error */
00156 #define ICP_RX_ERR_RUNT 0x02
00157 
00158 /** Receive alignment error */
00159 #define ICP_RX_ERR_ALIGN 0x04
00160 
00161 /** Receive FCS error */
00162 #define ICP_RX_ERR_FCS 0x08
00163 
00164 /** Receive oversized frame error */
00165 #define ICP_RX_ERR_OVERSIZED 0x10
00166 
00167 /** Recieve length error */
00168 #define ICP_RX_ERR_LEN 0x20
00169 
00170 /** Descriptor ring */
00171 struct icplus_ring {
00172         /** Producer counter */
00173         unsigned int prod;
00174         /** Consumer counter */
00175         unsigned int cons;
00176         /** Ring entries */
00177         struct icplus_descriptor *entry;
00178         /* List pointer register */
00179         unsigned int listptr;
00180 };
00181 
00182 /** Number of descriptors */
00183 #define ICP_NUM_DESC 4
00184 
00185 /** Maximum receive packet length */
00186 #define ICP_RX_MAX_LEN ETH_FRAME_LEN
00187 
00188 /** An IC+ network card */
00189 struct icplus_nic {
00190         /** Registers */
00191         void *regs;
00192         /** EEPROM */
00193         struct nvs_device eeprom;
00194         /** MII bit bashing interface */
00195         struct mii_bit_basher miibit;
00196         /** MII device */
00197         struct mii_device mii;
00198         /** Transmit descriptor ring */
00199         struct icplus_ring tx;
00200         /** Receive descriptor ring */
00201         struct icplus_ring rx;
00202         /** Receive I/O buffers */
00203         struct io_buffer *rx_iobuf[ICP_NUM_DESC];
00204 };
00205 
00206 #endif /* _ICPLUS_H */