iPXE
rhine.h
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00001 #ifndef _RHINE_H
00002 #define _RHINE_H
00003 
00004 /** @file
00005  *
00006  * VIA Rhine network driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER );
00011 
00012 /** Rhine BAR size */
00013 #define RHINE_BAR_SIZE          256
00014 
00015 /** Default timeout */
00016 #define RHINE_TIMEOUT_US        10000
00017 
00018 /** Rhine descriptor format */
00019 struct rhine_descriptor {
00020         uint32_t        des0;
00021         uint32_t        des1;
00022         uint32_t        buffer;
00023         uint32_t        next;
00024 } __attribute__ (( packed ));
00025 
00026 #define RHINE_DES0_OWN          (1 << 31)       /*< Owned descriptor */
00027 #define RHINE_DES1_IC           (1 << 23)       /*< Generate interrupt */
00028 #define RHINE_TDES1_EDP         (1 << 22)       /*< End of packet */
00029 #define RHINE_TDES1_STP         (1 << 21)       /*< Start of packet */
00030 #define RHINE_TDES1_TCPCK       (1 << 20)       /*< HW TCP checksum */
00031 #define RHINE_TDES1_UDPCK       (1 << 19)       /*< HW UDP checksum */
00032 #define RHINE_TDES1_IPCK        (1 << 18)       /*< HW IP checksum */
00033 #define RHINE_TDES1_TAG         (1 << 17)       /*< Tagged frame */
00034 #define RHINE_TDES1_CRC         (1 << 16)       /*< No CRC */
00035 #define RHINE_DES1_CHAIN        (1 << 15)       /*< Chained descriptor */
00036 #define RHINE_DES1_SIZE(_x)     ((_x) & 0x7ff)  /*< Frame size */
00037 #define RHINE_DES0_GETSIZE(_x)  (((_x) >> 16) & 0x7ff)
00038 
00039 #define RHINE_RDES0_RXOK        (1 << 15)
00040 #define RHINE_RDES0_VIDHIT      (1 << 14)
00041 #define RHINE_RDES0_MAR         (1 << 13)
00042 #define RHINE_RDES0_BAR         (1 << 12)
00043 #define RHINE_RDES0_PHY         (1 << 11)
00044 #define RHINE_RDES0_CHN         (1 << 10)
00045 #define RHINE_RDES0_STP         (1 << 9)
00046 #define RHINE_RDES0_EDP         (1 << 8)
00047 #define RHINE_RDES0_BUFF        (1 << 7)
00048 #define RHINE_RDES0_FRAG        (1 << 6)
00049 #define RHINE_RDES0_RUNT        (1 << 5)
00050 #define RHINE_RDES0_LONG        (1 << 4)
00051 #define RHINE_RDES0_FOV         (1 << 3)
00052 #define RHINE_RDES0_FAE         (1 << 2)
00053 #define RHINE_RDES0_CRCE        (1 << 1)
00054 #define RHINE_RDES0_RERR        (1 << 0)
00055 
00056 #define RHINE_TDES0_TERR        (1 << 15)
00057 #define RHINE_TDES0_UDF         (1 << 11)
00058 #define RHINE_TDES0_CRS         (1 << 10)
00059 #define RHINE_TDES0_OWC         (1 << 9)
00060 #define RHINE_TDES0_ABT         (1 << 8)
00061 #define RHINE_TDES0_CDH         (1 << 7)
00062 #define RHINE_TDES0_COLS        (1 << 4)
00063 #define RHINE_TDES0_NCR(_x)     ((_x) & 0xf)
00064 
00065 #define RHINE_RING_ALIGN        4
00066 
00067 /** Rhine descriptor rings sizes */
00068 #define RHINE_RXDESC_NUM        4
00069 #define RHINE_TXDESC_NUM        8
00070 #define RHINE_RX_MAX_LEN        1536
00071 
00072 /** Rhine MAC address registers */
00073 #define RHINE_MAC               0x00
00074 
00075 /** Receive control register */
00076 #define RHINE_RCR               0x06
00077 #define RHINE_RCR_FIFO_TRSH(_x) (((_x) & 0x7) << 5) /*< RX FIFO threshold */
00078 #define RHINE_RCR_PHYS_ACCEPT   (1 << 4)        /*< Accept matching PA */
00079 #define RHINE_RCR_BCAST_ACCEPT  (1 << 3)        /*< Accept broadcast */
00080 #define RHINE_RCR_MCAST_ACCEPT  (1 << 2)        /*< Accept multicast */
00081 #define RHINE_RCR_RUNT_ACCEPT   (1 << 1)        /*< Accept runt frames */
00082 #define RHINE_RCR_ERR_ACCEPT    (1 << 0)        /*< Accept erroneous frames */
00083 
00084 /** Transmit control register */
00085 #define RHINE_TCR               0x07
00086 #define RHINE_TCR_LOOPBACK(_x)  (((_x) & 0x3) << 1) /*< Transmit loop mode */
00087 #define RHINE_TCR_TAGGING       (1 << 0)        /*< 802.1P/Q packet tagging */
00088 
00089 /** Command 0 register */
00090 #define RHINE_CR0               0x08
00091 #define RHINE_CR0_RXSTART       (1 << 6)
00092 #define RHINE_CR0_TXSTART       (1 << 5)
00093 #define RHINE_CR0_TXEN          (1 << 4)        /*< Transmit enable */
00094 #define RHINE_CR0_RXEN          (1 << 3)        /*< Receive enable */
00095 #define RHINE_CR0_STOPNIC       (1 << 2)        /*< Stop NIC */
00096 #define RHINE_CR0_STARTNIC      (1 << 1)        /*< Start NIC */
00097 
00098 /** Command 1 register */
00099 #define RHINE_CR1               0x09
00100 #define RHINE_CR1_RESET         (1 << 7)        /*< Software reset */
00101 #define RHINE_CR1_RXPOLL        (1 << 6)        /*< Receive poll demand */
00102 #define RHINE_CR1_TXPOLL        (1 << 5)        /*< Xmit poll demand */
00103 #define RHINE_CR1_AUTOPOLL      (1 << 3)        /*< Disable autopoll */
00104 #define RHINE_CR1_FDX           (1 << 2)        /*< Full duplex */
00105 #define RIHNE_CR1_ACCUNI        (1 << 1)        /*< Disable accept unicast */
00106 
00107 /** Transmit queue wake register */
00108 #define RHINE_TXQUEUE_WAKE      0x0a
00109 
00110 /** Interrupt service 0 */
00111 #define RHINE_ISR0              0x0c
00112 #define RHINE_ISR0_MIBOVFL      (1 << 7)
00113 #define RHINE_ISR0_PCIERR       (1 << 6)
00114 #define RHINE_ISR0_RXRINGERR    (1 << 5)
00115 #define RHINE_ISR0_TXRINGERR    (1 << 4)
00116 #define RHINE_ISR0_TXERR        (1 << 3)
00117 #define RHINE_ISR0_RXERR        (1 << 2)
00118 #define RHINE_ISR0_TXDONE       (1 << 1)
00119 #define RHINE_ISR0_RXDONE       (1 << 0)
00120 
00121 /** Interrupt service 1 */
00122 #define RHINE_ISR1              0x0d
00123 #define RHINE_ISR1_GPI          (1 << 7)
00124 #define RHINE_ISR1_PORTSTATE    (1 << 6)
00125 #define RHINE_ISR1_TXABORT      (1 << 5)
00126 #define RHINE_ISR1_RXNOBUF      (1 << 4)
00127 #define RHINE_ISR1_RXFIFOOVFL   (1 << 3)
00128 #define RHINE_ISR1_RXFIFOUNFL   (1 << 2)
00129 #define RHINE_ISR1_TXFIFOUNFL   (1 << 1)
00130 #define RHINE_ISR1_EARLYRX      (1 << 0)
00131 
00132 /** Interrupt enable mask register 0 */
00133 #define RHINE_IMR0              0x0e
00134 
00135 /** Interrupt enable mask register 1 */
00136 #define RHINE_IMR1              0x0f
00137 
00138 /** RX queue descriptor base address */
00139 #define RHINE_RXQUEUE_BASE      0x18
00140 
00141 /** TX queue 0 descriptor base address */
00142 #define RHINE_TXQUEUE_BASE      0x1c
00143 
00144 /** MII configuration */
00145 #define RHINE_MII_CFG           0x6c
00146 
00147 /** MII status register */
00148 #define RHINE_MII_SR            0x6d
00149 #define RHINE_MII_SR_PHYRST     (1 << 7)        /*< PHY reset */
00150 #define RHINE_MII_SR_LINKNWAY   (1 << 4)        /*< Link status after N-Way */
00151 #define RHINE_MII_SR_PHYERR     (1 << 3)        /*< PHY device error */
00152 #define RHINE_MII_SR_DUPLEX     (1 << 2)        /*< Duplex mode after N-Way */
00153 #define RHINE_MII_SR_LINKPOLL   (1 << 1)        /*< Link status after poll */
00154 #define RHINE_MII_SR_LINKSPD    (1 << 0)        /*< Link speed after N-Way */
00155 
00156 /** MII bus control 0 register */
00157 #define RHINE_MII_BCR0          0x6e
00158 
00159 /** MII bus control 1 register */
00160 #define RHINE_MII_BCR1          0x6f
00161 
00162 /** MII control register */
00163 #define RHINE_MII_CR            0x70
00164 #define RHINE_MII_CR_AUTOPOLL   (1 << 7)        /*< MII auto polling */
00165 #define RHINE_MII_CR_RDEN       (1 << 6)        /*< PHY read enable */
00166 #define RHINE_MII_CR_WREN       (1 << 5)        /*< PHY write enable */
00167 #define RHINE_MII_CR_DIRECT     (1 << 4)        /*< Direct programming mode */
00168 #define RHINE_MII_CR_MDIOOUT    (1 << 3)        /*< MDIO output enable */
00169 
00170 /** MII port address */
00171 #define RHINE_MII_ADDR          0x71
00172 #define RHINE_MII_ADDR_MSRCEN   (1 << 6)
00173 #define RHINE_MII_ADDR_MDONE    (1 << 5)
00174 
00175 /** MII read/write data */
00176 #define RHINE_MII_RDWR          0x72
00177 
00178 /** EERPOM control/status register */
00179 #define RHINE_EEPROM_CTRL       0x74
00180 #define RHINE_EEPROM_CTRL_STATUS        (1 << 7) /*< EEPROM status */
00181 #define RHINE_EEPROM_CTRL_RELOAD        (1 << 5) /*< EEPROM reload */
00182 
00183 /** Chip configuration A */
00184 #define RHINE_CHIPCFG_A         0x78
00185 /* MMIO enable. Only valid for Rhine I. Reserved on later boards */
00186 #define RHINE_CHIPCFG_A_MMIO    (1 << 5)
00187 
00188 /** Chip configuration B */
00189 #define RHINE_CHIPCFG_B         0x79
00190 
00191 /** Chip configuation C */
00192 #define RHINE_CHIPCFG_C         0x7a
00193 
00194 /** Chip configuration D */
00195 #define RHINE_CHIPCFG_D         0x7b
00196 /* MMIO enable. Only valid on Rhine II and later. GPIOEN on Rhine I */
00197 #define RHINE_CHIPCFG_D_MMIO    (1 << 7)
00198 
00199 #define RHINE_REVISION_OLD      0x20
00200 
00201 /** A VIA Rhine descriptor ring */
00202 struct rhine_ring {
00203         /** Descriptors */
00204         struct rhine_descriptor *desc;
00205         /** Producer index */
00206         unsigned int prod;
00207         /** Consumer index */
00208         unsigned int cons;
00209 
00210         /** Number of descriptors */
00211         unsigned int count;
00212         /** Register address */
00213         unsigned int reg;
00214 };
00215 
00216 /**
00217  * Initialise descriptor ring
00218  *
00219  * @v ring              Descriptor ring
00220  * @v count             Number of descriptors (must be a power of 2)
00221  * @v reg               Register address
00222  */
00223 static inline __attribute__ (( always_inline)) void
00224 rhine_init_ring ( struct rhine_ring *ring, unsigned int count,
00225                   unsigned int reg ) {
00226         ring->count = count;
00227         ring->reg = reg;
00228 }
00229 
00230 /** A VIA Rhine network card */
00231 struct rhine_nic {
00232         /** I/O address (some PIO access is always required) */
00233         unsigned long ioaddr;
00234         /** Registers */
00235         void *regs;
00236         /** Cached value of CR1 (to avoid read-modify-write on fast path) */
00237         uint8_t cr1;
00238 
00239         /** MII interface */
00240         struct mii_interface mdio;
00241         /** MII device */
00242         struct mii_device mii;
00243 
00244         /** Transmit descriptor ring */
00245         struct rhine_ring tx;
00246         /** Receive descriptor ring */
00247         struct rhine_ring rx;
00248         /** Receive I/O buffers */
00249         struct io_buffer *rx_iobuf[RHINE_RXDESC_NUM];
00250 };
00251 
00252 #endif /* _RHINE_H */