iPXE
thunderx.h
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00001 #ifndef _THUNDERX_H
00002 #define _THUNDERX_H
00003 
00004 /** @file
00005  *
00006  * Cavium ThunderX Ethernet driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00011 
00012 #include <stdint.h>
00013 #include <ipxe/list.h>
00014 #include <ipxe/netdevice.h>
00015 #include <ipxe/uaccess.h>
00016 
00017 /******************************************************************************
00018  *
00019  * Address space
00020  *
00021  ******************************************************************************
00022  */
00023 
00024 /** Size of a cache line */
00025 #define TXNIC_LINE_SIZE 128
00026 
00027 /** Virtual function BAR size */
00028 #define TXNIC_VF_BAR_SIZE 0x200000UL
00029 
00030 /** Physical function BAR size */
00031 #define TXNIC_PF_BAR_SIZE 0x40000000UL
00032 
00033 /** BGX BAR size */
00034 #define TXNIC_BGX_BAR_SIZE 0x400000UL
00035 
00036 /** Maximum number of BGX Ethernet interfaces (per node) */
00037 #define TXNIC_NUM_BGX 2
00038 
00039 /** Maximum number of Logical MACs (per BGX) */
00040 #define TXNIC_NUM_LMAC 4
00041 
00042 /** Maximum number of destination MAC addresses (per BGX) */
00043 #define TXNIC_NUM_DMAC 32
00044 
00045 /** Maximum number of steering rules (per BGX) */
00046 #define TXNIC_NUM_STEERING 8
00047 
00048 /**
00049  * Calculate node ID
00050  *
00051  * @v addr              PCI BAR base address
00052  * @ret node            Node ID
00053  */
00054 static inline unsigned int txnic_address_node ( uint64_t addr ) {
00055 
00056         /* Node ID is in bits [45:44] of the hardcoded BAR address */
00057         return ( ( addr >> 44 ) & 0x3 );
00058 }
00059 
00060 /**
00061  * Calculate BGX Ethernet interface index
00062  *
00063  * @v addr              PCI BAR base address
00064  * @ret index           Index
00065  */
00066 static inline unsigned int txnic_address_bgx ( uint64_t addr ) {
00067 
00068         /* Index is in bit 24 of the hardcoded BAR address */
00069         return ( ( addr >> 24 ) & 0x1 );
00070 }
00071 
00072 /******************************************************************************
00073  *
00074  * Send queue
00075  *
00076  ******************************************************************************
00077  */
00078 
00079 /** Send queue configuration */
00080 #define TXNIC_QS_SQ_CFG(q)              ( ( (q) << 18 ) | 0x010800 )
00081 #define TXNIC_QS_SQ_CFG_ENA                     (                1ULL   << 19 )
00082 #define TXNIC_QS_SQ_CFG_RESET                   (                1ULL   << 17 )
00083 #define TXNIC_QS_SQ_CFG_QSIZE(sz)               ( ( ( uint64_t ) (sz) ) <<  8 )
00084 #define TXNIC_QS_SQ_CFG_QSIZE_1K \
00085         TXNIC_QS_SQ_CFG_QSIZE ( 0 )
00086 
00087 /** Send queue base address */
00088 #define TXNIC_QS_SQ_BASE(q)             ( ( (q) << 18 ) | 0x010820 )
00089 
00090 /** Send queue head pointer */
00091 #define TXNIC_QS_SQ_HEAD(q)             ( ( (q) << 18 ) | 0x010828 )
00092 
00093 /** Send queue tail pointer */
00094 #define TXNIC_QS_SQ_TAIL(q)             ( ( (q) << 18 ) | 0x010830 )
00095 
00096 /** Send queue doorbell */
00097 #define TXNIC_QS_SQ_DOOR(q)             ( ( (q) << 18 ) | 0x010838 )
00098 
00099 /** Send queue status */
00100 #define TXNIC_QS_SQ_STATUS(q)           ( ( (q) << 18 ) | 0x010840 )
00101 #define TXNIC_QS_SQ_STATUS_STOPPED              (                1ULL   << 21 )
00102 
00103 /** Maximum time to wait for a send queue to stop
00104  *
00105  * This is a policy decision.
00106  */
00107 #define TXNIC_SQ_STOP_MAX_WAIT_MS 100
00108 
00109 /** A send header subdescriptor */
00110 struct txnic_send_header {
00111         /** Total length */
00112         uint32_t total;
00113         /** Unused */
00114         uint8_t unused_a[2];
00115         /** Subdescriptor count */
00116         uint8_t subdcnt;
00117         /** Flags */
00118         uint8_t flags;
00119         /** Unused */
00120         uint8_t unused_b[8];
00121 } __attribute__ (( packed ));
00122 
00123 /** Flags for send header subdescriptor
00124  *
00125  * These comprise SUBDC=0x1 and PNC=0x1.
00126  */
00127 #define TXNIC_SEND_HDR_FLAGS 0x14
00128 
00129 /** A send gather subdescriptor */
00130 struct txnic_send_gather {
00131         /** Size */
00132         uint16_t size;
00133         /** Unused */
00134         uint8_t unused[5];
00135         /** Flags */
00136         uint8_t flags;
00137         /** Address */
00138         uint64_t addr;
00139 } __attribute__ (( packed ));
00140 
00141 /** Flags for send gather subdescriptor
00142  *
00143  * These comprise SUBDC=0x4 and LD_TYPE=0x0.
00144  */
00145 #define TXNIC_SEND_GATHER_FLAGS 0x40
00146 
00147 /** A send queue entry
00148  *
00149  * Each send queue entry comprises a single send header subdescriptor
00150  * and a single send gather subdescriptor.
00151  */
00152 struct txnic_sqe {
00153         /** Send header descriptor */
00154         struct txnic_send_header hdr;
00155         /** Send gather descriptor */
00156         struct txnic_send_gather gather;
00157 } __attribute__ (( packed ));
00158 
00159 /** Number of subdescriptors per send queue entry */
00160 #define TXNIC_SQE_SUBDESCS ( sizeof ( struct txnic_sqe ) / \
00161                              sizeof ( struct txnic_send_header ) )
00162 
00163 /** Number of send queue entries
00164  *
00165  * The minimum send queue size is 1024 entries.
00166  */
00167 #define TXNIC_SQES ( 1024 / TXNIC_SQE_SUBDESCS )
00168 
00169 /** Send queue maximum fill level
00170  *
00171  * This is a policy decision.
00172  */
00173 #define TXNIC_SQ_FILL 32
00174 
00175 /** Send queue alignment */
00176 #define TXNIC_SQ_ALIGN TXNIC_LINE_SIZE
00177 
00178 /** Send queue stride */
00179 #define TXNIC_SQ_STRIDE sizeof ( struct txnic_sqe )
00180 
00181 /** Send queue size */
00182 #define TXNIC_SQ_SIZE ( TXNIC_SQES * TXNIC_SQ_STRIDE )
00183 
00184 /** A send queue */
00185 struct txnic_sq {
00186         /** Producer counter */
00187         unsigned int prod;
00188         /** Consumer counter */
00189         unsigned int cons;
00190         /** Send queue entries */
00191         userptr_t sqe;
00192 };
00193 
00194 /******************************************************************************
00195  *
00196  * Receive queue
00197  *
00198  ******************************************************************************
00199  */
00200 
00201 /** Receive queue configuration */
00202 #define TXNIC_QS_RQ_CFG(q)              ( ( (q) << 18 ) | 0x010600 )
00203 #define TXNIC_QS_RQ_CFG_ENA                     (                1ULL   <<  1 )
00204 
00205 /** Maximum time to wait for a receive queue to disable
00206  *
00207  * This is a policy decision.
00208  */
00209 #define TXNIC_RQ_DISABLE_MAX_WAIT_MS 100
00210 
00211 /** Receive buffer descriptor ring configuration */
00212 #define TXNIC_QS_RBDR_CFG(q)            ( ( (q) << 18 ) | 0x010c00 )
00213 #define TXNIC_QS_RBDR_CFG_ENA                   (                1ULL   << 44 )
00214 #define TXNIC_QS_RBDR_CFG_RESET                 (                1ULL   << 43 )
00215 #define TXNIC_QS_RBDR_CFG_QSIZE(sz)             ( ( ( uint64_t ) (sz) ) << 32 )
00216 #define TXNIC_QS_RBDR_CFG_QSIZE_8K \
00217         TXNIC_QS_RBDR_CFG_QSIZE ( 0 )
00218 #define TXNIC_QS_RBDR_CFG_LINES(sz)             ( ( ( uint64_t ) (sz) ) <<  0 )
00219 
00220 /** Receive buffer descriptor ring base address */
00221 #define TXNIC_QS_RBDR_BASE(q)           ( ( (q) << 18 ) | 0x010c20 )
00222 
00223 /** Receive buffer descriptor ring head pointer */
00224 #define TXNIC_QS_RBDR_HEAD(q)           ( ( (q) << 18 ) | 0x010c28 )
00225 
00226 /** Receive buffer descriptor ring tail pointer */
00227 #define TXNIC_QS_RBDR_TAIL(q)           ( ( (q) << 18 ) | 0x010c30 )
00228 
00229 /** Receive buffer descriptor ring doorbell */
00230 #define TXNIC_QS_RBDR_DOOR(q)           ( ( (q) << 18 ) | 0x010c38 )
00231 
00232 /** Receive buffer descriptor ring status 0 */
00233 #define TXNIC_QS_RBDR_STATUS0(q)        ( ( (q) << 18 ) | 0x010c40 )
00234 
00235 /** A receive buffer descriptor ring entry */
00236 struct txnic_rbdr_entry {
00237         /** Address */
00238         uint64_t addr;
00239 } __attribute__ (( packed ));
00240 
00241 /** A receive queue entry */
00242 struct txnic_rqe {
00243         /** Receive buffer descriptor ring entry */
00244         struct txnic_rbdr_entry rbdre;
00245 } __attribute__ (( packed ));
00246 
00247 /** Number of receive queue entries
00248  *
00249  * The minimum receive queue size is 8192 entries.
00250  */
00251 #define TXNIC_RQES 8192
00252 
00253 /** Receive queue maximum fill level
00254  *
00255  * This is a policy decision.  Must not exceed TXNIC_RQES.
00256  */
00257 #define TXNIC_RQ_FILL 32
00258 
00259 /** Receive queue entry size
00260  *
00261  * This is a policy decision.
00262  */
00263 #define TXNIC_RQE_SIZE ( ( ETH_DATA_ALIGN + ETH_FRAME_LEN +             \
00264                            4 /* VLAN */ + TXNIC_LINE_SIZE - 1 )         \
00265                          & ~( TXNIC_LINE_SIZE - 1 ) )
00266 
00267 /** Receive queue alignment */
00268 #define TXNIC_RQ_ALIGN TXNIC_LINE_SIZE
00269 
00270 /** Receive queue stride */
00271 #define TXNIC_RQ_STRIDE sizeof ( struct txnic_rqe )
00272 
00273 /** Receive queue size */
00274 #define TXNIC_RQ_SIZE ( TXNIC_RQES * TXNIC_RQ_STRIDE )
00275 
00276 /** A receive queue */
00277 struct txnic_rq {
00278         /** Producer counter */
00279         unsigned int prod;
00280         /** Consumer counter */
00281         unsigned int cons;
00282         /** Receive queue entries */
00283         userptr_t rqe;
00284         /** I/O buffers */
00285         struct io_buffer *iobuf[TXNIC_RQ_FILL];
00286 };
00287 
00288 /******************************************************************************
00289  *
00290  * Completion queue
00291  *
00292  ******************************************************************************
00293  */
00294 
00295 /** Completion queue configuration */
00296 #define TXNIC_QS_CQ_CFG(q)              ( ( (q) << 18 ) | 0x010400 )
00297 #define TXNIC_QS_CQ_CFG_ENA                     (                1ULL   << 42 )
00298 #define TXNIC_QS_CQ_CFG_RESET                   (                1ULL   << 41 )
00299 #define TXNIC_QS_CQ_CFG_QSIZE(sz)               ( ( ( uint64_t ) (sz) ) << 32 )
00300 #define TXNIC_QS_CQ_CFG_QSIZE_256 \
00301         TXNIC_QS_CQ_CFG_QSIZE ( 7 )
00302 
00303 /** Maximum time to wait for a completion queue to disable
00304  *
00305  * This is a policy decision.
00306  */
00307 #define TXNIC_CQ_DISABLE_MAX_WAIT_MS 100
00308 
00309 /** Completion queue base address */
00310 #define TXNIC_QS_CQ_BASE(q)             ( ( (q) << 18 ) | 0x010420 )
00311 
00312 /** Completion queue head pointer */
00313 #define TXNIC_QS_CQ_HEAD(q)             ( ( (q) << 18 ) | 0x010428 )
00314 
00315 /** Completion queue tail pointer */
00316 #define TXNIC_QS_CQ_TAIL(q)             ( ( (q) << 18 ) | 0x010430 )
00317 
00318 /** Completion queue doorbell */
00319 #define TXNIC_QS_CQ_DOOR(q)             ( ( (q) << 18 ) | 0x010438 )
00320 
00321 /** Completion queue status */
00322 #define TXNIC_QS_CQ_STATUS(q)           ( ( (q) << 18 ) | 0x010440 )
00323 #define TXNIC_QS_CQ_STATUS_QCOUNT(status) \
00324         ( ( (status) >> 0 ) & 0xffff )
00325 
00326 /** Completion queue status 2 */
00327 #define TXNIC_QS_CQ_STATUS2(q)          ( ( (q) << 18 ) | 0x010448 )
00328 
00329 /** A send completion queue entry */
00330 struct txnic_cqe_send {
00331         /** Status */
00332         uint8_t send_status;
00333         /** Unused */
00334         uint8_t unused[4];
00335         /** Send queue entry pointer */
00336         uint16_t sqe_ptr;
00337         /** Type */
00338         uint8_t cqe_type;
00339 } __attribute__ (( packed ));
00340 
00341 /** Send completion queue entry type */
00342 #define TXNIC_CQE_TYPE_SEND 0x80
00343 
00344 /** A receive completion queue entry */
00345 struct txnic_cqe_rx {
00346         /** Error opcode */
00347         uint8_t errop;
00348         /** Unused */
00349         uint8_t unused_a[6];
00350         /** Type */
00351         uint8_t cqe_type;
00352         /** Unused */
00353         uint8_t unused_b[1];
00354         /** Padding */
00355         uint8_t apad;
00356         /** Unused */
00357         uint8_t unused_c[4];
00358         /** Length */
00359         uint16_t len;
00360 } __attribute__ (( packed ));
00361 
00362 /** Receive completion queue entry type */
00363 #define TXNIC_CQE_TYPE_RX 0x20
00364 
00365 /** Applied padding */
00366 #define TXNIC_CQE_RX_APAD_LEN( apad ) ( (apad) >> 5 )
00367 
00368 /** Completion queue entry common fields */
00369 struct txnic_cqe_common {
00370         /** Unused */
00371         uint8_t unused_a[7];
00372         /** Type */
00373         uint8_t cqe_type;
00374 } __attribute__ (( packed ));
00375 
00376 /** A completion queue entry */
00377 union txnic_cqe {
00378         /** Common fields */
00379         struct txnic_cqe_common common;
00380         /** Send completion */
00381         struct txnic_cqe_send send;
00382         /** Receive completion */
00383         struct txnic_cqe_rx rx;
00384 };
00385 
00386 /** Number of completion queue entries
00387  *
00388  * The minimum completion queue size is 256 entries.
00389  */
00390 #define TXNIC_CQES 256
00391 
00392 /** Completion queue alignment */
00393 #define TXNIC_CQ_ALIGN 512
00394 
00395 /** Completion queue stride */
00396 #define TXNIC_CQ_STRIDE 512
00397 
00398 /** Completion queue size */
00399 #define TXNIC_CQ_SIZE ( TXNIC_CQES * TXNIC_CQ_STRIDE )
00400 
00401 /** A completion queue */
00402 struct txnic_cq {
00403         /** Consumer counter */
00404         unsigned int cons;
00405         /** Completion queue entries */
00406         userptr_t cqe;
00407 };
00408 
00409 /******************************************************************************
00410  *
00411  * Virtual NIC
00412  *
00413  ******************************************************************************
00414  */
00415 
00416 /** A virtual NIC */
00417 struct txnic {
00418         /** Registers */
00419         void *regs;
00420         /** Device name (for debugging) */
00421         const char *name;
00422         /** Network device */
00423         struct net_device *netdev;
00424 
00425         /** Send queue */
00426         struct txnic_sq sq;
00427         /** Receive queue */
00428         struct txnic_rq rq;
00429         /** Completion queue */
00430         struct txnic_cq cq;
00431 };
00432 
00433 /******************************************************************************
00434  *
00435  * Physical function
00436  *
00437  ******************************************************************************
00438  */
00439 
00440 /** Physical function configuration */
00441 #define TXNIC_PF_CFG                    0x000000
00442 #define TXNIC_PF_CFG_ENA                        (                1ULL   <<  0 )
00443 
00444 /** Backpressure configuration */
00445 #define TXNIC_PF_BP_CFG                 0x000080
00446 #define TXNIC_PF_BP_CFG_BP_POLL_ENA             (                1ULL   <<  6 )
00447 #define TXNIC_PF_BP_CFG_BP_POLL_DLY(dl)         ( ( ( uint64_t ) (dl) ) <<  0 )
00448 #define TXNIC_PF_BP_CFG_BP_POLL_DLY_DEFAULT \
00449         TXNIC_PF_BP_CFG_BP_POLL_DLY ( 3 )
00450 
00451 /** Interface send configuration */
00452 #define TXNIC_PF_INTF_SEND_CFG(in)      ( ( (in) << 8 ) | 0x000200 )
00453 #define TXNIC_PF_INTF_SEND_CFG_BLOCK_BGX        (                1ULL   <<  3 )
00454 #define TXNIC_PF_INTF_SEND_CFG_BLOCK(bl)        ( ( ( uint64_t ) (bl) ) <<  0 )
00455 
00456 /** Interface backpressure configuration */
00457 #define TXNIC_PF_INTF_BP_CFG(in)        ( ( (in) << 8 ) | 0x000208 )
00458 #define TXNIC_PF_INTF_BP_CFG_BP_ENA             (                1ULL   << 63 )
00459 #define TXNIC_PF_INTF_BP_CFG_BP_ID_BGX          (                1ULL   <<  3 )
00460 #define TXNIC_PF_INTF_BP_CFG_BP_ID(bp)          ( ( ( uint64_t ) (bp) ) <<  0 )
00461 
00462 /** Port kind configuration */
00463 #define TXNIC_PF_PKIND_CFG(pk)          ( ( (pk) << 3 ) | 0x000600 )
00464 #define TXNIC_PF_PKIND_CFG_LENERR_EN            (                1ULL   << 33 )
00465 #define TXNIC_PF_PKIND_CFG_MAXLEN(ct)           ( ( ( uint64_t ) (ct) ) << 16 )
00466 #define TXNIC_PF_PKIND_CFG_MAXLEN_DISABLE \
00467         TXNIC_PF_PKIND_CFG_MAXLEN ( 0xffff )
00468 #define TXNIC_PF_PKIND_CFG_MINLEN(ct)           ( ( ( uint64_t ) (ct) ) <<  0 )
00469 #define TXNIC_PF_PKIND_CFG_MINLEN_DISABLE \
00470         TXNIC_PF_PKIND_CFG_MINLEN ( 0x0000 )
00471 
00472 /** Match parse index configuration */
00473 #define TXNIC_PF_MPI_CFG(ix)            ( ( (ix) << 3 ) | 0x210000 )
00474 #define TXNIC_PF_MPI_CFG_VNIC(vn)               ( ( ( uint64_t ) (vn) ) << 24 )
00475 #define TXNIC_PF_MPI_CFG_RSSI_BASE(ix)          ( ( ( uint64_t ) (ix) ) <<  0 )
00476 
00477 /** RSS indirection receive queue */
00478 #define TXNIC_PF_RSSI_RQ(ix)            ( ( (ix) << 3 ) | 0x220000 )
00479 #define TXNIC_PF_RSSI_RQ_RQ_QS(qs)              ( ( ( uint64_t ) (qs) ) << 3 )
00480 
00481 /** LMAC registers */
00482 #define TXNIC_PF_LMAC(lm)               ( ( (lm) << 3 ) | 0x240000 )
00483 
00484 /** LMAC configuration */
00485 #define TXNIC_PF_LMAC_CFG               0x000000
00486 #define TXNIC_PF_LMAC_CFG_ADJUST(ad)            ( ( ( uint64_t ) (ad) ) <<  8 )
00487 #define TXNIC_PF_LMAC_CFG_ADJUST_DEFAULT \
00488         TXNIC_PF_LMAC_CFG_ADJUST ( 6 )
00489 #define TXNIC_PF_LMAC_CFG_MIN_PKT_SIZE(sz)      ( ( ( uint64_t ) (sz) ) <<  0 )
00490 
00491 /** LMAC configuration 2 */
00492 #define TXNIC_PF_LMAC_CFG2              0x000100
00493 #define TXNIC_PF_LMAC_CFG2_MAX_PKT_SIZE(sz)     ( ( ( uint64_t ) (sz) ) <<  0 )
00494 
00495 /** LMAC credit */
00496 #define TXNIC_PF_LMAC_CREDIT            0x004000
00497 #define TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT(ct)    ( ( ( uint64_t ) (ct) ) << 12 )
00498 #define TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT_DEFAULT \
00499         TXNIC_PF_LMAC_CREDIT_CC_UNIT_CNT ( 192 )
00500 #define TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT(ct)  ( ( ( uint64_t ) (ct) ) <<  2 )
00501 #define TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT_DEFAULT \
00502         TXNIC_PF_LMAC_CREDIT_CC_PACKET_CNT ( 511 )
00503 #define TXNIC_PF_LMAC_CREDIT_CC_ENABLE          (                1ULL   <<  1 )
00504 
00505 /** Channel registers */
00506 #define TXNIC_PF_CHAN(ch)               ( ( (ch) << 3 ) | 0x400000 )
00507 
00508 /** Channel transmit configuration */
00509 #define TXNIC_PF_CHAN_TX_CFG            0x000000
00510 #define TXNIC_PF_CHAN_TX_CFG_BP_ENA             (                1ULL   <<  0 )
00511 
00512 /** Channel receive configuration */
00513 #define TXNIC_PF_CHAN_RX_CFG            0x020000
00514 #define TXNIC_PF_CHAN_RX_CFG_CPI_BASE(ix)       ( ( ( uint64_t ) (ix) ) << 48 )
00515 
00516 /** Channel receive backpressure configuration */
00517 #define TXNIC_PF_CHAN_RX_BP_CFG         0x080000
00518 #define TXNIC_PF_CHAN_RX_BP_CFG_ENA             (                1ULL   << 63 )
00519 #define TXNIC_PF_CHAN_RX_BP_CFG_BPID(bp)        ( ( ( uint64_t ) (bp) ) <<  0 )
00520 
00521 /** Traffic limiter 2 configuration */
00522 #define TXNIC_PF_TL2_CFG(tl)            ( ( (tl) << 3 ) | 0x500000 )
00523 #define TXNIC_PF_TL2_CFG_RR_QUANTUM(rr)         ( ( ( uint64_t ) (rr) ) <<  0 )
00524 #define TXNIC_PF_TL2_CFG_RR_QUANTUM_DEFAULT \
00525         TXNIC_PF_TL2_CFG_RR_QUANTUM ( 0x905 )
00526 
00527 /** Traffic limiter 3 configuration */
00528 #define TXNIC_PF_TL3_CFG(tl)            ( ( (tl) << 3 ) | 0x600000 )
00529 #define TXNIC_PF_TL3_CFG_RR_QUANTUM(rr)         ( ( ( uint64_t ) (rr) ) <<  0 )
00530 #define TXNIC_PF_TL3_CFG_RR_QUANTUM_DEFAULT \
00531         TXNIC_PF_TL3_CFG_RR_QUANTUM ( 0x905 )
00532 
00533 /** Traffic limiter 3 channel mapping */
00534 #define TXNIC_PF_TL3_CHAN(tl)           ( ( (tl) << 3 ) | 0x620000 )
00535 #define TXNIC_PF_TL3_CHAN_CHAN(ch)              ( ( (ch) & 0x7f ) << 0 )
00536 
00537 /** Traffic limiter 4 configuration */
00538 #define TXNIC_PF_TL4_CFG(tl)            ( ( (tl) << 3 ) | 0x800000 )
00539 #define TXNIC_PF_TL4_CFG_SQ_QS(qs)              ( ( ( uint64_t ) (qs) ) << 27 )
00540 #define TXNIC_PF_TL4_CFG_RR_QUANTUM(rr)         ( ( ( uint64_t ) (rr) ) <<  0 )
00541 #define TXNIC_PF_TL4_CFG_RR_QUANTUM_DEFAULT \
00542         TXNIC_PF_TL4_CFG_RR_QUANTUM ( 0x905 )
00543 
00544 /** Queue set registers */
00545 #define TXNIC_PF_QS(qs)                 ( ( (qs) << 21 ) | 0x20000000UL )
00546 
00547 /** Queue set configuration */
00548 #define TXNIC_PF_QS_CFG                 0x010000
00549 #define TXNIC_PF_QS_CFG_ENA                     (                1ULL   << 31 )
00550 #define TXNIC_PF_QS_CFG_VNIC(vn)                ( ( ( uint64_t ) (vn) ) <<  0 )
00551 
00552 /** Receive queue configuration */
00553 #define TXNIC_PF_QS_RQ_CFG(q)           ( ( (q) << 18 ) | 0x010400 )
00554 #define TXNIC_PF_QS_RQ_CFG_CACHING(cx)          ( ( ( uint64_t ) (cx) ) << 26 )
00555 #define TXNIC_PF_QS_RQ_CFG_CACHING_ALL \
00556         TXNIC_PF_QS_RQ_CFG_CACHING ( 1 )
00557 #define TXNIC_PF_QS_RQ_CFG_CQ_QS(qs)            ( ( ( uint64_t ) (qs) ) << 19 )
00558 #define TXNIC_PF_QS_RQ_CFG_RBDR_CONT_QS(qs)     ( ( ( uint64_t ) (qs) ) <<  9 )
00559 #define TXNIC_PF_QS_RQ_CFG_RBDR_STRT_QS(qs)     ( ( ( uint64_t ) (qs) ) <<  1 )
00560 
00561 /** Receive queue drop configuration */
00562 #define TXNIC_PF_QS_RQ_DROP_CFG(q)      ( ( (q) << 18 ) | 0x010420 )
00563 
00564 /** Receive queue backpressure configuration */
00565 #define TXNIC_PF_QS_RQ_BP_CFG(q)        ( ( (q) << 18 ) | 0x010500 )
00566 #define TXNIC_PF_QS_RQ_BP_CFG_RBDR_BP_ENA       (                1ULL   << 63 )
00567 #define TXNIC_PF_QS_RQ_BP_CFG_CQ_BP_ENA         (                1ULL   << 62 )
00568 #define TXNIC_PF_QS_RQ_BP_CFG_BPID(bp)          ( ( ( uint64_t ) (bp) ) <<  0 )
00569 
00570 /** Send queue configuration */
00571 #define TXNIC_PF_QS_SQ_CFG(q)           ( ( (q) << 18 ) | 0x010c00 )
00572 #define TXNIC_PF_QS_SQ_CFG_CQ_QS(qs)            ( ( ( uint64_t ) (qs) ) <<  3 )
00573 
00574 /** Send queue configuration 2 */
00575 #define TXNIC_PF_QS_SQ_CFG2(q)          ( ( (q) << 18 ) | 0x010c08 )
00576 #define TXNIC_PF_QS_SQ_CFG2_TL4(tl)             ( ( ( uint64_t ) (tl) ) <<  0 )
00577 
00578 /** A physical function */
00579 struct txnic_pf {
00580         /** Registers */
00581         void *regs;
00582         /** PCI device */
00583         struct pci_device *pci;
00584         /** Node ID */
00585         unsigned int node;
00586 
00587         /** Virtual function BAR base */
00588         unsigned long vf_membase;
00589         /** Virtual function BAR stride */
00590         unsigned long vf_stride;
00591 
00592         /** List of physical functions */
00593         struct list_head list;
00594         /** BGX Ethernet interfaces (if known) */
00595         struct txnic_bgx *bgx[TXNIC_NUM_BGX];
00596 };
00597 
00598 /**
00599  * Calculate virtual NIC index
00600  *
00601  * @v bgx_idx           BGX Ethernet interface index
00602  * @v lmac_idx          Logical MAC index
00603  * @ret vnic_idx        Virtual NIC index
00604  */
00605 #define TXNIC_VNIC_IDX( bgx_idx, lmac_idx ) \
00606         ( ( (bgx_idx) * TXNIC_NUM_LMAC ) + (lmac_idx) )
00607 
00608 /**
00609  * Calculate BGX Ethernet interface index
00610  *
00611  * @v vnic_idx          Virtual NIC index
00612  * @ret bgx_idx         BGX Ethernet interface index
00613  */
00614 #define TXNIC_BGX_IDX( vnic_idx ) ( (vnic_idx) / TXNIC_NUM_LMAC )
00615 
00616 /**
00617  * Calculate logical MAC index
00618  *
00619  * @v vnic_idx          Virtual NIC index
00620  * @ret lmac_idx        Logical MAC index
00621  */
00622 #define TXNIC_LMAC_IDX( vnic_idx ) ( (vnic_idx) % TXNIC_NUM_LMAC )
00623 
00624 /**
00625  * Calculate traffic limiter 2 index
00626  *
00627  * @v vnic_idx          Virtual NIC index
00628  * @v tl2_idx           Traffic limiter 2 index
00629  */
00630 #define TXNIC_TL2_IDX( vnic_idx ) ( (vnic_idx) << 3 )
00631 
00632 /**
00633  * Calculate traffic limiter 3 index
00634  *
00635  * @v vnic_idx          Virtual NIC index
00636  * @v tl3_idx           Traffic limiter 3 index
00637  */
00638 #define TXNIC_TL3_IDX( vnic_idx ) ( (vnic_idx) << 5 )
00639 
00640 /**
00641  * Calculate traffic limiter 4 index
00642  *
00643  * @v vnic_idx          Virtual NIC index
00644  * @v tl4_idx           Traffic limiter 4 index
00645  */
00646 #define TXNIC_TL4_IDX( vnic_idx ) ( (vnic_idx) << 7 )
00647 
00648 /**
00649  * Calculate channel index
00650  *
00651  * @v vnic_idx          Virtual NIC index
00652  * @v chan_idx          Channel index
00653  */
00654 #define TXNIC_CHAN_IDX( vnic_idx ) ( ( TXNIC_BGX_IDX (vnic_idx) << 7 ) | \
00655                                      ( TXNIC_LMAC_IDX (vnic_idx) << 4 ) )
00656 
00657 /******************************************************************************
00658  *
00659  * BGX Ethernet interface
00660  *
00661  ******************************************************************************
00662  */
00663 
00664 /** Per-LMAC registers */
00665 #define BGX_LMAC(lm)                    ( ( (lm) << 20 ) | 0x00000000UL )
00666 
00667 /** CMR configuration */
00668 #define BGX_CMR_CONFIG                  0x000000
00669 #define BGX_CMR_CONFIG_ENABLE                   (                1ULL   << 15 )
00670 #define BGX_CMR_CONFIG_DATA_PKT_RX_EN           (                1ULL   << 14 )
00671 #define BGX_CMR_CONFIG_DATA_PKT_TX_EN           (                1ULL   << 13 )
00672 #define BGX_CMR_CONFIG_LMAC_TYPE_GET(config) \
00673         ( ( (config) >> 8 ) & 0x7 )
00674 #define BGX_CMR_CONFIG_LMAC_TYPE_SET(ty)        ( ( ( uint64_t ) (ty) ) <<  8 )
00675 #define BGX_CMR_CONFIG_LANE_TO_SDS(ls)          ( ( ( uint64_t ) (ls) ) <<  0 )
00676 
00677 /** CMR global configuration */
00678 #define BGX_CMR_GLOBAL_CONFIG           0x000008
00679 #define BGX_CMR_GLOBAL_CONFIG_FCS_STRIP         (                1ULL   <<  6 )
00680 
00681 /** CMR receive statistics 0 */
00682 #define BGX_CMR_RX_STAT0                0x000070
00683 
00684 /** CMR receive statistics 1 */
00685 #define BGX_CMR_RX_STAT1                0x000078
00686 
00687 /** CMR receive statistics 2 */
00688 #define BGX_CMR_RX_STAT2                0x000080
00689 
00690 /** CMR receive statistics 3 */
00691 #define BGX_CMR_RX_STAT3                0x000088
00692 
00693 /** CMR receive statistics 4 */
00694 #define BGX_CMR_RX_STAT4                0x000090
00695 
00696 /** CMR receive statistics 5 */
00697 #define BGX_CMR_RX_STAT5                0x000098
00698 
00699 /** CMR receive statistics 6 */
00700 #define BGX_CMR_RX_STAT6                0x0000a0
00701 
00702 /** CMR receive statistics 7 */
00703 #define BGX_CMR_RX_STAT7                0x0000a8
00704 
00705 /** CMR receive statistics 8 */
00706 #define BGX_CMR_RX_STAT8                0x0000b0
00707 
00708 /** CMR receive statistics 9 */
00709 #define BGX_CMR_RX_STAT9                0x0000b8
00710 
00711 /** CMR receive statistics 10 */
00712 #define BGX_CMR_RX_STAT10               0x0000c0
00713 
00714 /** CMR destination MAC control */
00715 #define BGX_CMR_RX_DMAC_CTL             0x0000e8
00716 #define BGX_CMR_RX_DMAC_CTL_MCST_MODE(md)       ( ( ( uint64_t ) (md) ) <<  1 )
00717 #define BGX_CMR_RX_DMAC_CTL_MCST_MODE_ACCEPT \
00718         BGX_CMR_RX_DMAC_CTL_MCST_MODE ( 1 )
00719 #define BGX_CMR_RX_DMAC_CTL_BCST_ACCEPT         (                1ULL   <<  0 )
00720 
00721 /** CMR destination MAC CAM */
00722 #define BGX_CMR_RX_DMAC_CAM(i)          ( ( (i) << 3 ) | 0x000200 )
00723 
00724 /** CMR receive steering */
00725 #define BGX_CMR_RX_STEERING(i)          ( ( (i) << 3 ) | 0x000300 )
00726 
00727 /** CMR backpressure channel mask AND */
00728 #define BGX_CMR_CHAN_MSK_AND            0x000450
00729 #define BGX_CMR_CHAN_MSK_AND_ALL(count) \
00730         ( 0xffffffffffffffffULL >> ( 16 * ( 4 - (count) ) ) )
00731 
00732 /** CMR transmit statistics 0 */
00733 #define BGX_CMR_TX_STAT0                0x000600
00734 
00735 /** CMR transmit statistics 1 */
00736 #define BGX_CMR_TX_STAT1                0x000608
00737 
00738 /** CMR transmit statistics 2 */
00739 #define BGX_CMR_TX_STAT2                0x000610
00740 
00741 /** CMR transmit statistics 3 */
00742 #define BGX_CMR_TX_STAT3                0x000618
00743 
00744 /** CMR transmit statistics 4 */
00745 #define BGX_CMR_TX_STAT4                0x000620
00746 
00747 /** CMR transmit statistics 5 */
00748 #define BGX_CMR_TX_STAT5                0x000628
00749 
00750 /** CMR transmit statistics 6 */
00751 #define BGX_CMR_TX_STAT6                0x000630
00752 
00753 /** CMR transmit statistics 7 */
00754 #define BGX_CMR_TX_STAT7                0x000638
00755 
00756 /** CMR transmit statistics 8 */
00757 #define BGX_CMR_TX_STAT8                0x000640
00758 
00759 /** CMR transmit statistics 9 */
00760 #define BGX_CMR_TX_STAT9                0x000648
00761 
00762 /** CMR transmit statistics 10 */
00763 #define BGX_CMR_TX_STAT10               0x000650
00764 
00765 /** CMR transmit statistics 11 */
00766 #define BGX_CMR_TX_STAT11               0x000658
00767 
00768 /** CMR transmit statistics 12 */
00769 #define BGX_CMR_TX_STAT12               0x000660
00770 
00771 /** CMR transmit statistics 13 */
00772 #define BGX_CMR_TX_STAT13               0x000668
00773 
00774 /** CMR transmit statistics 14 */
00775 #define BGX_CMR_TX_STAT14               0x000670
00776 
00777 /** CMR transmit statistics 15 */
00778 #define BGX_CMR_TX_STAT15               0x000678
00779 
00780 /** CMR transmit statistics 16 */
00781 #define BGX_CMR_TX_STAT16               0x000680
00782 
00783 /** CMR transmit statistics 17 */
00784 #define BGX_CMR_TX_STAT17               0x000688
00785 
00786 /** CMR receive logical MACs */
00787 #define BGX_CMR_RX_LMACS                0x000468
00788 #define BGX_CMR_RX_LMACS_LMACS_GET(lmacs) \
00789         ( ( (lmacs) >> 0 ) & 0x7 )
00790 #define BGX_CMR_RX_LMACS_LMACS_SET(ct)          ( ( ( uint64_t ) (ct) ) <<  0 )
00791 
00792 /** CMR transmit logical MACs */
00793 #define BGX_CMR_TX_LMACS                0x001000
00794 #define BGX_CMR_TX_LMACS_LMACS_GET(lmacs) \
00795         ( ( (lmacs) >> 0 ) & 0x7 )
00796 #define BGX_CMR_TX_LMACS_LMACS_SET(ct)          ( ( ( uint64_t ) (ct) ) <<  0 )
00797 
00798 /** SPU control 1 */
00799 #define BGX_SPU_CONTROL1                0x010000
00800 #define BGX_SPU_CONTROL1_RESET                  (                1ULL   << 15 )
00801 #define BGX_SPU_CONTROL1_LO_PWR                 (                1ULL   << 11 )
00802 
00803 /** SPU reset delay */
00804 #define BGX_SPU_RESET_DELAY_MS 10
00805 
00806 /** SPU status 1 */
00807 #define BGX_SPU_STATUS1                 0x010008
00808 #define BGX_SPU_STATUS1_FLT                     (                1ULL   <<  7 )
00809 #define BGX_SPU_STATUS1_RCV_LNK                 (                1ULL   <<  2 )
00810 
00811 /** SPU status 2 */
00812 #define BGX_SPU_STATUS2                 0x010020
00813 #define BGX_SPU_STATUS2_RCVFLT                  (                1ULL   << 10 )
00814 
00815 /** SPU BASE-R status 1 */
00816 #define BGX_SPU_BR_STATUS1              0x010030
00817 #define BGX_SPU_BR_STATUS1_RCV_LNK              (                1ULL   << 12 )
00818 #define BGX_SPU_BR_STATUS1_HI_BER               (                1ULL   <<  1 )
00819 #define BGX_SPU_BR_STATUS1_BLK_LOCK             (                1ULL   <<  0 )
00820 
00821 /** SPU BASE-R status 2 */
00822 #define BGX_SPU_BR_STATUS2              0x010038
00823 #define BGX_SPU_BR_STATUS2_LATCHED_LOCK         (                1ULL   << 15 )
00824 #define BGX_SPU_BR_STATUS2_LATCHED_BER          (                1ULL   << 14 )
00825 
00826 /** SPU BASE-R alignment status */
00827 #define BGX_SPU_BR_ALGN_STATUS          0x010050
00828 #define BGX_SPU_BR_ALGN_STATUS_ALIGND           (                1ULL   << 12 )
00829 
00830 /** SPU BASE-R link training control */
00831 #define BGX_SPU_BR_PMD_CONTROL          0x010068
00832 #define BGX_SPU_BR_PMD_CONTROL_TRAIN_EN         (                1ULL   <<  1 )
00833 
00834 /** SPU BASE-R link training status */
00835 #define BGX_SPU_BR_PMD_STATUS           0x010070
00836 
00837 /** SPU link partner coefficient update */
00838 #define BGX_SPU_BR_PMD_LP_CUP           0x010078
00839 
00840 /** SPU local device coefficient update */
00841 #define BGX_SPU_BR_PMD_LD_CUP           0x010088
00842 
00843 /** SPU local device status report */
00844 #define BGX_SPU_BR_PMD_LD_REP           0x010090
00845 
00846 /** SPU forward error correction control */
00847 #define BGX_SPU_FEC_CONTROL             0x0100a0
00848 
00849 /** SPU autonegotation control */
00850 #define BGX_SPU_AN_CONTROL              0x0100c8
00851 
00852 /** SPU autonegotiation status */
00853 #define BGX_SPU_AN_STATUS               0x0100d0
00854 #define BGX_SPU_AN_STATUS_XNP_STAT              (                1ULL   <<  7 )
00855 #define BGX_SPU_AN_STATUS_PAGE_RX               (                1ULL   <<  6 )
00856 #define BGX_SPU_AN_STATUS_AN_COMPLETE           (                1ULL   <<  5 )
00857 #define BGX_SPU_AN_STATUS_LINK_STATUS           (                1ULL   <<  2 )
00858 #define BGX_SPU_AN_STATUS_LP_AN_ABLE            (                1ULL   <<  0 )
00859 
00860 /** SPU interrupt */
00861 #define BGX_SPU_INT                     0x010220
00862 #define BGX_SPU_INT_TRAINING_FAIL               (                1ULL   << 14 )
00863 #define BGX_SPU_INT_TRAINING_DONE               (                1ULL   << 13 )
00864 #define BGX_SPU_INT_AN_COMPLETE                 (                1ULL   << 12 )
00865 #define BGX_SPU_INT_AN_LINK_GOOD                (                1ULL   << 11 )
00866 #define BGX_SPU_INT_AN_PAGE_RX                  (                1ULL   << 10 )
00867 #define BGX_SPU_INT_FEC_UNCORR                  (                1ULL   <<  9 )
00868 #define BGX_SPU_INT_FEC_CORR                    (                1ULL   <<  8 )
00869 #define BGX_SPU_INT_BIP_ERR                     (                1ULL   <<  7 )
00870 #define BGX_SPU_INT_DBG_SYNC                    (                1ULL   <<  6 )
00871 #define BGX_SPU_INT_ALGNLOS                     (                1ULL   <<  5 )
00872 #define BGX_SPU_INT_SYNLOS                      (                1ULL   <<  4 )
00873 #define BGX_SPU_INT_BITLCKLS                    (                1ULL   <<  3 )
00874 #define BGX_SPU_INT_ERR_BLK                     (                1ULL   <<  2 )
00875 #define BGX_SPU_INT_RX_LINK_DOWN                (                1ULL   <<  1 )
00876 #define BGX_SPU_INT_RX_LINK_UP                  (                1ULL   <<  0 )
00877 
00878 /** LMAC types */
00879 enum txnic_lmac_types {
00880         TXNIC_LMAC_SGMII        = 0x0,          /**< SGMII/1000BASE-X */
00881         TXNIC_LMAC_XAUI         = 0x1,          /**< 10GBASE-X/XAUI or DXAUI */
00882         TXNIC_LMAC_RXAUI        = 0x2,          /**< Reduced XAUI */
00883         TXNIC_LMAC_10G_R        = 0x3,          /**< 10GBASE-R */
00884         TXNIC_LMAC_40G_R        = 0x4,          /**< 40GBASE-R */
00885 };
00886 
00887 /** An LMAC type */
00888 struct txnic_lmac_type {
00889         /** Name */
00890         const char *name;
00891         /** Number of LMACs */
00892         uint8_t count;
00893         /** Lane-to-SDS mapping */
00894         uint32_t lane_to_sds;
00895 };
00896 
00897 /** An LMAC address */
00898 union txnic_lmac_address {
00899         struct {
00900                 uint8_t pad[2];
00901                 uint8_t raw[ETH_ALEN];
00902         } __attribute__ (( packed ));
00903         uint64_t be64;
00904 };
00905 
00906 /** A Logical MAC (LMAC) */
00907 struct txnic_lmac {
00908         /** Registers */
00909         void *regs;
00910         /** Containing BGX Ethernet interface */
00911         struct txnic_bgx *bgx;
00912         /** Virtual NIC index */
00913         unsigned int idx;
00914 
00915         /** MAC address */
00916         union txnic_lmac_address mac;
00917 
00918         /** Virtual NIC (if applicable) */
00919         struct txnic *vnic;
00920 };
00921 
00922 /** A BGX Ethernet interface */
00923 struct txnic_bgx {
00924         /** Registers */
00925         void *regs;
00926         /** PCI device */
00927         struct pci_device *pci;
00928         /** Node ID */
00929         unsigned int node;
00930         /** BGX index */
00931         unsigned int idx;
00932 
00933         /** LMAC type */
00934         struct txnic_lmac_type *type;
00935         /** Number of LMACs */
00936         unsigned int count;
00937         /** Link training is in use */
00938         int training;
00939 
00940         /** List of BGX Ethernet interfaces */
00941         struct list_head list;
00942         /** Physical function (if known) */
00943         struct txnic_pf *pf;
00944 
00945         /** Logical MACs */
00946         struct txnic_lmac lmac[TXNIC_NUM_LMAC];
00947 };
00948 
00949 #endif /* _THUNDERX_H */