iPXE
velocity.h
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00001 #ifndef _VELOCITY_H
00002 #define _VELOCITY_H
00003 
00004 /** @file
00005  *
00006  * VIA Velocity network driver
00007  *
00008  */
00009 
00010 FILE_LICENCE ( GPL2_OR_LATER );
00011 
00012 /** Skeleton BAR size */
00013 #define VELOCITY_BAR_SIZE       256
00014 
00015 /** Default timeout */
00016 #define VELOCITY_TIMEOUT_US     10 * 1000
00017 
00018 struct velocity_frag {
00019         uint32_t        addr;
00020         uint32_t        des2;
00021 } __attribute__ ((packed));
00022 
00023 /** Velocity descriptor format */
00024 struct velocity_tx_descriptor {
00025         uint32_t        des0;
00026         uint32_t        des1;
00027         /* We only use the first fragment, the HW requires us to have 7 */
00028         struct velocity_frag frags[7];
00029 } __attribute__ ((packed));
00030 
00031 struct velocity_rx_descriptor {
00032         uint32_t        des0;
00033         uint32_t        des1;
00034         uint32_t        addr;
00035         uint32_t        des2;
00036 } __attribute__ ((packed));
00037 
00038 #define VELOCITY_DES0_RMBC(_n)  (((_n) >> 16) & 0x1fff)
00039 #define VELOCITY_DES0_OWN       (1 << 31)
00040 #define VELOCITY_DES0_TERR      (1 << 15)
00041 #define VELOCITY_DES0_RXOK      (1 << 15)
00042 #define VELOCITY_DES0_FDX       (1 << 14)
00043 #define VELOCITY_DES0_GMII      (1 << 13)
00044 #define VELOCITY_DES0_LNKFL     (1 << 12)
00045 #define VELOCITY_DES0_SHDN      (1 << 10)
00046 #define VELOCITY_DES0_CRS       (1 << 9)
00047 #define VELOCITY_DES0_CDH       (1 << 8)
00048 #define VELOCITY_DES0_ABT       (1 << 7)
00049 #define VELOCITY_DES0_OWT       (1 << 6)
00050 #define VELOCITY_DES0_OWC       (1 << 5)
00051 #define VELOCITY_DES0_COLS      (1 << 4)
00052 
00053 #define VELOCITY_DES0_RXSHDN    (1 << 30)
00054 #define VELOCITY_DES0_RXER      (1 << 5)
00055 #define VELOCITY_DES0_RLE       (1 << 4)
00056 #define VELOCITY_DES0_CE        (1 << 3)
00057 #define VELOCITY_DES0_FAE       (1 << 2)
00058 #define VELOCITY_DES0_CRC       (1 << 1)
00059 #define VELOCITY_DES0_RX_ERR    ( VELOCITY_DES0_RXER | \
00060                                   VELOCITY_DES0_RLE | \
00061                                   VELOCITY_DES0_CE | \
00062                                   VELOCITY_DES0_FAE | \
00063                                   VELOCITY_DES0_CRC )
00064 
00065 /** TX descriptor fragment number */
00066 #define VELOCITY_DES1_FRAG(_n)  (((_n + 1) & 0xf) << 28)
00067 #define VELOCITY_DES1_TCPLS     ((1 << 24) | (1 << 25))
00068 #define VELOCITY_DES1_INTR      (1 << 23)
00069 #define VELOCITY_DES1_PIC       (1 << 22)
00070 #define VELOCITY_DES1_VETAG     (1 << 21)
00071 #define VELOCITY_DES1_IPCK      (1 << 20)
00072 #define VELOCITY_DES1_UDPCK     (1 << 19)
00073 #define VELOCITY_DES1_TCPCK     (1 << 18)
00074 #define VELOCITY_DES1_JMBO      (1 << 17)
00075 #define VELOCITY_DES1_CRC       (1 << 16)
00076 
00077 #define VELOCITY_DES2_IC        (1 << 31)
00078 #define VELOCITY_DES2_SIZE(_n)  (((_n) & 0x1fff) << 16)
00079 
00080 /** Number of receive descriptors
00081  *
00082  * Must be a multiple of 4 (hardware requirement).
00083  */
00084 #define VELOCITY_RXDESC_NUM     8
00085 #define VELOCITY_RXDESC_SIZE    \
00086     ( VELOCITY_RXDESC_NUM * sizeof ( struct velocity_rx_descriptor ) )
00087 
00088 /** Number of transmit descriptors */
00089 #define VELOCITY_TXDESC_NUM     8
00090 #define VELOCITY_TXDESC_SIZE    \
00091     ( VELOCITY_TXDESC_NUM * sizeof ( struct velocity_tx_descriptor ) )
00092 
00093 /** Descriptor alignment */
00094 #define VELOCITY_RING_ALIGN     64
00095 
00096 /** Receive buffer length */
00097 #define VELOCITY_RX_MAX_LEN 1536
00098 
00099 /** MAC address registers */
00100 #define VELOCITY_MAC0           0x00
00101 #define VELOCITY_MAC1           0x01
00102 #define VELOCITY_MAC2           0x02
00103 #define VELOCITY_MAC3           0x03
00104 #define VELOCITY_MAC4           0x04
00105 #define VELOCITY_MAC5           0x05
00106 
00107 /** Receive control register */
00108 #define VELOCITY_RCR            0x06
00109 #define RHINE_RCR_SYMERR_ACCEPT (1 << 7)        /*< Accept symbol error */
00110 #define RHINE_RCR_FILTER_ACCEPT (1 << 6)        /*< Accept based on filter */
00111 #define RHINE_RCR_LONG_ACCEPT   (1 << 5)        /*< Accept long packets */
00112 #define RHINE_RCR_PROMISC       (1 << 4)        /*< Promiscuous mode */
00113 #define RHINE_RCR_BCAST_ACCEPT  (1 << 3)        /*< Accept broadcast */
00114 #define RHINE_RCR_MCAST_ACCEPT  (1 << 2)        /*< Accept multicast */
00115 #define RHINE_RCR_RUNT_ACCEPT   (1 << 1)        /*< Accept runt frames */
00116 #define RHINE_RCR_ERR_ACCEPT    (1 << 0)        /*< Accept erroneous frames */
00117 
00118 /** Transmit control register */
00119 #define VELOCITY_TCR                    0x07
00120 #define VELOCITY_TCR_LB0        (1 << 0)        /*< Loopback control */
00121 #define VELOCITY_TCR_LB1        (1 << 1)        /*< Loopback control */
00122 #define VELOCITY_TCR_COLTMC0    (1 << 2)        /*< Collision retry control */
00123 #define VELOCITY_TCR_COLTMC1    (1 << 3)        /*< Collision retry control */
00124 
00125 /** Command register 0 (set) */
00126 #define VELOCITY_CRS0                   0x08
00127 #define VELOCITY_CR0_TXON       (1 << 3)        /*< Transmit enable */
00128 #define VELOCITY_CR0_RXON       (1 << 2)        /*< Receive enable */
00129 #define VELOCITY_CR0_STOP       (1 << 1)        /*< Stop NIC */
00130 #define VELOCITY_CR0_START      (1 << 0)        /*< Start NIC */
00131 
00132 /** Command register 1 (set) */
00133 #define VELOCITY_CRS1                   0x09
00134 #define VELOCITY_CR1_SFRST      (1 << 7)        /*< Software reset */
00135 #define VELOCITY_CR1_TM1EN      (1 << 6)        /*< Perioding software counting */
00136 #define VELOCITY_CR1_TM0EN      (1 << 5)        /*< Single-shot software counting */
00137 #define VELOCITY_CR1_DPOLL      (1 << 3)        /*< Disable auto polling */
00138 #define VELOCITY_CR1_DISAU      (1 << 0)        /*< Unicast reception disable */
00139 
00140 /** Command register 2 (set) */
00141 #define VELOCITY_CRS2                   0x0A
00142 #define VELOCITY_CR2_XONEN      (1 << 7)        /*< XON/XOFF mode enable */
00143 #define VELOCITY_CR2_FDXTFCEN   (1 << 6)        /*< FDX flow control TX */
00144 #define VELOCITY_CR2_FDXRFCEN   (1 << 5)
00145 #define VELOCITY_CR2_HDXFCEN    (1 << 4)
00146 
00147 /** Command register 3 (set) */
00148 #define VELOCITY_CRS3                   0x0B
00149 #define VELOCITY_CR3_FOSRST             (1 << 6)
00150 #define VELOCITY_CR3_FPHYRST            (1 << 5)
00151 #define VELOCITY_CR3_DIAG               (1 << 4)
00152 #define VELOCITY_CR3_INTPCTL            (1 << 2)
00153 #define VELOCITY_CR3_GINTMSK1           (1 << 1)
00154 #define VELOCITY_CR3_SWPEND             (1 << 0)
00155 
00156 /** Command register 0 (clear) */
00157 #define VELOCITY_CRC0                   0x0C
00158 
00159 /** Command register 1 (clear) */
00160 #define VELOCITY_CRC1                   0x0D
00161 
00162 /** Command register 2 (clear */
00163 #define VELOCITY_CRC2                   0x0E
00164 
00165 /** Command register 3 (clear */
00166 #define VELOCITY_CRC3                   0x0F
00167 #define VELOCITY_CAM0                   0x10
00168 #define VELOCITY_CAM1                   0x11
00169 #define VELOCITY_CAM2                   0x12
00170 #define VELOCITY_CAM3                   0x13
00171 #define VELOCITY_CAM4                   0x14
00172 #define VELOCITY_CAM5                   0x15
00173 #define VELOCITY_CAM6                   0x16
00174 #define VELOCITY_CAM7                   0x17
00175 #define VELOCITY_TXDESC_HI              0x18    /* Hi part of 64bit txdesc base addr */
00176 #define VELOCITY_DATABUF_HI             0x1D    /* Hi part of 64bit data buffer addr */
00177 #define VELOCITY_INTCTL0                0x20    /* interrupt control register */
00178 #define VELOCITY_RXSUPPTHR              0x20
00179 #define VELOCITY_TXSUPPTHR              0x20
00180 #define VELOCITY_INTHOLDOFF             0x20
00181 #define VELOCITY_INTCTL1                0x21    /* interrupt control register */
00182 #define VELOCITY_TXHOSTERR              0x22    /* TX host error status */
00183 #define VELOCITY_RXHOSTERR              0x23    /* RX host error status */
00184 
00185 /** Interrupt status register 0 */
00186 #define VELOCITY_ISR0                   0x24
00187 #define VELOCITY_ISR0_PTX3              (1 << 7)
00188 #define VELOCITY_ISR0_PTX2              (1 << 6)
00189 #define VELOCITY_ISR0_PTX1              (1 << 5)
00190 #define VELOCITY_ISR0_PTX0              (1 << 4)
00191 #define VELOCITY_ISR0_PTXI              (1 << 3)
00192 #define VELOCITY_ISR0_PRXI              (1 << 2)
00193 #define VELOCITY_ISR0_PPTXI             (1 << 1)
00194 #define VELOCITY_ISR0_PPRXI             (1 << 0)
00195 
00196 /** Interrupt status register 1 */
00197 #define VELOCITY_ISR1                   0x25
00198 #define VELOCITY_ISR1_SRCI              (1 << 7)
00199 #define VELOCITY_ISR1_LSTPEI            (1 << 6)
00200 #define VELOCITY_ISR1_LSTEI             (1 << 5)
00201 #define VELOCITY_ISR1_OVFL              (1 << 4)
00202 #define VELOCITY_ISR1_FLONI             (1 << 3)
00203 #define VELOCITY_ISR1_RACEI             (1 << 2)
00204 
00205 /** Interrupt status register 2 */
00206 #define VELOCITY_ISR2                   0x26
00207 #define VELOCITY_ISR2_HFLD              (1 << 7)
00208 #define VELOCITY_ISR2_UDPI              (1 << 6)
00209 #define VELOCITY_ISR2_MIBFI             (1 << 5)
00210 #define VELOCITY_ISR2_SHDNII            (1 << 4)
00211 #define VELOCITY_ISR2_PHYI              (1 << 3)
00212 #define VELOCITY_ISR2_PWEI              (1 << 2)
00213 #define VELOCITY_ISR2_TMR1I             (1 << 1)
00214 #define VELOCITY_ISR2_TMR0I             (1 << 0)
00215 
00216 /** Interrupt status register 3 */
00217 #define VELOCITY_ISR3                   0x27
00218 
00219 /** Interrupt mask register 0 */
00220 #define VELOCITY_IMR0                   0x28
00221 
00222 /** Interrupt mask register 1 */
00223 #define VELOCITY_IMR1                   0x29
00224 
00225 /** Interrupt mask register 2 */
00226 #define VELOCITY_IMR2                   0x2a
00227 
00228 /** Interrupt mask register 3 */
00229 #define VELOCITY_IMR3                   0x2b
00230 
00231 #define VELOCITY_TXSTS_PORT             0x2C    /* Transmit status port (???) */
00232 #define VELOCITY_TXQCSRS                0x30    /* TX queue ctl/status set */
00233 
00234 #define VELOCITY_TXQCSRS_DEAD3          (1 << 15)
00235 #define VELOCITY_TXQCSRS_WAK3           (1 << 14)
00236 #define VELOCITY_TXQCSRS_ACT3           (1 << 13)
00237 #define VELOCITY_TXQCSRS_RUN3           (1 << 12)
00238 #define VELOCITY_TXQCSRS_DEAD2          (1 << 11)
00239 #define VELOCITY_TXQCSRS_WAK2           (1 << 10)
00240 #define VELOCITY_TXQCSRS_ACT2           (1 << 9)
00241 #define VELOCITY_TXQCSRS_RUN2           (1 << 8)
00242 #define VELOCITY_TXQCSRS_DEAD1          (1 << 7)
00243 #define VELOCITY_TXQCSRS_WAK1           (1 << 6)
00244 #define VELOCITY_TXQCSRS_ACT1           (1 << 5)
00245 #define VELOCITY_TXQCSRS_RUN1           (1 << 4)
00246 #define VELOCITY_TXQCSRS_DEAD0          (1 << 3)
00247 #define VELOCITY_TXQCSRS_WAK0           (1 << 2)
00248 #define VELOCITY_TXQCSRS_ACT0           (1 << 1)
00249 #define VELOCITY_TXQCSRS_RUN0           (1 << 0)
00250 
00251 #define VELOCITY_RXQCSRS                0x32    /* RX queue ctl/status set */
00252 #define VELOCITY_RXQCSRC                0x36
00253 
00254 #define VELOCITY_RXQCSR_DEAD            (1 << 3)
00255 #define VELOCITY_RXQCSR_WAK             (1 << 2)
00256 #define VELOCITY_RXQCSR_ACT             (1 << 1)
00257 #define VELOCITY_RXQCSR_RUN             (1 << 0)
00258 
00259 #define VELOCITY_TXQCSRC                0x34    /* TX queue ctl/status clear */
00260 #define VELOCITY_RXQCSRC                0x36    /* RX queue ctl/status clear */
00261 #define VELOCITY_RXDESC_ADDR_LO         0x38    /* RX desc base addr (lo 32 bits) */
00262 #define VELOCITY_RXDESC_CONSIDX         0x3C    /* Current RX descriptor index */
00263 #define VELOCITY_TXQTIMER               0x3E    /* TX queue timer pend register */
00264 #define VELOCITY_RXQTIMER               0x3F    /* RX queue timer pend register */
00265 #define VELOCITY_TXDESC_ADDR_LO0        0x40    /* TX desc0 base addr (lo 32 bits) */
00266 #define VELOCITY_TXDESC_ADDR_LO1        0x44    /* TX desc1 base addr (lo 32 bits) */
00267 #define VELOCITY_TXDESC_ADDR_LO2        0x48    /* TX desc2 base addr (lo 32 bits) */
00268 #define VELOCITY_TXDESC_ADDR_LO3        0x4C    /* TX desc3 base addr (lo 32 bits) */
00269 #define VELOCITY_RXDESCNUM              0x50    /* Size of RX desc ring */
00270 #define VELOCITY_TXDESCNUM              0x52    /* Size of TX desc ring */
00271 #define VELOCITY_TXDESC_CONSIDX0        0x54    /* Current TX descriptor index */
00272 #define VELOCITY_TXDESC_CONSIDX1        0x56    /* Current TX descriptor index */
00273 #define VELOCITY_TXDESC_CONSIDX2        0x58    /* Current TX descriptor index */
00274 #define VELOCITY_TXDESC_CONSIDX3        0x5A    /* Current TX descriptor index */
00275 #define VELOCITY_TX_PAUSE_TIMER         0x5C    /* TX pause frame timer */
00276 #define VELOCITY_RXDESC_RESIDUECNT      0x5E    /* RX descriptor residue count */
00277 #define VELOCITY_FIFOTEST0              0x60    /* FIFO test register */
00278 #define VELOCITY_FIFOTEST1              0x64    /* FIFO test register */
00279 #define VELOCITY_CAMADDR                0x68    /* CAM address register */
00280 #define VELOCITY_CAMCTL                 0x69    /* CAM control register */
00281 #define VELOCITY_MIICFG                 0x6C    /* MII port config register */
00282 #define VELOCITY_MIISR                  0x6D    /* MII port status register */
00283 #define VELOCITY_MIISR_IDLE             (1 << 7)
00284 #define VELOCITY_PHYSTS0                0x6E    /* PHY status register */
00285 #define VELOCITY_PHYSTS0_LINK           (1 << 6)
00286 #define VELOCITY_PHYSTS1                0x6F    /* PHY status register */
00287 #define VELOCITY_MIICR                  0x70    /* MII command register */
00288 #define VELOCITY_MIICR_MAUTO            (1 << 7)
00289 #define VELOCITY_MIICR_RCMD             (1 << 6)
00290 #define VELOCITY_MIICR_WCMD             (1 << 5)
00291 #define VELOCITY_MIICR_MDPM             (1 << 4)
00292 #define VELOCITY_MIICR_MOUT             (1 << 3)
00293 #define VELOCITY_MIICR_MDO              (1 << 2)
00294 #define VELOCITY_MIICR_MDI              (1 << 1)
00295 #define VELOCITY_MIICR_MDC              (1 << 0)
00296 
00297 #define VELOCITY_MIIADDR                0x71    /* MII address register */
00298 #define VELOCITY_MIIDATA                0x72    /* MII data register */
00299 #define VELOCITY_SSTIMER                0x74    /* single-shot timer */
00300 #define VELOCITY_PTIMER                 0x76    /* periodic timer */
00301 #define VELOCITY_DMACFG0                0x7C    /* DMA config 0 */
00302 #define VELOCITY_DMACFG1                0x7D    /* DMA config 1 */
00303 #define VELOCITY_RXCFG                  0x7E    /* MAC RX config */
00304 #define VELOCITY_TXCFG                  0x7F    /* MAC TX config */
00305 #define VELOCITY_SWEEDATA               0x85    /* EEPROM software loaded data */
00306 
00307 /** Chip Configuration Register A */
00308 #define VELOCITY_CFGA                   0x78
00309 #define VELOCITY_CFGA_PACPI             (1 << 0)
00310 
00311 /** Power Management Sticky Register */
00312 #define VELOCITY_STICKY                 0x83
00313 #define VELOCITY_STICKY_DS0             (1 << 0)
00314 #define VELOCITY_STICKY_DS1             (1 << 1)
00315 
00316 #define VELOCITY_EEWRDAT                0x8C    /* EEPROM embedded write */
00317 #define VELOCITY_EECSUM                 0x92    /* EEPROM checksum */
00318 #define VELOCITY_EECSR                  0x93    /* EEPROM control/status */
00319 #define VELOCITY_EECSR_RELOAD           (1 << 5)
00320 #define VELOCITY_EERDDAT                0x94    /* EEPROM embedded read */
00321 #define VELOCITY_EEADDR                 0x96    /* EEPROM address */
00322 #define VELOCITY_EECMD                  0x97    /* EEPROM embedded command */
00323 
00324 /** A Velocity network card */
00325 struct velocity_nic {
00326         /** Registers */
00327         void *regs;
00328         /** MII interface */
00329         struct mii_interface mdio;
00330         /** MII device */
00331         struct mii_device mii;
00332         /** Netdev */
00333         struct net_device *netdev;
00334 
00335         /** Receive descriptor ring */
00336         struct velocity_rx_descriptor *rx_ring;
00337         /** Receive I/O buffers */
00338         struct io_buffer *rx_buffs[VELOCITY_RXDESC_NUM];
00339         /** Receive producer index */
00340         unsigned int rx_prod;
00341         /** Receive consumer index */
00342         unsigned int rx_cons;
00343         /** Receive commit number
00344           *
00345           * Used to fullfill the hardware requirement of returning receive buffers
00346           * to the hardware only in blocks of 4.
00347           */
00348         unsigned int rx_commit;
00349 
00350         /** Transmit descriptor ring */
00351         struct velocity_tx_descriptor *tx_ring;
00352         /** Transmit producer index */
00353         unsigned int tx_prod;
00354         /** Transmit consumer index */
00355         unsigned int tx_cons;
00356 };
00357 
00358 #endif /* _VELOCITY_H */