iPXE
vmxnet3.h
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00001 #ifndef _VMXNET3_H
00002 #define _VMXNET3_H
00003 
00004 /*
00005  * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
00006  *
00007  * This program is free software; you can redistribute it and/or
00008  * modify it under the terms of the GNU General Public License as
00009  * published by the Free Software Foundation; either version 2 of the
00010  * License, or any later version.
00011  *
00012  * This program is distributed in the hope that it will be useful, but
00013  * WITHOUT ANY WARRANTY; without even the implied warranty of
00014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00015  * General Public License for more details.
00016  *
00017  * You should have received a copy of the GNU General Public License
00018  * along with this program; if not, write to the Free Software
00019  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00020  * 02110-1301, USA.
00021  *
00022  * You can also choose to distribute this program under the terms of
00023  * the Unmodified Binary Distribution Licence (as given in the file
00024  * COPYING.UBDL), provided that you have satisfied its requirements.
00025  */
00026 
00027 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00028 
00029 /**
00030  * @file
00031  *
00032  * VMware vmxnet3 virtual NIC driver
00033  *
00034  */
00035 
00036 #include <ipxe/pci.h>
00037 
00038 /** Maximum number of TX queues */
00039 #define VMXNET3_MAX_TX_QUEUES 8
00040 
00041 /** Maximum number of RX queues */
00042 #define VMXNET3_MAX_RX_QUEUES 16
00043 
00044 /** Maximum number of interrupts */
00045 #define VMXNET3_MAX_INTRS 25
00046 
00047 /** Maximum packet size */
00048 #define VMXNET3_MAX_PACKET_LEN 0x4000
00049 
00050 /** "PT" PCI BAR address */
00051 #define VMXNET3_PT_BAR PCI_BASE_ADDRESS_0
00052 
00053 /** "PT" PCI BAR size */
00054 #define VMXNET3_PT_LEN 0x1000
00055 
00056 /** Interrupt Mask Register */
00057 #define VMXNET3_PT_IMR 0x0
00058 
00059 /** Transmit producer index */
00060 #define VMXNET3_PT_TXPROD 0x600
00061 
00062 /** Rx producer index for ring 1 */
00063 #define VMXNET3_PT_RXPROD 0x800
00064 
00065 /** Rx producer index for ring 2 */
00066 #define VMXNET3_PT_RXPROD2 0xa00
00067 
00068 /** "VD" PCI BAR address */
00069 #define VMXNET3_VD_BAR PCI_BASE_ADDRESS_1
00070 
00071 /** "VD" PCI BAR size */
00072 #define VMXNET3_VD_LEN 0x1000
00073 
00074 /** vmxnet3 Revision Report Selection */
00075 #define VMXNET3_VD_VRRS 0x0
00076 
00077 /** UPT Version Report Selection */
00078 #define VMXNET3_VD_UVRS 0x8
00079 
00080 /** Driver Shared Address Low */
00081 #define VMXNET3_VD_DSAL 0x10
00082 
00083 /** Driver Shared Address High */
00084 #define VMXNET3_VD_DSAH 0x18
00085 
00086 /** Command */
00087 #define VMXNET3_VD_CMD  0x20
00088 
00089 /** MAC Address Low */
00090 #define VMXNET3_VD_MACL 0x28
00091 
00092 /** MAC Address High */
00093 #define VMXNET3_VD_MACH 0x30
00094 
00095 /** Interrupt Cause Register */
00096 #define VMXNET3_VD_ICR  0x38
00097 
00098 /** Event Cause Register */
00099 #define VMXNET3_VD_ECR  0x40
00100 
00101 /** Commands */
00102 enum vmxnet3_command {
00103         VMXNET3_CMD_FIRST_SET = 0xcafe0000,
00104         VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
00105         VMXNET3_CMD_QUIESCE_DEV,
00106         VMXNET3_CMD_RESET_DEV,
00107         VMXNET3_CMD_UPDATE_RX_MODE,
00108         VMXNET3_CMD_UPDATE_MAC_FILTERS,
00109         VMXNET3_CMD_UPDATE_VLAN_FILTERS,
00110         VMXNET3_CMD_UPDATE_RSSIDT,
00111         VMXNET3_CMD_UPDATE_IML,
00112         VMXNET3_CMD_UPDATE_PMCFG,
00113         VMXNET3_CMD_UPDATE_FEATURE,
00114         VMXNET3_CMD_LOAD_PLUGIN,
00115 
00116         VMXNET3_CMD_FIRST_GET = 0xf00d0000,
00117         VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
00118         VMXNET3_CMD_GET_STATS,
00119         VMXNET3_CMD_GET_LINK,
00120         VMXNET3_CMD_GET_PERM_MAC_LO,
00121         VMXNET3_CMD_GET_PERM_MAC_HI,
00122         VMXNET3_CMD_GET_DID_LO,
00123         VMXNET3_CMD_GET_DID_HI,
00124         VMXNET3_CMD_GET_DEV_EXTRA_INFO,
00125         VMXNET3_CMD_GET_CONF_INTR
00126 };
00127 
00128 /** Events */
00129 enum vmxnet3_event {
00130         VMXNET3_ECR_RQERR = 0x00000001,
00131         VMXNET3_ECR_TQERR = 0x00000002,
00132         VMXNET3_ECR_LINK = 0x00000004,
00133         VMXNET3_ECR_DIC = 0x00000008,
00134         VMXNET3_ECR_DEBUG = 0x00000010,
00135 };
00136 
00137 /** Miscellaneous configuration descriptor */
00138 struct vmxnet3_misc_config {
00139         /** Driver version */
00140         uint32_t version;
00141         /** Guest information */
00142         uint32_t guest_info;
00143         /** Version supported */
00144         uint32_t version_support;
00145         /** UPT version supported */
00146         uint32_t upt_version_support;
00147         /** UPT features supported */
00148         uint64_t upt_features;
00149         /** Driver-private data address */
00150         uint64_t driver_data_address;
00151         /** Queue descriptors data address */
00152         uint64_t queue_desc_address;
00153         /** Driver-private data length */
00154         uint32_t driver_data_len;
00155         /** Queue descriptors data length */
00156         uint32_t queue_desc_len;
00157         /** Maximum transmission unit */
00158         uint32_t mtu;
00159         /** Maximum number of RX scatter-gather */
00160         uint16_t max_num_rx_sg;
00161         /** Number of TX queues */
00162         uint8_t num_tx_queues;
00163         /** Number of RX queues */
00164         uint8_t num_rx_queues;
00165         /** Reserved */
00166         uint32_t reserved0[4];
00167 } __attribute__ (( packed ));
00168 
00169 /** Driver version magic */
00170 #define VMXNET3_VERSION_MAGIC 0x69505845
00171 
00172 /** Interrupt configuration */
00173 struct vmxnet3_interrupt_config {
00174         uint8_t mask_mode;
00175         uint8_t num_intrs;
00176         uint8_t event_intr_index;
00177         uint8_t moderation_level[VMXNET3_MAX_INTRS];
00178         uint32_t control;
00179         uint32_t reserved0[2];
00180 } __attribute__ (( packed ));
00181 
00182 /** Interrupt control - disable all interrupts */
00183 #define VMXNET3_IC_DISABLE_ALL 0x1
00184 
00185 /** Receive filter configuration */
00186 struct vmxnet3_rx_filter_config {
00187         /** Receive filter mode */
00188         uint32_t mode;
00189         /** Multicast filter table length */
00190         uint16_t multicast_len;
00191         /** Reserved */
00192         uint16_t reserved0;
00193         /** Multicast filter table address */
00194         uint64_t multicast_address;
00195         /** VLAN filter table (one bit per possible VLAN) */
00196         uint8_t vlan_filter[512];
00197 } __attribute__ (( packed ));
00198 
00199 /** Receive filter mode */
00200 enum vmxnet3_rx_filter_mode {
00201         VMXNET3_RXM_UCAST       = 0x01,  /**< Unicast only */
00202         VMXNET3_RXM_MCAST       = 0x02,  /**< Multicast passing the filters */
00203         VMXNET3_RXM_BCAST       = 0x04,  /**< Broadcast only */
00204         VMXNET3_RXM_ALL_MULTI   = 0x08,  /**< All multicast */
00205         VMXNET3_RXM_PROMISC     = 0x10,  /**< Promiscuous */
00206 };
00207 
00208 /** Variable-length configuration descriptor */
00209 struct vmxnet3_variable_config {
00210         uint32_t version;
00211         uint32_t length;
00212         uint64_t address;
00213 } __attribute__ (( packed ));
00214 
00215 /** Driver shared area */
00216 struct vmxnet3_shared {
00217         /** Magic signature */
00218         uint32_t magic;
00219         /** Reserved */
00220         uint32_t reserved0;
00221         /** Miscellaneous configuration */
00222         struct vmxnet3_misc_config misc;
00223         /** Interrupt configuration */
00224         struct vmxnet3_interrupt_config interrupt;
00225         /** Receive filter configuration */
00226         struct vmxnet3_rx_filter_config rx_filter;
00227         /** RSS configuration */
00228         struct vmxnet3_variable_config rss;
00229         /** Pattern-matching configuration */
00230         struct vmxnet3_variable_config pattern;
00231         /** Plugin configuration */
00232         struct vmxnet3_variable_config plugin;
00233         /** Event notifications */
00234         uint32_t ecr;
00235         /** Reserved */
00236         uint32_t reserved1[5];
00237 } __attribute__ (( packed ));
00238 
00239 /** Alignment of driver shared area */
00240 #define VMXNET3_SHARED_ALIGN 8
00241 
00242 /** Driver shared area magic */
00243 #define VMXNET3_SHARED_MAGIC 0xbabefee1
00244 
00245 /** Transmit descriptor */
00246 struct vmxnet3_tx_desc {
00247         /** Address */
00248         uint64_t address;
00249         /** Flags */
00250         uint32_t flags[2];
00251 } __attribute__ (( packed ));
00252 
00253 /** Transmit generation flag */
00254 #define VMXNET3_TXF_GEN 0x00004000UL
00255 
00256 /** Transmit end-of-packet flag */
00257 #define VMXNET3_TXF_EOP 0x000001000UL
00258 
00259 /** Transmit completion request flag */
00260 #define VMXNET3_TXF_CQ 0x000002000UL
00261 
00262 /** Transmit completion descriptor */
00263 struct vmxnet3_tx_comp {
00264         /** Index of the end-of-packet descriptor */
00265         uint32_t index;
00266         /** Reserved */
00267         uint32_t reserved0[2];
00268         /** Flags */
00269         uint32_t flags;
00270 } __attribute__ (( packed ));
00271 
00272 /** Transmit completion generation flag */
00273 #define VMXNET3_TXCF_GEN 0x80000000UL
00274 
00275 /** Transmit queue control */
00276 struct vmxnet3_tx_queue_control {
00277         uint32_t num_deferred;
00278         uint32_t threshold;
00279         uint64_t reserved0;
00280 } __attribute__ (( packed ));
00281 
00282 /** Transmit queue configuration */
00283 struct vmxnet3_tx_queue_config {
00284         /** Descriptor ring address */
00285         uint64_t desc_address;
00286         /** Data ring address */
00287         uint64_t immediate_address;
00288         /** Completion ring address */
00289         uint64_t comp_address;
00290         /** Driver-private data address */
00291         uint64_t driver_data_address;
00292         /** Reserved */
00293         uint64_t reserved0;
00294         /** Number of descriptors */
00295         uint32_t num_desc;
00296         /** Number of data descriptors */
00297         uint32_t num_immediate;
00298         /** Number of completion descriptors */
00299         uint32_t num_comp;
00300         /** Driver-private data length */
00301         uint32_t driver_data_len;
00302         /** Interrupt index */
00303         uint8_t intr_index;
00304         /** Reserved */
00305         uint8_t reserved[7];
00306 } __attribute__ (( packed ));
00307 
00308 /** Transmit queue statistics */
00309 struct vmxnet3_tx_stats {
00310         /** Reserved */
00311         uint64_t reserved[10];
00312 } __attribute__ (( packed ));
00313 
00314 /** Receive descriptor */
00315 struct vmxnet3_rx_desc {
00316         /** Address */
00317         uint64_t address;
00318         /** Flags */
00319         uint32_t flags;
00320         /** Reserved */
00321         uint32_t reserved0;
00322 } __attribute__ (( packed ));
00323 
00324 /** Receive generation flag */
00325 #define VMXNET3_RXF_GEN 0x80000000UL
00326 
00327 /** Receive completion descriptor */
00328 struct vmxnet3_rx_comp {
00329         /** Descriptor index */
00330         uint32_t index;
00331         /** RSS hash value */
00332         uint32_t rss;
00333         /** Length */
00334         uint32_t len;
00335         /** Flags */
00336         uint32_t flags;
00337 } __attribute__ (( packed ));
00338 
00339 /** Receive completion generation flag */
00340 #define VMXNET3_RXCF_GEN 0x80000000UL
00341 
00342 /** Receive queue control */
00343 struct vmxnet3_rx_queue_control {
00344         uint8_t update_prod;
00345         uint8_t reserved0[7];
00346         uint64_t reserved1;
00347 } __attribute__ (( packed ));
00348 
00349 /** Receive queue configuration */
00350 struct vmxnet3_rx_queue_config {
00351         /** Descriptor ring addresses */
00352         uint64_t desc_address[2];
00353         /** Completion ring address */
00354         uint64_t comp_address;
00355         /** Driver-private data address */
00356         uint64_t driver_data_address;
00357         /** Reserved */
00358         uint64_t reserved0;
00359         /** Number of descriptors */
00360         uint32_t num_desc[2];
00361         /** Number of completion descriptors */
00362         uint32_t num_comp;
00363         /** Driver-private data length */
00364         uint32_t driver_data_len;
00365         /** Interrupt index */
00366         uint8_t intr_index;
00367         /** Reserved */
00368         uint8_t reserved[7];
00369 } __attribute__ (( packed ));
00370 
00371 /** Receive queue statistics */
00372 struct vmxnet3_rx_stats {
00373         /** Reserved */
00374         uint64_t reserved[10];
00375 } __attribute__ (( packed ));
00376 
00377 /** Queue status */
00378 struct vmxnet3_queue_status {
00379         uint8_t stopped;
00380         uint8_t reserved0[3];
00381         uint32_t error;
00382 } __attribute__ (( packed ));
00383 
00384 /** Transmit queue descriptor */
00385 struct vmxnet3_tx_queue {
00386         struct vmxnet3_tx_queue_control ctrl;
00387         struct vmxnet3_tx_queue_config cfg;
00388         struct vmxnet3_queue_status status;
00389         struct vmxnet3_tx_stats state;
00390         uint8_t reserved[88];
00391 } __attribute__ (( packed ));
00392 
00393 /** Receive queue descriptor */
00394 struct vmxnet3_rx_queue {
00395         struct vmxnet3_rx_queue_control ctrl;
00396         struct vmxnet3_rx_queue_config cfg;
00397         struct vmxnet3_queue_status status;
00398         struct vmxnet3_rx_stats stats;
00399         uint8_t reserved[88];
00400 } __attribute__ (( packed ));
00401 
00402 /**
00403  * Queue descriptor set
00404  *
00405  * We use only a single TX and RX queue
00406  */
00407 struct vmxnet3_queues {
00408         /** Transmit queue descriptor(s) */
00409         struct vmxnet3_tx_queue tx;
00410         /** Receive queue descriptor(s) */
00411         struct vmxnet3_rx_queue rx;
00412 } __attribute__ (( packed ));
00413 
00414 /** Alignment of queue descriptor set */
00415 #define VMXNET3_QUEUES_ALIGN 128
00416 
00417 /** Alignment of rings */
00418 #define VMXNET3_RING_ALIGN 512
00419 
00420 /** Number of TX descriptors */
00421 #define VMXNET3_NUM_TX_DESC 32
00422 
00423 /** Number of TX completion descriptors */
00424 #define VMXNET3_NUM_TX_COMP 32
00425 
00426 /** Number of RX descriptors */
00427 #define VMXNET3_NUM_RX_DESC 32
00428 
00429 /** Number of RX completion descriptors */
00430 #define VMXNET3_NUM_RX_COMP 32
00431 
00432 /**
00433  * DMA areas
00434  *
00435  * These are arranged in order of decreasing alignment, to allow for a
00436  * single allocation
00437  */
00438 struct vmxnet3_dma {
00439         /** TX descriptor ring */
00440         struct vmxnet3_tx_desc tx_desc[VMXNET3_NUM_TX_DESC];
00441         /** TX completion ring */
00442         struct vmxnet3_tx_comp tx_comp[VMXNET3_NUM_TX_COMP];
00443         /** RX descriptor ring */
00444         struct vmxnet3_rx_desc rx_desc[VMXNET3_NUM_RX_DESC];
00445         /** RX completion ring */
00446         struct vmxnet3_rx_comp rx_comp[VMXNET3_NUM_RX_COMP];
00447         /** Queue descriptors */
00448         struct vmxnet3_queues queues;
00449         /** Shared area */
00450         struct vmxnet3_shared shared;
00451 } __attribute__ (( packed ));
00452 
00453 /** DMA area alignment */
00454 #define VMXNET3_DMA_ALIGN 512
00455 
00456 /** Producer and consumer counters */
00457 struct vmxnet3_counters {
00458         /** Transmit producer counter */
00459         unsigned int tx_prod;
00460         /** Transmit completion consumer counter */
00461         unsigned int tx_cons;
00462         /** Receive producer counter */
00463         unsigned int rx_prod;
00464         /** Receive fill level */
00465         unsigned int rx_fill;
00466         /** Receive consumer counter */
00467         unsigned int rx_cons;
00468 };
00469 
00470 /** A vmxnet3 NIC */
00471 struct vmxnet3_nic {
00472         /** "PT" register base address */
00473         void *pt;
00474         /** "VD" register base address */
00475         void *vd;
00476 
00477         /** DMA area */
00478         struct vmxnet3_dma *dma;
00479         /** Producer and consumer counters */
00480         struct vmxnet3_counters count;
00481         /** Transmit I/O buffers */
00482         struct io_buffer *tx_iobuf[VMXNET3_NUM_TX_DESC];
00483         /** Receive I/O buffers */
00484         struct io_buffer *rx_iobuf[VMXNET3_NUM_RX_DESC];
00485 };
00486 
00487 /** vmxnet3 version that we support */
00488 #define VMXNET3_VERSION_SELECT 1
00489 
00490 /** UPT version that we support */
00491 #define VMXNET3_UPT_VERSION_SELECT 1
00492 
00493 /** MTU size */
00494 #define VMXNET3_MTU ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* FCS */ )
00495 
00496 /** Transmit ring maximum fill level */
00497 #define VMXNET3_TX_FILL ( VMXNET3_NUM_TX_DESC - 1 )
00498 
00499 /** Receive ring maximum fill level */
00500 #define VMXNET3_RX_FILL 8
00501 
00502 /** Received packet alignment padding */
00503 #define NET_IP_ALIGN 2
00504 
00505 #endif /* _VMXNET3_H */