iPXE
dmfe.c
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00001 /**************************************************************************
00002 *
00003 *    dmfe.c -- Etherboot device driver for the Davicom 
00004 *       DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast ethernet card
00005 *
00006 *    Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
00007 *
00008 *    This program is free software; you can redistribute it and/or modify
00009 *    it under the terms of the GNU General Public License as published by
00010 *    the Free Software Foundation; either version 2 of the License, or
00011 *    (at your option) any later version.
00012 *
00013 *    This program is distributed in the hope that it will be useful,
00014 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
00015 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00016 *    GNU General Public License for more details.
00017 *
00018 *    You should have received a copy of the GNU General Public License
00019 *    along with this program; if not, write to the Free Software
00020 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00021 *    02110-1301, USA.
00022 *
00023 *    Portions of this code based on:
00024 *
00025 *       dmfe.c:     A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 
00026 *               NIC fast ethernet driver for Linux.
00027 *       Copyright (C) 1997  Sten Wang
00028 *       (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
00029 *
00030 *
00031 *    REVISION HISTORY:
00032 *    ================
00033 *    v1.0       10-02-2004      timlegge        Boots ltsp needs cleanup 
00034 *
00035 *    Indent Options: indent -kr -i8
00036 *
00037 *
00038 ***************************************************************************/
00039 
00040 FILE_LICENCE ( GPL2_OR_LATER );
00041 
00042 /* to get some global routines like printf */
00043 #include "etherboot.h"
00044 /* to get the interface to the body of the program */
00045 #include "nic.h"
00046 /* to get the PCI support functions, if this is a PCI NIC */
00047 #include <ipxe/pci.h>
00048 #include <ipxe/ethernet.h>
00049 
00050 /* #define EDEBUG 1 */
00051 #ifdef EDEBUG
00052 #define dprintf(x) printf x
00053 #else
00054 #define dprintf(x)
00055 #endif
00056 
00057 /* Condensed operations for readability. */
00058 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
00059 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
00060 
00061 /* Board/System/Debug information/definition ---------------- */
00062 #define PCI_DM9132_ID   0x91321282      /* Davicom DM9132 ID */
00063 #define PCI_DM9102_ID   0x91021282      /* Davicom DM9102 ID */
00064 #define PCI_DM9100_ID   0x91001282      /* Davicom DM9100 ID */
00065 #define PCI_DM9009_ID   0x90091282      /* Davicom DM9009 ID */
00066 
00067 #define DM9102_IO_SIZE  0x80
00068 #define DM9102A_IO_SIZE 0x100
00069 #define TX_MAX_SEND_CNT 0x1     /* Maximum tx packet per time */
00070 #define TX_DESC_CNT     0x10    /* Allocated Tx descriptors */
00071 #define RX_DESC_CNT     0x20    /* Allocated Rx descriptors */
00072 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2)      /* Max TX packet count */
00073 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3)      /* TX wakeup count */
00074 #define DESC_ALL_CNT    (TX_DESC_CNT + RX_DESC_CNT)
00075 #define TX_BUF_ALLOC    0x600
00076 #define RX_ALLOC_SIZE   0x620
00077 #define DM910X_RESET    1
00078 #define CR0_DEFAULT     0x00E00000      /* TX & RX burst mode */
00079 #define CR6_DEFAULT     0x00080000      /* HD */
00080 #define CR7_DEFAULT     0x180c1
00081 #define CR15_DEFAULT    0x06    /* TxJabber RxWatchdog */
00082 #define TDES0_ERR_MASK  0x4302  /* TXJT, LC, EC, FUE */
00083 #define MAX_PACKET_SIZE 1514
00084 #define DMFE_MAX_MULTICAST 14
00085 #define RX_COPY_SIZE    100
00086 #define MAX_CHECK_PACKET 0x8000
00087 #define DM9801_NOISE_FLOOR 8
00088 #define DM9802_NOISE_FLOOR 5
00089 
00090 #define DMFE_10MHF      0
00091 #define DMFE_100MHF     1
00092 #define DMFE_10MFD      4
00093 #define DMFE_100MFD     5
00094 #define DMFE_AUTO       8
00095 #define DMFE_1M_HPNA    0x10
00096 
00097 #define DMFE_TXTH_72    0x400000        /* TX TH 72 byte */
00098 #define DMFE_TXTH_96    0x404000        /* TX TH 96 byte */
00099 #define DMFE_TXTH_128   0x0000  /* TX TH 128 byte */
00100 #define DMFE_TXTH_256   0x4000  /* TX TH 256 byte */
00101 #define DMFE_TXTH_512   0x8000  /* TX TH 512 byte */
00102 #define DMFE_TXTH_1K    0xC000  /* TX TH 1K  byte */
00103 
00104 #define DMFE_TIMER_WUT  (jiffies + HZ * 1)      /* timer wakeup time : 1 second */
00105 #define DMFE_TX_TIMEOUT ((3*HZ)/2)      /* tx packet time-out time 1.5 s" */
00106 #define DMFE_TX_KICK    (HZ/2)  /* tx packet Kick-out time 0.5 s" */
00107 
00108 #define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
00109 
00110 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
00111 
00112 
00113 /* CR9 definition: SROM/MII */
00114 #define CR9_SROM_READ   0x4800
00115 #define CR9_SRCS        0x1
00116 #define CR9_SRCLK       0x2
00117 #define CR9_CRDOUT      0x8
00118 #define SROM_DATA_0     0x0
00119 #define SROM_DATA_1     0x4
00120 #define PHY_DATA_1      0x20000
00121 #define PHY_DATA_0      0x00000
00122 #define MDCLKH          0x10000
00123 
00124 #define PHY_POWER_DOWN  0x800
00125 
00126 #define SROM_V41_CODE   0x14
00127 
00128 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
00129 
00130 #define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
00131 #define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
00132 
00133 /* Sten Check */
00134 #define DEVICE net_device
00135 
00136 /* Structure/enum declaration ------------------------------- */
00137 struct tx_desc {
00138         u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
00139         void * tx_buf_ptr;              /* Data for us */
00140         struct tx_desc * next_tx_desc;
00141 } __attribute__ ((aligned(32)));
00142 
00143 struct rx_desc {
00144         u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
00145         void * rx_skb_ptr;              /* Data for us */
00146         struct rx_desc * next_rx_desc;
00147 } __attribute__ ((aligned(32)));
00148 
00149 static struct dmfe_private {
00150         u32 chip_id;            /* Chip vendor/Device ID */
00151         u32 chip_revision;      /* Chip revision */
00152         u32 cr0_data;
00153 //      u32 cr5_data;
00154         u32 cr6_data;
00155         u32 cr7_data;
00156         u32 cr15_data;
00157 
00158         u16 HPNA_command;       /* For HPNA register 16 */
00159         u16 HPNA_timer;         /* For HPNA remote device check */
00160         u16 NIC_capability;     /* NIC media capability */
00161         u16 PHY_reg4;           /* Saved Phyxcer register 4 value */
00162 
00163         u8 HPNA_present;        /* 0:none, 1:DM9801, 2:DM9802 */
00164         u8 chip_type;           /* Keep DM9102A chip type */
00165         u8 media_mode;          /* user specify media mode */
00166         u8 op_mode;             /* real work media mode */
00167         u8 phy_addr;
00168         u8 dm910x_chk_mode;     /* Operating mode check */
00169 
00170         /* NIC SROM data */
00171         unsigned char srom[128];
00172         /* Etherboot Only */
00173         u8 cur_tx;
00174         u8 cur_rx;
00175 } dfx;
00176 
00177 static struct dmfe_private *db;
00178 
00179 enum dmfe_offsets {
00180         DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
00181         DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
00182         DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 =
00183             0x70,
00184         DCR15 = 0x78
00185 };
00186 
00187 enum dmfe_CR6_bits {
00188         CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
00189         CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
00190         CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
00191 };
00192 
00193 /* Global variable declaration ----------------------------- */
00194 static struct nic_operations dmfe_operations;
00195 
00196 static unsigned char dmfe_media_mode = DMFE_AUTO;
00197 static u32 dmfe_cr6_user_set;
00198 
00199 /* For module input parameter */
00200 static u8 chkmode = 1;
00201 static u8 HPNA_mode;            /* Default: Low Power/High Speed */
00202 static u8 HPNA_rx_cmd;          /* Default: Disable Rx remote command */
00203 static u8 HPNA_tx_cmd;          /* Default: Don't issue remote command */
00204 static u8 HPNA_NoiseFloor;      /* Default: HPNA NoiseFloor */
00205 static u8 SF_mode;              /* Special Function: 1:VLAN, 2:RX Flow Control
00206                                    4: TX pause packet */
00207 
00208 
00209 /**********************************************
00210 * Descriptor Ring and Buffer defination
00211 ***********************************************/
00212 struct {
00213         struct tx_desc txd[TX_DESC_CNT] __attribute__ ((aligned(32)));
00214         unsigned char txb[TX_BUF_ALLOC * TX_DESC_CNT]
00215         __attribute__ ((aligned(32)));
00216         struct rx_desc rxd[RX_DESC_CNT] __attribute__ ((aligned(32)));
00217         unsigned char rxb[RX_ALLOC_SIZE * RX_DESC_CNT]
00218         __attribute__ ((aligned(32)));
00219 } dmfe_bufs __shared;
00220 #define txd dmfe_bufs.txd
00221 #define txb dmfe_bufs.txb
00222 #define rxd dmfe_bufs.rxd
00223 #define rxb dmfe_bufs.rxb
00224 
00225 /* NIC specific static variables go here */
00226 static long int BASE;
00227 
00228 static u16 read_srom_word(long ioaddr, int offset);
00229 static void dmfe_init_dm910x(struct nic *nic);
00230 static void dmfe_descriptor_init(struct nic *, unsigned long ioaddr);
00231 static void update_cr6(u32, unsigned long);
00232 static void send_filter_frame(struct nic *nic);
00233 static void dm9132_id_table(struct nic *nic);
00234 
00235 static u16 phy_read(unsigned long, u8, u8, u32);
00236 static void phy_write(unsigned long, u8, u8, u16, u32);
00237 static void phy_write_1bit(unsigned long, u32);
00238 static u16 phy_read_1bit(unsigned long);
00239 static void dmfe_set_phyxcer(struct nic *nic);
00240 
00241 static void dmfe_parse_srom(struct nic *nic);
00242 static void dmfe_program_DM9801(struct nic *nic, int);
00243 static void dmfe_program_DM9802(struct nic *nic);
00244 
00245 static void dmfe_reset(struct nic *nic)
00246 {
00247         /* system variable init */
00248         db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
00249 
00250         db->NIC_capability = 0xf;       /* All capability */
00251         db->PHY_reg4 = 0x1e0;
00252 
00253         /* CR6 operation mode decision */
00254         if (!chkmode || (db->chip_id == PCI_DM9132_ID) ||
00255             (db->chip_revision >= 0x02000030)) {
00256                 db->cr6_data |= DMFE_TXTH_256;
00257                 db->cr0_data = CR0_DEFAULT;
00258                 db->dm910x_chk_mode = 4;        /* Enter the normal mode */
00259         } else {
00260                 db->cr6_data |= CR6_SFT;        /* Store & Forward mode */
00261                 db->cr0_data = 0;
00262                 db->dm910x_chk_mode = 1;        /* Enter the check mode */
00263         }
00264         /* Initialize DM910X board */
00265         dmfe_init_dm910x(nic);
00266 
00267         return;
00268 }
00269 
00270 /*      Initialize DM910X board
00271  *      Reset DM910X board
00272  *      Initialize TX/Rx descriptor chain structure
00273  *      Send the set-up frame
00274  *      Enable Tx/Rx machine
00275  */
00276 
00277 static void dmfe_init_dm910x(struct nic *nic)
00278 {
00279         unsigned long ioaddr = BASE;
00280 
00281         /* Reset DM910x MAC controller */
00282         outl(DM910X_RESET, ioaddr + DCR0);      /* RESET MAC */
00283         udelay(100);
00284         outl(db->cr0_data, ioaddr + DCR0);
00285         udelay(5);
00286 
00287         /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
00288         db->phy_addr = 1;
00289 
00290         /* Parser SROM and media mode */
00291         dmfe_parse_srom(nic);
00292         db->media_mode = dmfe_media_mode;
00293 
00294         /* RESET Phyxcer Chip by GPR port bit 7 */
00295         outl(0x180, ioaddr + DCR12);    /* Let bit 7 output port */
00296         if (db->chip_id == PCI_DM9009_ID) {
00297                 outl(0x80, ioaddr + DCR12);     /* Issue RESET signal */
00298                 mdelay(300);    /* Delay 300 ms */
00299         }
00300         outl(0x0, ioaddr + DCR12);      /* Clear RESET signal */
00301 
00302         /* Process Phyxcer Media Mode */
00303         if (!(db->media_mode & 0x10))   /* Force 1M mode */
00304                 dmfe_set_phyxcer(nic);
00305 
00306         /* Media Mode Process */
00307         if (!(db->media_mode & DMFE_AUTO))
00308                 db->op_mode = db->media_mode;   /* Force Mode */
00309 
00310         /* Initiliaze Transmit/Receive descriptor and CR3/4 */
00311         dmfe_descriptor_init(nic, ioaddr);
00312 
00313         /* tx descriptor start pointer */
00314         outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
00315 
00316         /* rx descriptor start pointer */
00317         outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
00318 
00319         /* Init CR6 to program DM910x operation */
00320         update_cr6(db->cr6_data, ioaddr);
00321 
00322         /* Send setup frame */
00323         if (db->chip_id == PCI_DM9132_ID) {
00324                 dm9132_id_table(nic);   /* DM9132 */
00325         } else {
00326                 send_filter_frame(nic); /* DM9102/DM9102A */
00327         }
00328 
00329         /* Init CR7, interrupt active bit */
00330         db->cr7_data = CR7_DEFAULT;
00331         outl(db->cr7_data, ioaddr + DCR7);
00332         /* Init CR15, Tx jabber and Rx watchdog timer */
00333         outl(db->cr15_data, ioaddr + DCR15);
00334         /* Enable DM910X Tx/Rx function */
00335         db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
00336         update_cr6(db->cr6_data, ioaddr);
00337 }
00338 #ifdef EDEBUG
00339 void hex_dump(const char *data, const unsigned int len);
00340 #endif
00341 /**************************************************************************
00342 POLL - Wait for a frame
00343 ***************************************************************************/
00344 static int dmfe_poll(struct nic *nic, int retrieve)
00345 {
00346         u32 rdes0;
00347         int entry = db->cur_rx % RX_DESC_CNT;
00348         int rxlen;
00349         rdes0 = le32_to_cpu(rxd[entry].rdes0);
00350         if (rdes0 & 0x80000000)
00351                 return 0;
00352 
00353         if (!retrieve)
00354                 return 1;
00355 
00356         if ((rdes0 & 0x300) != 0x300) {
00357                 /* A packet without First/Last flag */
00358                 printf("strange Packet\n");
00359                 rxd[entry].rdes0 = cpu_to_le32(0x80000000);
00360                 return 0;
00361         } else {
00362                 /* A packet with First/Last flag */
00363                 rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
00364                 /* error summary bit check */
00365                 if (rdes0 & 0x8000) {
00366                         printf("Error\n");
00367                         return 0;
00368                 }
00369                 if (!(rdes0 & 0x8000) ||
00370                     ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
00371                         if (db->dm910x_chk_mode & 1)
00372                                 printf("Silly check mode\n");
00373 
00374                         nic->packetlen = rxlen;
00375                         memcpy(nic->packet, rxb + (entry * RX_ALLOC_SIZE),
00376                                nic->packetlen);
00377                 }
00378         }
00379         rxd[entry].rdes0 = cpu_to_le32(0x80000000);
00380         db->cur_rx++;
00381         return 1;
00382 }
00383 
00384 static void dmfe_irq(struct nic *nic __unused, irq_action_t action __unused)
00385 {
00386         switch ( action ) {
00387                 case DISABLE :
00388                         break;
00389                 case ENABLE :
00390                         break;
00391                 case FORCE :
00392                         break;
00393         }
00394 }
00395 
00396 /**************************************************************************
00397 TRANSMIT - Transmit a frame
00398 ***************************************************************************/
00399 static void dmfe_transmit(struct nic *nic, 
00400         const char *dest,       /* Destination */
00401         unsigned int type,      /* Type */
00402         unsigned int size,      /* size */
00403         const char *packet)     /* Packet */
00404 {       
00405         u16 nstype;
00406         u8 *ptxb;
00407 
00408         ptxb = &txb[db->cur_tx];
00409 
00410         /* Stop Tx */
00411         outl(0, BASE + DCR7);
00412         memcpy(ptxb, dest, ETH_ALEN);
00413         memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
00414         nstype = htons((u16) type);
00415         memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
00416         memcpy(ptxb + ETH_HLEN, packet, size);
00417 
00418         size += ETH_HLEN;
00419         while (size < ETH_ZLEN)
00420                 ptxb[size++] = '\0';
00421 
00422         /* setup the transmit descriptor */
00423         txd[db->cur_tx].tdes1 = cpu_to_le32(0xe1000000 | size);
00424         txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);        /* give ownership to device */
00425 
00426         /* immediate transmit demand */
00427         outl(0x1, BASE + DCR1);
00428         outl(db->cr7_data, BASE + DCR7);
00429 
00430         /* Point to next TX descriptor */
00431         db->cur_tx++;
00432         db->cur_tx = db->cur_tx % TX_DESC_CNT;
00433 }
00434 
00435 /**************************************************************************
00436 DISABLE - Turn off ethernet interface
00437 ***************************************************************************/
00438 static void dmfe_disable ( struct nic *nic __unused ) {
00439         /* Reset & stop DM910X board */
00440         outl(DM910X_RESET, BASE + DCR0);
00441         udelay(5);
00442         phy_write(BASE, db->phy_addr, 0, 0x8000, db->chip_id);
00443 
00444 }
00445 
00446 /**************************************************************************
00447 PROBE - Look for an adapter, this routine's visible to the outside
00448 ***************************************************************************/
00449 
00450 #define board_found 1
00451 #define valid_link 0
00452 static int dmfe_probe ( struct nic *nic, struct pci_device *pci ) {
00453 
00454         uint32_t dev_rev, pci_pmr;
00455         int i;
00456 
00457         if (pci->ioaddr == 0)
00458                 return 0;
00459 
00460         BASE = pci->ioaddr;
00461         printf("dmfe.c: Found %s Vendor=0x%hX Device=0x%hX\n",
00462                pci->id->name, pci->vendor, pci->device);
00463 
00464         /* Read Chip revision */
00465         pci_read_config_dword(pci, PCI_REVISION, &dev_rev);
00466         dprintf(("Revision %lX\n", dev_rev));
00467 
00468         /* point to private storage */
00469         db = &dfx;
00470 
00471         db->chip_id = ((u32) pci->device << 16) | pci->vendor;
00472         BASE = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
00473         db->chip_revision = dev_rev;
00474 
00475         pci_read_config_dword(pci, 0x50, &pci_pmr);
00476         pci_pmr &= 0x70000;
00477         if ((pci_pmr == 0x10000) && (dev_rev == 0x02000031))
00478                 db->chip_type = 1;      /* DM9102A E3 */
00479         else
00480                 db->chip_type = 0;
00481 
00482         dprintf(("Chip type : %d\n", db->chip_type));
00483 
00484         /* read 64 word srom data */
00485         for (i = 0; i < 64; i++)
00486                 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(BASE, i));
00487 
00488         /* Set Node address */
00489         for (i = 0; i < 6; i++)
00490                 nic->node_addr[i] = db->srom[20 + i];
00491 
00492         /* Print out some hardware info */
00493         DBG ( "%s: %s at ioaddr %4.4lx\n",
00494               pci->id->name, eth_ntoa ( nic->node_addr ), BASE );
00495 
00496         /* Set the card as PCI Bus Master */
00497         adjust_pci_device(pci);
00498 
00499         dmfe_reset(nic);
00500 
00501         nic->irqno  = 0;
00502         nic->ioaddr = pci->ioaddr;
00503 
00504         /* point to NIC specific routines */
00505         nic->nic_op     = &dmfe_operations;
00506 
00507         return 1;
00508 }
00509 
00510 /*
00511  *      Initialize transmit/Receive descriptor
00512  *      Using Chain structure, and allocate Tx/Rx buffer
00513  */
00514 
00515 static void dmfe_descriptor_init(struct nic *nic __unused, unsigned long ioaddr)
00516 {
00517         int i;
00518         db->cur_tx = 0;
00519         db->cur_rx = 0;
00520 
00521         /* tx descriptor start pointer */
00522         outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
00523 
00524         /* rx descriptor start pointer */
00525         outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
00526 
00527         /* Init Transmit chain */
00528         for (i = 0; i < TX_DESC_CNT; i++) {
00529                 txd[i].tx_buf_ptr = &txb[i];
00530                 txd[i].tdes0 = cpu_to_le32(0);
00531                 txd[i].tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
00532                 txd[i].tdes2 = cpu_to_le32(virt_to_bus(&txb[i]));
00533                 txd[i].tdes3 = cpu_to_le32(virt_to_bus(&txd[i + 1]));
00534                 txd[i].next_tx_desc = &txd[i + 1];
00535         }
00536         /* Mark the last entry as wrapping the ring */
00537         txd[i - 1].tdes3 = virt_to_le32desc(&txd[0]);
00538         txd[i - 1].next_tx_desc = &txd[0];
00539 
00540         /* receive descriptor chain */
00541         for (i = 0; i < RX_DESC_CNT; i++) {
00542                 rxd[i].rx_skb_ptr = &rxb[i * RX_ALLOC_SIZE];
00543                 rxd[i].rdes0 = cpu_to_le32(0x80000000);
00544                 rxd[i].rdes1 = cpu_to_le32(0x01000600);
00545                 rxd[i].rdes2 =
00546                     cpu_to_le32(virt_to_bus(&rxb[i * RX_ALLOC_SIZE]));
00547                 rxd[i].rdes3 = cpu_to_le32(virt_to_bus(&rxd[i + 1]));
00548                 rxd[i].next_rx_desc = &rxd[i + 1];
00549         }
00550         /* Mark the last entry as wrapping the ring */
00551         rxd[i - 1].rdes3 = cpu_to_le32(virt_to_bus(&rxd[0]));
00552         rxd[i - 1].next_rx_desc = &rxd[0];
00553 
00554 }
00555 
00556 /*
00557  *      Update CR6 value
00558  *      Firstly stop DM910X , then written value and start
00559  */
00560 
00561 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
00562 {
00563         u32 cr6_tmp;
00564 
00565         cr6_tmp = cr6_data & ~0x2002;   /* stop Tx/Rx */
00566         outl(cr6_tmp, ioaddr + DCR6);
00567         udelay(5);
00568         outl(cr6_data, ioaddr + DCR6);
00569         udelay(5);
00570 }
00571 
00572 
00573 /*
00574  *      Send a setup frame for DM9132
00575  *      This setup frame initialize DM910X address filter mode
00576 */
00577 
00578 static void dm9132_id_table(struct nic *nic __unused)
00579 {
00580 #ifdef LINUX
00581         u16 *addrptr;
00582         u8 dmi_addr[8];
00583         unsigned long ioaddr = BASE + 0xc0;     /* ID Table */
00584         u32 hash_val;
00585         u16 i, hash_table[4];
00586 #endif
00587         dprintf(("dm9132_id_table\n"));
00588 
00589         printf("FIXME: This function is broken.  If you have this card contact "
00590                 "Timothy Legge at the etherboot-user list\n");
00591 
00592 #ifdef LINUX
00593         //DMFE_DBUG(0, "dm9132_id_table()", 0);
00594 
00595         /* Node address */
00596         addrptr = (u16 *) nic->node_addr;
00597         outw(addrptr[0], ioaddr);
00598         ioaddr += 4;
00599         outw(addrptr[1], ioaddr);
00600         ioaddr += 4;
00601         outw(addrptr[2], ioaddr);
00602         ioaddr += 4;
00603 
00604         /* Clear Hash Table */
00605         for (i = 0; i < 4; i++)
00606                 hash_table[i] = 0x0;
00607 
00608         /* broadcast address */
00609         hash_table[3] = 0x8000;
00610 
00611         /* the multicast address in Hash Table : 64 bits */
00612         for (mcptr = mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
00613                 hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
00614                 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
00615         }
00616 
00617         /* Write the hash table to MAC MD table */
00618         for (i = 0; i < 4; i++, ioaddr += 4)
00619                 outw(hash_table[i], ioaddr);
00620 #endif
00621 }
00622 
00623 
00624 /*
00625  *      Send a setup frame for DM9102/DM9102A
00626  *      This setup frame initialize DM910X address filter mode
00627  */
00628 
00629 static void send_filter_frame(struct nic *nic)
00630 {
00631 
00632         u8 *ptxb;
00633         int i;
00634 
00635         dprintf(("send_filter_frame\n"));
00636         /* point to the current txb incase multiple tx_rings are used */
00637         ptxb = &txb[db->cur_tx];
00638 
00639         /* construct perfect filter frame with mac address as first match
00640            and broadcast address for all others */
00641         for (i = 0; i < 192; i++)
00642                 ptxb[i] = 0xFF;
00643         ptxb[0] = nic->node_addr[0];
00644         ptxb[1] = nic->node_addr[1];
00645         ptxb[4] = nic->node_addr[2];
00646         ptxb[5] = nic->node_addr[3];
00647         ptxb[8] = nic->node_addr[4];
00648         ptxb[9] = nic->node_addr[5];
00649 
00650         /* prepare the setup frame */
00651         txd[db->cur_tx].tdes1 = cpu_to_le32(0x890000c0);
00652         txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);
00653         update_cr6(db->cr6_data | 0x2000, BASE);
00654         outl(0x1, BASE + DCR1); /* Issue Tx polling */
00655         update_cr6(db->cr6_data, BASE);
00656         db->cur_tx++;
00657 }
00658 
00659 /*
00660  *      Read one word data from the serial ROM
00661  */
00662 
00663 static u16 read_srom_word(long ioaddr, int offset)
00664 {
00665         int i;
00666         u16 srom_data = 0;
00667         long cr9_ioaddr = ioaddr + DCR9;
00668 
00669         outl(CR9_SROM_READ, cr9_ioaddr);
00670         outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
00671 
00672         /* Send the Read Command 110b */
00673         SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
00674         SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
00675         SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
00676 
00677         /* Send the offset */
00678         for (i = 5; i >= 0; i--) {
00679                 srom_data =
00680                     (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
00681                 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
00682         }
00683 
00684         outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
00685 
00686         for (i = 16; i > 0; i--) {
00687                 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
00688                 udelay(5);
00689                 srom_data =
00690                     (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1
00691                                         : 0);
00692                 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
00693                 udelay(5);
00694         }
00695 
00696         outl(CR9_SROM_READ, cr9_ioaddr);
00697         return srom_data;
00698 }
00699 
00700 
00701 /*
00702  *      Auto sense the media mode
00703  */
00704 
00705 #if 0 /* not used */
00706 static u8 dmfe_sense_speed(struct nic *nic __unused)
00707 {
00708         u8 ErrFlag = 0;
00709         u16 phy_mode;
00710 
00711         /* CR6 bit18=0, select 10/100M */
00712         update_cr6((db->cr6_data & ~0x40000), BASE);
00713 
00714         phy_mode = phy_read(BASE, db->phy_addr, 1, db->chip_id);
00715         phy_mode = phy_read(BASE, db->phy_addr, 1, db->chip_id);
00716 
00717         if ((phy_mode & 0x24) == 0x24) {
00718                 if (db->chip_id == PCI_DM9132_ID)       /* DM9132 */
00719                         phy_mode =
00720                             phy_read(BASE, db->phy_addr, 7,
00721                                      db->chip_id) & 0xf000;
00722                 else            /* DM9102/DM9102A */
00723                         phy_mode =
00724                             phy_read(BASE, db->phy_addr, 17,
00725                                      db->chip_id) & 0xf000;
00726                 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
00727                 switch (phy_mode) {
00728                 case 0x1000:
00729                         db->op_mode = DMFE_10MHF;
00730                         break;
00731                 case 0x2000:
00732                         db->op_mode = DMFE_10MFD;
00733                         break;
00734                 case 0x4000:
00735                         db->op_mode = DMFE_100MHF;
00736                         break;
00737                 case 0x8000:
00738                         db->op_mode = DMFE_100MFD;
00739                         break;
00740                 default:
00741                         db->op_mode = DMFE_10MHF;
00742                         ErrFlag = 1;
00743                         break;
00744                 }
00745         } else {
00746                 db->op_mode = DMFE_10MHF;
00747                 //DMFE_DBUG(0, "Link Failed :", phy_mode);
00748                 ErrFlag = 1;
00749         }
00750 
00751         return ErrFlag;
00752 }
00753 #endif
00754 
00755 /*
00756  *      Set 10/100 phyxcer capability
00757  *      AUTO mode : phyxcer register4 is NIC capability
00758  *      Force mode: phyxcer register4 is the force media
00759  */
00760 
00761 static void dmfe_set_phyxcer(struct nic *nic __unused)
00762 {
00763         u16 phy_reg;
00764 
00765         /* Select 10/100M phyxcer */
00766         db->cr6_data &= ~0x40000;
00767         update_cr6(db->cr6_data, BASE);
00768 
00769         /* DM9009 Chip: Phyxcer reg18 bit12=0 */
00770         if (db->chip_id == PCI_DM9009_ID) {
00771                 phy_reg =
00772                     phy_read(BASE, db->phy_addr, 18,
00773                              db->chip_id) & ~0x1000;
00774                 phy_write(BASE, db->phy_addr, 18, phy_reg, db->chip_id);
00775         }
00776 
00777         /* Phyxcer capability setting */
00778         phy_reg = phy_read(BASE, db->phy_addr, 4, db->chip_id) & ~0x01e0;
00779 
00780         if (db->media_mode & DMFE_AUTO) {
00781                 /* AUTO Mode */
00782                 phy_reg |= db->PHY_reg4;
00783         } else {
00784                 /* Force Mode */
00785                 switch (db->media_mode) {
00786                 case DMFE_10MHF:
00787                         phy_reg |= 0x20;
00788                         break;
00789                 case DMFE_10MFD:
00790                         phy_reg |= 0x40;
00791                         break;
00792                 case DMFE_100MHF:
00793                         phy_reg |= 0x80;
00794                         break;
00795                 case DMFE_100MFD:
00796                         phy_reg |= 0x100;
00797                         break;
00798                 }
00799                 if (db->chip_id == PCI_DM9009_ID)
00800                         phy_reg &= 0x61;
00801         }
00802 
00803         /* Write new capability to Phyxcer Reg4 */
00804         if (!(phy_reg & 0x01e0)) {
00805                 phy_reg |= db->PHY_reg4;
00806                 db->media_mode |= DMFE_AUTO;
00807         }
00808         phy_write(BASE, db->phy_addr, 4, phy_reg, db->chip_id);
00809 
00810         /* Restart Auto-Negotiation */
00811         if (db->chip_type && (db->chip_id == PCI_DM9102_ID))
00812                 phy_write(BASE, db->phy_addr, 0, 0x1800, db->chip_id);
00813         if (!db->chip_type)
00814                 phy_write(BASE, db->phy_addr, 0, 0x1200, db->chip_id);
00815 }
00816 
00817 
00818 /*
00819  *      Process op-mode
00820  *      AUTO mode : PHY controller in Auto-negotiation Mode
00821  *      Force mode: PHY controller in force mode with HUB
00822  *                      N-way force capability with SWITCH
00823  */
00824 
00825 #if 0 /* not used */
00826 static void dmfe_process_mode(struct nic *nic __unused)
00827 {
00828         u16 phy_reg;
00829 
00830         /* Full Duplex Mode Check */
00831         if (db->op_mode & 0x4)
00832                 db->cr6_data |= CR6_FDM;        /* Set Full Duplex Bit */
00833         else
00834                 db->cr6_data &= ~CR6_FDM;       /* Clear Full Duplex Bit */
00835 
00836         /* Transciver Selection */
00837         if (db->op_mode & 0x10) /* 1M HomePNA */
00838                 db->cr6_data |= 0x40000;        /* External MII select */
00839         else
00840                 db->cr6_data &= ~0x40000;       /* Internal 10/100 transciver */
00841 
00842         update_cr6(db->cr6_data, BASE);
00843 
00844         /* 10/100M phyxcer force mode need */
00845         if (!(db->media_mode & 0x18)) {
00846                 /* Forece Mode */
00847                 phy_reg = phy_read(BASE, db->phy_addr, 6, db->chip_id);
00848                 if (!(phy_reg & 0x1)) {
00849                         /* parter without N-Way capability */
00850                         phy_reg = 0x0;
00851                         switch (db->op_mode) {
00852                         case DMFE_10MHF:
00853                                 phy_reg = 0x0;
00854                                 break;
00855                         case DMFE_10MFD:
00856                                 phy_reg = 0x100;
00857                                 break;
00858                         case DMFE_100MHF:
00859                                 phy_reg = 0x2000;
00860                                 break;
00861                         case DMFE_100MFD:
00862                                 phy_reg = 0x2100;
00863                                 break;
00864                         }
00865                         phy_write(BASE, db->phy_addr, 0, phy_reg,
00866                                   db->chip_id);
00867                         if (db->chip_type
00868                             && (db->chip_id == PCI_DM9102_ID))
00869                                 mdelay(20);
00870                         phy_write(BASE, db->phy_addr, 0, phy_reg,
00871                                   db->chip_id);
00872                 }
00873         }
00874 }
00875 #endif
00876 
00877 /*
00878  *      Write a word to Phy register
00879  */
00880 
00881 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
00882                       u16 phy_data, u32 chip_id)
00883 {
00884         u16 i;
00885         unsigned long ioaddr;
00886 
00887         if (chip_id == PCI_DM9132_ID) {
00888                 ioaddr = iobase + 0x80 + offset * 4;
00889                 outw(phy_data, ioaddr);
00890         } else {
00891                 /* DM9102/DM9102A Chip */
00892                 ioaddr = iobase + DCR9;
00893 
00894                 /* Send 33 synchronization clock to Phy controller */
00895                 for (i = 0; i < 35; i++)
00896                         phy_write_1bit(ioaddr, PHY_DATA_1);
00897 
00898                 /* Send start command(01) to Phy */
00899                 phy_write_1bit(ioaddr, PHY_DATA_0);
00900                 phy_write_1bit(ioaddr, PHY_DATA_1);
00901 
00902                 /* Send write command(01) to Phy */
00903                 phy_write_1bit(ioaddr, PHY_DATA_0);
00904                 phy_write_1bit(ioaddr, PHY_DATA_1);
00905 
00906                 /* Send Phy address */
00907                 for (i = 0x10; i > 0; i = i >> 1)
00908                         phy_write_1bit(ioaddr,
00909                                        phy_addr & i ? PHY_DATA_1 :
00910                                        PHY_DATA_0);
00911 
00912                 /* Send register address */
00913                 for (i = 0x10; i > 0; i = i >> 1)
00914                         phy_write_1bit(ioaddr,
00915                                        offset & i ? PHY_DATA_1 :
00916                                        PHY_DATA_0);
00917 
00918                 /* written trasnition */
00919                 phy_write_1bit(ioaddr, PHY_DATA_1);
00920                 phy_write_1bit(ioaddr, PHY_DATA_0);
00921 
00922                 /* Write a word data to PHY controller */
00923                 for (i = 0x8000; i > 0; i >>= 1)
00924                         phy_write_1bit(ioaddr,
00925                                        phy_data & i ? PHY_DATA_1 :
00926                                        PHY_DATA_0);
00927         }
00928 }
00929 
00930 
00931 /*
00932  *      Read a word data from phy register
00933  */
00934 
00935 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
00936                     u32 chip_id)
00937 {
00938         int i;
00939         u16 phy_data;
00940         unsigned long ioaddr;
00941 
00942         if (chip_id == PCI_DM9132_ID) {
00943                 /* DM9132 Chip */
00944                 ioaddr = iobase + 0x80 + offset * 4;
00945                 phy_data = inw(ioaddr);
00946         } else {
00947                 /* DM9102/DM9102A Chip */
00948                 ioaddr = iobase + DCR9;
00949 
00950                 /* Send 33 synchronization clock to Phy controller */
00951                 for (i = 0; i < 35; i++)
00952                         phy_write_1bit(ioaddr, PHY_DATA_1);
00953 
00954                 /* Send start command(01) to Phy */
00955                 phy_write_1bit(ioaddr, PHY_DATA_0);
00956                 phy_write_1bit(ioaddr, PHY_DATA_1);
00957 
00958                 /* Send read command(10) to Phy */
00959                 phy_write_1bit(ioaddr, PHY_DATA_1);
00960                 phy_write_1bit(ioaddr, PHY_DATA_0);
00961 
00962                 /* Send Phy address */
00963                 for (i = 0x10; i > 0; i = i >> 1)
00964                         phy_write_1bit(ioaddr,
00965                                        phy_addr & i ? PHY_DATA_1 :
00966                                        PHY_DATA_0);
00967 
00968                 /* Send register address */
00969                 for (i = 0x10; i > 0; i = i >> 1)
00970                         phy_write_1bit(ioaddr,
00971                                        offset & i ? PHY_DATA_1 :
00972                                        PHY_DATA_0);
00973 
00974                 /* Skip transition state */
00975                 phy_read_1bit(ioaddr);
00976 
00977                 /* read 16bit data */
00978                 for (phy_data = 0, i = 0; i < 16; i++) {
00979                         phy_data <<= 1;
00980                         phy_data |= phy_read_1bit(ioaddr);
00981                 }
00982         }
00983 
00984         return phy_data;
00985 }
00986 
00987 
00988 /*
00989  *      Write one bit data to Phy Controller
00990  */
00991 
00992 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
00993 {
00994         outl(phy_data, ioaddr); /* MII Clock Low */
00995         udelay(1);
00996         outl(phy_data | MDCLKH, ioaddr);        /* MII Clock High */
00997         udelay(1);
00998         outl(phy_data, ioaddr); /* MII Clock Low */
00999         udelay(1);
01000 }
01001 
01002 
01003 /*
01004  *      Read one bit phy data from PHY controller
01005  */
01006 
01007 static u16 phy_read_1bit(unsigned long ioaddr)
01008 {
01009         u16 phy_data;
01010 
01011         outl(0x50000, ioaddr);
01012         udelay(1);
01013         phy_data = (inl(ioaddr) >> 19) & 0x1;
01014         outl(0x40000, ioaddr);
01015         udelay(1);
01016 
01017         return phy_data;
01018 }
01019 
01020 
01021 /*
01022  *      Parser SROM and media mode
01023  */
01024 
01025 static void dmfe_parse_srom(struct nic *nic)
01026 {
01027         unsigned char *srom = db->srom;
01028         int dmfe_mode, tmp_reg;
01029 
01030         /* Init CR15 */
01031         db->cr15_data = CR15_DEFAULT;
01032 
01033         /* Check SROM Version */
01034         if (((int) srom[18] & 0xff) == SROM_V41_CODE) {
01035                 /* SROM V4.01 */
01036                 /* Get NIC support media mode */
01037                 db->NIC_capability = *(u16 *) (srom + 34);
01038                 db->PHY_reg4 = 0;
01039                 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
01040                         switch (db->NIC_capability & tmp_reg) {
01041                         case 0x1:
01042                                 db->PHY_reg4 |= 0x0020;
01043                                 break;
01044                         case 0x2:
01045                                 db->PHY_reg4 |= 0x0040;
01046                                 break;
01047                         case 0x4:
01048                                 db->PHY_reg4 |= 0x0080;
01049                                 break;
01050                         case 0x8:
01051                                 db->PHY_reg4 |= 0x0100;
01052                                 break;
01053                         }
01054                 }
01055 
01056                 /* Media Mode Force or not check */
01057                 dmfe_mode = *((int *) srom + 34) & *((int *) srom + 36);
01058                 switch (dmfe_mode) {
01059                 case 0x4:
01060                         dmfe_media_mode = DMFE_100MHF;
01061                         break;  /* 100MHF */
01062                 case 0x2:
01063                         dmfe_media_mode = DMFE_10MFD;
01064                         break;  /* 10MFD */
01065                 case 0x8:
01066                         dmfe_media_mode = DMFE_100MFD;
01067                         break;  /* 100MFD */
01068                 case 0x100:
01069                 case 0x200:
01070                         dmfe_media_mode = DMFE_1M_HPNA;
01071                         break;  /* HomePNA */
01072                 }
01073 
01074                 /* Special Function setting */
01075                 /* VLAN function */
01076                 if ((SF_mode & 0x1) || (srom[43] & 0x80))
01077                         db->cr15_data |= 0x40;
01078 
01079                 /* Flow Control */
01080                 if ((SF_mode & 0x2) || (srom[40] & 0x1))
01081                         db->cr15_data |= 0x400;
01082 
01083                 /* TX pause packet */
01084                 if ((SF_mode & 0x4) || (srom[40] & 0xe))
01085                         db->cr15_data |= 0x9800;
01086         }
01087 
01088         /* Parse HPNA parameter */
01089         db->HPNA_command = 1;
01090 
01091         /* Accept remote command or not */
01092         if (HPNA_rx_cmd == 0)
01093                 db->HPNA_command |= 0x8000;
01094 
01095         /* Issue remote command & operation mode */
01096         if (HPNA_tx_cmd == 1)
01097                 switch (HPNA_mode) {    /* Issue Remote Command */
01098                 case 0:
01099                         db->HPNA_command |= 0x0904;
01100                         break;
01101                 case 1:
01102                         db->HPNA_command |= 0x0a00;
01103                         break;
01104                 case 2:
01105                         db->HPNA_command |= 0x0506;
01106                         break;
01107                 case 3:
01108                         db->HPNA_command |= 0x0602;
01109                         break;
01110         } else
01111                 switch (HPNA_mode) {    /* Don't Issue */
01112                 case 0:
01113                         db->HPNA_command |= 0x0004;
01114                         break;
01115                 case 1:
01116                         db->HPNA_command |= 0x0000;
01117                         break;
01118                 case 2:
01119                         db->HPNA_command |= 0x0006;
01120                         break;
01121                 case 3:
01122                         db->HPNA_command |= 0x0002;
01123                         break;
01124                 }
01125 
01126         /* Check DM9801 or DM9802 present or not */
01127         db->HPNA_present = 0;
01128         update_cr6(db->cr6_data | 0x40000, BASE);
01129         tmp_reg = phy_read(BASE, db->phy_addr, 3, db->chip_id);
01130         if ((tmp_reg & 0xfff0) == 0xb900) {
01131                 /* DM9801 or DM9802 present */
01132                 db->HPNA_timer = 8;
01133                 if (phy_read(BASE, db->phy_addr, 31, db->chip_id) ==
01134                     0x4404) {
01135                         /* DM9801 HomeRun */
01136                         db->HPNA_present = 1;
01137                         dmfe_program_DM9801(nic, tmp_reg);
01138                 } else {
01139                         /* DM9802 LongRun */
01140                         db->HPNA_present = 2;
01141                         dmfe_program_DM9802(nic);
01142                 }
01143         }
01144 
01145 }
01146 
01147 /*
01148  *      Init HomeRun DM9801
01149  */
01150 
01151 static void dmfe_program_DM9801(struct nic *nic __unused, int HPNA_rev)
01152 {
01153         u32 reg17, reg25;
01154 
01155         if (!HPNA_NoiseFloor)
01156                 HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
01157         switch (HPNA_rev) {
01158         case 0xb900:            /* DM9801 E3 */
01159                 db->HPNA_command |= 0x1000;
01160                 reg25 = phy_read(BASE, db->phy_addr, 24, db->chip_id);
01161                 reg25 = ((reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
01162                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
01163                 break;
01164         case 0xb901:            /* DM9801 E4 */
01165                 reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
01166                 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
01167                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
01168                 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
01169                 break;
01170         case 0xb902:            /* DM9801 E5 */
01171         case 0xb903:            /* DM9801 E6 */
01172         default:
01173                 db->HPNA_command |= 0x1000;
01174                 reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
01175                 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
01176                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
01177                 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
01178                 break;
01179         }
01180         phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id);
01181         phy_write(BASE, db->phy_addr, 17, reg17, db->chip_id);
01182         phy_write(BASE, db->phy_addr, 25, reg25, db->chip_id);
01183 }
01184 
01185 
01186 /*
01187  *      Init HomeRun DM9802
01188  */
01189 
01190 static void dmfe_program_DM9802(struct nic *nic __unused)
01191 {
01192         u32 phy_reg;
01193 
01194         if (!HPNA_NoiseFloor)
01195                 HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
01196         phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id);
01197         phy_reg = phy_read(BASE, db->phy_addr, 25, db->chip_id);
01198         phy_reg = (phy_reg & 0xff00) + HPNA_NoiseFloor;
01199         phy_write(BASE, db->phy_addr, 25, phy_reg, db->chip_id);
01200 }
01201 
01202 static struct nic_operations dmfe_operations = {
01203         .connect        = dummy_connect,
01204         .poll           = dmfe_poll,
01205         .transmit       = dmfe_transmit,
01206         .irq            = dmfe_irq,
01207 
01208 };
01209 
01210 static struct pci_device_id dmfe_nics[] = {
01211         PCI_ROM(0x1282, 0x9100, "dmfe9100", "Davicom 9100", 0),
01212         PCI_ROM(0x1282, 0x9102, "dmfe9102", "Davicom 9102", 0),
01213         PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0),
01214         PCI_ROM(0x1282, 0x9132, "dmfe9132", "Davicom 9132", 0), /* Needs probably some fixing */
01215 };
01216 
01217 PCI_DRIVER ( dmfe_driver, dmfe_nics, PCI_NO_CLASS );
01218 
01219 DRIVER ( "DMFE/PCI", nic_driver, pci_driver, dmfe_driver,
01220          dmfe_probe, dmfe_disable );
01221 
01222 /*
01223  * Local variables:
01224  *  c-basic-offset: 8
01225  *  c-indent-level: 8
01226  *  tab-width: 8
01227  * End:
01228  */