iPXE
3c509.h
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1 /*
2  * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are
6  * met: 1. Redistributions of source code must retain the above copyright
7  * notice, this list of conditions and the following disclaimer. 2. The name
8  * of the author may not be used to endorse or promote products derived from
9  * this software withough specific prior written permission
10  *
11  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
14  * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
15  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
16  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
17  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
18  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
19  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
20  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21  *
22  * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
23  *
24  October 2, 1994
25 
26  Modified by: Andres Vega Garcia
27 
28  INRIA - Sophia Antipolis, France
29  e-mail: avega@sophia.inria.fr
30  finger: avega@pax.inria.fr
31 
32  */
33 
34 FILE_LICENCE ( BSD3 );
35 
36 #include "nic.h"
37 
38 /*
39  * Ethernet software status per interface.
40  */
41 /*
42  * Some global constants
43  */
44 
45 #define TX_INIT_RATE 16
46 #define TX_INIT_MAX_RATE 64
47 #define RX_INIT_LATENCY 64
48 #define RX_INIT_EARLY_THRESH 64
49 #define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */
50 #define MIN_RX_EARLY_THRESHL 4
51 
52 #define EEPROMSIZE 0x40
53 #define MAX_EEPROMBUSY 1000
54 #define EP_ID_PORT_START 0x110 /* avoid 0x100 to avoid conflict with SB16 */
55 #define EP_ID_PORT_INC 0x10
56 #define EP_ID_PORT_END 0x200
57 #define EP_TAG_MAX 0x7 /* must be 2^n - 1 */
58 
59 /*
60  * Commands to read/write EEPROM trough EEPROM command register (Window 0,
61  * Offset 0xa)
62  */
63 #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
64 #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
65 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
66 #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
67 
68 #define EEPROM_BUSY (1<<15)
69 #define EEPROM_TST_MODE (1<<14)
70 
71 /*
72  * Some short functions, worth to let them be a macro
73  */
74 #define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
75 #define GO_WINDOW(b,x) outw(WINDOW_SELECT|(x), (b)+EP_COMMAND)
76 
77 /**************************************************************************
78  *
79  * These define the EEPROM data structure. They are used in the probe
80  * function to verify the existence of the adapter after having sent
81  * the ID_Sequence.
82  *
83  * There are others but only the ones we use are defined here.
84  *
85  **************************************************************************/
86 
87 #define EEPROM_NODE_ADDR_0 0x0 /* Word */
88 #define EEPROM_NODE_ADDR_1 0x1 /* Word */
89 #define EEPROM_NODE_ADDR_2 0x2 /* Word */
90 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
91 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */
92 #define EEPROM_ADDR_CFG 0x8 /* Base addr */
93 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
94 
95 /**************************************************************************
96  *
97  * These are the registers for the 3Com 3c509 and their bit patterns when
98  * applicable. They have been taken out the the "EtherLink III Parallel
99  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual
100  * from 3com.
101  *
102  * Getting this document out of 3Com is almost impossible. However,
103  * archived copies are available at
104  * http://www.osdever.net/cottontail/downloads/docs/3c5x9b.zip and
105  * several other places on the web (search for 3c5x9b.pdf).
106  *
107  **************************************************************************/
108 
109 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a
110  * command reg. */
111 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status
112  * reg. */
113 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window
114  * reg. */
115 /*
116  * Window 0 registers. Setup.
117  */
118 /* Write */
119 #define EP_W0_EEPROM_DATA 0x0c
120 #define EP_W0_EEPROM_COMMAND 0x0a
121 #define EP_W0_RESOURCE_CFG 0x08
122 #define EP_W0_ADDRESS_CFG 0x06
123 #define EP_W0_CONFIG_CTRL 0x04
124 /* Read */
125 #define EP_W0_PRODUCT_ID 0x02
126 #define EP_W0_MFG_ID 0x00
127 
128 /*
129  * Window 1 registers. Operating Set.
130  */
131 /* Write */
132 #define EP_W1_TX_PIO_WR_2 0x02
133 #define EP_W1_TX_PIO_WR_1 0x00
134 /* Read */
135 #define EP_W1_FREE_TX 0x0c
136 #define EP_W1_TX_STATUS 0x0b /* byte */
137 #define EP_W1_TIMER 0x0a /* byte */
138 #define EP_W1_RX_STATUS 0x08
139 #define EP_W1_RX_PIO_RD_2 0x02
140 #define EP_W1_RX_PIO_RD_1 0x00
141 
142 /*
143  * Window 2 registers. Station Address Setup/Read
144  */
145 /* Read/Write */
146 #define EP_W2_ADDR_5 0x05
147 #define EP_W2_ADDR_4 0x04
148 #define EP_W2_ADDR_3 0x03
149 #define EP_W2_ADDR_2 0x02
150 #define EP_W2_ADDR_1 0x01
151 #define EP_W2_ADDR_0 0x00
152 
153 /*
154  * Window 3 registers. FIFO Management.
155  */
156 /* Read */
157 #define EP_W3_FREE_TX 0x0c
158 #define EP_W3_FREE_RX 0x0a
159 
160 /*
161  * Window 4 registers. Diagnostics.
162  */
163 /* Read/Write */
164 #define EP_W4_MEDIA_TYPE 0x0a
165 #define EP_W4_CTRLR_STATUS 0x08
166 #define EP_W4_NET_DIAG 0x06
167 #define EP_W4_FIFO_DIAG 0x04
168 #define EP_W4_HOST_DIAG 0x02
169 #define EP_W4_TX_DIAG 0x00
170 
171 /*
172  * Window 5 Registers. Results and Internal status.
173  */
174 /* Read */
175 #define EP_W5_READ_0_MASK 0x0c
176 #define EP_W5_INTR_MASK 0x0a
177 #define EP_W5_RX_FILTER 0x08
178 #define EP_W5_RX_EARLY_THRESH 0x06
179 #define EP_W5_TX_AVAIL_THRESH 0x02
180 #define EP_W5_TX_START_THRESH 0x00
181 
182 /*
183  * Window 6 registers. Statistics.
184  */
185 /* Read/Write */
186 #define TX_TOTAL_OK 0x0c
187 #define RX_TOTAL_OK 0x0a
188 #define TX_DEFERRALS 0x08
189 #define RX_FRAMES_OK 0x07
190 #define TX_FRAMES_OK 0x06
191 #define RX_OVERRUNS 0x05
192 #define TX_COLLISIONS 0x04
193 #define TX_AFTER_1_COLLISION 0x03
194 #define TX_AFTER_X_COLLISIONS 0x02
195 #define TX_NO_SQE 0x01
196 #define TX_CD_LOST 0x00
197 
198 /****************************************
199  *
200  * Register definitions.
201  *
202  ****************************************/
203 
204 /*
205  * Command register. All windows.
206  *
207  * 16 bit register.
208  * 15-11: 5-bit code for command to be executed.
209  * 10-0: 11-bit arg if any. For commands with no args;
210  * this can be set to anything.
211  */
212 #define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms
213  * after issuing */
214 #define WINDOW_SELECT (unsigned short) (0x1<<11)
215 #define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to
216  * determine whether
217  * this is needed. If
218  * so; wait 800 uSec
219  * before using trans-
220  * ceiver. */
221 #define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on
222  * power-up */
223 #define RX_ENABLE (unsigned short) (0x4<<11)
224 #define RX_RESET (unsigned short) (0x5<<11)
225 #define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11)
226 #define TX_ENABLE (unsigned short) (0x9<<11)
227 #define TX_DISABLE (unsigned short) (0xa<<11)
228 #define TX_RESET (unsigned short) (0xb<<11)
229 #define REQ_INTR (unsigned short) (0xc<<11)
230 #define SET_INTR_MASK (unsigned short) (0xe<<11)
231 #define SET_RD_0_MASK (unsigned short) (0xf<<11)
232 #define SET_RX_FILTER (unsigned short) (0x10<<11)
233 #define FIL_INDIVIDUAL (unsigned short) (0x1)
234 #define FIL_GROUP (unsigned short) (0x2)
235 #define FIL_BRDCST (unsigned short) (0x4)
236 #define FIL_ALL (unsigned short) (0x8)
237 #define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11)
238 #define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11)
239 #define SET_TX_START_THRESH (unsigned short) (0x13<<11)
240 #define STATS_ENABLE (unsigned short) (0x15<<11)
241 #define STATS_DISABLE (unsigned short) (0x16<<11)
242 #define STOP_TRANSCEIVER (unsigned short) (0x17<<11)
243 /*
244  * The following C_* acknowledge the various interrupts. Some of them don't
245  * do anything. See the manual.
246  */
247 #define ACK_INTR (unsigned short) (0x6800)
248 #define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1)
249 #define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2)
250 #define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4)
251 #define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8)
252 #define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10)
253 #define C_RX_EARLY (unsigned short) (ACK_INTR|0x20)
254 #define C_INT_RQD (unsigned short) (ACK_INTR|0x40)
255 #define C_UPD_STATS (unsigned short) (ACK_INTR|0x80)
256 
257 /*
258  * Status register. All windows.
259  *
260  * 15-13: Window number(0-7).
261  * 12: Command_in_progress.
262  * 11: reserved.
263  * 10: reserved.
264  * 9: reserved.
265  * 8: reserved.
266  * 7: Update Statistics.
267  * 6: Interrupt Requested.
268  * 5: RX Early.
269  * 4: RX Complete.
270  * 3: TX Available.
271  * 2: TX Complete.
272  * 1: Adapter Failure.
273  * 0: Interrupt Latch.
274  */
275 #define S_INTR_LATCH (unsigned short) (0x1)
276 #define S_CARD_FAILURE (unsigned short) (0x2)
277 #define S_TX_COMPLETE (unsigned short) (0x4)
278 #define S_TX_AVAIL (unsigned short) (0x8)
279 #define S_RX_COMPLETE (unsigned short) (0x10)
280 #define S_RX_EARLY (unsigned short) (0x20)
281 #define S_INT_RQD (unsigned short) (0x40)
282 #define S_UPD_STATS (unsigned short) (0x80)
283 #define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\
284  S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
285 #define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000)
286 
287 /*
288  * FIFO Registers.
289  * RX Status. Window 1/Port 08
290  *
291  * 15: Incomplete or FIFO empty.
292  * 14: 1: Error in RX Packet 0: Incomplete or no error.
293  * 13-11: Type of error.
294  * 1000 = Overrun.
295  * 1011 = Run Packet Error.
296  * 1100 = Alignment Error.
297  * 1101 = CRC Error.
298  * 1001 = Oversize Packet Error (>1514 bytes)
299  * 0010 = Dribble Bits.
300  * (all other error codes, no errors.)
301  *
302  * 10-0: RX Bytes (0-1514)
303  */
304 #define ERR_RX_INCOMPLETE (unsigned short) (0x1<<15)
305 #define ERR_RX (unsigned short) (0x1<<14)
306 #define ERR_RX_OVERRUN (unsigned short) (0x8<<11)
307 #define ERR_RX_RUN_PKT (unsigned short) (0xb<<11)
308 #define ERR_RX_ALIGN (unsigned short) (0xc<<11)
309 #define ERR_RX_CRC (unsigned short) (0xd<<11)
310 #define ERR_RX_OVERSIZE (unsigned short) (0x9<<11)
311 #define ERR_RX_DRIBBLE (unsigned short) (0x2<<11)
312 
313 /*
314  * FIFO Registers.
315  * TX Status. Window 1/Port 0B
316  *
317  * Reports the transmit status of a completed transmission. Writing this
318  * register pops the transmit completion stack.
319  *
320  * Window 1/Port 0x0b.
321  *
322  * 7: Complete
323  * 6: Interrupt on successful transmission requested.
324  * 5: Jabber Error (TP Only, TX Reset required. )
325  * 4: Underrun (TX Reset required. )
326  * 3: Maximum Collisions.
327  * 2: TX Status Overflow.
328  * 1-0: Undefined.
329  *
330  */
331 #define TXS_COMPLETE 0x80
332 #define TXS_SUCCES_INTR_REQ 0x40
333 #define TXS_JABBER 0x20
334 #define TXS_UNDERRUN 0x10
335 #define TXS_MAX_COLLISION 0x8
336 #define TXS_STATUS_OVERFLOW 0x4
337 
338 /*
339  * Configuration control register.
340  * Window 0/Port 04
341  */
342 /* Read */
343 #define IS_AUI (1<<13)
344 #define IS_BNC (1<<12)
345 #define IS_UTP (1<<9)
346 /* Write */
347 #define ENABLE_DRQ_IRQ 0x0001
348 #define W0_P4_CMD_RESET_ADAPTER 0x4
349 #define W0_P4_CMD_ENABLE_ADAPTER 0x1
350 /*
351  * Media type and status.
352  * Window 4/Port 0A
353  */
354 #define ENABLE_UTP 0xc0
355 #define DISABLE_UTP 0x0
356 
357 /*
358  * Resource control register
359  */
360 
361 #define SET_IRQ(i) ( ((i)<<12) | 0xF00) /* set IRQ i */
362 
363 /*
364  * Receive status register
365  */
366 
367 #define RX_BYTES_MASK (unsigned short) (0x07ff)
368 #define RX_ERROR 0x4000
369 #define RX_INCOMPLETE 0x8000
370 
371 /*
372  * Misc defines for various things.
373  */
374 #define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
375 #define PROD_ID 0x9150
376 
377 #define AUI 0x1
378 #define BNC 0x2
379 #define UTP 0x4
380 
381 #define RX_BYTES_MASK (unsigned short) (0x07ff)
382 
383 /*
384  * Function shared between 3c509.c and 3c529.c
385  */
386 extern int t5x9_probe ( struct nic *nic,
387  uint16_t prod_id_check, uint16_t prod_id_mask );
388 extern void t5x9_disable ( struct nic *nic );
389 
390 /*
391  * Local variables:
392  * c-basic-offset: 8
393  * End:
394  */
unsigned short uint16_t
Definition: stdint.h:11
void t5x9_disable(struct nic *nic)
Definition: 3c5x9.c:40
FILE_LICENCE(BSD3)
Definition: nic.h:49
int t5x9_probe(struct nic *nic, uint16_t prod_id_check, uint16_t prod_id_mask)
Definition: 3c5x9.c:342