iPXE
|
#include "nic.h"
Go to the source code of this file.
Macros | |
#define | TX_INIT_RATE 16 |
#define | TX_INIT_MAX_RATE 64 |
#define | RX_INIT_LATENCY 64 |
#define | RX_INIT_EARLY_THRESH 64 |
#define | MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ |
#define | MIN_RX_EARLY_THRESHL 4 |
#define | EEPROMSIZE 0x40 |
#define | MAX_EEPROMBUSY 1000 |
#define | EP_ID_PORT_START 0x110 /* avoid 0x100 to avoid conflict with SB16 */ |
#define | EP_ID_PORT_INC 0x10 |
#define | EP_ID_PORT_END 0x200 |
#define | EP_TAG_MAX 0x7 /* must be 2^n - 1 */ |
#define | EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ |
#define | EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ |
#define | EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ |
#define | EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ |
#define | EEPROM_BUSY (1<<15) |
#define | EEPROM_TST_MODE (1<<14) |
#define | is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) |
#define | GO_WINDOW(b, x) outw(WINDOW_SELECT|(x), (b)+EP_COMMAND) |
#define | EEPROM_NODE_ADDR_0 0x0 /* Word */ |
#define | EEPROM_NODE_ADDR_1 0x1 /* Word */ |
#define | EEPROM_NODE_ADDR_2 0x2 /* Word */ |
#define | EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ |
#define | EEPROM_MFG_ID 0x7 /* 0x6d50 */ |
#define | EEPROM_ADDR_CFG 0x8 /* Base addr */ |
#define | EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ |
#define | EP_COMMAND |
#define | EP_STATUS |
#define | EP_WINDOW |
#define | EP_W0_EEPROM_DATA 0x0c |
#define | EP_W0_EEPROM_COMMAND 0x0a |
#define | EP_W0_RESOURCE_CFG 0x08 |
#define | EP_W0_ADDRESS_CFG 0x06 |
#define | EP_W0_CONFIG_CTRL 0x04 |
#define | EP_W0_PRODUCT_ID 0x02 |
#define | EP_W0_MFG_ID 0x00 |
#define | EP_W1_TX_PIO_WR_2 0x02 |
#define | EP_W1_TX_PIO_WR_1 0x00 |
#define | EP_W1_FREE_TX 0x0c |
#define | EP_W1_TX_STATUS 0x0b /* byte */ |
#define | EP_W1_TIMER 0x0a /* byte */ |
#define | EP_W1_RX_STATUS 0x08 |
#define | EP_W1_RX_PIO_RD_2 0x02 |
#define | EP_W1_RX_PIO_RD_1 0x00 |
#define | EP_W2_ADDR_5 0x05 |
#define | EP_W2_ADDR_4 0x04 |
#define | EP_W2_ADDR_3 0x03 |
#define | EP_W2_ADDR_2 0x02 |
#define | EP_W2_ADDR_1 0x01 |
#define | EP_W2_ADDR_0 0x00 |
#define | EP_W3_FREE_TX 0x0c |
#define | EP_W3_FREE_RX 0x0a |
#define | EP_W4_MEDIA_TYPE 0x0a |
#define | EP_W4_CTRLR_STATUS 0x08 |
#define | EP_W4_NET_DIAG 0x06 |
#define | EP_W4_FIFO_DIAG 0x04 |
#define | EP_W4_HOST_DIAG 0x02 |
#define | EP_W4_TX_DIAG 0x00 |
#define | EP_W5_READ_0_MASK 0x0c |
#define | EP_W5_INTR_MASK 0x0a |
#define | EP_W5_RX_FILTER 0x08 |
#define | EP_W5_RX_EARLY_THRESH 0x06 |
#define | EP_W5_TX_AVAIL_THRESH 0x02 |
#define | EP_W5_TX_START_THRESH 0x00 |
#define | TX_TOTAL_OK 0x0c |
#define | RX_TOTAL_OK 0x0a |
#define | TX_DEFERRALS 0x08 |
#define | RX_FRAMES_OK 0x07 |
#define | TX_FRAMES_OK 0x06 |
#define | RX_OVERRUNS 0x05 |
#define | TX_COLLISIONS 0x04 |
#define | TX_AFTER_1_COLLISION 0x03 |
#define | TX_AFTER_X_COLLISIONS 0x02 |
#define | TX_NO_SQE 0x01 |
#define | TX_CD_LOST 0x00 |
#define | GLOBAL_RESET |
#define | WINDOW_SELECT (unsigned short) (0x1<<11) |
#define | START_TRANSCEIVER |
#define | RX_DISABLE |
#define | RX_ENABLE (unsigned short) (0x4<<11) |
#define | RX_RESET (unsigned short) (0x5<<11) |
#define | RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) |
#define | TX_ENABLE (unsigned short) (0x9<<11) |
#define | TX_DISABLE (unsigned short) (0xa<<11) |
#define | TX_RESET (unsigned short) (0xb<<11) |
#define | REQ_INTR (unsigned short) (0xc<<11) |
#define | SET_INTR_MASK (unsigned short) (0xe<<11) |
#define | SET_RD_0_MASK (unsigned short) (0xf<<11) |
#define | SET_RX_FILTER (unsigned short) (0x10<<11) |
#define | FIL_INDIVIDUAL (unsigned short) (0x1) |
#define | FIL_GROUP (unsigned short) (0x2) |
#define | FIL_BRDCST (unsigned short) (0x4) |
#define | FIL_ALL (unsigned short) (0x8) |
#define | SET_RX_EARLY_THRESH (unsigned short) (0x11<<11) |
#define | SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) |
#define | SET_TX_START_THRESH (unsigned short) (0x13<<11) |
#define | STATS_ENABLE (unsigned short) (0x15<<11) |
#define | STATS_DISABLE (unsigned short) (0x16<<11) |
#define | STOP_TRANSCEIVER (unsigned short) (0x17<<11) |
#define | ACK_INTR (unsigned short) (0x6800) |
#define | C_INTR_LATCH (unsigned short) (ACK_INTR|0x1) |
#define | C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) |
#define | C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) |
#define | C_TX_AVAIL (unsigned short) (ACK_INTR|0x8) |
#define | C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) |
#define | C_RX_EARLY (unsigned short) (ACK_INTR|0x20) |
#define | C_INT_RQD (unsigned short) (ACK_INTR|0x40) |
#define | C_UPD_STATS (unsigned short) (ACK_INTR|0x80) |
#define | S_INTR_LATCH (unsigned short) (0x1) |
#define | S_CARD_FAILURE (unsigned short) (0x2) |
#define | S_TX_COMPLETE (unsigned short) (0x4) |
#define | S_TX_AVAIL (unsigned short) (0x8) |
#define | S_RX_COMPLETE (unsigned short) (0x10) |
#define | S_RX_EARLY (unsigned short) (0x20) |
#define | S_INT_RQD (unsigned short) (0x40) |
#define | S_UPD_STATS (unsigned short) (0x80) |
#define | S_5_INTS |
#define | S_COMMAND_IN_PROGRESS (unsigned short) (0x1000) |
#define | ERR_RX_INCOMPLETE (unsigned short) (0x1<<15) |
#define | ERR_RX (unsigned short) (0x1<<14) |
#define | ERR_RX_OVERRUN (unsigned short) (0x8<<11) |
#define | ERR_RX_RUN_PKT (unsigned short) (0xb<<11) |
#define | ERR_RX_ALIGN (unsigned short) (0xc<<11) |
#define | ERR_RX_CRC (unsigned short) (0xd<<11) |
#define | ERR_RX_OVERSIZE (unsigned short) (0x9<<11) |
#define | ERR_RX_DRIBBLE (unsigned short) (0x2<<11) |
#define | TXS_COMPLETE 0x80 |
#define | TXS_SUCCES_INTR_REQ 0x40 |
#define | TXS_JABBER 0x20 |
#define | TXS_UNDERRUN 0x10 |
#define | TXS_MAX_COLLISION 0x8 |
#define | TXS_STATUS_OVERFLOW 0x4 |
#define | IS_AUI (1<<13) |
#define | IS_BNC (1<<12) |
#define | IS_UTP (1<<9) |
#define | ENABLE_DRQ_IRQ 0x0001 |
#define | W0_P4_CMD_RESET_ADAPTER 0x4 |
#define | W0_P4_CMD_ENABLE_ADAPTER 0x1 |
#define | ENABLE_UTP 0xc0 |
#define | DISABLE_UTP 0x0 |
#define | SET_IRQ(i) ( ((i)<<12) | 0xF00) /* set IRQ i */ |
#define | RX_BYTES_MASK (unsigned short) (0x07ff) |
#define | RX_ERROR 0x4000 |
#define | RX_INCOMPLETE 0x8000 |
#define | MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */ |
#define | PROD_ID 0x9150 |
#define | AUI 0x1 |
#define | BNC 0x2 |
#define | UTP 0x4 |
#define | RX_BYTES_MASK (unsigned short) (0x07ff) |
Functions | |
FILE_LICENCE (BSD3) | |
int | t5x9_probe (struct nic *nic, uint16_t prod_id_check, uint16_t prod_id_mask) |
void | t5x9_disable (struct nic *nic) |
#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ |
#define EP_ID_PORT_START 0x110 /* avoid 0x100 to avoid conflict with SB16 */ |
#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ |
#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ |
#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ |
#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ |
#define is_eeprom_busy | ( | b | ) | (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) |
#define GO_WINDOW | ( | b, | |
x | |||
) | outw(WINDOW_SELECT|(x), (b)+EP_COMMAND) |
#define EP_COMMAND |
#define EP_STATUS |
#define EP_WINDOW |
#define GLOBAL_RESET |
#define START_TRANSCEIVER |
#define RX_DISABLE |
#define S_5_INTS |
FILE_LICENCE | ( | BSD3 | ) |
Definition at line 342 of file 3c5x9.c.
References bnc, connector, DBG, EEPROM_PROD_ID, EP_W0_ADDRESS_CFG, EP_W0_CONFIG_CTRL, EP_W2_ADDR_0, ETH_ALEN, eth_ntoa(), get_e(), GO_WINDOW, htons, inw(), nic::ioaddr, IS_AUI, IS_BNC, IS_UTP, nic::nic_op, nic::node_addr, ntohs, outw, printf(), t509_operations, t509_reset(), and utp.
Referenced by el3_eisa_probe(), legacy_t509_probe(), and t529_probe().
void t5x9_disable | ( | struct nic * | nic | ) |
Definition at line 40 of file 3c5x9.c.
References C_INTR_LATCH, EP_COMMAND, EP_STATUS, EP_W0_CONFIG_CTRL, EP_W0_RESOURCE_CFG, GO_WINDOW, inw(), nic::ioaddr, outw, RX_DISABLE, RX_DISCARD_TOP_PACK, RX_RESET, S_COMMAND_IN_PROGRESS, SET_INTR_MASK, SET_IRQ, SET_RD_0_MASK, SET_RX_FILTER, STOP_TRANSCEIVER, TX_DISABLE, TX_RESET, and udelay().
Referenced by el3_eisa_disable(), legacy_t509_disable(), t509_reset(), and t529_disable().