iPXE
arch-arm.h
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1 /******************************************************************************
2  * arch-arm.h
3  *
4  * Guest OS interface to ARM Xen.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to
8  * deal in the Software without restriction, including without limitation the
9  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10  * sell copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Copyright 2011 (C) Citrix Systems
25  */
26 
27 #ifndef __XEN_PUBLIC_ARCH_ARM_H__
28 #define __XEN_PUBLIC_ARCH_ARM_H__
29 
30 FILE_LICENCE ( MIT );
31 
32 /*
33  * `incontents 50 arm_abi Hypercall Calling Convention
34  *
35  * A hypercall is issued using the ARM HVC instruction.
36  *
37  * A hypercall can take up to 5 arguments. These are passed in
38  * registers, the first argument in x0/r0 (for arm64/arm32 guests
39  * respectively irrespective of whether the underlying hypervisor is
40  * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2,
41  * the forth in x3/r3 and the fifth in x4/r4.
42  *
43  * The hypercall number is passed in r12 (arm) or x16 (arm64). In both
44  * cases the relevant ARM procedure calling convention specifies this
45  * is an inter-procedure-call scratch register (e.g. for use in linker
46  * stubs). This use does not conflict with use during a hypercall.
47  *
48  * The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG.
49  *
50  * The return value is in x0/r0.
51  *
52  * The hypercall will clobber x16/r12 and the argument registers used
53  * by that hypercall (except r0 which is the return value) i.e. in
54  * addition to x16/r12 a 2 argument hypercall will clobber x1/r1 and a
55  * 4 argument hypercall will clobber x1/r1, x2/r2 and x3/r3.
56  *
57  * Parameter structs passed to hypercalls are laid out according to
58  * the Procedure Call Standard for the ARM Architecture (AAPCS, AKA
59  * EABI) and Procedure Call Standard for the ARM 64-bit Architecture
60  * (AAPCS64). Where there is a conflict the 64-bit standard should be
61  * used regardless of guest type. Structures which are passed as
62  * hypercall arguments are always little endian.
63  *
64  * All memory which is shared with other entities in the system
65  * (including the hypervisor and other guests) must reside in memory
66  * which is mapped as Normal Inner-cacheable. This applies to:
67  * - hypercall arguments passed via a pointer to guest memory.
68  * - memory shared via the grant table mechanism (including PV I/O
69  * rings etc).
70  * - memory shared with the hypervisor (struct shared_info, struct
71  * vcpu_info, the grant table, etc).
72  *
73  * Any Inner cache allocation strategy (Write-Back, Write-Through etc)
74  * is acceptable. There is no restriction on the Outer-cacheability.
75  */
76 
77 /*
78  * `incontents 55 arm_hcall Supported Hypercalls
79  *
80  * Xen on ARM makes extensive use of hardware facilities and therefore
81  * only a subset of the potential hypercalls are required.
82  *
83  * Since ARM uses second stage paging any machine/physical addresses
84  * passed to hypercalls are Guest Physical Addresses (Intermediate
85  * Physical Addresses) unless otherwise noted.
86  *
87  * The following hypercalls (and sub operations) are supported on the
88  * ARM platform. Other hypercalls should be considered
89  * unavailable/unsupported.
90  *
91  * HYPERVISOR_memory_op
92  * All generic sub-operations.
93  *
94  * In addition the following arch specific sub-ops:
95  * * XENMEM_add_to_physmap
96  * * XENMEM_add_to_physmap_batch
97  *
98  * HYPERVISOR_domctl
99  * All generic sub-operations, with the exception of:
100  * * XEN_DOMCTL_iomem_permission (not yet implemented)
101  * * XEN_DOMCTL_irq_permission (not yet implemented)
102  *
103  * HYPERVISOR_sched_op
104  * All generic sub-operations, with the exception of:
105  * * SCHEDOP_block -- prefer wfi hardware instruction
106  *
107  * HYPERVISOR_console_io
108  * All generic sub-operations
109  *
110  * HYPERVISOR_xen_version
111  * All generic sub-operations
112  *
113  * HYPERVISOR_event_channel_op
114  * All generic sub-operations
115  *
116  * HYPERVISOR_physdev_op
117  * No sub-operations are currenty supported
118  *
119  * HYPERVISOR_sysctl
120  * All generic sub-operations, with the exception of:
121  * * XEN_SYSCTL_page_offline_op
122  * * XEN_SYSCTL_get_pmstat
123  * * XEN_SYSCTL_pm_op
124  *
125  * HYPERVISOR_hvm_op
126  * Exactly these sub-operations are supported:
127  * * HVMOP_set_param
128  * * HVMOP_get_param
129  *
130  * HYPERVISOR_grant_table_op
131  * All generic sub-operations
132  *
133  * HYPERVISOR_vcpu_op
134  * Exactly these sub-operations are supported:
135  * * VCPUOP_register_vcpu_info
136  * * VCPUOP_register_runstate_memory_area
137  *
138  *
139  * Other notes on the ARM ABI:
140  *
141  * - struct start_info is not exported to ARM guests.
142  *
143  * - struct shared_info is mapped by ARM guests using the
144  * HYPERVISOR_memory_op sub-op XENMEM_add_to_physmap, passing
145  * XENMAPSPACE_shared_info as space parameter.
146  *
147  * - All the per-cpu struct vcpu_info are mapped by ARM guests using the
148  * HYPERVISOR_vcpu_op sub-op VCPUOP_register_vcpu_info, including cpu0
149  * struct vcpu_info.
150  *
151  * - The grant table is mapped using the HYPERVISOR_memory_op sub-op
152  * XENMEM_add_to_physmap, passing XENMAPSPACE_grant_table as space
153  * parameter. The memory range specified under the Xen compatible
154  * hypervisor node on device tree can be used as target gpfn for the
155  * mapping.
156  *
157  * - Xenstore is initialized by using the two hvm_params
158  * HVM_PARAM_STORE_PFN and HVM_PARAM_STORE_EVTCHN. They can be read
159  * with the HYPERVISOR_hvm_op sub-op HVMOP_get_param.
160  *
161  * - The paravirtualized console is initialized by using the two
162  * hvm_params HVM_PARAM_CONSOLE_PFN and HVM_PARAM_CONSOLE_EVTCHN. They
163  * can be read with the HYPERVISOR_hvm_op sub-op HVMOP_get_param.
164  *
165  * - Event channel notifications are delivered using the percpu GIC
166  * interrupt specified under the Xen compatible hypervisor node on
167  * device tree.
168  *
169  * - The device tree Xen compatible node is fully described under Linux
170  * at Documentation/devicetree/bindings/arm/xen.txt.
171  */
172 
173 #define XEN_HYPERCALL_TAG 0XEA1
174 
175 #define uint64_aligned_t uint64_t __attribute__((aligned(8)))
176 
177 #ifndef __ASSEMBLY__
178 #define ___DEFINE_XEN_GUEST_HANDLE(name, type) \
179  typedef union { type *p; unsigned long q; } \
180  __guest_handle_ ## name; \
181  typedef union { type *p; uint64_aligned_t q; } \
182  __guest_handle_64_ ## name;
183 
184 /*
185  * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field
186  * in a struct in memory. On ARM is always 8 bytes sizes and 8 bytes
187  * aligned.
188  * XEN_GUEST_HANDLE_PARAM represent a guest pointer, when passed as an
189  * hypercall argument. It is 4 bytes on aarch and 8 bytes on aarch64.
190  */
191 #define __DEFINE_XEN_GUEST_HANDLE(name, type) \
192  ___DEFINE_XEN_GUEST_HANDLE(name, type); \
193  ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type)
194 #define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name)
195 #define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name
196 #define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name)
197 /* this is going to be changed on 64 bit */
198 #define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name
199 #define set_xen_guest_handle_raw(hnd, val) \
200  do { \
201  typeof(&(hnd)) _sxghr_tmp = &(hnd); \
202  _sxghr_tmp->q = 0; \
203  _sxghr_tmp->p = val; \
204  } while ( 0 )
205 #ifdef __XEN_TOOLS__
206 #define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0)
207 #endif
208 #define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)
209 
210 #if defined(__GNUC__) && !defined(__STRICT_ANSI__)
211 /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */
212 # define __DECL_REG(n64, n32) union { \
213  uint64_t n64; \
214  uint32_t n32; \
215  }
216 #else
217 /* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */
218 #define __DECL_REG(n64, n32) uint64_t n64
219 #endif
220 
222 {
223  /* Aarch64 Aarch32 */
224  __DECL_REG(x0, r0_usr);
225  __DECL_REG(x1, r1_usr);
226  __DECL_REG(x2, r2_usr);
227  __DECL_REG(x3, r3_usr);
228  __DECL_REG(x4, r4_usr);
229  __DECL_REG(x5, r5_usr);
230  __DECL_REG(x6, r6_usr);
231  __DECL_REG(x7, r7_usr);
232  __DECL_REG(x8, r8_usr);
233  __DECL_REG(x9, r9_usr);
234  __DECL_REG(x10, r10_usr);
235  __DECL_REG(x11, r11_usr);
236  __DECL_REG(x12, r12_usr);
237 
238  __DECL_REG(x13, sp_usr);
239  __DECL_REG(x14, lr_usr);
240 
241  __DECL_REG(x15, __unused_sp_hyp);
242 
243  __DECL_REG(x16, lr_irq);
244  __DECL_REG(x17, sp_irq);
245 
246  __DECL_REG(x18, lr_svc);
247  __DECL_REG(x19, sp_svc);
248 
249  __DECL_REG(x20, lr_abt);
250  __DECL_REG(x21, sp_abt);
251 
252  __DECL_REG(x22, lr_und);
253  __DECL_REG(x23, sp_und);
254 
255  __DECL_REG(x24, r8_fiq);
256  __DECL_REG(x25, r9_fiq);
257  __DECL_REG(x26, r10_fiq);
258  __DECL_REG(x27, r11_fiq);
259  __DECL_REG(x28, r12_fiq);
260 
261  __DECL_REG(x29, sp_fiq);
262  __DECL_REG(x30, lr_fiq);
263 
264  /* Return address and mode */
265  __DECL_REG(pc64, pc32); /* ELR_EL2 */
266  uint32_t cpsr; /* SPSR_EL2 */
267 
268  union {
269  uint32_t spsr_el1; /* AArch64 */
270  uint32_t spsr_svc; /* AArch32 */
271  };
272 
273  /* AArch32 guests only */
275 
276  /* AArch64 guests only */
279 };
282 
283 #undef __DECL_REG
284 
286 #define PRI_xen_pfn PRIx64
287 
288 /* Maximum number of virtual CPUs in legacy multi-processor guests. */
289 /* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */
290 #define XEN_LEGACY_MAX_VCPUS 1
291 
293 #define PRI_xen_ulong PRIx64
294 
295 #if defined(__XEN__) || defined(__XEN_TOOLS__)
296 struct vcpu_guest_context {
297 #define _VGCF_online 0
298 #define VGCF_online (1<<_VGCF_online)
299  uint32_t flags; /* VGCF_* */
300 
301  struct vcpu_guest_core_regs user_regs; /* Core CPU registers */
302 
303  uint32_t sctlr;
304  uint64_t ttbcr, ttbr0, ttbr1;
305 };
308 #endif
309 
311 };
313 
315 };
318 
319 #endif
320 
321 #if defined(__XEN__) || defined(__XEN_TOOLS__)
322 
323 /* PSR bits (CPSR, SPSR)*/
324 
325 #define PSR_THUMB (1<<5) /* Thumb Mode enable */
326 #define PSR_FIQ_MASK (1<<6) /* Fast Interrupt mask */
327 #define PSR_IRQ_MASK (1<<7) /* Interrupt mask */
328 #define PSR_ABT_MASK (1<<8) /* Asynchronous Abort mask */
329 #define PSR_BIG_ENDIAN (1<<9) /* arm32: Big Endian Mode */
330 #define PSR_DBG_MASK (1<<9) /* arm64: Debug Exception mask */
331 #define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */
332 #define PSR_JAZELLE (1<<24) /* Jazelle Mode */
333 
334 /* 32 bit modes */
335 #define PSR_MODE_USR 0x10
336 #define PSR_MODE_FIQ 0x11
337 #define PSR_MODE_IRQ 0x12
338 #define PSR_MODE_SVC 0x13
339 #define PSR_MODE_MON 0x16
340 #define PSR_MODE_ABT 0x17
341 #define PSR_MODE_HYP 0x1a
342 #define PSR_MODE_UND 0x1b
343 #define PSR_MODE_SYS 0x1f
344 
345 /* 64 bit modes */
346 #define PSR_MODE_BIT 0x10 /* Set iff AArch32 */
347 #define PSR_MODE_EL3h 0x0d
348 #define PSR_MODE_EL3t 0x0c
349 #define PSR_MODE_EL2h 0x09
350 #define PSR_MODE_EL2t 0x08
351 #define PSR_MODE_EL1h 0x05
352 #define PSR_MODE_EL1t 0x04
353 #define PSR_MODE_EL0t 0x00
354 
355 #define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)
356 #define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)
357 
358 #define SCTLR_GUEST_INIT 0x00c50078
359 
360 /*
361  * Virtual machine platform (memory layout, interrupts)
362  *
363  * These are defined for consistency between the tools and the
364  * hypervisor. Guests must not rely on these hardcoded values but
365  * should instead use the FDT.
366  */
367 
368 /* Physical Address Space */
369 #define GUEST_GICD_BASE 0x03001000ULL
370 #define GUEST_GICD_SIZE 0x00001000ULL
371 #define GUEST_GICC_BASE 0x03002000ULL
372 #define GUEST_GICC_SIZE 0x00000100ULL
373 
374 /* 16MB == 4096 pages reserved for guest to use as a region to map its
375  * grant table in.
376  */
377 #define GUEST_GNTTAB_BASE 0x38000000ULL
378 #define GUEST_GNTTAB_SIZE 0x01000000ULL
379 
380 #define GUEST_MAGIC_BASE 0x39000000ULL
381 #define GUEST_MAGIC_SIZE 0x01000000ULL
382 
383 #define GUEST_RAM_BANKS 2
384 
385 #define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of low RAM @ 1GB */
386 #define GUEST_RAM0_SIZE 0xc0000000ULL
387 
388 #define GUEST_RAM1_BASE 0x0200000000ULL /* 1016GB of RAM @ 8GB */
389 #define GUEST_RAM1_SIZE 0xfe00000000ULL
390 
391 #define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */
392 /* Largest amount of actual RAM, not including holes */
393 #define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE)
394 /* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */
395 #define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE }
396 #define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE }
397 
398 /* Interrupts */
399 #define GUEST_TIMER_VIRT_PPI 27
400 #define GUEST_TIMER_PHYS_S_PPI 29
401 #define GUEST_TIMER_PHYS_NS_PPI 30
402 #define GUEST_EVTCHN_PPI 31
403 
404 /* PSCI functions */
405 #define PSCI_cpu_suspend 0
406 #define PSCI_cpu_off 1
407 #define PSCI_cpu_on 2
408 #define PSCI_migrate 3
409 
410 #endif
411 
412 #endif /* __XEN_PUBLIC_ARCH_ARM_H__ */
413 
414 /*
415  * Local variables:
416  * mode: C
417  * c-file-style: "BSD"
418  * c-basic-offset: 4
419  * tab-width: 4
420  * indent-tabs-mode: nil
421  * End:
422  */
unsigned long long uint64_t
Definition: stdint.h:13
uint64_t xen_ulong_t
Definition: arch-arm.h:292
unsigned long flags
Definition: xen.h:184
#define DEFINE_XEN_GUEST_HANDLE(name)
Definition: arch-arm.h:194
struct cpu_user_regs user_regs
Definition: xen.h:185
__DECL_REG(x0, r0_usr)
unsigned int uint32_t
Definition: stdint.h:12
uint64_t xen_pfn_t
Definition: arch-arm.h:285
FILE_LICENCE(MIT)
uint64_t xen_callback_t
Definition: arch-arm.h:317