iPXE
Data Structures | Macros
bnxt_hsi.h File Reference

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Data Structures

struct  hwrm_cmd_hdr
 
struct  hwrm_resp_hdr
 
struct  tlv
 
struct  input
 
struct  output
 
struct  hwrm_short_input
 
struct  cmd_nums
 
struct  ret_codes
 
struct  hwrm_err_output
 
struct  hwrm_ver_get_input
 
struct  hwrm_ver_get_output
 
struct  eject_cmpl
 
struct  hwrm_cmpl
 
struct  hwrm_fwd_req_cmpl
 
struct  hwrm_fwd_resp_cmpl
 
struct  hwrm_async_event_cmpl
 
struct  hwrm_async_event_cmpl_link_status_change
 
struct  hwrm_async_event_cmpl_link_mtu_change
 
struct  hwrm_async_event_cmpl_link_speed_change
 
struct  hwrm_async_event_cmpl_dcb_config_change
 
struct  hwrm_async_event_cmpl_port_conn_not_allowed
 
struct  hwrm_async_event_cmpl_link_speed_cfg_not_allowed
 
struct  hwrm_async_event_cmpl_link_speed_cfg_change
 
struct  hwrm_async_event_cmpl_port_phy_cfg_change
 
struct  hwrm_async_event_cmpl_reset_notify
 
struct  hwrm_async_event_cmpl_func_drvr_unload
 
struct  hwrm_async_event_cmpl_func_drvr_load
 
struct  hwrm_async_event_cmpl_func_flr_proc_cmplt
 
struct  hwrm_async_event_cmpl_pf_drvr_unload
 
struct  hwrm_async_event_cmpl_pf_drvr_load
 
struct  hwrm_async_event_cmpl_vf_flr
 
struct  hwrm_async_event_cmpl_vf_mac_addr_change
 
struct  hwrm_async_event_cmpl_pf_vf_comm_status_change
 
struct  hwrm_async_event_cmpl_vf_cfg_change
 
struct  hwrm_async_event_cmpl_llfc_pfc_change
 
struct  hwrm_async_event_cmpl_default_vnic_change
 
struct  hwrm_async_event_cmpl_hw_flow_aged
 
struct  hwrm_async_event_cmpl_hwrm_error
 
struct  hwrm_func_reset_input
 
struct  hwrm_func_reset_output
 
struct  hwrm_func_getfid_input
 
struct  hwrm_func_getfid_output
 
struct  hwrm_func_vf_alloc_input
 
struct  hwrm_func_vf_alloc_output
 
struct  hwrm_func_vf_free_input
 
struct  hwrm_func_vf_free_output
 
struct  hwrm_func_vf_cfg_input
 
struct  hwrm_func_vf_cfg_output
 
struct  hwrm_func_qcaps_input
 
struct  hwrm_func_qcaps_output
 
struct  hwrm_func_qcfg_input
 
struct  hwrm_func_qcfg_output
 
struct  hwrm_func_cfg_input
 
struct  hwrm_func_cfg_output
 
struct  hwrm_func_qstats_input
 
struct  hwrm_func_qstats_output
 
struct  hwrm_func_clr_stats_input
 
struct  hwrm_func_clr_stats_output
 
struct  hwrm_func_vf_resc_free_input
 
struct  hwrm_func_vf_resc_free_output
 
struct  hwrm_func_drv_rgtr_input
 
struct  hwrm_func_drv_rgtr_output
 
struct  hwrm_func_drv_unrgtr_input
 
struct  hwrm_func_drv_unrgtr_output
 
struct  hwrm_func_buf_rgtr_input
 
struct  hwrm_func_buf_rgtr_output
 
struct  hwrm_func_buf_unrgtr_input
 
struct  hwrm_func_buf_unrgtr_output
 
struct  hwrm_func_drv_qver_input
 
struct  hwrm_func_drv_qver_output
 
struct  hwrm_func_resource_qcaps_input
 
struct  hwrm_func_resource_qcaps_output
 
struct  hwrm_func_vf_resource_cfg_input
 
struct  hwrm_func_vf_resource_cfg_output
 
struct  hwrm_func_backing_store_qcaps_input
 
struct  hwrm_func_backing_store_qcaps_output
 
struct  hwrm_func_backing_store_cfg_input
 
struct  hwrm_func_backing_store_cfg_output
 
struct  hwrm_func_backing_store_qcfg_input
 
struct  hwrm_func_backing_store_qcfg_output
 
struct  hwrm_func_vlan_qcfg_input
 
struct  hwrm_func_vlan_qcfg_output
 
struct  hwrm_func_vlan_cfg_input
 
struct  hwrm_func_vlan_cfg_output
 
struct  hwrm_func_vf_vnic_ids_query_input
 
struct  hwrm_func_vf_vnic_ids_query_output
 
struct  hwrm_func_vf_bw_cfg_input
 
struct  hwrm_func_vf_bw_cfg_output
 
struct  hwrm_func_vf_bw_qcfg_input
 
struct  hwrm_func_vf_bw_qcfg_output
 
struct  hwrm_func_drv_if_change_input
 
struct  hwrm_func_drv_if_change_output
 
struct  hwrm_port_phy_cfg_input
 
struct  hwrm_port_phy_cfg_output
 
struct  hwrm_port_phy_cfg_cmd_err
 
struct  hwrm_port_phy_qcfg_input
 
struct  hwrm_port_phy_qcfg_output
 
struct  hwrm_port_mac_cfg_input
 
struct  hwrm_port_mac_cfg_output
 
struct  hwrm_port_mac_qcfg_input
 
struct  hwrm_port_mac_qcfg_output
 
struct  hwrm_port_mac_ptp_qcfg_input
 
struct  hwrm_port_mac_ptp_qcfg_output
 
struct  tx_port_stats
 
struct  rx_port_stats
 
struct  hwrm_port_qstats_input
 
struct  hwrm_port_qstats_output
 
struct  tx_port_stats_ext
 
struct  rx_port_stats_ext
 
struct  hwrm_port_qstats_ext_input
 
struct  hwrm_port_qstats_ext_output
 
struct  hwrm_port_lpbk_qstats_input
 
struct  hwrm_port_lpbk_qstats_output
 
struct  hwrm_port_clr_stats_input
 
struct  hwrm_port_clr_stats_output
 
struct  hwrm_port_lpbk_clr_stats_input
 
struct  hwrm_port_lpbk_clr_stats_output
 
struct  hwrm_port_ts_query_input
 
struct  hwrm_port_ts_query_output
 
struct  hwrm_port_phy_qcaps_input
 
struct  hwrm_port_phy_qcaps_output
 
struct  hwrm_port_phy_i2c_write_input
 
struct  hwrm_port_phy_i2c_write_output
 
struct  hwrm_port_phy_i2c_read_input
 
struct  hwrm_port_phy_i2c_read_output
 
struct  hwrm_port_led_cfg_input
 
struct  hwrm_port_led_cfg_output
 
struct  hwrm_port_led_qcfg_input
 
struct  hwrm_port_led_qcfg_output
 
struct  hwrm_port_led_qcaps_input
 
struct  hwrm_port_led_qcaps_output
 
struct  hwrm_queue_qportcfg_input
 
struct  hwrm_queue_qportcfg_output
 
struct  hwrm_queue_qcfg_input
 
struct  hwrm_queue_qcfg_output
 
struct  hwrm_queue_cfg_input
 
struct  hwrm_queue_cfg_output
 
struct  hwrm_queue_pfcenable_qcfg_input
 
struct  hwrm_queue_pfcenable_qcfg_output
 
struct  hwrm_queue_pfcenable_cfg_input
 
struct  hwrm_queue_pfcenable_cfg_output
 
struct  hwrm_queue_pri2cos_qcfg_input
 
struct  hwrm_queue_pri2cos_qcfg_output
 
struct  hwrm_queue_pri2cos_cfg_input
 
struct  hwrm_queue_pri2cos_cfg_output
 
struct  hwrm_queue_cos2bw_qcfg_input
 
struct  hwrm_queue_cos2bw_qcfg_output
 
struct  hwrm_queue_cos2bw_cfg_input
 
struct  hwrm_queue_cos2bw_cfg_output
 
struct  hwrm_queue_dscp_qcaps_input
 
struct  hwrm_queue_dscp_qcaps_output
 
struct  hwrm_queue_dscp2pri_qcfg_input
 
struct  hwrm_queue_dscp2pri_qcfg_output
 
struct  hwrm_queue_dscp2pri_cfg_input
 
struct  hwrm_queue_dscp2pri_cfg_output
 
struct  hwrm_vnic_alloc_input
 
struct  hwrm_vnic_alloc_output
 
struct  hwrm_vnic_free_input
 
struct  hwrm_vnic_free_output
 
struct  hwrm_vnic_cfg_input
 
struct  hwrm_vnic_cfg_output
 
struct  hwrm_vnic_qcfg_input
 
struct  hwrm_vnic_qcfg_output
 
struct  hwrm_vnic_qcaps_input
 
struct  hwrm_vnic_qcaps_output
 
struct  hwrm_vnic_tpa_cfg_input
 
struct  hwrm_vnic_tpa_cfg_output
 
struct  hwrm_vnic_tpa_qcfg_input
 
struct  hwrm_vnic_tpa_qcfg_output
 
struct  hwrm_vnic_rss_cfg_input
 
struct  hwrm_vnic_rss_cfg_output
 
struct  hwrm_vnic_rss_qcfg_input
 
struct  hwrm_vnic_rss_qcfg_output
 
struct  hwrm_vnic_plcmodes_cfg_input
 
struct  hwrm_vnic_plcmodes_cfg_output
 
struct  hwrm_vnic_plcmodes_qcfg_input
 
struct  hwrm_vnic_plcmodes_qcfg_output
 
struct  hwrm_vnic_rss_cos_lb_ctx_alloc_input
 
struct  hwrm_vnic_rss_cos_lb_ctx_alloc_output
 
struct  hwrm_vnic_rss_cos_lb_ctx_free_input
 
struct  hwrm_vnic_rss_cos_lb_ctx_free_output
 
struct  hwrm_ring_alloc_input
 
struct  hwrm_ring_alloc_output
 
struct  hwrm_ring_free_input
 
struct  hwrm_ring_free_output
 
struct  hwrm_ring_reset_input
 
struct  hwrm_ring_reset_output
 
struct  hwrm_ring_aggint_qcaps_input
 
struct  hwrm_ring_aggint_qcaps_output
 
struct  hwrm_ring_cmpl_ring_qaggint_params_input
 
struct  hwrm_ring_cmpl_ring_qaggint_params_output
 
struct  hwrm_ring_cmpl_ring_cfg_aggint_params_input
 
struct  hwrm_ring_cmpl_ring_cfg_aggint_params_output
 
struct  hwrm_ring_grp_alloc_input
 
struct  hwrm_ring_grp_alloc_output
 
struct  hwrm_ring_grp_free_input
 
struct  hwrm_ring_grp_free_output
 
struct  hwrm_cfa_l2_filter_alloc_input
 
struct  hwrm_cfa_l2_filter_alloc_output
 
struct  hwrm_cfa_l2_filter_free_input
 
struct  hwrm_cfa_l2_filter_free_output
 
struct  hwrm_cfa_l2_filter_cfg_input
 
struct  hwrm_cfa_l2_filter_cfg_output
 
struct  hwrm_cfa_l2_set_rx_mask_input
 
struct  hwrm_cfa_l2_set_rx_mask_output
 
struct  hwrm_cfa_l2_set_rx_mask_cmd_err
 
struct  hwrm_cfa_vlan_antispoof_cfg_input
 
struct  hwrm_cfa_vlan_antispoof_cfg_output
 
struct  hwrm_cfa_vlan_antispoof_qcfg_input
 
struct  hwrm_cfa_vlan_antispoof_qcfg_output
 
struct  hwrm_cfa_tunnel_filter_alloc_input
 
struct  hwrm_cfa_tunnel_filter_alloc_output
 
struct  hwrm_cfa_tunnel_filter_free_input
 
struct  hwrm_cfa_tunnel_filter_free_output
 
struct  hwrm_cfa_redirect_tunnel_type_alloc_input
 
struct  hwrm_cfa_redirect_tunnel_type_alloc_output
 
struct  hwrm_cfa_redirect_tunnel_type_free_input
 
struct  hwrm_cfa_redirect_tunnel_type_free_output
 
struct  hwrm_cfa_redirect_tunnel_type_info_input
 
struct  hwrm_cfa_redirect_tunnel_type_info_output
 
struct  hwrm_vxlan_ipv4_hdr
 
struct  hwrm_vxlan_ipv6_hdr
 
struct  hwrm_cfa_encap_data_vxlan
 
struct  hwrm_cfa_encap_record_alloc_input
 
struct  hwrm_cfa_encap_record_alloc_output
 
struct  hwrm_cfa_encap_record_free_input
 
struct  hwrm_cfa_encap_record_free_output
 
struct  hwrm_cfa_ntuple_filter_alloc_input
 
struct  hwrm_cfa_ntuple_filter_alloc_output
 
struct  hwrm_cfa_ntuple_filter_alloc_cmd_err
 
struct  hwrm_cfa_ntuple_filter_free_input
 
struct  hwrm_cfa_ntuple_filter_free_output
 
struct  hwrm_cfa_ntuple_filter_cfg_input
 
struct  hwrm_cfa_ntuple_filter_cfg_output
 
struct  hwrm_cfa_em_flow_alloc_input
 
struct  hwrm_cfa_em_flow_alloc_output
 
struct  hwrm_cfa_em_flow_free_input
 
struct  hwrm_cfa_em_flow_free_output
 
struct  hwrm_cfa_em_flow_cfg_input
 
struct  hwrm_cfa_em_flow_cfg_output
 
struct  hwrm_cfa_meter_profile_alloc_input
 
struct  hwrm_cfa_meter_profile_alloc_output
 
struct  hwrm_cfa_meter_profile_free_input
 
struct  hwrm_cfa_meter_profile_free_output
 
struct  hwrm_cfa_meter_profile_cfg_input
 
struct  hwrm_cfa_meter_profile_cfg_output
 
struct  hwrm_cfa_meter_instance_alloc_input
 
struct  hwrm_cfa_meter_instance_alloc_output
 
struct  hwrm_cfa_meter_instance_free_input
 
struct  hwrm_cfa_meter_instance_free_output
 
struct  hwrm_cfa_decap_filter_alloc_input
 
struct  hwrm_cfa_decap_filter_alloc_output
 
struct  hwrm_cfa_decap_filter_free_input
 
struct  hwrm_cfa_decap_filter_free_output
 
struct  hwrm_cfa_flow_alloc_input
 
struct  hwrm_cfa_flow_alloc_output
 
struct  hwrm_cfa_flow_free_input
 
struct  hwrm_cfa_flow_free_output
 
struct  hwrm_cfa_flow_info_input
 
struct  hwrm_cfa_flow_info_output
 
struct  hwrm_cfa_flow_flush_input
 
struct  hwrm_cfa_flow_flush_output
 
struct  hwrm_cfa_flow_stats_input
 
struct  hwrm_cfa_flow_stats_output
 
struct  hwrm_cfa_flow_aging_timer_reset_input
 
struct  hwrm_cfa_flow_aging_timer_reset_output
 
struct  hwrm_cfa_flow_aging_cfg_input
 
struct  hwrm_cfa_flow_aging_cfg_output
 
struct  hwrm_cfa_flow_aging_qcfg_input
 
struct  hwrm_cfa_flow_aging_qcfg_output
 
struct  hwrm_cfa_flow_aging_qcaps_input
 
struct  hwrm_cfa_flow_aging_qcaps_output
 
struct  hwrm_cfa_vf_pair_alloc_input
 
struct  hwrm_cfa_vf_pair_alloc_output
 
struct  hwrm_cfa_vf_pair_free_input
 
struct  hwrm_cfa_vf_pair_free_output
 
struct  hwrm_cfa_vf_pair_info_input
 
struct  hwrm_cfa_vf_pair_info_output
 
struct  hwrm_cfa_pair_alloc_input
 
struct  hwrm_cfa_pair_alloc_output
 
struct  hwrm_cfa_pair_free_input
 
struct  hwrm_cfa_pair_free_output
 
struct  hwrm_cfa_pair_info_input
 
struct  hwrm_cfa_pair_info_output
 
struct  hwrm_cfa_vfr_alloc_input
 
struct  hwrm_cfa_vfr_alloc_output
 
struct  hwrm_cfa_vfr_free_input
 
struct  hwrm_cfa_vfr_free_output
 
struct  hwrm_cfa_redirect_query_tunnel_type_input
 
struct  hwrm_cfa_redirect_query_tunnel_type_output
 
struct  hwrm_tunnel_dst_port_query_input
 
struct  hwrm_tunnel_dst_port_query_output
 
struct  hwrm_tunnel_dst_port_alloc_input
 
struct  hwrm_tunnel_dst_port_alloc_output
 
struct  hwrm_tunnel_dst_port_free_input
 
struct  hwrm_tunnel_dst_port_free_output
 
struct  ctx_hw_stats
 
struct  ctx_eng_stats
 
struct  hwrm_stat_ctx_alloc_input
 
struct  hwrm_stat_ctx_alloc_output
 
struct  hwrm_stat_ctx_free_input
 
struct  hwrm_stat_ctx_free_output
 
struct  hwrm_stat_ctx_query_input
 
struct  hwrm_stat_ctx_query_output
 
struct  hwrm_stat_ctx_eng_query_input
 
struct  hwrm_stat_ctx_eng_query_output
 
struct  hwrm_stat_ctx_clr_stats_input
 
struct  hwrm_stat_ctx_clr_stats_output
 
struct  hwrm_pcie_qstats_input
 
struct  hwrm_pcie_qstats_output
 
struct  pcie_ctx_hw_stats
 
struct  hwrm_fw_reset_input
 
struct  hwrm_fw_reset_output
 
struct  hwrm_fw_qstatus_input
 
struct  hwrm_fw_qstatus_output
 
struct  hwrm_fw_set_time_input
 
struct  hwrm_fw_set_time_output
 
struct  hwrm_fw_get_time_input
 
struct  hwrm_fw_get_time_output
 
struct  hwrm_struct_hdr
 
struct  hwrm_struct_data_dcbx_ets
 
struct  hwrm_struct_data_dcbx_pfc
 
struct  hwrm_struct_data_dcbx_app
 
struct  hwrm_struct_data_dcbx_feature_state
 
struct  hwrm_struct_data_lldp
 
struct  hwrm_struct_data_lldp_generic
 
struct  hwrm_struct_data_lldp_device
 
struct  hwrm_struct_data_port_description
 
struct  hwrm_struct_data_rss_v2
 
struct  hwrm_struct_data_power_information
 
struct  hwrm_fw_set_structured_data_input
 
struct  hwrm_fw_set_structured_data_output
 
struct  hwrm_fw_set_structured_data_cmd_err
 
struct  hwrm_fw_get_structured_data_input
 
struct  hwrm_fw_get_structured_data_output
 
struct  hwrm_fw_get_structured_data_cmd_err
 
struct  hwrm_fw_ipc_msg_input
 
struct  hwrm_fw_ipc_msg_output
 
struct  hwrm_fw_ipc_mailbox_input
 
struct  hwrm_fw_ipc_mailbox_output
 
struct  hwrm_fw_ipc_mailbox_cmd_err
 
struct  hwrm_fw_health_check_input
 
struct  hwrm_fw_health_check_output
 
struct  hwrm_fw_sync_input
 
struct  hwrm_fw_sync_output
 
struct  hwrm_exec_fwd_resp_input
 
struct  hwrm_exec_fwd_resp_output
 
struct  hwrm_reject_fwd_resp_input
 
struct  hwrm_reject_fwd_resp_output
 
struct  hwrm_fwd_resp_input
 
struct  hwrm_fwd_resp_output
 
struct  hwrm_fwd_async_event_cmpl_input
 
struct  hwrm_fwd_async_event_cmpl_output
 
struct  hwrm_temp_monitor_query_input
 
struct  hwrm_temp_monitor_query_output
 
struct  hwrm_wol_filter_alloc_input
 
struct  hwrm_wol_filter_alloc_output
 
struct  hwrm_wol_filter_free_input
 
struct  hwrm_wol_filter_free_output
 
struct  hwrm_wol_filter_qcfg_input
 
struct  hwrm_wol_filter_qcfg_output
 
struct  hwrm_wol_reason_qcfg_input
 
struct  hwrm_wol_reason_qcfg_output
 
struct  hwrm_dbg_read_direct_input
 
struct  hwrm_dbg_read_direct_output
 
struct  hwrm_dbg_write_direct_input
 
struct  hwrm_dbg_write_direct_output
 
struct  hwrm_dbg_read_indirect_input
 
struct  hwrm_dbg_read_indirect_output
 
struct  hwrm_dbg_write_indirect_input
 
struct  hwrm_dbg_write_indirect_output
 
struct  hwrm_dbg_dump_input
 
struct  hwrm_dbg_dump_output
 
struct  hwrm_dbg_erase_nvm_input
 
struct  hwrm_dbg_erase_nvm_output
 
struct  hwrm_dbg_cfg_input
 
struct  hwrm_dbg_cfg_output
 
struct  coredump_segment_record
 
struct  hwrm_dbg_coredump_list_input
 
struct  hwrm_dbg_coredump_list_output
 
struct  hwrm_dbg_coredump_initiate_input
 
struct  hwrm_dbg_coredump_initiate_output
 
struct  coredump_data_hdr
 
struct  hwrm_dbg_coredump_retrieve_input
 
struct  hwrm_dbg_coredump_retrieve_output
 
struct  hwrm_dbg_i2c_cmd_input
 
struct  hwrm_dbg_i2c_cmd_output
 
struct  hwrm_dbg_fw_cli_input
 
struct  hwrm_dbg_fw_cli_output
 
struct  hwrm_dbg_ring_info_get_input
 
struct  hwrm_dbg_ring_info_get_output
 
struct  hwrm_nvm_raw_write_blk_input
 
struct  hwrm_nvm_raw_write_blk_output
 
struct  hwrm_nvm_read_input
 
struct  hwrm_nvm_read_output
 
struct  hwrm_nvm_raw_dump_input
 
struct  hwrm_nvm_raw_dump_output
 
struct  hwrm_nvm_get_dir_entries_input
 
struct  hwrm_nvm_get_dir_entries_output
 
struct  hwrm_nvm_get_dir_info_input
 
struct  hwrm_nvm_get_dir_info_output
 
struct  hwrm_nvm_write_input
 
struct  hwrm_nvm_write_output
 
struct  hwrm_nvm_write_cmd_err
 
struct  hwrm_nvm_modify_input
 
struct  hwrm_nvm_modify_output
 
struct  hwrm_nvm_find_dir_entry_input
 
struct  hwrm_nvm_find_dir_entry_output
 
struct  hwrm_nvm_erase_dir_entry_input
 
struct  hwrm_nvm_erase_dir_entry_output
 
struct  hwrm_nvm_get_dev_info_input
 
struct  hwrm_nvm_get_dev_info_output
 
struct  hwrm_nvm_mod_dir_entry_input
 
struct  hwrm_nvm_mod_dir_entry_output
 
struct  hwrm_nvm_verify_update_input
 
struct  hwrm_nvm_verify_update_output
 
struct  hwrm_nvm_install_update_input
 
struct  hwrm_nvm_install_update_output
 
struct  hwrm_nvm_install_update_cmd_err
 
struct  hwrm_nvm_flush_input
 
struct  hwrm_nvm_flush_output
 
struct  hwrm_nvm_flush_cmd_err
 
struct  hwrm_nvm_get_variable_input
 
struct  hwrm_nvm_get_variable_output
 
struct  hwrm_nvm_get_variable_cmd_err
 
struct  hwrm_nvm_set_variable_input
 
struct  hwrm_nvm_set_variable_output
 
struct  hwrm_nvm_set_variable_cmd_err
 
struct  hwrm_nvm_validate_option_input
 
struct  hwrm_nvm_validate_option_output
 
struct  hwrm_nvm_validate_option_cmd_err
 
struct  hwrm_nvm_factory_defaults_input
 
struct  hwrm_nvm_factory_defaults_output
 
struct  hwrm_nvm_factory_defaults_cmd_err
 
struct  hwrm_selftest_qlist_input
 
struct  hwrm_selftest_qlist_output
 
struct  hwrm_selftest_exec_input
 
struct  hwrm_selftest_exec_output
 
struct  hwrm_selftest_irq_input
 
struct  hwrm_selftest_irq_output
 
struct  hwrm_selftest_retrieve_serdes_data_input
 
struct  hwrm_selftest_retrieve_serdes_data_output
 
struct  hwrm_oem_cmd_input
 
struct  hwrm_oem_cmd_output
 

Macros

#define CMD_DISCR_TLV_ENCAP   0x8000UL
 
#define CMD_DISCR_LAST   CMD_DISCR_TLV_ENCAP
 
#define TLV_TYPE_HWRM_REQUEST   0x1UL
 
#define TLV_TYPE_HWRM_RESPONSE   0x2UL
 
#define TLV_TYPE_ROCE_SP_COMMAND   0x3UL
 
#define TLV_TYPE_QUERY_ROCE_CC_GEN1   0x4UL
 
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1   0x5UL
 
#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER   0x8001UL
 
#define TLV_TYPE_ENGINE_CKV_NONCE   0x8002UL
 
#define TLV_TYPE_ENGINE_CKV_IV   0x8003UL
 
#define TLV_TYPE_ENGINE_CKV_AUTH_TAG   0x8004UL
 
#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT   0x8005UL
 
#define TLV_TYPE_ENGINE_CKV_ALGORITHMS   0x8006UL
 
#define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY   0x8007UL
 
#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE   0x8008UL
 
#define TLV_TYPE_LAST   TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
 
#define TLV_FLAGS_MORE   0x1UL
 
#define TLV_FLAGS_MORE_LAST   0x0UL
 
#define TLV_FLAGS_MORE_NOT_LAST   0x1UL
 
#define TLV_FLAGS_REQUIRED   0x2UL
 
#define TLV_FLAGS_REQUIRED_NO   (0x0UL << 1)
 
#define TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)
 
#define TLV_FLAGS_REQUIRED_LAST   TLV_FLAGS_REQUIRED_YES
 
#define SHORT_REQ_SIGNATURE_SHORT_CMD   0x4321UL
 
#define SHORT_REQ_SIGNATURE_LAST   SHORT_REQ_SIGNATURE_SHORT_CMD
 
#define HWRM_VER_GET   0x0UL
 
#define HWRM_FUNC_DRV_IF_CHANGE   0xdUL
 
#define HWRM_FUNC_BUF_UNRGTR   0xeUL
 
#define HWRM_FUNC_VF_CFG   0xfUL
 
#define HWRM_RESERVED1   0x10UL
 
#define HWRM_FUNC_RESET   0x11UL
 
#define HWRM_FUNC_GETFID   0x12UL
 
#define HWRM_FUNC_VF_ALLOC   0x13UL
 
#define HWRM_FUNC_VF_FREE   0x14UL
 
#define HWRM_FUNC_QCAPS   0x15UL
 
#define HWRM_FUNC_QCFG   0x16UL
 
#define HWRM_FUNC_CFG   0x17UL
 
#define HWRM_FUNC_QSTATS   0x18UL
 
#define HWRM_FUNC_CLR_STATS   0x19UL
 
#define HWRM_FUNC_DRV_UNRGTR   0x1aUL
 
#define HWRM_FUNC_VF_RESC_FREE   0x1bUL
 
#define HWRM_FUNC_VF_VNIC_IDS_QUERY   0x1cUL
 
#define HWRM_FUNC_DRV_RGTR   0x1dUL
 
#define HWRM_FUNC_DRV_QVER   0x1eUL
 
#define HWRM_FUNC_BUF_RGTR   0x1fUL
 
#define HWRM_PORT_PHY_CFG   0x20UL
 
#define HWRM_PORT_MAC_CFG   0x21UL
 
#define HWRM_PORT_TS_QUERY   0x22UL
 
#define HWRM_PORT_QSTATS   0x23UL
 
#define HWRM_PORT_LPBK_QSTATS   0x24UL
 
#define HWRM_PORT_CLR_STATS   0x25UL
 
#define HWRM_PORT_LPBK_CLR_STATS   0x26UL
 
#define HWRM_PORT_PHY_QCFG   0x27UL
 
#define HWRM_PORT_MAC_QCFG   0x28UL
 
#define HWRM_PORT_MAC_PTP_QCFG   0x29UL
 
#define HWRM_PORT_PHY_QCAPS   0x2aUL
 
#define HWRM_PORT_PHY_I2C_WRITE   0x2bUL
 
#define HWRM_PORT_PHY_I2C_READ   0x2cUL
 
#define HWRM_PORT_LED_CFG   0x2dUL
 
#define HWRM_PORT_LED_QCFG   0x2eUL
 
#define HWRM_PORT_LED_QCAPS   0x2fUL
 
#define HWRM_QUEUE_QPORTCFG   0x30UL
 
#define HWRM_QUEUE_QCFG   0x31UL
 
#define HWRM_QUEUE_CFG   0x32UL
 
#define HWRM_FUNC_VLAN_CFG   0x33UL
 
#define HWRM_FUNC_VLAN_QCFG   0x34UL
 
#define HWRM_QUEUE_PFCENABLE_QCFG   0x35UL
 
#define HWRM_QUEUE_PFCENABLE_CFG   0x36UL
 
#define HWRM_QUEUE_PRI2COS_QCFG   0x37UL
 
#define HWRM_QUEUE_PRI2COS_CFG   0x38UL
 
#define HWRM_QUEUE_COS2BW_QCFG   0x39UL
 
#define HWRM_QUEUE_COS2BW_CFG   0x3aUL
 
#define HWRM_QUEUE_DSCP_QCAPS   0x3bUL
 
#define HWRM_QUEUE_DSCP2PRI_QCFG   0x3cUL
 
#define HWRM_QUEUE_DSCP2PRI_CFG   0x3dUL
 
#define HWRM_VNIC_ALLOC   0x40UL
 
#define HWRM_VNIC_FREE   0x41UL
 
#define HWRM_VNIC_CFG   0x42UL
 
#define HWRM_VNIC_QCFG   0x43UL
 
#define HWRM_VNIC_TPA_CFG   0x44UL
 
#define HWRM_VNIC_TPA_QCFG   0x45UL
 
#define HWRM_VNIC_RSS_CFG   0x46UL
 
#define HWRM_VNIC_RSS_QCFG   0x47UL
 
#define HWRM_VNIC_PLCMODES_CFG   0x48UL
 
#define HWRM_VNIC_PLCMODES_QCFG   0x49UL
 
#define HWRM_VNIC_QCAPS   0x4aUL
 
#define HWRM_RING_ALLOC   0x50UL
 
#define HWRM_RING_FREE   0x51UL
 
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS   0x52UL
 
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS   0x53UL
 
#define HWRM_RING_AGGINT_QCAPS   0x54UL
 
#define HWRM_RING_RESET   0x5eUL
 
#define HWRM_RING_GRP_ALLOC   0x60UL
 
#define HWRM_RING_GRP_FREE   0x61UL
 
#define HWRM_RESERVED5   0x64UL
 
#define HWRM_RESERVED6   0x65UL
 
#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC   0x70UL
 
#define HWRM_VNIC_RSS_COS_LB_CTX_FREE   0x71UL
 
#define HWRM_CFA_L2_FILTER_ALLOC   0x90UL
 
#define HWRM_CFA_L2_FILTER_FREE   0x91UL
 
#define HWRM_CFA_L2_FILTER_CFG   0x92UL
 
#define HWRM_CFA_L2_SET_RX_MASK   0x93UL
 
#define HWRM_CFA_VLAN_ANTISPOOF_CFG   0x94UL
 
#define HWRM_CFA_TUNNEL_FILTER_ALLOC   0x95UL
 
#define HWRM_CFA_TUNNEL_FILTER_FREE   0x96UL
 
#define HWRM_CFA_ENCAP_RECORD_ALLOC   0x97UL
 
#define HWRM_CFA_ENCAP_RECORD_FREE   0x98UL
 
#define HWRM_CFA_NTUPLE_FILTER_ALLOC   0x99UL
 
#define HWRM_CFA_NTUPLE_FILTER_FREE   0x9aUL
 
#define HWRM_CFA_NTUPLE_FILTER_CFG   0x9bUL
 
#define HWRM_CFA_EM_FLOW_ALLOC   0x9cUL
 
#define HWRM_CFA_EM_FLOW_FREE   0x9dUL
 
#define HWRM_CFA_EM_FLOW_CFG   0x9eUL
 
#define HWRM_TUNNEL_DST_PORT_QUERY   0xa0UL
 
#define HWRM_TUNNEL_DST_PORT_ALLOC   0xa1UL
 
#define HWRM_TUNNEL_DST_PORT_FREE   0xa2UL
 
#define HWRM_STAT_CTX_ENG_QUERY   0xafUL
 
#define HWRM_STAT_CTX_ALLOC   0xb0UL
 
#define HWRM_STAT_CTX_FREE   0xb1UL
 
#define HWRM_STAT_CTX_QUERY   0xb2UL
 
#define HWRM_STAT_CTX_CLR_STATS   0xb3UL
 
#define HWRM_PORT_QSTATS_EXT   0xb4UL
 
#define HWRM_FW_RESET   0xc0UL
 
#define HWRM_FW_QSTATUS   0xc1UL
 
#define HWRM_FW_HEALTH_CHECK   0xc2UL
 
#define HWRM_FW_SYNC   0xc3UL
 
#define HWRM_FW_SET_TIME   0xc8UL
 
#define HWRM_FW_GET_TIME   0xc9UL
 
#define HWRM_FW_SET_STRUCTURED_DATA   0xcaUL
 
#define HWRM_FW_GET_STRUCTURED_DATA   0xcbUL
 
#define HWRM_FW_IPC_MAILBOX   0xccUL
 
#define HWRM_EXEC_FWD_RESP   0xd0UL
 
#define HWRM_REJECT_FWD_RESP   0xd1UL
 
#define HWRM_FWD_RESP   0xd2UL
 
#define HWRM_FWD_ASYNC_EVENT_CMPL   0xd3UL
 
#define HWRM_OEM_CMD   0xd4UL
 
#define HWRM_TEMP_MONITOR_QUERY   0xe0UL
 
#define HWRM_WOL_FILTER_ALLOC   0xf0UL
 
#define HWRM_WOL_FILTER_FREE   0xf1UL
 
#define HWRM_WOL_FILTER_QCFG   0xf2UL
 
#define HWRM_WOL_REASON_QCFG   0xf3UL
 
#define HWRM_CFA_METER_PROFILE_ALLOC   0xf5UL
 
#define HWRM_CFA_METER_PROFILE_FREE   0xf6UL
 
#define HWRM_CFA_METER_PROFILE_CFG   0xf7UL
 
#define HWRM_CFA_METER_INSTANCE_ALLOC   0xf8UL
 
#define HWRM_CFA_METER_INSTANCE_FREE   0xf9UL
 
#define HWRM_CFA_VFR_ALLOC   0xfdUL
 
#define HWRM_CFA_VFR_FREE   0xfeUL
 
#define HWRM_CFA_VF_PAIR_ALLOC   0x100UL
 
#define HWRM_CFA_VF_PAIR_FREE   0x101UL
 
#define HWRM_CFA_VF_PAIR_INFO   0x102UL
 
#define HWRM_CFA_FLOW_ALLOC   0x103UL
 
#define HWRM_CFA_FLOW_FREE   0x104UL
 
#define HWRM_CFA_FLOW_FLUSH   0x105UL
 
#define HWRM_CFA_FLOW_STATS   0x106UL
 
#define HWRM_CFA_FLOW_INFO   0x107UL
 
#define HWRM_CFA_DECAP_FILTER_ALLOC   0x108UL
 
#define HWRM_CFA_DECAP_FILTER_FREE   0x109UL
 
#define HWRM_CFA_VLAN_ANTISPOOF_QCFG   0x10aUL
 
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC   0x10bUL
 
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE   0x10cUL
 
#define HWRM_CFA_PAIR_ALLOC   0x10dUL
 
#define HWRM_CFA_PAIR_FREE   0x10eUL
 
#define HWRM_CFA_PAIR_INFO   0x10fUL
 
#define HWRM_FW_IPC_MSG   0x110UL
 
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO   0x111UL
 
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE   0x112UL
 
#define HWRM_CFA_FLOW_AGING_TIMER_RESET   0x113UL
 
#define HWRM_CFA_FLOW_AGING_CFG   0x114UL
 
#define HWRM_CFA_FLOW_AGING_QCFG   0x115UL
 
#define HWRM_CFA_FLOW_AGING_QCAPS   0x116UL
 
#define HWRM_ENGINE_CKV_HELLO   0x12dUL
 
#define HWRM_ENGINE_CKV_STATUS   0x12eUL
 
#define HWRM_ENGINE_CKV_CKEK_ADD   0x12fUL
 
#define HWRM_ENGINE_CKV_CKEK_DELETE   0x130UL
 
#define HWRM_ENGINE_CKV_KEY_ADD   0x131UL
 
#define HWRM_ENGINE_CKV_KEY_DELETE   0x132UL
 
#define HWRM_ENGINE_CKV_FLUSH   0x133UL
 
#define HWRM_ENGINE_CKV_RNG_GET   0x134UL
 
#define HWRM_ENGINE_CKV_KEY_GEN   0x135UL
 
#define HWRM_ENGINE_QG_CONFIG_QUERY   0x13cUL
 
#define HWRM_ENGINE_QG_QUERY   0x13dUL
 
#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY   0x13eUL
 
#define HWRM_ENGINE_QG_METER_PROFILE_QUERY   0x13fUL
 
#define HWRM_ENGINE_QG_METER_PROFILE_ALLOC   0x140UL
 
#define HWRM_ENGINE_QG_METER_PROFILE_FREE   0x141UL
 
#define HWRM_ENGINE_QG_METER_QUERY   0x142UL
 
#define HWRM_ENGINE_QG_METER_BIND   0x143UL
 
#define HWRM_ENGINE_QG_METER_UNBIND   0x144UL
 
#define HWRM_ENGINE_QG_FUNC_BIND   0x145UL
 
#define HWRM_ENGINE_SG_CONFIG_QUERY   0x146UL
 
#define HWRM_ENGINE_SG_QUERY   0x147UL
 
#define HWRM_ENGINE_SG_METER_QUERY   0x148UL
 
#define HWRM_ENGINE_SG_METER_CONFIG   0x149UL
 
#define HWRM_ENGINE_SG_QG_BIND   0x14aUL
 
#define HWRM_ENGINE_QG_SG_UNBIND   0x14bUL
 
#define HWRM_ENGINE_CONFIG_QUERY   0x154UL
 
#define HWRM_ENGINE_STATS_CONFIG   0x155UL
 
#define HWRM_ENGINE_STATS_CLEAR   0x156UL
 
#define HWRM_ENGINE_STATS_QUERY   0x157UL
 
#define HWRM_ENGINE_RQ_ALLOC   0x15eUL
 
#define HWRM_ENGINE_RQ_FREE   0x15fUL
 
#define HWRM_ENGINE_CQ_ALLOC   0x160UL
 
#define HWRM_ENGINE_CQ_FREE   0x161UL
 
#define HWRM_ENGINE_NQ_ALLOC   0x162UL
 
#define HWRM_ENGINE_NQ_FREE   0x163UL
 
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS   0x164UL
 
#define HWRM_FUNC_RESOURCE_QCAPS   0x190UL
 
#define HWRM_FUNC_VF_RESOURCE_CFG   0x191UL
 
#define HWRM_FUNC_BACKING_STORE_QCAPS   0x192UL
 
#define HWRM_FUNC_BACKING_STORE_CFG   0x193UL
 
#define HWRM_FUNC_BACKING_STORE_QCFG   0x194UL
 
#define HWRM_FUNC_VF_BW_CFG   0x195UL
 
#define HWRM_FUNC_VF_BW_QCFG   0x196UL
 
#define HWRM_SELFTEST_QLIST   0x200UL
 
#define HWRM_SELFTEST_EXEC   0x201UL
 
#define HWRM_SELFTEST_IRQ   0x202UL
 
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA   0x203UL
 
#define HWRM_PCIE_QSTATS   0x204UL
 
#define HWRM_DBG_READ_DIRECT   0xff10UL
 
#define HWRM_DBG_READ_INDIRECT   0xff11UL
 
#define HWRM_DBG_WRITE_DIRECT   0xff12UL
 
#define HWRM_DBG_WRITE_INDIRECT   0xff13UL
 
#define HWRM_DBG_DUMP   0xff14UL
 
#define HWRM_DBG_ERASE_NVM   0xff15UL
 
#define HWRM_DBG_CFG   0xff16UL
 
#define HWRM_DBG_COREDUMP_LIST   0xff17UL
 
#define HWRM_DBG_COREDUMP_INITIATE   0xff18UL
 
#define HWRM_DBG_COREDUMP_RETRIEVE   0xff19UL
 
#define HWRM_DBG_FW_CLI   0xff1aUL
 
#define HWRM_DBG_I2C_CMD   0xff1bUL
 
#define HWRM_DBG_RING_INFO_GET   0xff1cUL
 
#define HWRM_NVM_FACTORY_DEFAULTS   0xffeeUL
 
#define HWRM_NVM_VALIDATE_OPTION   0xffefUL
 
#define HWRM_NVM_FLUSH   0xfff0UL
 
#define HWRM_NVM_GET_VARIABLE   0xfff1UL
 
#define HWRM_NVM_SET_VARIABLE   0xfff2UL
 
#define HWRM_NVM_INSTALL_UPDATE   0xfff3UL
 
#define HWRM_NVM_MODIFY   0xfff4UL
 
#define HWRM_NVM_VERIFY_UPDATE   0xfff5UL
 
#define HWRM_NVM_GET_DEV_INFO   0xfff6UL
 
#define HWRM_NVM_ERASE_DIR_ENTRY   0xfff7UL
 
#define HWRM_NVM_MOD_DIR_ENTRY   0xfff8UL
 
#define HWRM_NVM_FIND_DIR_ENTRY   0xfff9UL
 
#define HWRM_NVM_GET_DIR_ENTRIES   0xfffaUL
 
#define HWRM_NVM_GET_DIR_INFO   0xfffbUL
 
#define HWRM_NVM_RAW_DUMP   0xfffcUL
 
#define HWRM_NVM_READ   0xfffdUL
 
#define HWRM_NVM_WRITE   0xfffeUL
 
#define HWRM_NVM_RAW_WRITE_BLK   0xffffUL
 
#define HWRM_LAST   HWRM_NVM_RAW_WRITE_BLK
 
#define HWRM_ERR_CODE_SUCCESS   0x0UL
 
#define HWRM_ERR_CODE_FAIL   0x1UL
 
#define HWRM_ERR_CODE_INVALID_PARAMS   0x2UL
 
#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED   0x3UL
 
#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR   0x4UL
 
#define HWRM_ERR_CODE_INVALID_FLAGS   0x5UL
 
#define HWRM_ERR_CODE_INVALID_ENABLES   0x6UL
 
#define HWRM_ERR_CODE_UNSUPPORTED_TLV   0x7UL
 
#define HWRM_ERR_CODE_NO_BUFFER   0x8UL
 
#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR   0x9UL
 
#define HWRM_ERR_CODE_HOT_RESET_PROGRESS   0xaUL
 
#define HWRM_ERR_CODE_HOT_RESET_FAIL   0xbUL
 
#define HWRM_ERR_CODE_HWRM_ERROR   0xfUL
 
#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE   0x8000UL
 
#define HWRM_ERR_CODE_UNKNOWN_ERR   0xfffeUL
 
#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED   0xffffUL
 
#define HWRM_ERR_CODE_LAST   HWRM_ERR_CODE_CMD_NOT_SUPPORTED
 
#define HWRM_NA_SIGNATURE   ((__le32)(-1))
 
#define HWRM_MAX_REQ_LEN   128
 
#define HWRM_MAX_RESP_LEN   280
 
#define HW_HASH_INDEX_SIZE   0x80
 
#define HW_HASH_KEY_SIZE   40
 
#define HWRM_RESP_VALID_KEY   1
 
#define HWRM_VERSION_MAJOR   1
 
#define HWRM_VERSION_MINOR   10
 
#define HWRM_VERSION_UPDATE   0
 
#define HWRM_VERSION_RSVD   18
 
#define HWRM_VERSION_STR   "1.10.0.18"
 
#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED   0x1UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED   0x2UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED   0x4UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED   0x8UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED   0x10UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED   0x20UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED   0x40UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED   0x80UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED   0x100UL
 
#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED   0x200UL
 
#define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC   0x0UL
 
#define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA   0x1UL
 
#define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM   0x2UL
 
#define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST   VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
 
#define VER_GET_RESP_FLAGS_DEV_NOT_RDY   0x1UL
 
#define VER_GET_RESP_FLAGS_EXT_VER_AVAIL   0x2UL
 
#define EJECT_CMPL_TYPE_MASK   0x3fUL
 
#define EJECT_CMPL_TYPE_SFT   0
 
#define EJECT_CMPL_TYPE_STAT_EJECT   0x1aUL
 
#define EJECT_CMPL_TYPE_LAST   EJECT_CMPL_TYPE_STAT_EJECT
 
#define EJECT_CMPL_FLAGS_MASK   0xffc0UL
 
#define EJECT_CMPL_FLAGS_SFT   6
 
#define EJECT_CMPL_FLAGS_ERROR   0x40UL
 
#define EJECT_CMPL_V   0x1UL
 
#define EJECT_CMPL_ERRORS_MASK   0xfffeUL
 
#define EJECT_CMPL_ERRORS_SFT   1
 
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK   0xeUL
 
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT   1
 
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER   (0x0UL << 1)
 
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (0x1UL << 1)
 
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT   (0x3UL << 1)
 
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH   (0x5UL << 1)
 
#define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST   EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
 
#define CMPL_TYPE_MASK   0x3fUL
 
#define CMPL_TYPE_SFT   0
 
#define CMPL_TYPE_HWRM_DONE   0x20UL
 
#define CMPL_TYPE_LAST   CMPL_TYPE_HWRM_DONE
 
#define CMPL_V   0x1UL
 
#define FWD_REQ_CMPL_TYPE_MASK   0x3fUL
 
#define FWD_REQ_CMPL_TYPE_SFT   0
 
#define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ   0x22UL
 
#define FWD_REQ_CMPL_TYPE_LAST   FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
 
#define FWD_REQ_CMPL_REQ_LEN_MASK   0xffc0UL
 
#define FWD_REQ_CMPL_REQ_LEN_SFT   6
 
#define FWD_REQ_CMPL_V   0x1UL
 
#define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK   0xfffffffeUL
 
#define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT   1
 
#define FWD_RESP_CMPL_TYPE_MASK   0x3fUL
 
#define FWD_RESP_CMPL_TYPE_SFT   0
 
#define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP   0x24UL
 
#define FWD_RESP_CMPL_TYPE_LAST   FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
 
#define FWD_RESP_CMPL_V   0x1UL
 
#define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK   0xfffffffeUL
 
#define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT   1
 
#define ASYNC_EVENT_CMPL_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_TYPE_LAST   ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE   0x0UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE   0x1UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE   0x2UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE   0x3UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED   0x4UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED   0x5UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE   0x6UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE   0x7UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY   0x8UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD   0x10UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD   0x11UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT   0x12UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD   0x20UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD   0x21UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR   0x30UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE   0x31UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE   0x32UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE   0x33UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE   0x34UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE   0x35UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED   0x36UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION   0x37UL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG   0xfeUL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR   0xffUL
 
#define ASYNC_EVENT_CMPL_EVENT_ID_LAST   ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
 
#define ASYNC_EVENT_CMPL_V   0x1UL
 
#define ASYNC_EVENT_CMPL_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE   0x0UL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN   0x0UL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST   ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK   0xeUL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT   1
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK   0xffff0UL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT   4
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK   0xff00000UL
 
#define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT   20
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT   0
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE   0x2UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK   0xfffeUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT   1
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB   (0x1UL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB   (0xaUL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB   (0x14UL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB   (0x19UL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB   (0x64UL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB   (0xc8UL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB   (0xfaUL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB   (0x190UL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB   (0x1f4UL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB   (0x3e8UL << 1)
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST   ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK   0xffff0000UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT   16
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE   0x3UL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS   0x1UL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC   0x2UL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP   0x4UL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK   0xff0000UL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT   16
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE   (0xffUL << 16)
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST   ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK   0xff000000UL
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT   24
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE   (0xffUL << 24)
 
#define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST   ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST   ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED   0x4UL
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST   ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V   0x1UL
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK   0xff0000UL
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT   16
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE   (0x0UL << 16)
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (0x1UL << 16)
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG   (0x2UL << 16)
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN   (0x3UL << 16)
 
#define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST   ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST   ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED   0x5UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST   ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE   0x6UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE   0x10000UL
 
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG   0x20000UL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE   0x7UL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE   0x10000UL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE   0x20000UL
 
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE   0x40000UL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST   ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY   0x8UL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_V   0x1UL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK   0xffUL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT   0
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE   0x1UL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN   0x2UL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK   0xff00UL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT   8
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST   (0x1UL << 8)
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL   (0x2UL << 8)
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL   (0x3UL << 8)
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK   0xffff0000UL
 
#define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT   16
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST   ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD   0x10UL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST   ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V   0x1UL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST   ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD   0x11UL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST   ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V   0x1UL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST   ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT   0x12UL
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST   ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V   0x1UL
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST   ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD   0x20UL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST   ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V   0x1UL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK   0x70000UL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT   16
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST   ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD   0x21UL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST   ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V   0x1UL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK   0x70000UL
 
#define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT   16
 
#define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST   ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR   0x30UL
 
#define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST   ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
 
#define ASYNC_EVENT_CMPL_VF_FLR_V   0x1UL
 
#define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK   0xff0000UL
 
#define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT   16
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE   0x31UL
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK   0xffffUL
 
#define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE   0x32UL
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED   0x1UL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE   0x33UL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE   0x1UL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE   0x2UL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE   0x4UL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE   0x8UL
 
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE   0x10UL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK   0xffc0UL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT   6
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE   0x34UL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK   0x3UL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT   0
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC   0x1UL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC   0x2UL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST   ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK   0x1cUL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT   2
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK   0x1fffe0UL
 
#define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT   5
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK   0xffc0UL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT   6
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION   0x35UL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V   0x1UL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK   0x3UL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT   0
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC   0x1UL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   0x2UL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK   0x3fcUL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT   2
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK   0x3fffc00UL
 
#define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT   10
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST   ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED   0x36UL
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST   ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V   0x1UL
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK   0x7fffffffUL
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT   0
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION   0x80000000UL
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX   (0x0UL << 31)
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX   (0x1UL << 31)
 
#define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST   ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK   0x3fUL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT   0
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT   0x2eUL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST   ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR   0xffUL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST   ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK   0xffUL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT   0
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING   0x0UL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL   0x1UL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL   0x2UL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST   ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_V   0x1UL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK   0xfeUL
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT   1
 
#define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP   0x1UL
 
#define FUNC_RESET_REQ_ENABLES_VF_ID_VALID   0x1UL
 
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL   0x0UL
 
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME   0x1UL
 
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN   0x2UL
 
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF   0x3UL
 
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST   FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
 
#define FUNC_GETFID_REQ_ENABLES_PCI_ID   0x1UL
 
#define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID   0x1UL
 
#define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID   0x1UL
 
#define FUNC_VF_CFG_REQ_ENABLES_MTU   0x1UL
 
#define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN   0x2UL
 
#define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR   0x4UL
 
#define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR   0x8UL
 
#define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS   0x10UL
 
#define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS   0x20UL
 
#define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS   0x40UL
 
#define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS   0x80UL
 
#define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS   0x100UL
 
#define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS   0x200UL
 
#define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS   0x400UL
 
#define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS   0x800UL
 
#define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST   0x1UL
 
#define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST   0x2UL
 
#define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST   0x4UL
 
#define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST   0x8UL
 
#define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST   0x10UL
 
#define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST   0x20UL
 
#define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST   0x40UL
 
#define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST   0x80UL
 
#define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED   0x1UL
 
#define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING   0x2UL
 
#define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED   0x4UL
 
#define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED   0x8UL
 
#define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED   0x10UL
 
#define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED   0x20UL
 
#define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED   0x40UL
 
#define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED   0x80UL
 
#define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED   0x100UL
 
#define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED   0x200UL
 
#define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED   0x400UL
 
#define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED   0x800UL
 
#define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED   0x1000UL
 
#define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED   0x2000UL
 
#define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED   0x4000UL
 
#define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED   0x8000UL
 
#define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED   0x10000UL
 
#define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED   0x20000UL
 
#define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED   0x40000UL
 
#define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED   0x80000UL
 
#define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE   0x100000UL
 
#define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC   0x200000UL
 
#define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE   0x400000UL
 
#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED   0x1UL
 
#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED   0x2UL
 
#define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED   0x4UL
 
#define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED   0x8UL
 
#define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED   0x10UL
 
#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST   0x20UL
 
#define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF   0x40UL
 
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF   0x0UL
 
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS   0x1UL
 
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0   0x2UL
 
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5   0x3UL
 
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0   0x4UL
 
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN   0xffUL
 
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST   FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
 
#define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL   0x0UL
 
#define FUNC_QCFG_RESP_PORT_PF_CNT_LAST   FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK   0xfffffffUL
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT   0
 
#define FUNC_QCFG_RESP_MIN_BW_SCALE   0x10000000UL
 
#define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS   (0x0UL << 28)
 
#define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES   (0x1UL << 28)
 
#define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST   FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK   0xe0000000UL
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT   29
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA   (0x0UL << 29)
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO   (0x2UL << 29)
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE   (0x4UL << 29)
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA   (0x6UL << 29)
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100   (0x1UL << 29)
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID   (0x7UL << 29)
 
#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST   FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK   0xfffffffUL
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT   0
 
#define FUNC_QCFG_RESP_MAX_BW_SCALE   0x10000000UL
 
#define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS   (0x0UL << 28)
 
#define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES   (0x1UL << 28)
 
#define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST   FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK   0xe0000000UL
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT   29
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA   (0x0UL << 29)
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO   (0x2UL << 29)
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE   (0x4UL << 29)
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA   (0x6UL << 29)
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100   (0x1UL << 29)
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID   (0x7UL << 29)
 
#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST   FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
 
#define FUNC_QCFG_RESP_EVB_MODE_NO_EVB   0x0UL
 
#define FUNC_QCFG_RESP_EVB_MODE_VEB   0x1UL
 
#define FUNC_QCFG_RESP_EVB_MODE_VEPA   0x2UL
 
#define FUNC_QCFG_RESP_EVB_MODE_LAST   FUNC_QCFG_RESP_EVB_MODE_VEPA
 
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK   0x3UL
 
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT   0
 
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64   0x0UL
 
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128   0x1UL
 
#define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST   FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
 
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK   0xcUL
 
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT   2
 
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN   (0x0UL << 2)
 
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP   (0x1UL << 2)
 
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO   (0x2UL << 2)
 
#define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST   FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
 
#define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK   0xf0UL
 
#define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT   4
 
#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE   0x1UL
 
#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE   0x2UL
 
#define FUNC_CFG_REQ_FLAGS_RSVD_MASK   0x1fcUL
 
#define FUNC_CFG_REQ_FLAGS_RSVD_SFT   2
 
#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE   0x200UL
 
#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE   0x400UL
 
#define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST   0x800UL
 
#define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC   0x1000UL
 
#define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST   0x2000UL
 
#define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST   0x4000UL
 
#define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST   0x8000UL
 
#define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST   0x10000UL
 
#define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST   0x20000UL
 
#define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST   0x40000UL
 
#define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST   0x80000UL
 
#define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST   0x100000UL
 
#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE   0x200000UL
 
#define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC   0x400000UL
 
#define FUNC_CFG_REQ_ENABLES_MTU   0x1UL
 
#define FUNC_CFG_REQ_ENABLES_MRU   0x2UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS   0x4UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS   0x8UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS   0x10UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS   0x20UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS   0x40UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_VNICS   0x80UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS   0x100UL
 
#define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR   0x200UL
 
#define FUNC_CFG_REQ_ENABLES_DFLT_VLAN   0x400UL
 
#define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR   0x800UL
 
#define FUNC_CFG_REQ_ENABLES_MIN_BW   0x1000UL
 
#define FUNC_CFG_REQ_ENABLES_MAX_BW   0x2000UL
 
#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR   0x4000UL
 
#define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE   0x8000UL
 
#define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS   0x10000UL
 
#define FUNC_CFG_REQ_ENABLES_EVB_MODE   0x20000UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS   0x40000UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS   0x80000UL
 
#define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE   0x100000UL
 
#define FUNC_CFG_REQ_ENABLES_NUM_MSIX   0x200000UL
 
#define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE   0x400000UL
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK   0xfffffffUL
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT   0
 
#define FUNC_CFG_REQ_MIN_BW_SCALE   0x10000000UL
 
#define FUNC_CFG_REQ_MIN_BW_SCALE_BITS   (0x0UL << 28)
 
#define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES   (0x1UL << 28)
 
#define FUNC_CFG_REQ_MIN_BW_SCALE_LAST   FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK   0xe0000000UL
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT   29
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA   (0x0UL << 29)
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO   (0x2UL << 29)
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE   (0x4UL << 29)
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA   (0x6UL << 29)
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100   (0x1UL << 29)
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID   (0x7UL << 29)
 
#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST   FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK   0xfffffffUL
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT   0
 
#define FUNC_CFG_REQ_MAX_BW_SCALE   0x10000000UL
 
#define FUNC_CFG_REQ_MAX_BW_SCALE_BITS   (0x0UL << 28)
 
#define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES   (0x1UL << 28)
 
#define FUNC_CFG_REQ_MAX_BW_SCALE_LAST   FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK   0xe0000000UL
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT   29
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA   (0x0UL << 29)
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO   (0x2UL << 29)
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE   (0x4UL << 29)
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA   (0x6UL << 29)
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100   (0x1UL << 29)
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID   (0x7UL << 29)
 
#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST   FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
 
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK   0x0UL
 
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN   0x1UL
 
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE   0x2UL
 
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN   0x3UL
 
#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST   FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
 
#define FUNC_CFG_REQ_EVB_MODE_NO_EVB   0x0UL
 
#define FUNC_CFG_REQ_EVB_MODE_VEB   0x1UL
 
#define FUNC_CFG_REQ_EVB_MODE_VEPA   0x2UL
 
#define FUNC_CFG_REQ_EVB_MODE_LAST   FUNC_CFG_REQ_EVB_MODE_VEPA
 
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK   0x3UL
 
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT   0
 
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64   0x0UL
 
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128   0x1UL
 
#define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST   FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
 
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK   0xcUL
 
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT   2
 
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN   (0x0UL << 2)
 
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP   (0x1UL << 2)
 
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO   (0x2UL << 2)
 
#define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST   FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
 
#define FUNC_CFG_REQ_OPTIONS_RSVD_MASK   0xf0UL
 
#define FUNC_CFG_REQ_OPTIONS_RSVD_SFT   4
 
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE   0x1UL
 
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE   0x2UL
 
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE   0x4UL
 
#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE   0x8UL
 
#define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT   0x10UL
 
#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE   0x1UL
 
#define FUNC_DRV_RGTR_REQ_ENABLES_VER   0x2UL
 
#define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP   0x4UL
 
#define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD   0x8UL
 
#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD   0x10UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN   0x0UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER   0x1UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS   0xeUL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS   0x12UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS   0x1dUL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX   0x24UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD   0x2aUL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI   0x68UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864   0x73UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2   0x74UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI   0x8000UL
 
#define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST   FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
 
#define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED   0x1UL
 
#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN   0x1UL
 
#define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID   0x1UL
 
#define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR   0x2UL
 
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B   0x4UL
 
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K   0xcUL
 
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K   0xdUL
 
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K   0x10UL
 
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M   0x15UL
 
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M   0x16UL
 
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G   0x1eUL
 
#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST   FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
 
#define FUNC_BUF_UNRGTR_REQ_ENABLES_VF_ID   0x1UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN   0x0UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER   0x1UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS   0xeUL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS   0x12UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS   0x1dUL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX   0x24UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD   0x2aUL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI   0x68UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864   0x73UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2   0x74UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI   0x8000UL
 
#define FUNC_DRV_QVER_RESP_OS_TYPE_LAST   FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
 
#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL   0x0UL
 
#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL   0x1UL
 
#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC   0x2UL
 
#define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST   FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
 
#define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED   0x1UL
 
#define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ   0x4UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC   0x8UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT   0x10UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP   0x20UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0   0x40UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1   0x80UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2   0x100UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3   0x200UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4   0x400UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5   0x800UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6   0x1000UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7   0x2000UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV   0x4000UL
 
#define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM   0x8000UL
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT   0
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST   FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_FLAGS_PREBOOT_MODE   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_QP   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_SRQ   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_CQ   0x4UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_VNIC   0x8UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_STAT   0x10UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_SP   0x20UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING0   0x40UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING1   0x80UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING2   0x100UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING3   0x200UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING4   0x400UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING5   0x800UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING6   0x1000UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING7   0x2000UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_MRAV   0x4000UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TIM   0x8000UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_MASK   0xfUL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_SFT   0
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_0   0x0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_1   0x1UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2   0x2UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LAST   FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_MASK   0xf0UL
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_SFT   4
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_4K   (0x0UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8K   (0x1UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_64K   (0x2UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_2M   (0x3UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8M   (0x4UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G   (0x5UL << 4)
 
#define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G
 
#define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID   0x1UL
 
#define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID   0x2UL
 
#define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP   0x4UL
 
#define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP   0x8UL
 
#define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID   0x10UL
 
#define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID   0x20UL
 
#define FUNC_VF_BW_CFG_REQ_VFN_VFID_MASK   0xfffUL
 
#define FUNC_VF_BW_CFG_REQ_VFN_VFID_SFT   0
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_MASK   0xf000UL
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_SFT   12
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_0   (0x0UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_6_66   (0x1UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_13_33   (0x2UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_20   (0x3UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_26_66   (0x4UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_33_33   (0x5UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_40   (0x6UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_46_66   (0x7UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_53_33   (0x8UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_60   (0x9UL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_66_66   (0xaUL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_73_33   (0xbUL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_80   (0xcUL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_86_66   (0xdUL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_93_33   (0xeUL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100   (0xfUL << 12)
 
#define FUNC_VF_BW_CFG_REQ_VFN_RATE_LAST   FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100
 
#define FUNC_VF_BW_QCFG_REQ_VFN_VFID_MASK   0xfffUL
 
#define FUNC_VF_BW_QCFG_REQ_VFN_VFID_SFT   0
 
#define FUNC_VF_BW_QCFG_RESP_VFN_VFID_MASK   0xfffUL
 
#define FUNC_VF_BW_QCFG_RESP_VFN_VFID_SFT   0
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_MASK   0xf000UL
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_SFT   12
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_0   (0x0UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_6_66   (0x1UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_13_33   (0x2UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_20   (0x3UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_26_66   (0x4UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_33_33   (0x5UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_40   (0x6UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_46_66   (0x7UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_53_33   (0x8UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_60   (0x9UL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_66_66   (0xaUL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_73_33   (0xbUL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_80   (0xcUL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_86_66   (0xdUL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_93_33   (0xeUL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100   (0xfUL << 12)
 
#define FUNC_VF_BW_QCFG_RESP_VFN_RATE_LAST   FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100
 
#define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP   0x1UL
 
#define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE   0x1UL
 
#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY   0x1UL
 
#define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED   0x2UL
 
#define PORT_PHY_CFG_REQ_FLAGS_FORCE   0x4UL
 
#define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG   0x8UL
 
#define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE   0x10UL
 
#define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE   0x20UL
 
#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE   0x40UL
 
#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE   0x80UL
 
#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE   0x100UL
 
#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE   0x200UL
 
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE   0x400UL
 
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE   0x800UL
 
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE   0x1000UL
 
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE   0x2000UL
 
#define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN   0x4000UL
 
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE   0x1UL
 
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX   0x2UL
 
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE   0x4UL
 
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED   0x8UL
 
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK   0x10UL
 
#define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED   0x20UL
 
#define PORT_PHY_CFG_REQ_ENABLES_LPBK   0x40UL
 
#define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS   0x80UL
 
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE   0x100UL
 
#define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK   0x200UL
 
#define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER   0x400UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB   0x1UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB   0xaUL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB   0x14UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB   0x19UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB   0x64UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB   0xc8UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB   0xfaUL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB   0x190UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB   0x1f4UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB   0x3e8UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB   0x7d0UL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB   0xffffUL
 
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST   PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
 
#define PORT_PHY_CFG_REQ_AUTO_MODE_NONE   0x0UL
 
#define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS   0x1UL
 
#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED   0x2UL
 
#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW   0x3UL
 
#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK   0x4UL
 
#define PORT_PHY_CFG_REQ_AUTO_MODE_LAST   PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
 
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF   0x0UL
 
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL   0x1UL
 
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH   0x2UL
 
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST   PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
 
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX   0x1UL
 
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX   0x2UL
 
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE   0x4UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB   0x1UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB   0xaUL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB   0x14UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB   0x19UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB   0x64UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB   0xc8UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB   0xfaUL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB   0x190UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB   0x1f4UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB   0x3e8UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB   0x7d0UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB   0xffffUL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST   PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD   0x1UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB   0x2UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD   0x4UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB   0x8UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB   0x10UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB   0x20UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB   0x40UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB   0x80UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB   0x100UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB   0x200UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB   0x400UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB   0x800UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD   0x1000UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB   0x2000UL
 
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB   0x4000UL
 
#define PORT_PHY_CFG_REQ_WIRESPEED_OFF   0x0UL
 
#define PORT_PHY_CFG_REQ_WIRESPEED_ON   0x1UL
 
#define PORT_PHY_CFG_REQ_WIRESPEED_LAST   PORT_PHY_CFG_REQ_WIRESPEED_ON
 
#define PORT_PHY_CFG_REQ_LPBK_NONE   0x0UL
 
#define PORT_PHY_CFG_REQ_LPBK_LOCAL   0x1UL
 
#define PORT_PHY_CFG_REQ_LPBK_REMOTE   0x2UL
 
#define PORT_PHY_CFG_REQ_LPBK_EXTERNAL   0x3UL
 
#define PORT_PHY_CFG_REQ_LPBK_LAST   PORT_PHY_CFG_REQ_LPBK_EXTERNAL
 
#define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX   0x1UL
 
#define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX   0x2UL
 
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1   0x1UL
 
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB   0x2UL
 
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2   0x4UL
 
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB   0x8UL
 
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3   0x10UL
 
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4   0x20UL
 
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB   0x40UL
 
#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK   0xffffffUL
 
#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT   0
 
#define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN   0x0UL
 
#define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED   0x1UL
 
#define PORT_PHY_CFG_CMD_ERR_CODE_RETRY   0x2UL
 
#define PORT_PHY_CFG_CMD_ERR_CODE_LAST   PORT_PHY_CFG_CMD_ERR_CODE_RETRY
 
#define PORT_PHY_QCFG_RESP_LINK_NO_LINK   0x0UL
 
#define PORT_PHY_QCFG_RESP_LINK_SIGNAL   0x1UL
 
#define PORT_PHY_QCFG_RESP_LINK_LINK   0x2UL
 
#define PORT_PHY_QCFG_RESP_LINK_LAST   PORT_PHY_QCFG_RESP_LINK_LINK
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB   0x1UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB   0xaUL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB   0x14UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB   0x19UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB   0x64UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB   0xc8UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB   0xfaUL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB   0x190UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB   0x1f4UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB   0x3e8UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB   0x7d0UL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB   0xffffUL
 
#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST   PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
 
#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF   0x0UL
 
#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL   0x1UL
 
#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST   PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
 
#define PORT_PHY_QCFG_RESP_PAUSE_TX   0x1UL
 
#define PORT_PHY_QCFG_RESP_PAUSE_RX   0x2UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD   0x1UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB   0x2UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD   0x4UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB   0x8UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB   0x10UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB   0x20UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB   0x40UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB   0x80UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB   0x100UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB   0x200UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB   0x400UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB   0x800UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD   0x1000UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB   0x2000UL
 
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB   0x4000UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB   0x1UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB   0xaUL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB   0x14UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB   0x19UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB   0x64UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB   0xc8UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB   0xfaUL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB   0x190UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB   0x1f4UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB   0x3e8UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB   0x7d0UL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB   0xffffUL
 
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST   PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
 
#define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE   0x0UL
 
#define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS   0x1UL
 
#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED   0x2UL
 
#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW   0x3UL
 
#define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK   0x4UL
 
#define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST   PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
 
#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX   0x1UL
 
#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX   0x2UL
 
#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE   0x4UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB   0x1UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB   0xaUL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB   0x14UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB   0x19UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB   0x64UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB   0xc8UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB   0xfaUL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB   0x190UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB   0x1f4UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB   0x3e8UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB   0x7d0UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB   0xffffUL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST   PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD   0x1UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB   0x2UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD   0x4UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB   0x8UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB   0x10UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB   0x20UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB   0x40UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB   0x80UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB   0x100UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB   0x200UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB   0x400UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB   0x800UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD   0x1000UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB   0x2000UL
 
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB   0x4000UL
 
#define PORT_PHY_QCFG_RESP_WIRESPEED_OFF   0x0UL
 
#define PORT_PHY_QCFG_RESP_WIRESPEED_ON   0x1UL
 
#define PORT_PHY_QCFG_RESP_WIRESPEED_LAST   PORT_PHY_QCFG_RESP_WIRESPEED_ON
 
#define PORT_PHY_QCFG_RESP_LPBK_NONE   0x0UL
 
#define PORT_PHY_QCFG_RESP_LPBK_LOCAL   0x1UL
 
#define PORT_PHY_QCFG_RESP_LPBK_REMOTE   0x2UL
 
#define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL   0x3UL
 
#define PORT_PHY_QCFG_RESP_LPBK_LAST   PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
 
#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX   0x1UL
 
#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX   0x2UL
 
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE   0x0UL
 
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX   0x1UL
 
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG   0x2UL
 
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN   0x3UL
 
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED   0x4UL
 
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE   0xffUL
 
#define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST   PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN   0x0UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR   0x1UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4   0x2UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR   0x3UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR   0x4UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2   0x5UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX   0x6UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR   0x7UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET   0x8UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE   0x9UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY   0xaUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L   0xbUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S   0xcUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N   0xdUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR   0xeUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4   0xfUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4   0x10UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4   0x11UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4   0x12UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10   0x13UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4   0x14UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4   0x15UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4   0x16UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4   0x17UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE   0x18UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET   0x19UL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX   0x1aUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX   0x1bUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4   0x1cUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4   0x1dUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4   0x1eUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4   0x1fUL
 
#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST   PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
 
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN   0x0UL
 
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP   0x1UL
 
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC   0x2UL
 
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE   0x3UL
 
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST   PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
 
#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL   0x1UL
 
#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL   0x2UL
 
#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST   PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
 
#define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK   0x1fUL
 
#define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT   0
 
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK   0xe0UL
 
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT   5
 
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED   0x20UL
 
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE   0x40UL
 
#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI   0x80UL
 
#define PORT_PHY_QCFG_RESP_PARALLEL_DETECT   0x1UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD   0x1UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB   0x2UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD   0x4UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB   0x8UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB   0x10UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB   0x20UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB   0x40UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB   0x80UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB   0x100UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB   0x200UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB   0x400UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB   0x800UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD   0x1000UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB   0x2000UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE   0x0UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS   0x1UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED   0x2UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW   0x3UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK   0x4UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST   PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX   0x1UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX   0x2UL
 
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1   0x1UL
 
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB   0x2UL
 
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2   0x4UL
 
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB   0x8UL
 
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3   0x10UL
 
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4   0x20UL
 
#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB   0x40UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1   0x1UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB   0x2UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2   0x4UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB   0x8UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3   0x10UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4   0x20UL
 
#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB   0x40UL
 
#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK   0xffffffUL
 
#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT   0
 
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK   0xff000000UL
 
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT   24
 
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN   (0x0UL << 24)
 
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP   (0x3UL << 24)
 
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP   (0xcUL << 24)
 
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS   (0xdUL << 24)
 
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28   (0x11UL << 24)
 
#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST   PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
 
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED   0x1UL
 
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED   0x2UL
 
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED   0x4UL
 
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED   0x8UL
 
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED   0x10UL
 
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED   0x20UL
 
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED   0x40UL
 
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF   0x0UL
 
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL   0x1UL
 
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST   PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
 
#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT   0x1UL
 
#define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK   0x1UL
 
#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE   0x2UL
 
#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE   0x4UL
 
#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE   0x8UL
 
#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE   0x10UL
 
#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE   0x20UL
 
#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE   0x40UL
 
#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE   0x80UL
 
#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE   0x100UL
 
#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE   0x200UL
 
#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE   0x400UL
 
#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE   0x800UL
 
#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE   0x1000UL
 
#define PORT_MAC_CFG_REQ_ENABLES_IPG   0x1UL
 
#define PORT_MAC_CFG_REQ_ENABLES_LPBK   0x2UL
 
#define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI   0x4UL
 
#define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI   0x10UL
 
#define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI   0x20UL
 
#define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE   0x40UL
 
#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE   0x80UL
 
#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG   0x100UL
 
#define PORT_MAC_CFG_REQ_LPBK_NONE   0x0UL
 
#define PORT_MAC_CFG_REQ_LPBK_LOCAL   0x1UL
 
#define PORT_MAC_CFG_REQ_LPBK_REMOTE   0x2UL
 
#define PORT_MAC_CFG_REQ_LPBK_LAST   PORT_MAC_CFG_REQ_LPBK_REMOTE
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1   0x1UL
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK   0x6UL
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT   1
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST   (0x0UL << 1)
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER   (0x1UL << 1)
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST   (0x2UL << 1)
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED   (0x3UL << 1)
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST   PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK   0x18UL
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT   3
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST   (0x0UL << 3)
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER   (0x1UL << 3)
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST   (0x2UL << 3)
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED   (0x3UL << 3)
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST   PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK   0xe0UL
 
#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT   5
 
#define PORT_MAC_CFG_RESP_LPBK_NONE   0x0UL
 
#define PORT_MAC_CFG_RESP_LPBK_LOCAL   0x1UL
 
#define PORT_MAC_CFG_RESP_LPBK_REMOTE   0x2UL
 
#define PORT_MAC_CFG_RESP_LPBK_LAST   PORT_MAC_CFG_RESP_LPBK_REMOTE
 
#define PORT_MAC_QCFG_RESP_LPBK_NONE   0x0UL
 
#define PORT_MAC_QCFG_RESP_LPBK_LOCAL   0x1UL
 
#define PORT_MAC_QCFG_RESP_LPBK_REMOTE   0x2UL
 
#define PORT_MAC_QCFG_RESP_LPBK_LAST   PORT_MAC_QCFG_RESP_LPBK_REMOTE
 
#define PORT_MAC_QCFG_RESP_FLAGS_VLAN_PRI2COS_ENABLE   0x1UL
 
#define PORT_MAC_QCFG_RESP_FLAGS_TUNNEL_PRI2COS_ENABLE   0x2UL
 
#define PORT_MAC_QCFG_RESP_FLAGS_IP_DSCP2COS_ENABLE   0x4UL
 
#define PORT_MAC_QCFG_RESP_FLAGS_OOB_WOL_ENABLE   0x8UL
 
#define PORT_MAC_QCFG_RESP_FLAGS_PTP_RX_TS_CAPTURE_ENABLE   0x10UL
 
#define PORT_MAC_QCFG_RESP_FLAGS_PTP_TX_TS_CAPTURE_ENABLE   0x20UL
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_RSVD   0x1UL
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_MASK   0x6UL
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_SFT   1
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST   (0x0UL << 1)
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER   (0x1UL << 1)
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST   (0x2UL << 1)
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED   (0x3UL << 1)
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_LAST   PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK   0x18UL
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT   3
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST   (0x0UL << 3)
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER   (0x1UL << 3)
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST   (0x2UL << 3)
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED   (0x3UL << 3)
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST   PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_MASK   0xe0UL
 
#define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_SFT   5
 
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS   0x1UL
 
#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS   0x2UL
 
#define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED   0x1UL
 
#define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS   0x1UL
 
#define PORT_TS_QUERY_REQ_FLAGS_PATH   0x1UL
 
#define PORT_TS_QUERY_REQ_FLAGS_PATH_TX   0x0UL
 
#define PORT_TS_QUERY_REQ_FLAGS_PATH_RX   0x1UL
 
#define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST   PORT_TS_QUERY_REQ_FLAGS_PATH_RX
 
#define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED   0x1UL
 
#define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED   0x2UL
 
#define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK   0xfcUL
 
#define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT   2
 
#define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN   0x0UL
 
#define PORT_PHY_QCAPS_RESP_PORT_CNT_1   0x1UL
 
#define PORT_PHY_QCAPS_RESP_PORT_CNT_2   0x2UL
 
#define PORT_PHY_QCAPS_RESP_PORT_CNT_3   0x3UL
 
#define PORT_PHY_QCAPS_RESP_PORT_CNT_4   0x4UL
 
#define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST   PORT_PHY_QCAPS_RESP_PORT_CNT_4
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD   0x1UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB   0x2UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD   0x4UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB   0x8UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB   0x10UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB   0x20UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB   0x40UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB   0x80UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB   0x100UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB   0x200UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB   0x400UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB   0x800UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD   0x1000UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB   0x2000UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD   0x1UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB   0x2UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD   0x4UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB   0x8UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB   0x10UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB   0x20UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB   0x40UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB   0x80UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB   0x100UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB   0x200UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB   0x400UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB   0x800UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD   0x1000UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB   0x2000UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1   0x1UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB   0x2UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2   0x4UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB   0x8UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3   0x10UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4   0x20UL
 
#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB   0x40UL
 
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK   0xffffffUL
 
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT   0
 
#define PORT_PHY_QCAPS_RESP_RSVD2_MASK   0xff000000UL
 
#define PORT_PHY_QCAPS_RESP_RSVD2_SFT   24
 
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK   0xffffffUL
 
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT   0
 
#define PORT_PHY_QCAPS_RESP_VALID_MASK   0xff000000UL
 
#define PORT_PHY_QCAPS_RESP_VALID_SFT   24
 
#define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET   0x1UL
 
#define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET   0x1UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED0_ID   0x1UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED0_STATE   0x2UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR   0x4UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON   0x8UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF   0x10UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID   0x20UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED1_ID   0x40UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED1_STATE   0x80UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR   0x100UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON   0x200UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF   0x400UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID   0x800UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED2_ID   0x1000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED2_STATE   0x2000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR   0x4000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON   0x8000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF   0x10000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID   0x20000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED3_ID   0x40000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED3_STATE   0x80000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR   0x100000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON   0x200000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF   0x400000UL
 
#define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID   0x800000UL
 
#define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT   0x0UL
 
#define PORT_LED_CFG_REQ_LED0_STATE_OFF   0x1UL
 
#define PORT_LED_CFG_REQ_LED0_STATE_ON   0x2UL
 
#define PORT_LED_CFG_REQ_LED0_STATE_BLINK   0x3UL
 
#define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT   0x4UL
 
#define PORT_LED_CFG_REQ_LED0_STATE_LAST   PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
 
#define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT   0x0UL
 
#define PORT_LED_CFG_REQ_LED0_COLOR_AMBER   0x1UL
 
#define PORT_LED_CFG_REQ_LED0_COLOR_GREEN   0x2UL
 
#define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER   0x3UL
 
#define PORT_LED_CFG_REQ_LED0_COLOR_LAST   PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
 
#define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT   0x0UL
 
#define PORT_LED_CFG_REQ_LED1_STATE_OFF   0x1UL
 
#define PORT_LED_CFG_REQ_LED1_STATE_ON   0x2UL
 
#define PORT_LED_CFG_REQ_LED1_STATE_BLINK   0x3UL
 
#define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT   0x4UL
 
#define PORT_LED_CFG_REQ_LED1_STATE_LAST   PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
 
#define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT   0x0UL
 
#define PORT_LED_CFG_REQ_LED1_COLOR_AMBER   0x1UL
 
#define PORT_LED_CFG_REQ_LED1_COLOR_GREEN   0x2UL
 
#define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER   0x3UL
 
#define PORT_LED_CFG_REQ_LED1_COLOR_LAST   PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
 
#define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT   0x0UL
 
#define PORT_LED_CFG_REQ_LED2_STATE_OFF   0x1UL
 
#define PORT_LED_CFG_REQ_LED2_STATE_ON   0x2UL
 
#define PORT_LED_CFG_REQ_LED2_STATE_BLINK   0x3UL
 
#define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT   0x4UL
 
#define PORT_LED_CFG_REQ_LED2_STATE_LAST   PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
 
#define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT   0x0UL
 
#define PORT_LED_CFG_REQ_LED2_COLOR_AMBER   0x1UL
 
#define PORT_LED_CFG_REQ_LED2_COLOR_GREEN   0x2UL
 
#define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER   0x3UL
 
#define PORT_LED_CFG_REQ_LED2_COLOR_LAST   PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
 
#define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT   0x0UL
 
#define PORT_LED_CFG_REQ_LED3_STATE_OFF   0x1UL
 
#define PORT_LED_CFG_REQ_LED3_STATE_ON   0x2UL
 
#define PORT_LED_CFG_REQ_LED3_STATE_BLINK   0x3UL
 
#define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT   0x4UL
 
#define PORT_LED_CFG_REQ_LED3_STATE_LAST   PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
 
#define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT   0x0UL
 
#define PORT_LED_CFG_REQ_LED3_COLOR_AMBER   0x1UL
 
#define PORT_LED_CFG_REQ_LED3_COLOR_GREEN   0x2UL
 
#define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER   0x3UL
 
#define PORT_LED_CFG_REQ_LED3_COLOR_LAST   PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
 
#define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED   0x0UL
 
#define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY   0x1UL
 
#define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID   0xffUL
 
#define PORT_LED_QCFG_RESP_LED0_TYPE_LAST   PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
 
#define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT   0x0UL
 
#define PORT_LED_QCFG_RESP_LED0_STATE_OFF   0x1UL
 
#define PORT_LED_QCFG_RESP_LED0_STATE_ON   0x2UL
 
#define PORT_LED_QCFG_RESP_LED0_STATE_BLINK   0x3UL
 
#define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT   0x4UL
 
#define PORT_LED_QCFG_RESP_LED0_STATE_LAST   PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
 
#define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT   0x0UL
 
#define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER   0x1UL
 
#define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN   0x2UL
 
#define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER   0x3UL
 
#define PORT_LED_QCFG_RESP_LED0_COLOR_LAST   PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
 
#define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED   0x0UL
 
#define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY   0x1UL
 
#define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID   0xffUL
 
#define PORT_LED_QCFG_RESP_LED1_TYPE_LAST   PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
 
#define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT   0x0UL
 
#define PORT_LED_QCFG_RESP_LED1_STATE_OFF   0x1UL
 
#define PORT_LED_QCFG_RESP_LED1_STATE_ON