bnxt__hsi_8h_source.html

 /* Broadcom NetXtreme-C/E network driver.
  *
  * Copyright (c) 2014-2016 Broadcom Corporation
  * Copyright (c) 2016-2019 Broadcom Limited
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation.
  *
  * DO NOT MODIFY!!! This file is automatically generated.
  */

 #ifndef _BNXT_HSI_H_
 #define _BNXT_HSI_H_

 /* hwrm_cmd_hdr (size:128b/16B) */
 struct hwrm_cmd_hdr {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_resp_hdr (size:64b/8B) */
 struct hwrm_resp_hdr {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
 };

 #define CMD_DISCR_TLV_ENCAP 0x8000UL
 #define CMD_DISCR_LAST     CMD_DISCR_TLV_ENCAP

 #define TLV_TYPE_HWRM_REQUEST                    0x1UL
 #define TLV_TYPE_HWRM_RESPONSE                   0x2UL
 #define TLV_TYPE_ROCE_SP_COMMAND                 0x3UL
 #define TLV_TYPE_QUERY_ROCE_CC_GEN1              0x4UL
 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1             0x5UL
 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL
 #define TLV_TYPE_ENGINE_CKV_NONCE                0x8002UL
 #define TLV_TYPE_ENGINE_CKV_IV                   0x8003UL
 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG             0x8004UL
 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT           0x8005UL
 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS           0x8006UL
 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY       0x8007UL
 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE      0x8008UL
 #define TLV_TYPE_LAST                           TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE

 /* tlv (size:64b/8B) */
 struct tlv {
         __le16  cmd_discr;
         u8      reserved_8b;
         u8      flags;
         #define TLV_FLAGS_MORE         0x1UL
         #define TLV_FLAGS_MORE_LAST      0x0UL
         #define TLV_FLAGS_MORE_NOT_LAST  0x1UL
         #define TLV_FLAGS_REQUIRED     0x2UL
         #define TLV_FLAGS_REQUIRED_NO    (0x0UL << 1)
         #define TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)
         #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
         __le16  tlv_type;
         __le16  length;
 };

 /* input (size:128b/16B) */
 struct input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* output (size:64b/8B) */
 struct output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
 };

 /* hwrm_short_input (size:128b/16B) */
 struct hwrm_short_input {
         __le16  req_type;
         __le16  signature;
         #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
         #define SHORT_REQ_SIGNATURE_LAST     SHORT_REQ_SIGNATURE_SHORT_CMD
         __le16  unused_0;
         __le16  size;
         __le64  req_addr;
 };

 /* cmd_nums (size:64b/8B) */
 struct cmd_nums {
         __le16  req_type;
         #define HWRM_VER_GET                              0x0UL
         #define HWRM_ER_QCFG                              0xcUL
         #define HWRM_FUNC_DRV_IF_CHANGE                   0xdUL
         #define HWRM_FUNC_BUF_UNRGTR                      0xeUL
         #define HWRM_FUNC_VF_CFG                          0xfUL
         #define HWRM_RESERVED1                            0x10UL
         #define HWRM_FUNC_RESET                           0x11UL
         #define HWRM_FUNC_GETFID                          0x12UL
         #define HWRM_FUNC_VF_ALLOC                        0x13UL
         #define HWRM_FUNC_VF_FREE                         0x14UL
         #define HWRM_FUNC_QCAPS                           0x15UL
         #define HWRM_FUNC_QCFG                            0x16UL
         #define HWRM_FUNC_CFG                             0x17UL
         #define HWRM_FUNC_QSTATS                          0x18UL
         #define HWRM_FUNC_CLR_STATS                       0x19UL
         #define HWRM_FUNC_DRV_UNRGTR                      0x1aUL
         #define HWRM_FUNC_VF_RESC_FREE                    0x1bUL
         #define HWRM_FUNC_VF_VNIC_IDS_QUERY               0x1cUL
         #define HWRM_FUNC_DRV_RGTR                        0x1dUL
         #define HWRM_FUNC_DRV_QVER                        0x1eUL
         #define HWRM_FUNC_BUF_RGTR                        0x1fUL
         #define HWRM_PORT_PHY_CFG                         0x20UL
         #define HWRM_PORT_MAC_CFG                         0x21UL
         #define HWRM_PORT_TS_QUERY                        0x22UL
         #define HWRM_PORT_QSTATS                          0x23UL
         #define HWRM_PORT_LPBK_QSTATS                     0x24UL
         #define HWRM_PORT_CLR_STATS                       0x25UL
         #define HWRM_PORT_LPBK_CLR_STATS                  0x26UL
         #define HWRM_PORT_PHY_QCFG                        0x27UL
         #define HWRM_PORT_MAC_QCFG                        0x28UL
         #define HWRM_PORT_MAC_PTP_QCFG                    0x29UL
         #define HWRM_PORT_PHY_QCAPS                       0x2aUL
         #define HWRM_PORT_PHY_I2C_WRITE                   0x2bUL
         #define HWRM_PORT_PHY_I2C_READ                    0x2cUL
         #define HWRM_PORT_LED_CFG                         0x2dUL
         #define HWRM_PORT_LED_QCFG                        0x2eUL
         #define HWRM_PORT_LED_QCAPS                       0x2fUL
         #define HWRM_QUEUE_QPORTCFG                       0x30UL
         #define HWRM_QUEUE_QCFG                           0x31UL
         #define HWRM_QUEUE_CFG                            0x32UL
         #define HWRM_FUNC_VLAN_CFG                        0x33UL
         #define HWRM_FUNC_VLAN_QCFG                       0x34UL
         #define HWRM_QUEUE_PFCENABLE_QCFG                 0x35UL
         #define HWRM_QUEUE_PFCENABLE_CFG                  0x36UL
         #define HWRM_QUEUE_PRI2COS_QCFG                   0x37UL
         #define HWRM_QUEUE_PRI2COS_CFG                    0x38UL
         #define HWRM_QUEUE_COS2BW_QCFG                    0x39UL
         #define HWRM_QUEUE_COS2BW_CFG                     0x3aUL
         #define HWRM_QUEUE_DSCP_QCAPS                     0x3bUL
         #define HWRM_QUEUE_DSCP2PRI_QCFG                  0x3cUL
         #define HWRM_QUEUE_DSCP2PRI_CFG                   0x3dUL
         #define HWRM_VNIC_ALLOC                           0x40UL
         #define HWRM_VNIC_FREE                            0x41UL
         #define HWRM_VNIC_CFG                             0x42UL
         #define HWRM_VNIC_QCFG                            0x43UL
         #define HWRM_VNIC_TPA_CFG                         0x44UL
         #define HWRM_VNIC_TPA_QCFG                        0x45UL
         #define HWRM_VNIC_RSS_CFG                         0x46UL
         #define HWRM_VNIC_RSS_QCFG                        0x47UL
         #define HWRM_VNIC_PLCMODES_CFG                    0x48UL
         #define HWRM_VNIC_PLCMODES_QCFG                   0x49UL
         #define HWRM_VNIC_QCAPS                           0x4aUL
         #define HWRM_RING_ALLOC                           0x50UL
         #define HWRM_RING_FREE                            0x51UL
         #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        0x52UL
         #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS     0x53UL
         #define HWRM_RING_AGGINT_QCAPS                    0x54UL
         #define HWRM_RING_RESET                           0x5eUL
         #define HWRM_RING_GRP_ALLOC                       0x60UL
         #define HWRM_RING_GRP_FREE                        0x61UL
         #define HWRM_RESERVED5                            0x64UL
         #define HWRM_RESERVED6                            0x65UL
         #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC            0x70UL
         #define HWRM_VNIC_RSS_COS_LB_CTX_FREE             0x71UL
         #define HWRM_CFA_L2_FILTER_ALLOC                  0x90UL
         #define HWRM_CFA_L2_FILTER_FREE                   0x91UL
         #define HWRM_CFA_L2_FILTER_CFG                    0x92UL
         #define HWRM_CFA_L2_SET_RX_MASK                   0x93UL
         #define HWRM_CFA_VLAN_ANTISPOOF_CFG               0x94UL
         #define HWRM_CFA_TUNNEL_FILTER_ALLOC              0x95UL
         #define HWRM_CFA_TUNNEL_FILTER_FREE               0x96UL
         #define HWRM_CFA_ENCAP_RECORD_ALLOC               0x97UL
         #define HWRM_CFA_ENCAP_RECORD_FREE                0x98UL
         #define HWRM_CFA_NTUPLE_FILTER_ALLOC              0x99UL
         #define HWRM_CFA_NTUPLE_FILTER_FREE               0x9aUL
         #define HWRM_CFA_NTUPLE_FILTER_CFG                0x9bUL
         #define HWRM_CFA_EM_FLOW_ALLOC                    0x9cUL
         #define HWRM_CFA_EM_FLOW_FREE                     0x9dUL
         #define HWRM_CFA_EM_FLOW_CFG                      0x9eUL
         #define HWRM_TUNNEL_DST_PORT_QUERY                0xa0UL
         #define HWRM_TUNNEL_DST_PORT_ALLOC                0xa1UL
         #define HWRM_TUNNEL_DST_PORT_FREE                 0xa2UL
         #define HWRM_STAT_CTX_ENG_QUERY                   0xafUL
         #define HWRM_STAT_CTX_ALLOC                       0xb0UL
         #define HWRM_STAT_CTX_FREE                        0xb1UL
         #define HWRM_STAT_CTX_QUERY                       0xb2UL
         #define HWRM_STAT_CTX_CLR_STATS                   0xb3UL
         #define HWRM_PORT_QSTATS_EXT                      0xb4UL
         #define HWRM_FW_RESET                             0xc0UL
         #define HWRM_FW_QSTATUS                           0xc1UL
         #define HWRM_FW_HEALTH_CHECK                      0xc2UL
         #define HWRM_FW_SYNC                              0xc3UL
         #define HWRM_FW_SET_TIME                          0xc8UL
         #define HWRM_FW_GET_TIME                          0xc9UL
         #define HWRM_FW_SET_STRUCTURED_DATA               0xcaUL
         #define HWRM_FW_GET_STRUCTURED_DATA               0xcbUL
         #define HWRM_FW_IPC_MAILBOX                       0xccUL
         #define HWRM_EXEC_FWD_RESP                        0xd0UL
         #define HWRM_REJECT_FWD_RESP                      0xd1UL
         #define HWRM_FWD_RESP                             0xd2UL
         #define HWRM_FWD_ASYNC_EVENT_CMPL                 0xd3UL
         #define HWRM_OEM_CMD                              0xd4UL
         #define HWRM_TEMP_MONITOR_QUERY                   0xe0UL
         #define HWRM_WOL_FILTER_ALLOC                     0xf0UL
         #define HWRM_WOL_FILTER_FREE                      0xf1UL
         #define HWRM_WOL_FILTER_QCFG                      0xf2UL
         #define HWRM_WOL_REASON_QCFG                      0xf3UL
         #define HWRM_CFA_METER_PROFILE_ALLOC              0xf5UL
         #define HWRM_CFA_METER_PROFILE_FREE               0xf6UL
         #define HWRM_CFA_METER_PROFILE_CFG                0xf7UL
         #define HWRM_CFA_METER_INSTANCE_ALLOC             0xf8UL
         #define HWRM_CFA_METER_INSTANCE_FREE              0xf9UL
         #define HWRM_CFA_VFR_ALLOC                        0xfdUL
         #define HWRM_CFA_VFR_FREE                         0xfeUL
         #define HWRM_CFA_VF_PAIR_ALLOC                    0x100UL
         #define HWRM_CFA_VF_PAIR_FREE                     0x101UL
         #define HWRM_CFA_VF_PAIR_INFO                     0x102UL
         #define HWRM_CFA_FLOW_ALLOC                       0x103UL
         #define HWRM_CFA_FLOW_FREE                        0x104UL
         #define HWRM_CFA_FLOW_FLUSH                       0x105UL
         #define HWRM_CFA_FLOW_STATS                       0x106UL
         #define HWRM_CFA_FLOW_INFO                        0x107UL
         #define HWRM_CFA_DECAP_FILTER_ALLOC               0x108UL
         #define HWRM_CFA_DECAP_FILTER_FREE                0x109UL
         #define HWRM_CFA_VLAN_ANTISPOOF_QCFG              0x10aUL
         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC       0x10bUL
         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE        0x10cUL
         #define HWRM_CFA_PAIR_ALLOC                       0x10dUL
         #define HWRM_CFA_PAIR_FREE                        0x10eUL
         #define HWRM_CFA_PAIR_INFO                        0x10fUL
         #define HWRM_FW_IPC_MSG                           0x110UL
         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        0x111UL
         #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       0x112UL
         #define HWRM_CFA_FLOW_AGING_TIMER_RESET           0x113UL
         #define HWRM_CFA_FLOW_AGING_CFG                   0x114UL
         #define HWRM_CFA_FLOW_AGING_QCFG                  0x115UL
         #define HWRM_CFA_FLOW_AGING_QCAPS                 0x116UL
         #define HWRM_ENGINE_CKV_HELLO                     0x12dUL
         #define HWRM_ENGINE_CKV_STATUS                    0x12eUL
         #define HWRM_ENGINE_CKV_CKEK_ADD                  0x12fUL
         #define HWRM_ENGINE_CKV_CKEK_DELETE               0x130UL
         #define HWRM_ENGINE_CKV_KEY_ADD                   0x131UL
         #define HWRM_ENGINE_CKV_KEY_DELETE                0x132UL
         #define HWRM_ENGINE_CKV_FLUSH                     0x133UL
         #define HWRM_ENGINE_CKV_RNG_GET                   0x134UL
         #define HWRM_ENGINE_CKV_KEY_GEN                   0x135UL
         #define HWRM_ENGINE_QG_CONFIG_QUERY               0x13cUL
         #define HWRM_ENGINE_QG_QUERY                      0x13dUL
         #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
         #define HWRM_ENGINE_QG_METER_PROFILE_QUERY        0x13fUL
         #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC        0x140UL
         #define HWRM_ENGINE_QG_METER_PROFILE_FREE         0x141UL
         #define HWRM_ENGINE_QG_METER_QUERY                0x142UL
         #define HWRM_ENGINE_QG_METER_BIND                 0x143UL
         #define HWRM_ENGINE_QG_METER_UNBIND               0x144UL
         #define HWRM_ENGINE_QG_FUNC_BIND                  0x145UL
         #define HWRM_ENGINE_SG_CONFIG_QUERY               0x146UL
         #define HWRM_ENGINE_SG_QUERY                      0x147UL
         #define HWRM_ENGINE_SG_METER_QUERY                0x148UL
         #define HWRM_ENGINE_SG_METER_CONFIG               0x149UL
         #define HWRM_ENGINE_SG_QG_BIND                    0x14aUL
         #define HWRM_ENGINE_QG_SG_UNBIND                  0x14bUL
         #define HWRM_ENGINE_CONFIG_QUERY                  0x154UL
         #define HWRM_ENGINE_STATS_CONFIG                  0x155UL
         #define HWRM_ENGINE_STATS_CLEAR                   0x156UL
         #define HWRM_ENGINE_STATS_QUERY                   0x157UL
         #define HWRM_ENGINE_RQ_ALLOC                      0x15eUL
         #define HWRM_ENGINE_RQ_FREE                       0x15fUL
         #define HWRM_ENGINE_CQ_ALLOC                      0x160UL
         #define HWRM_ENGINE_CQ_FREE                       0x161UL
         #define HWRM_ENGINE_NQ_ALLOC                      0x162UL
         #define HWRM_ENGINE_NQ_FREE                       0x163UL
         #define HWRM_ENGINE_ON_DIE_RQE_CREDITS            0x164UL
         #define HWRM_FUNC_RESOURCE_QCAPS                  0x190UL
         #define HWRM_FUNC_VF_RESOURCE_CFG                 0x191UL
         #define HWRM_FUNC_BACKING_STORE_QCAPS             0x192UL
         #define HWRM_FUNC_BACKING_STORE_CFG               0x193UL
         #define HWRM_FUNC_BACKING_STORE_QCFG              0x194UL
         #define HWRM_FUNC_VF_BW_CFG                       0x195UL
         #define HWRM_FUNC_VF_BW_QCFG                      0x196UL
         #define HWRM_SELFTEST_QLIST                       0x200UL
         #define HWRM_SELFTEST_EXEC                        0x201UL
         #define HWRM_SELFTEST_IRQ                         0x202UL
         #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA        0x203UL
         #define HWRM_PCIE_QSTATS                          0x204UL
         #define HWRM_DBG_READ_DIRECT                      0xff10UL
         #define HWRM_DBG_READ_INDIRECT                    0xff11UL
         #define HWRM_DBG_WRITE_DIRECT                     0xff12UL
         #define HWRM_DBG_WRITE_INDIRECT                   0xff13UL
         #define HWRM_DBG_DUMP                             0xff14UL
         #define HWRM_DBG_ERASE_NVM                        0xff15UL
         #define HWRM_DBG_CFG                              0xff16UL
         #define HWRM_DBG_COREDUMP_LIST                    0xff17UL
         #define HWRM_DBG_COREDUMP_INITIATE                0xff18UL
         #define HWRM_DBG_COREDUMP_RETRIEVE                0xff19UL
         #define HWRM_DBG_FW_CLI                           0xff1aUL
         #define HWRM_DBG_I2C_CMD                          0xff1bUL
         #define HWRM_DBG_RING_INFO_GET                    0xff1cUL
         #define HWRM_NVM_FACTORY_DEFAULTS                 0xffeeUL
         #define HWRM_NVM_VALIDATE_OPTION                  0xffefUL
         #define HWRM_NVM_FLUSH                            0xfff0UL
         #define HWRM_NVM_GET_VARIABLE                     0xfff1UL
         #define HWRM_NVM_SET_VARIABLE                     0xfff2UL
         #define HWRM_NVM_INSTALL_UPDATE                   0xfff3UL
         #define HWRM_NVM_MODIFY                           0xfff4UL
         #define HWRM_NVM_VERIFY_UPDATE                    0xfff5UL
         #define HWRM_NVM_GET_DEV_INFO                     0xfff6UL
         #define HWRM_NVM_ERASE_DIR_ENTRY                  0xfff7UL
         #define HWRM_NVM_MOD_DIR_ENTRY                    0xfff8UL
         #define HWRM_NVM_FIND_DIR_ENTRY                   0xfff9UL
         #define HWRM_NVM_GET_DIR_ENTRIES                  0xfffaUL
         #define HWRM_NVM_GET_DIR_INFO                     0xfffbUL
         #define HWRM_NVM_RAW_DUMP                         0xfffcUL
         #define HWRM_NVM_READ                             0xfffdUL
         #define HWRM_NVM_WRITE                            0xfffeUL
         #define HWRM_NVM_RAW_WRITE_BLK                    0xffffUL
         #define HWRM_LAST                                HWRM_NVM_RAW_WRITE_BLK
         __le16  unused_0[3];
 };

 /* ret_codes (size:64b/8B) */
 struct ret_codes {
         __le16  error_code;
         #define HWRM_ERR_CODE_SUCCESS                   0x0UL
         #define HWRM_ERR_CODE_FAIL                      0x1UL
         #define HWRM_ERR_CODE_INVALID_PARAMS            0x2UL
         #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED    0x3UL
         #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR      0x4UL
         #define HWRM_ERR_CODE_INVALID_FLAGS             0x5UL
         #define HWRM_ERR_CODE_INVALID_ENABLES           0x6UL
         #define HWRM_ERR_CODE_UNSUPPORTED_TLV           0x7UL
         #define HWRM_ERR_CODE_NO_BUFFER                 0x8UL
         #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR    0x9UL
         #define HWRM_ERR_CODE_HOT_RESET_PROGRESS        0xaUL
         #define HWRM_ERR_CODE_HOT_RESET_FAIL            0xbUL
         #define HWRM_ERR_CODE_HWRM_ERROR                0xfUL
         #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
         #define HWRM_ERR_CODE_UNKNOWN_ERR               0xfffeUL
         #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED         0xffffUL
         #define HWRM_ERR_CODE_LAST                     HWRM_ERR_CODE_CMD_NOT_SUPPORTED
         __le16  unused_0[3];
 };

 /* hwrm_err_output (size:128b/16B) */
 struct hwrm_err_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  opaque_0;
         __le16  opaque_1;
         u8      cmd_err;
         u8      valid;
 };

 #define HWRM_NA_SIGNATURE ((__le32)(-1))
 #define HWRM_MAX_REQ_LEN 128
 #define HWRM_MAX_RESP_LEN 280
 #define HW_HASH_INDEX_SIZE 0x80
 #define HW_HASH_KEY_SIZE 40
 #define HWRM_RESP_VALID_KEY 1
 #define HWRM_VERSION_MAJOR 1
 #define HWRM_VERSION_MINOR 10
 #define HWRM_VERSION_UPDATE 0
 #define HWRM_VERSION_RSVD 18
 #define HWRM_VERSION_STR "1.10.0.18"

 /* hwrm_ver_get_input (size:192b/24B) */
 struct hwrm_ver_get_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      hwrm_intf_maj;
         u8      hwrm_intf_min;
         u8      hwrm_intf_upd;
         u8      unused_0[5];
 };

 /* hwrm_ver_get_output (size:1408b/176B) */
 struct hwrm_ver_get_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      hwrm_intf_maj_8b;
         u8      hwrm_intf_min_8b;
         u8      hwrm_intf_upd_8b;
         u8      hwrm_intf_rsvd_8b;
         u8      hwrm_fw_maj_8b;
         u8      hwrm_fw_min_8b;
         u8      hwrm_fw_bld_8b;
         u8      hwrm_fw_rsvd_8b;
         u8      mgmt_fw_maj_8b;
         u8      mgmt_fw_min_8b;
         u8      mgmt_fw_bld_8b;
         u8      mgmt_fw_rsvd_8b;
         u8      netctrl_fw_maj_8b;
         u8      netctrl_fw_min_8b;
         u8      netctrl_fw_bld_8b;
         u8      netctrl_fw_rsvd_8b;
         __le32  dev_caps_cfg;
         #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED                  0x1UL
         #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED                  0x2UL
         #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED                      0x4UL
         #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED                       0x8UL
         #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED                   0x10UL
         #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED              0x20UL
         #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED     0x40UL
         #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED         0x80UL
         #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED                     0x100UL
         #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED                     0x200UL
         u8      roce_fw_maj_8b;
         u8      roce_fw_min_8b;
         u8      roce_fw_bld_8b;
         u8      roce_fw_rsvd_8b;
         char    hwrm_fw_name[16];
         char    mgmt_fw_name[16];
         char    netctrl_fw_name[16];
         u8      reserved2[16];
         char    roce_fw_name[16];
         __le16  chip_num;
         u8      chip_rev;
         u8      chip_metal;
         u8      chip_bond_id;
         u8      chip_platform_type;
         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC      0x0UL
         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA      0x1UL
         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST     VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
         __le16  max_req_win_len;
         __le16  max_resp_len;
         __le16  def_req_timeout;
         u8      flags;
         #define VER_GET_RESP_FLAGS_DEV_NOT_RDY       0x1UL
         #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL     0x2UL
         u8      unused_0[2];
         u8      always_1;
         __le16  hwrm_intf_major;
         __le16  hwrm_intf_minor;
         __le16  hwrm_intf_build;
         __le16  hwrm_intf_patch;
         __le16  hwrm_fw_major;
         __le16  hwrm_fw_minor;
         __le16  hwrm_fw_build;
         __le16  hwrm_fw_patch;
         __le16  mgmt_fw_major;
         __le16  mgmt_fw_minor;
         __le16  mgmt_fw_build;
         __le16  mgmt_fw_patch;
         __le16  netctrl_fw_major;
         __le16  netctrl_fw_minor;
         __le16  netctrl_fw_build;
         __le16  netctrl_fw_patch;
         __le16  roce_fw_major;
         __le16  roce_fw_minor;
         __le16  roce_fw_build;
         __le16  roce_fw_patch;
         __le16  max_ext_req_len;
         u8      unused_1[5];
         u8      valid;
 };

 /* eject_cmpl (size:128b/16B) */
 struct eject_cmpl {
         __le16  type;
         #define EJECT_CMPL_TYPE_MASK       0x3fUL
         #define EJECT_CMPL_TYPE_SFT        0
         #define EJECT_CMPL_TYPE_STAT_EJECT   0x1aUL
         #define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT
         #define EJECT_CMPL_FLAGS_MASK      0xffc0UL
         #define EJECT_CMPL_FLAGS_SFT       6
         #define EJECT_CMPL_FLAGS_ERROR      0x40UL
         __le16  len;
         __le32  opaque;
         __le16  v;
         #define EJECT_CMPL_V                              0x1UL
         #define EJECT_CMPL_ERRORS_MASK                    0xfffeUL
         #define EJECT_CMPL_ERRORS_SFT                     1
         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        0xeUL
         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1
         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER     (0x0UL << 1)
         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (0x1UL << 1)
         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT    (0x3UL << 1)
         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH         (0x5UL << 1)
         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST         EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
         __le16  reserved16;
         __le32  unused_2;
 };

 /* hwrm_cmpl (size:128b/16B) */
 struct hwrm_cmpl {
         __le16  type;
         #define CMPL_TYPE_MASK     0x3fUL
         #define CMPL_TYPE_SFT      0
         #define CMPL_TYPE_HWRM_DONE  0x20UL
         #define CMPL_TYPE_LAST      CMPL_TYPE_HWRM_DONE
         __le16  sequence_id;
         __le32  unused_1;
         __le32  v;
         #define CMPL_V     0x1UL
         __le32  unused_3;
 };

 /* hwrm_fwd_req_cmpl (size:128b/16B) */
 struct hwrm_fwd_req_cmpl {
         __le16  req_len_type;
         #define FWD_REQ_CMPL_TYPE_MASK        0x3fUL
         #define FWD_REQ_CMPL_TYPE_SFT         0
         #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ  0x22UL
         #define FWD_REQ_CMPL_TYPE_LAST         FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
         #define FWD_REQ_CMPL_REQ_LEN_MASK     0xffc0UL
         #define FWD_REQ_CMPL_REQ_LEN_SFT      6
         __le16  source_id;
         __le32  unused0;
         __le32  req_buf_addr_v[2];
         #define FWD_REQ_CMPL_V                0x1UL
         #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
         #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
 };

 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
 struct hwrm_fwd_resp_cmpl {
         __le16  type;
         #define FWD_RESP_CMPL_TYPE_MASK         0x3fUL
         #define FWD_RESP_CMPL_TYPE_SFT          0
         #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP  0x24UL
         #define FWD_RESP_CMPL_TYPE_LAST          FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
         __le16  source_id;
         __le16  resp_len;
         __le16  unused_1;
         __le32  resp_buf_addr_v[2];
         #define FWD_RESP_CMPL_V                 0x1UL
         #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
         #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
 };

 /* hwrm_async_event_cmpl (size:128b/16B) */
 struct hwrm_async_event_cmpl {
         __le16  type;
         #define ASYNC_EVENT_CMPL_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_TYPE_LAST             ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE         0x0UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE            0x1UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE          0x2UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE          0x3UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED      0x4UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE      0x6UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE        0x7UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY               0x8UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY             0x9UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD           0x10UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD             0x11UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT        0x12UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD             0x20UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD               0x21UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR                     0x30UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE         0x31UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE   0x32UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE              0x33UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE            0x34UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE        0x35UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED               0x36UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION         0x37UL
         #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG               0xfeUL
         #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                 0xffUL
         #define ASYNC_EVENT_CMPL_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_V          0x1UL
         #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_ER_EVENT_DATA1_MASTER_FUNC          0x1UL
         #define ASYNC_EVENT_CMPL_ER_EVENT_DATA1_RECOVERY_ENABLED     0x2UL
         #define ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_FATAL       (0x2UL << 8)
         #define ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_MASK        0xff00UL
 };

 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_link_status_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE     0x1UL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN  0x0UL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP    0x1UL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK       0xeUL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT        1
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK    0xffff0UL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT     4
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK      0xff00000UL
         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT       20
 };

 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_link_mtu_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST           ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
 };

 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_link_speed_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_FORCE                       0x1UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_MASK 0xfffeUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_SFT  1
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_100MB  (0x1UL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_1GB    (0xaUL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_2GB    (0x14UL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_2_5GB  (0x19UL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_10GB   (0x64UL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_20GB   (0xc8UL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_25GB   (0xfaUL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_40GB   (0x190UL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_50GB   (0x1f4UL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_100GB  (0x3e8UL << 1)
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_LAST  ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_100GB
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_PORT_ID_MASK                0xffff0000UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_PORT_ID_SFT                 16
 };

 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_dcb_config_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST             ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
         __le32  event_data2;
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS     0x1UL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC     0x2UL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP     0x4UL
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK                0xffffUL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT                 0
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE  (0xffUL << 16)
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK  0xff000000UL
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT   24
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE    (0xffUL << 24)
         #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST   ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
 };

 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
 struct hwrm_async_event_cmpl_port_conn_not_allowed {
         __le16  type;
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V          0x1UL
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK                 0xffffUL
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT                  0
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK      0xff0000UL
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT       16
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE        (0x0UL << 16)
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (0x1UL << 16)
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG  (0x2UL << 16)
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN     (0x3UL << 16)
         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST       ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
 };

 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
         __le16  type;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V          0x1UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
 };

 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_link_speed_cfg_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_PORT_ID_MASK                     0xffffUL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_PORT_ID_SFT                      0
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_SUPPORTED_LINK_SPEEDS_CHANGE     0x10000UL
         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_ILLEGAL_LINK_SPEED_CFG           0x20000UL
 };

 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_port_phy_cfg_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST               ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_PORT_ID_MASK         0xffffUL
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_PORT_ID_SFT          0
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_FEC_CFG_CHANGE       0x10000UL
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EEE_CFG_CHANGE       0x20000UL
         #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_PAUSE_CFG_CHANGE     0x40000UL
 };

 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
 struct hwrm_async_event_cmpl_reset_notify {
         __le16  type;
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST             ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST        ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V          0x1UL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK                  0xffUL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT                   0
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE    0x1UL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN           0x2UL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST                   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK                    0xff00UL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT                     8
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST  (0x1UL << 8)
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL        (0x2UL << 8)
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL    (0x3UL << 8)
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST                     ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK           0xffff0000UL
         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT            16
 };

 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
 struct hwrm_async_event_cmpl_func_drvr_unload {
         __le16  type;
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST             ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST            ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V          0x1UL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
 };

 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
 struct hwrm_async_event_cmpl_func_drvr_load {
         __le16  type;
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST             ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST          ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V          0x1UL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
 };

 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
         __le16  type;
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST             ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST               ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V          0x1UL
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0
 };

 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
 struct hwrm_async_event_cmpl_pf_drvr_unload {
         __le16  type;
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST             ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST          ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V          0x1UL
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK   0x70000UL
         #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT    16
 };

 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
 struct hwrm_async_event_cmpl_pf_drvr_load {
         __le16  type;
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST             ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST        ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V          0x1UL
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK   0x70000UL
         #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT    16
 };

 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
 struct hwrm_async_event_cmpl_vf_flr {
         __le16  type;
         #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST             ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL
         #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST  ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_VF_FLR_V          0x1UL
         #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
         #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK 0xff0000UL
         #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
 };

 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_vf_mac_addr_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
         #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
 };

 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST                    ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED     0x1UL
 };

 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_vf_cfg_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST         ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE                0x1UL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE                0x2UL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE      0x4UL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE          0x8UL
         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE     0x10UL
 };

 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_llfc_pfc_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK         0xffc0UL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT          6
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST           ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK 0x3UL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT 0
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC  0x1UL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC   0x2UL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK    0x1cUL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT     2
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK 0x1fffe0UL
         #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT  5
 };

 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
 struct hwrm_async_event_cmpl_default_vnic_change {
         __le16  type;
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK         0xffc0UL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT          6
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST                   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V          0x1UL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK          0x3UL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT           0
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC  0x1UL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   0x2UL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST           ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK                   0x3fcUL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT                    2
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK                   0x3fffc00UL
         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT                    10
 };

 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
 struct hwrm_async_event_cmpl_hw_flow_aged {
         __le16  type;
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST             ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST        ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
         __le32  event_data2;
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          0x1UL
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK       0x7fffffffUL
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT        0
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION     0x80000000UL
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX    (0x0UL << 31)
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX    (0x1UL << 31)
         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
 };

 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
 struct hwrm_async_event_cmpl_hwrm_error {
         __le16  type;
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK            0x3fUL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT             0
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT  0x2eUL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST             ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
         __le16  event_id;
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST      ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
         __le32  event_data2;
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK    0xffUL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT     0
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING   0x0UL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL  0x1UL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL     0x2UL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST     ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
         u8      opaque_v;
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_V          0x1UL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
         u8      timestamp_lo;
         __le16  timestamp_hi;
         __le32  event_data1;
         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP     0x1UL
 };

 /* hwrm_func_reset_input (size:192b/24B) */
 struct hwrm_func_reset_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID     0x1UL
         __le16  vf_id;
         u8      func_reset_level;
         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL      0x0UL
         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME       0x1UL
         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF       0x3UL
         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST         FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
         u8      unused_0;
 };

 /* hwrm_func_reset_output (size:128b/16B) */
 struct hwrm_func_reset_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_getfid_input (size:192b/24B) */
 struct hwrm_func_getfid_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define FUNC_GETFID_REQ_ENABLES_PCI_ID     0x1UL
         __le16  pci_id;
         u8      unused_0[2];
 };

 /* hwrm_func_getfid_output (size:128b/16B) */
 struct hwrm_func_getfid_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  fid;
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_func_vf_alloc_input (size:192b/24B) */
 struct hwrm_func_vf_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID     0x1UL
         __le16  first_vf_id;
         __le16  num_vfs;
 };

 /* hwrm_func_vf_alloc_output (size:128b/16B) */
 struct hwrm_func_vf_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  first_vf_id;
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_func_vf_free_input (size:192b/24B) */
 struct hwrm_func_vf_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID     0x1UL
         __le16  first_vf_id;
         __le16  num_vfs;
 };

 /* hwrm_func_vf_free_output (size:128b/16B) */
 struct hwrm_func_vf_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_vf_cfg_input (size:448b/56B) */
 struct hwrm_func_vf_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define FUNC_VF_CFG_REQ_ENABLES_MTU                  0x1UL
         #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN           0x2UL
         #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR       0x4UL
         #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR        0x8UL
         #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS      0x10UL
         #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS       0x20UL
         #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS         0x40UL
         #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS         0x80UL
         #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS          0x100UL
         #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS            0x200UL
         #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS        0x400UL
         #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS     0x800UL
         __le16  mtu;
         __le16  guest_vlan;
         __le16  async_event_cr;
         u8      dflt_mac_addr[6];
         __le32  flags;
         #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST             0x1UL
         #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST             0x2UL
         #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST           0x4UL
         #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST     0x8UL
         #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST       0x10UL
         #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST       0x20UL
         #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST           0x40UL
         #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST         0x80UL
         __le16  num_rsscos_ctxs;
         __le16  num_cmpl_rings;
         __le16  num_tx_rings;
         __le16  num_rx_rings;
         __le16  num_l2_ctxs;
         __le16  num_vnics;
         __le16  num_stat_ctxs;
         __le16  num_hw_ring_grps;
         u8      unused_0[4];
 };

 /* hwrm_func_vf_cfg_output (size:128b/16B) */
 struct hwrm_func_vf_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_qcaps_input (size:192b/24B) */
 struct hwrm_func_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[6];
 };

 /* hwrm_func_qcaps_output (size:640b/80B) */
 struct hwrm_func_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  fid;
         __le16  port_id;
         __le32  flags;
         #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED             0x1UL
         #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING         0x2UL
         #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED                   0x4UL
         #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED               0x8UL
         #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED               0x10UL
         #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED          0x20UL
         #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED               0x40UL
         #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED            0x80UL
         #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED             0x100UL
         #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED         0x200UL
         #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED             0x400UL
         #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED      0x800UL
         #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED      0x1000UL
         #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED       0x2000UL
         #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED         0x4000UL
         #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED        0x8000UL
         #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED            0x10000UL
         #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED            0x20000UL
         #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED              0x40000UL
         #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED     0x80000UL
         #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE                   0x100000UL
         #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC           0x200000UL
         #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE               0x400000UL
         #define FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE        0x800000UL
         u8      mac_address[6];
         __le16  max_rsscos_ctx;
         __le16  max_cmpl_rings;
         __le16  max_tx_rings;
         __le16  max_rx_rings;
         __le16  max_l2_ctxs;
         __le16  max_vnics;
         __le16  first_vf_id;
         __le16  max_vfs;
         __le16  max_stat_ctx;
         __le32  max_encap_records;
         __le32  max_decap_records;
         __le32  max_tx_em_flows;
         __le32  max_tx_wm_flows;
         __le32  max_rx_em_flows;
         __le32  max_rx_wm_flows;
         __le32  max_mcast_filters;
         __le32  max_flow_id;
         __le32  max_hw_ring_grps;
         __le16  max_sp_tx_rings;
         u8      unused_0;
         u8      valid;
 };

 /* hwrm_func_qcfg_input (size:192b/24B) */
 struct hwrm_func_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[6];
 };

 /* hwrm_func_qcfg_output (size:704b/88B) */
 struct hwrm_func_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  fid;
         __le16  port_id;
         __le16  vlan;
         __le16  flags;
         #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED     0x1UL
         #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED          0x2UL
         #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED        0x4UL
         #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED     0x8UL
         #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED        0x10UL
         #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST                   0x20UL
         #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF                   0x40UL
         u8      mac_address[6];
         __le16  pci_id;
         __le16  alloc_rsscos_ctx;
         __le16  alloc_cmpl_rings;
         __le16  alloc_tx_rings;
         __le16  alloc_rx_rings;
         __le16  alloc_l2_ctx;
         __le16  alloc_vnics;
         __le16  mtu;
         __le16  mru;
         __le16  stat_ctx_id;
         u8      port_partition_type;
         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF     0x0UL
         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS    0x1UL
         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST   FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
         u8      port_pf_cnt;
         #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
         #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST   FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
         __le16  dflt_vnic_id;
         __le16  max_mtu_configured;
         __le32  min_bw;
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT              0
         #define FUNC_QCFG_RESP_MIN_BW_SCALE                     0x10000000UL
         #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  max_bw;
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT              0
         #define FUNC_QCFG_RESP_MAX_BW_SCALE                     0x10000000UL
         #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      evb_mode;
         #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
         #define FUNC_QCFG_RESP_EVB_MODE_VEB    0x1UL
         #define FUNC_QCFG_RESP_EVB_MODE_VEPA   0x2UL
         #define FUNC_QCFG_RESP_EVB_MODE_LAST  FUNC_QCFG_RESP_EVB_MODE_VEPA
         u8      options;
         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK         0x3UL
         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT          0
         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL
         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL
         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST          FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL
         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT        2
         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)
         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)
         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)
         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
         #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK                   0xf0UL
         #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT                    4
         __le16  alloc_vfs;
         __le32  alloc_mcast_filters;
         __le32  alloc_hw_ring_grps;
         __le16  alloc_sp_tx_rings;
         __le16  alloc_stat_ctx;
         __le16  alloc_msix;
         __le16  registered_vfs;
         u8      unused_1[3];
         u8      always_1;
         __le32  reset_addr_poll;
         u8      unused_2[3];
         u8      valid;
 };

 /* hwrm_func_cfg_input (size:704b/88B) */
 struct hwrm_func_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         __le16  num_msix;
         __le32  flags;
         #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE     0x1UL
         #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE      0x2UL
         #define FUNC_CFG_REQ_FLAGS_RSVD_MASK                      0x1fcUL
         #define FUNC_CFG_REQ_FLAGS_RSVD_SFT                       2
         #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE        0x200UL
         #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE       0x400UL
         #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST               0x800UL
         #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC         0x1000UL
         #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST                 0x2000UL
         #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST                 0x4000UL
         #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST               0x8000UL
         #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST         0x10000UL
         #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST           0x20000UL
         #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST           0x40000UL
         #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST               0x80000UL
         #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST             0x100000UL
         #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE              0x200000UL
         #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC          0x400000UL
         __le32  enables;
         #define FUNC_CFG_REQ_ENABLES_MTU                     0x1UL
         #define FUNC_CFG_REQ_ENABLES_MRU                     0x2UL
         #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS         0x4UL
         #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS          0x8UL
         #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS            0x10UL
         #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS            0x20UL
         #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS             0x40UL
         #define FUNC_CFG_REQ_ENABLES_NUM_VNICS               0x80UL
         #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS           0x100UL
         #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR           0x200UL
         #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN               0x400UL
         #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR            0x800UL
         #define FUNC_CFG_REQ_ENABLES_MIN_BW                  0x1000UL
         #define FUNC_CFG_REQ_ENABLES_MAX_BW                  0x2000UL
         #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR          0x4000UL
         #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE     0x8000UL
         #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS       0x10000UL
         #define FUNC_CFG_REQ_ENABLES_EVB_MODE                0x20000UL
         #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS       0x40000UL
         #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS        0x80000UL
         #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE          0x100000UL
         #define FUNC_CFG_REQ_ENABLES_NUM_MSIX                0x200000UL
         #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE        0x400000UL
         __le16  mtu;
         __le16  mru;
         __le16  num_rsscos_ctxs;
         __le16  num_cmpl_rings;
         __le16  num_tx_rings;
         __le16  num_rx_rings;
         __le16  num_l2_ctxs;
         __le16  num_vnics;
         __le16  num_stat_ctxs;
         __le16  num_hw_ring_grps;
         u8      dflt_mac_addr[6];
         __le16  dflt_vlan;
         __be32  dflt_ip_addr[4];
         __le32  min_bw;
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT              0
         #define FUNC_CFG_REQ_MIN_BW_SCALE                     0x10000000UL
         #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  max_bw;
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT              0
         #define FUNC_CFG_REQ_MAX_BW_SCALE                     0x10000000UL
         #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
         __le16  async_event_cr;
         u8      vlan_antispoof_mode;
         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK                 0x0UL
         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN           0x1UL
         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE       0x2UL
         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST                   FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
         u8      allowed_vlan_pris;
         u8      evb_mode;
         #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
         #define FUNC_CFG_REQ_EVB_MODE_VEB    0x1UL
         #define FUNC_CFG_REQ_EVB_MODE_VEPA   0x2UL
         #define FUNC_CFG_REQ_EVB_MODE_LAST  FUNC_CFG_REQ_EVB_MODE_VEPA
         u8      options;
         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK         0x3UL
         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT          0
         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL
         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL
         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST          FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL
         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT        2
         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)
         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)
         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)
         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
         #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK                   0xf0UL
         #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT                    4
         __le16  num_mcast_filters;
 };

 /* hwrm_func_cfg_output (size:128b/16B) */
 struct hwrm_func_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_qstats_input (size:192b/24B) */
 struct hwrm_func_qstats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[6];
 };

 /* hwrm_func_qstats_output (size:1408b/176B) */
 struct hwrm_func_qstats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  tx_ucast_pkts;
         __le64  tx_mcast_pkts;
         __le64  tx_bcast_pkts;
         __le64  tx_discard_pkts;
         __le64  tx_drop_pkts;
         __le64  tx_ucast_bytes;
         __le64  tx_mcast_bytes;
         __le64  tx_bcast_bytes;
         __le64  rx_ucast_pkts;
         __le64  rx_mcast_pkts;
         __le64  rx_bcast_pkts;
         __le64  rx_discard_pkts;
         __le64  rx_drop_pkts;
         __le64  rx_ucast_bytes;
         __le64  rx_mcast_bytes;
         __le64  rx_bcast_bytes;
         __le64  rx_agg_pkts;
         __le64  rx_agg_bytes;
         __le64  rx_agg_events;
         __le64  rx_agg_aborts;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_clr_stats_input (size:192b/24B) */
 struct hwrm_func_clr_stats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[6];
 };

 /* hwrm_func_clr_stats_output (size:128b/16B) */
 struct hwrm_func_clr_stats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
 struct hwrm_func_vf_resc_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  vf_id;
         u8      unused_0[6];
 };

 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
 struct hwrm_func_vf_resc_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_error_recovery_input (size:192b/24B) */
 struct hwrm_error_recovery_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      unused_0[8];
 };

 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
 struct hwrm_error_recovery_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  flags;
         #define ER_QCFG_FLAGS_HOST       0x1UL
         #define ER_QCFG_FLAGS_CO_CPU     0x2UL
         __le32  driver_polling_freq;
         __le32  master_wait_period;
         __le32  normal_wait_period;
         __le32  master_wait_post_reset;
         __le32  max_bailout_time;
         __le32  fw_health_status_reg;
         #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK    0x3UL
         #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_SFT     0
         #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG  0x0UL
         #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC       0x1UL
         #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0      0x2UL
         #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1      0x3UL
         #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_LAST     ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1
         #define ER_QCFG_FW_HEALTH_REG_ADDR_MASK          0xfffffffcUL
         #define ER_QCFG_FW_HEALTH_REG_ADDR_SFT           2
         __le32  fw_heartbeat_reg;
         #define ER_QCFG_FW_HB_REG_ADDR_SPACE_MASK    0x3UL
         #define ER_QCFG_FW_HB_REG_ADDR_SPACE_SFT     0
         #define ER_QCFG_FW_HB_REG_ADDR_SPACE_PCIE_CFG  0x0UL
         #define ER_QCFG_FW_HB_REG_ADDR_SPACE_GRC       0x1UL
         #define ER_QCFG_FW_HB_REG_ADDR_SPACE_BAR0      0x2UL
         #define ER_QCFG_FW_HB_REG_ADDR_SPACE_BAR1      0x3UL
         #define ER_QCFG_FW_HB_REG_ADDR_SPACE_LAST     ER_QCFG_FW_HB_REG_ADDR_SPACE_BAR1
         #define ER_QCFG_FW_HB_REG_ADDR_MASK          0xfffffffcUL
         #define ER_QCFG_FW_HB_REG_ADDR_SFT           2
         __le32  fw_reset_cnt_reg;
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_MASK    0x3UL
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_SFT     0
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_GRC       0x1UL
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_BAR0      0x2UL
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_BAR1      0x3UL
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_LAST     ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_MASK          0xfffffffcUL
         #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SFT           2
         __le32  reset_inprogress_reg;
         #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_MASK    0x3UL
         #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_SFT     0
         #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_PCIE_CFG  0x0UL
         #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_GRC       0x1UL
         #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_BAR0      0x2UL
         #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_BAR1      0x3UL
         #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_LAST     ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_BAR1
         #define ER_QCFG_RESET_INPRG_REG_ADDR_MASK          0xfffffffcUL
         #define ER_QCFG_RESET_INPRG_REG_ADDR_SFT           2
         __le32  reset_inprogress_reg_mask;
         u8      unused_0[3];
         u8      reg_array_cnt;
         __le32  reset_reg[16];
         #define ER_QCFG_RESET_REG_ADDR_SPACE_MASK    0x3UL
         #define ER_QCFG_RESET_REG_ADDR_SPACE_SFT     0
         #define ER_QCFG_RESET_REG_ADDR_SPACE_PCIE_CFG  0x0UL
         #define ER_QCFG_RESET_REG_ADDR_SPACE_GRC       0x1UL
         #define ER_QCFG_RESET_REG_ADDR_SPACE_BAR0      0x2UL
         #define ER_QCFG_RESET_REG_ADDR_SPACE_BAR1      0x3UL
         #define ER_QCFG_RESET_REG_ADDR_SPACE_LAST     ER_QCFG_RESET_REG_ADDR_SPACE_BAR1
         #define ER_QCFG_RESET_REG_ADDR_MASK          0xfffffffcUL
         #define ER_QCFG_RESET_REG_ADDR_SFT           2
         __le32  reset_reg_val[16];
         u8      delay_after_reset[16];
         __le32  err_recovery_cnt_reg;
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_MASK    0x3UL
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_SFT     0
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_GRC       0x1UL
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_BAR0      0x2UL
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_BAR1      0x3UL
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_LAST     ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_BAR1
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_MASK          0xfffffffcUL
         #define ER_QCFG_RCVRY_CNT_REG_ADDR_SFT           2
         u8      unused_1[3];
         u8      valid;
 };

 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
 struct hwrm_func_drv_rgtr_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE               0x1UL
         #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE              0x2UL
         #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE             0x4UL
         #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE     0x8UL
         #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT          0x10UL
         #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT     0x20UL
         #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT             0x40UL
         __le32  enables;
         #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE             0x1UL
         #define FUNC_DRV_RGTR_REQ_ENABLES_VER                 0x2UL
         #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP           0x4UL
         #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD          0x8UL
         #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD     0x10UL
         __le16  os_type;
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN   0x0UL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER     0x1UL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS     0xeUL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS   0x12UL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS   0x1dUL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX     0x24UL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD   0x2aUL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI      0x68UL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864    0x73UL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI      0x8000UL
         #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST     FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
         u8      ver_maj_8b;
         u8      ver_min_8b;
         u8      ver_upd_8b;
         u8      unused_0[3];
         __le32  timestamp;
         u8      unused_1[4];
         __le32  vf_req_fwd[8];
         __le32  async_event_fwd[8];
         __le16  ver_maj;
         __le16  ver_min;
         __le16  ver_upd;
         __le16  ver_patch;
 };

 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
 struct hwrm_func_drv_rgtr_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  flags;
         #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED     0x1UL
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
 struct hwrm_func_drv_unrgtr_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN     0x1UL
         u8      unused_0[4];
 };

 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
 struct hwrm_func_drv_unrgtr_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
 struct hwrm_func_buf_rgtr_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID            0x1UL
         #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR     0x2UL
         __le16  vf_id;
         __le16  req_buf_num_pages;
         __le16  req_buf_page_size;
         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K  0xcUL
         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K  0xdUL
         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M  0x15UL
         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M  0x16UL
         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G  0x1eUL
         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
         __le16  req_buf_len;
         __le16  resp_buf_len;
         u8      unused_0[2];
         __le64  req_buf_page_addr0;
         __le64  req_buf_page_addr1;
         __le64  req_buf_page_addr2;
         __le64  req_buf_page_addr3;
         __le64  req_buf_page_addr4;
         __le64  req_buf_page_addr5;
         __le64  req_buf_page_addr6;
         __le64  req_buf_page_addr7;
         __le64  req_buf_page_addr8;
         __le64  req_buf_page_addr9;
         __le64  error_buf_addr;
         __le64  resp_buf_addr;
 };

 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
 struct hwrm_func_buf_rgtr_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
 struct hwrm_func_buf_unrgtr_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define FUNC_BUF_UNRGTR_REQ_ENABLES_VF_ID     0x1UL
         __le16  vf_id;
         u8      unused_0[2];
 };

 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
 struct hwrm_func_buf_unrgtr_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_drv_qver_input (size:192b/24B) */
 struct hwrm_func_drv_qver_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  reserved;
         __le16  fid;
         u8      unused_0[2];
 };

 /* hwrm_func_drv_qver_output (size:256b/32B) */
 struct hwrm_func_drv_qver_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  os_type;
         #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN   0x0UL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER     0x1UL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS     0xeUL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS   0x12UL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS   0x1dUL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX     0x24UL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD   0x2aUL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI      0x68UL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864    0x73UL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI      0x8000UL
         #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST     FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
         u8      ver_maj_8b;
         u8      ver_min_8b;
         u8      ver_upd_8b;
         u8      unused_0[3];
         __le16  ver_maj;
         __le16  ver_min;
         __le16  ver_upd;
         __le16  ver_patch;
         u8      unused_1[7];
         u8      valid;
 };

 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
 struct hwrm_func_resource_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[6];
 };

 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
 struct hwrm_func_resource_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  max_vfs;
         __le16  max_msix;
         __le16  vf_reservation_strategy;
         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL        0x0UL
         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL        0x1UL
         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST          FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
         __le16  min_rsscos_ctx;
         __le16  max_rsscos_ctx;
         __le16  min_cmpl_rings;
         __le16  max_cmpl_rings;
         __le16  min_tx_rings;
         __le16  max_tx_rings;
         __le16  min_rx_rings;
         __le16  max_rx_rings;
         __le16  min_l2_ctxs;
         __le16  max_l2_ctxs;
         __le16  min_vnics;
         __le16  max_vnics;
         __le16  min_stat_ctx;
         __le16  max_stat_ctx;
         __le16  min_hw_ring_grps;
         __le16  max_hw_ring_grps;
         __le16  max_tx_scheduler_inputs;
         __le16  flags;
         #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED     0x1UL
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
 struct hwrm_func_vf_resource_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  vf_id;
         __le16  max_msix;
         __le16  min_rsscos_ctx;
         __le16  max_rsscos_ctx;
         __le16  min_cmpl_rings;
         __le16  max_cmpl_rings;
         __le16  min_tx_rings;
         __le16  max_tx_rings;
         __le16  min_rx_rings;
         __le16  max_rx_rings;
         __le16  min_l2_ctxs;
         __le16  max_l2_ctxs;
         __le16  min_vnics;
         __le16  max_vnics;
         __le16  min_stat_ctx;
         __le16  max_stat_ctx;
         __le16  min_hw_ring_grps;
         __le16  max_hw_ring_grps;
         __le16  flags;
         #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED     0x1UL
         u8      unused_0[2];
 };

 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
 struct hwrm_func_vf_resource_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  reserved_rsscos_ctx;
         __le16  reserved_cmpl_rings;
         __le16  reserved_tx_rings;
         __le16  reserved_rx_rings;
         __le16  reserved_l2_ctxs;
         __le16  reserved_vnics;
         __le16  reserved_stat_ctx;
         __le16  reserved_hw_ring_grps;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
 struct hwrm_func_backing_store_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
 struct hwrm_func_backing_store_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  qp_max_entries;
         __le16  qp_min_qp1_entries;
         __le16  qp_max_l2_entries;
         __le16  qp_entry_size;
         __le16  srq_max_l2_entries;
         __le32  srq_max_entries;
         __le16  srq_entry_size;
         __le16  cq_max_l2_entries;
         __le32  cq_max_entries;
         __le16  cq_entry_size;
         __le16  vnic_max_vnic_entries;
         __le16  vnic_max_ring_table_entries;
         __le16  vnic_entry_size;
         __le32  stat_max_entries;
         __le16  stat_entry_size;
         __le16  tqm_entry_size;
         __le32  tqm_min_entries_per_ring;
         __le32  tqm_max_entries_per_ring;
         __le32  mrav_max_entries;
         __le16  mrav_entry_size;
         __le16  tim_entry_size;
         __le32  tim_max_entries;
         u8      unused_0[2];
         u8      tqm_entries_multiple;
         u8      valid;
 };

 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
 struct hwrm_func_backing_store_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE     0x1UL
         __le32  enables;
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP            0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ           0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ            0x4UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC          0x8UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT          0x10UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP        0x20UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0     0x40UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1     0x80UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2     0x100UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3     0x200UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4     0x400UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5     0x800UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6     0x1000UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7     0x2000UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV          0x4000UL
         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM           0x8000UL
         u8      qpc_pg_size_qpc_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
         u8      srq_pg_size_srq_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
         u8      cq_pg_size_cq_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
         u8      vnic_pg_size_vnic_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
         u8      stat_pg_size_stat_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
         u8      tqm_sp_pg_size_tqm_sp_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
         u8      tqm_ring0_pg_size_tqm_ring0_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
         u8      tqm_ring1_pg_size_tqm_ring1_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
         u8      tqm_ring2_pg_size_tqm_ring2_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
         u8      tqm_ring3_pg_size_tqm_ring3_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
         u8      tqm_ring4_pg_size_tqm_ring4_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
         u8      tqm_ring5_pg_size_tqm_ring5_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
         u8      tqm_ring6_pg_size_tqm_ring6_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
         u8      tqm_ring7_pg_size_tqm_ring7_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
         u8      mrav_pg_size_mrav_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
         u8      tim_pg_size_tim_lvl;
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT       0
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
         __le64  qpc_page_dir;
         __le64  srq_page_dir;
         __le64  cq_page_dir;
         __le64  vnic_page_dir;
         __le64  stat_page_dir;
         __le64  tqm_sp_page_dir;
         __le64  tqm_ring0_page_dir;
         __le64  tqm_ring1_page_dir;
         __le64  tqm_ring2_page_dir;
         __le64  tqm_ring3_page_dir;
         __le64  tqm_ring4_page_dir;
         __le64  tqm_ring5_page_dir;
         __le64  tqm_ring6_page_dir;
         __le64  tqm_ring7_page_dir;
         __le64  mrav_page_dir;
         __le64  tim_page_dir;
         __le32  qp_num_entries;
         __le32  srq_num_entries;
         __le32  cq_num_entries;
         __le32  stat_num_entries;
         __le32  tqm_sp_num_entries;
         __le32  tqm_ring0_num_entries;
         __le32  tqm_ring1_num_entries;
         __le32  tqm_ring2_num_entries;
         __le32  tqm_ring3_num_entries;
         __le32  tqm_ring4_num_entries;
         __le32  tqm_ring5_num_entries;
         __le32  tqm_ring6_num_entries;
         __le32  tqm_ring7_num_entries;
         __le32  mrav_num_entries;
         __le32  tim_num_entries;
         __le16  qp_num_qp1_entries;
         __le16  qp_num_l2_entries;
         __le16  qp_entry_size;
         __le16  srq_num_l2_entries;
         __le16  srq_entry_size;
         __le16  cq_num_l2_entries;
         __le16  cq_entry_size;
         __le16  vnic_num_vnic_entries;
         __le16  vnic_num_ring_table_entries;
         __le16  vnic_entry_size;
         __le16  stat_entry_size;
         __le16  tqm_entry_size;
         __le16  mrav_entry_size;
         __le16  tim_entry_size;
 };

 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
 struct hwrm_func_backing_store_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
 struct hwrm_func_backing_store_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
 struct hwrm_func_backing_store_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  flags;
         #define FUNC_BACKING_STORE_QCFG_RESP_FLAGS_PREBOOT_MODE     0x1UL
         u8      unused_0[4];
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_QP            0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_SRQ           0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_CQ            0x4UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_VNIC          0x8UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_STAT          0x10UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_SP        0x20UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING0     0x40UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING1     0x80UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING2     0x100UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING3     0x200UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING4     0x400UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING5     0x800UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING6     0x1000UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING7     0x2000UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_MRAV          0x4000UL
         #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TIM           0x8000UL
         u8      qpc_pg_size_qpc_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G
         u8      srq_pg_size_srq_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G
         u8      cq_pg_size_cq_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G
         u8      vnic_pg_size_vnic_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G
         u8      stat_pg_size_stat_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G
         u8      tqm_sp_pg_size_tqm_sp_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G
         u8      tqm_ring0_pg_size_tqm_ring0_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G
         u8      tqm_ring1_pg_size_tqm_ring1_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G
         u8      tqm_ring2_pg_size_tqm_ring2_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G
         u8      tqm_ring3_pg_size_tqm_ring3_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G
         u8      tqm_ring4_pg_size_tqm_ring4_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G
         u8      tqm_ring5_pg_size_tqm_ring5_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G
         u8      tqm_ring6_pg_size_tqm_ring6_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G
         u8      tqm_ring7_pg_size_tqm_ring7_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G
         u8      mrav_pg_size_mrav_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G
         u8      tim_pg_size_tim_lvl;
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_MASK      0xfUL
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_SFT       0
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_0       0x0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_1       0x1UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2       0x2UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_MASK  0xf0UL
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_SFT   4
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_4K   (0x0UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8K   (0x1UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_64K  (0x2UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_2M   (0x3UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8M   (0x4UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G   (0x5UL << 4)
         #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G
         __le64  qpc_page_dir;
         __le64  srq_page_dir;
         __le64  cq_page_dir;
         __le64  vnic_page_dir;
         __le64  stat_page_dir;
         __le64  tqm_sp_page_dir;
         __le64  tqm_ring0_page_dir;
         __le64  tqm_ring1_page_dir;
         __le64  tqm_ring2_page_dir;
         __le64  tqm_ring3_page_dir;
         __le64  tqm_ring4_page_dir;
         __le64  tqm_ring5_page_dir;
         __le64  tqm_ring6_page_dir;
         __le64  tqm_ring7_page_dir;
         __le64  mrav_page_dir;
         __le64  tim_page_dir;
         __le16  qp_num_qp1_entries;
         __le16  qp_num_l2_entries;
         __le32  qp_num_entries;
         __le32  srq_num_entries;
         __le16  srq_num_l2_entries;
         __le16  cq_num_l2_entries;
         __le32  cq_num_entries;
         __le16  vnic_num_vnic_entries;
         __le16  vnic_num_ring_table_entries;
         __le32  stat_num_entries;
         __le32  tqm_sp_num_entries;
         __le32  tqm_ring0_num_entries;
         __le32  tqm_ring1_num_entries;
         __le32  tqm_ring2_num_entries;
         __le32  tqm_ring3_num_entries;
         __le32  tqm_ring4_num_entries;
         __le32  tqm_ring5_num_entries;
         __le32  tqm_ring6_num_entries;
         __le32  tqm_ring7_num_entries;
         __le32  mrav_num_entries;
         __le32  tim_num_entries;
         u8      unused_1[7];
         u8      valid;
 };

 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
 struct hwrm_func_vlan_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[6];
 };

 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
 struct hwrm_func_vlan_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  unused_0;
         __le16  stag_vid;
         u8      stag_pcp;
         u8      unused_1;
         __be16  stag_tpid;
         __le16  ctag_vid;
         u8      ctag_pcp;
         u8      unused_2;
         __be16  ctag_tpid;
         __le32  rsvd2;
         __le32  rsvd3;
         u8      unused_3[3];
         u8      valid;
 };

 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
 struct hwrm_func_vlan_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[2];
         __le32  enables;
         #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID      0x1UL
         #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID      0x2UL
         #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP      0x4UL
         #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP      0x8UL
         #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID     0x10UL
         #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID     0x20UL
         __le16  stag_vid;
         u8      stag_pcp;
         u8      unused_1;
         __be16  stag_tpid;
         __le16  ctag_vid;
         u8      ctag_pcp;
         u8      unused_2;
         __be16  ctag_tpid;
         __le32  rsvd1;
         __le32  rsvd2;
         u8      unused_3[4];
 };

 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
 struct hwrm_func_vlan_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
 struct hwrm_func_vf_vnic_ids_query_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  vf_id;
         u8      unused_0[2];
         __le32  max_vnic_id_cnt;
         __le64  vnic_id_tbl_addr;
 };

 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
 struct hwrm_func_vf_vnic_ids_query_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  vnic_id_cnt;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
 struct hwrm_func_vf_bw_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  num_vfs;
         __le16  unused[3];
         __le16  vfn[48];
         #define FUNC_VF_BW_CFG_REQ_VFN_VFID_MASK     0xfffUL
         #define FUNC_VF_BW_CFG_REQ_VFN_VFID_SFT      0
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_MASK     0xf000UL
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_SFT      12
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_0      (0x0UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_6_66   (0x1UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_13_33  (0x2UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_20     (0x3UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_26_66  (0x4UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_33_33  (0x5UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_40     (0x6UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_46_66  (0x7UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_53_33  (0x8UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_60     (0x9UL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_66_66  (0xaUL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_73_33  (0xbUL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_80     (0xcUL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_86_66  (0xdUL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_93_33  (0xeUL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100    (0xfUL << 12)
         #define FUNC_VF_BW_CFG_REQ_VFN_RATE_LAST      FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100
 };

 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
 struct hwrm_func_vf_bw_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
 struct hwrm_func_vf_bw_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  num_vfs;
         __le16  unused[3];
         __le16  vfn[48];
         #define FUNC_VF_BW_QCFG_REQ_VFN_VFID_MASK 0xfffUL
         #define FUNC_VF_BW_QCFG_REQ_VFN_VFID_SFT 0
 };

 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
 struct hwrm_func_vf_bw_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  num_vfs;
         __le16  unused[3];
         __le16  vfn[48];
         #define FUNC_VF_BW_QCFG_RESP_VFN_VFID_MASK     0xfffUL
         #define FUNC_VF_BW_QCFG_RESP_VFN_VFID_SFT      0
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_MASK     0xf000UL
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_SFT      12
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_0      (0x0UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_6_66   (0x1UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_13_33  (0x2UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_20     (0x3UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_26_66  (0x4UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_33_33  (0x5UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_40     (0x6UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_46_66  (0x7UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_53_33  (0x8UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_60     (0x9UL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_66_66  (0xaUL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_73_33  (0xbUL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_80     (0xcUL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_86_66  (0xdUL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_93_33  (0xeUL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100    (0xfUL << 12)
         #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_LAST      FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_func_drv_if_change_input (size:192b/24B) */
 struct hwrm_func_drv_if_change_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP     0x1UL
         __le32  unused;
 };

 /* hwrm_func_drv_if_change_output (size:128b/16B) */
 struct hwrm_func_drv_if_change_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  flags;
         #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE     0x1UL
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_port_phy_cfg_input (size:512b/64B) */
 struct hwrm_port_phy_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY                0x1UL
         #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED               0x2UL
         #define PORT_PHY_CFG_REQ_FLAGS_FORCE                    0x4UL
         #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG          0x8UL
         #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE               0x10UL
         #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE              0x20UL
         #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE        0x40UL
         #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE       0x80UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE       0x100UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE      0x200UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE      0x400UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE     0x800UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE      0x1000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE     0x2000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN           0x4000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE     0x8000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE    0x10000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE    0x20000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE   0x40000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE     0x80000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE    0x100000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE    0x200000UL
         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE   0x400000UL

         __le32  enables;
         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE                0x1UL
         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX              0x2UL
         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE               0x4UL
         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED          0x8UL
         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK     0x10UL
         #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED                0x20UL
         #define PORT_PHY_CFG_REQ_ENABLES_LPBK                     0x40UL
         #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS              0x80UL
         #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE              0x100UL
         #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK      0x200UL
         #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER             0x400UL
         #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED         0x800UL
         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK     0x1000UL
         #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2            0x2000UL
         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK        0x4000UL
         __le16  port_id;
         __le16  force_link_speed;
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB   0xaUL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB   0x14UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB  0x64UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB  0xc8UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB  0xfaUL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB  0x190UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB  0x1f4UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB  0xffffUL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
         u8      auto_mode;
         #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE         0x0UL
         #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS   0x1UL
         #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED    0x2UL
         #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
         #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK   0x4UL
         #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST        PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
         u8      auto_duplex;
         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
         u8      auto_pause;
         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX                0x1UL
         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX                0x2UL
         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL
         u8      unused_0;
         __le16  auto_link_speed;
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB   0xaUL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB   0x14UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB  0x64UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB  0xc8UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB  0xfaUL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB  0x190UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB  0x1f4UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB  0xffffUL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
         __le16  auto_link_speed_mask;
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB       0x2UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB         0x8UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB         0x10UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB        0x40UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB        0x80UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB        0x100UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB        0x200UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB        0x400UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB       0x800UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB        0x2000UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB       0x4000UL
         u8      wirespeed;
         #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
         #define PORT_PHY_CFG_REQ_WIRESPEED_ON  0x1UL
         #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
         u8      lpbk;
         #define PORT_PHY_CFG_REQ_LPBK_NONE     0x0UL
         #define PORT_PHY_CFG_REQ_LPBK_LOCAL    0x1UL
         #define PORT_PHY_CFG_REQ_LPBK_REMOTE   0x2UL
         #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
         #define PORT_PHY_CFG_REQ_LPBK_LAST    PORT_PHY_CFG_REQ_LPBK_EXTERNAL
         u8      force_pause;
         #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX     0x1UL
         #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX     0x2UL
         u8      unused_1;
         __le32  preemphasis;
         __le16  eee_link_speed_mask;
         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB     0x2UL
         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB       0x8UL
         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB      0x40UL
         __le16  force_pam4_link_speed;
         #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL
         #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
         #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
         #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
         __le32  tx_lpi_timer;
         #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
         #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
         __le16  auto_link_pam4_speed_mask;
         #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G      0x1UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G     0x2UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G     0x4UL
         __le16  force_link_speeds2;
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB            0xaUL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB           0x64UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB           0xfaUL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB           0x190UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB           0x1f4UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB          0x3e8UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56   0x1f5UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56  0x3e9UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56  0x7d1UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56  0xfa1UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL
         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
         __le16  auto_link_speeds2_mask;
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB                0x1UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB               0x2UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB               0x4UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB               0x8UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB               0x10UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB              0x20UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56       0x40UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56      0x80UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56      0x100UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56      0x200UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112     0x400UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112     0x800UL
         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112     0x1000UL
         u8      unused_2[6];
 };

 /* hwrm_port_phy_cfg_output (size:128b/16B) */
 struct hwrm_port_phy_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
 struct hwrm_port_phy_cfg_cmd_err {
         u8      code;
         #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN       0x0UL
         #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
         #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY         0x2UL
         #define PORT_PHY_CFG_CMD_ERR_CODE_LAST         PORT_PHY_CFG_CMD_ERR_CODE_RETRY
         u8      unused_0[7];
 };

 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
 struct hwrm_port_phy_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
 };

 /* hwrm_port_phy_qcfg_output (size:832b/104B) */
 struct hwrm_port_phy_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      link;
         #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
         #define PORT_PHY_QCFG_RESP_LINK_SIGNAL  0x1UL
         #define PORT_PHY_QCFG_RESP_LINK_LINK    0x2UL
         #define PORT_PHY_QCFG_RESP_LINK_LAST   PORT_PHY_QCFG_RESP_LINK_LINK
         u8      active_fec_signal_mode;
         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK     0xfUL
         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT      0
         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ      0x0UL
         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4     0x1UL
         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL
         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST     HWRM_PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK                   0xf0UL
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT                    4
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE        (0x0UL << 4)
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE    (0x1UL << 4)
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE    (0x2UL << 4)
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE   (0x3UL << 4)
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE  (0x4UL << 4)
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE   (0x5UL << 4)
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE  (0x6UL << 4)
         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST                   PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
         __le16  link_speed;
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB   0xaUL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB   0x14UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB  0x64UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB  0xc8UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB  0xfaUL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB  0x190UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB  0x1f4UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB  0xffffUL
         #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
         u8      duplex_cfg;
         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
         u8      pause;
         #define PORT_PHY_QCFG_RESP_PAUSE_TX     0x1UL
         #define PORT_PHY_QCFG_RESP_PAUSE_RX     0x2UL
         __le16  support_speeds;
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD     0x1UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB       0x2UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD       0x4UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB         0x8UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB         0x10UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB       0x20UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB        0x40UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB        0x80UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB        0x100UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB        0x200UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB        0x400UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB       0x800UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD      0x1000UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB        0x2000UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB       0x4000UL
         __le16  force_link_speed;
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB   0xaUL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB   0x14UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB  0x64UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB  0xc8UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB  0xfaUL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB  0x190UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB  0x1f4UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB  0xffffUL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
         u8      auto_mode;
         #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE         0x0UL
         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS   0x1UL
         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED    0x2UL
         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
         #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK   0x4UL
         #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
         u8      auto_pause;
         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX                0x1UL
         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX                0x2UL
         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL
         __le16  auto_link_speed;
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB   0xaUL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB   0x14UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB  0x64UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB  0xc8UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB  0xfaUL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB  0x190UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB  0x1f4UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB  0xffffUL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
         __le16  auto_link_speed_mask;
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB       0x2UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB         0x8UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB         0x10UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB        0x40UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB        0x80UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB        0x100UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB        0x200UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB        0x400UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB       0x800UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB        0x2000UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB       0x4000UL
         u8      wirespeed;
         #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
         #define PORT_PHY_QCFG_RESP_WIRESPEED_ON  0x1UL
         #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
         u8      lpbk;
         #define PORT_PHY_QCFG_RESP_LPBK_NONE     0x0UL
         #define PORT_PHY_QCFG_RESP_LPBK_LOCAL    0x1UL
         #define PORT_PHY_QCFG_RESP_LPBK_REMOTE   0x2UL
         #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
         #define PORT_PHY_QCFG_RESP_LPBK_LAST    PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
         u8      force_pause;
         #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX     0x1UL
         #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX     0x2UL
         u8      module_status;
         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE          0x0UL
         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX     0x1UL
         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG    0x2UL
         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN       0x3UL
         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED   0x4UL
         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST         PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
         __le32  preemphasis;
         u8      phy_maj;
         u8      phy_min;
         u8      phy_bld;
         u8      phy_type;
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN          0x0UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR           0x1UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4          0x2UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR           0x3UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR           0x4UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2          0x5UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX           0x6UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR           0x7UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET            0x8UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE           0x9UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY      0xaUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L  0xbUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S  0xcUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N  0xdUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR       0xeUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4     0xfUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4     0x10UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4     0x11UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4     0x12UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10    0x13UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4      0x14UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4      0x15UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4      0x16UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4      0x17UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET         0x19UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX        0x1aUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX        0x1bUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4     0x1cUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4     0x1dUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4     0x1eUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4     0x1fUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR       0x20UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR       0x21UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR       0x22UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER       0x23UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2     0x24UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2     0x25UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2     0x26UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2     0x27UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR      0x28UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR      0x29UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR      0x2aUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER      0x2bUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2     0x2cUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2     0x2dUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2     0x2eUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2     0x2fUL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8     0x30UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8     0x31UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8     0x32UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8     0x33UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4     0x34UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4     0x35UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4     0x36UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4     0x37UL
         #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4
         u8      media_type;
         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP      0x1UL
         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC     0x2UL
         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE   0x3UL
         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST   PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
         u8      xcvr_pkg_type;
         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST         PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
         u8      eee_config_phy_addr;
         #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK              0x1fUL
         #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT               0
         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK            0xe0UL
         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT             5
         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED      0x20UL
         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE       0x40UL
         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI       0x80UL
         u8      parallel_detect;
         #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT     0x1UL
         __le16  link_partner_adv_speeds;
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD     0x1UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB       0x2UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD       0x4UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB         0x8UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB         0x10UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB       0x20UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB        0x40UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB        0x80UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB        0x100UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB        0x200UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB        0x400UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB       0x800UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD      0x1000UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB        0x2000UL
         u8      link_partner_adv_auto_mode;
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE         0x0UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS   0x1UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED    0x2UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK   0x4UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
         u8      link_partner_adv_pause;
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX     0x1UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX     0x2UL
         __le16  adv_eee_link_speed_mask;
         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL
         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL
         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL
         __le16  link_partner_adv_eee_link_speed_mask;
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL
         __le32  xcvr_identifier_type_tx_lpi_timer;
         #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK            0xffffffUL
         #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT             0
         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK    0xff000000UL
         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT     24
         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN   (0x0UL << 24)
         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP       (0x3UL << 24)
         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP      (0xcUL << 24)
         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS  (0xdUL << 24)
         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28    (0x11UL << 24)
         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST     PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
         __le16  fec_cfg;
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED         0x1UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED      0x2UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED        0x4UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED     0x8UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED       0x10UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED     0x20UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED       0x40UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED    0x80UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED      0x100UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED   0x200UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED     0x400UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED    0x800UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED      0x1000UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED   0x2000UL
         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED     0x4000UL
         u8      duplex_state;
         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
         u8      option_flags;
         #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT     0x1UL
         #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN     0x2UL
         #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED     0x4UL
         char    phy_vendor_name[16];
         char    phy_vendor_partnumber[16];
         __le16  support_pam4_speeds;
         #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G      0x1UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G     0x2UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G     0x4UL
         __le16  force_pam4_link_speed;
         #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL
         #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
         #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
         #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
         __le16  auto_pam4_link_speed_mask;
         #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G      0x1UL
         #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G     0x2UL
         #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G     0x4UL
         u8      link_partner_pam4_adv_speeds;
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB      0x1UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB     0x2UL
         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB     0x4UL
         u8      link_down_reason;
         #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF     0x1UL
         __le16  support_speeds2;
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB                0x1UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB               0x2UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB               0x4UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB               0x8UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB               0x10UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB              0x20UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56       0x40UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56      0x80UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56      0x100UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56      0x200UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112     0x400UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112     0x800UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112     0x1000UL
         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112     0x2000UL
         __le16  force_link_speeds2;
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB            0xaUL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB           0x64UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB           0xfaUL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB           0x190UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB           0x1f4UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB          0x3e8UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56   0x1f5UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56  0x3e9UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56  0x7d1UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56  0xfa1UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL
         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112
         __le16  auto_link_speeds2;
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB                0x1UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB               0x2UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB               0x4UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB               0x8UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB               0x10UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB              0x20UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56       0x40UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56      0x80UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56      0x100UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56      0x200UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112     0x400UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112     0x800UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112     0x1000UL
         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112     0x2000UL
         u8      active_lanes;
         u8      valid;
 };

 /* hwrm_port_mac_cfg_input (size:320b/40B) */
 struct hwrm_port_mac_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK                    0x1UL
         #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE           0x2UL
         #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE         0x4UL
         #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE            0x8UL
         #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE      0x10UL
         #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE     0x20UL
         #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE      0x40UL
         #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE     0x80UL
         #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE                0x100UL
         #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE               0x200UL
         #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE          0x400UL
         #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE        0x800UL
         #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE           0x1000UL
         __le32  enables;
         #define PORT_MAC_CFG_REQ_ENABLES_IPG                            0x1UL
         #define PORT_MAC_CFG_REQ_ENABLES_LPBK                           0x2UL
         #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI           0x4UL
         #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI         0x10UL
         #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI               0x20UL
         #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE     0x40UL
         #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE     0x80UL
         #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG                  0x100UL
         __le16  port_id;
         u8      ipg;
         u8      lpbk;
         #define PORT_MAC_CFG_REQ_LPBK_NONE   0x0UL
         #define PORT_MAC_CFG_REQ_LPBK_LOCAL  0x1UL
         #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
         #define PORT_MAC_CFG_REQ_LPBK_LAST  PORT_MAC_CFG_REQ_LPBK_REMOTE
         u8      vlan_pri2cos_map_pri;
         u8      reserved1;
         u8      tunnel_pri2cos_map_pri;
         u8      dscp2pri_map_pri;
         __le16  rx_ts_capture_ptp_msg_type;
         __le16  tx_ts_capture_ptp_msg_type;
         u8      cos_field_cfg;
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1                     0x1UL
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK         0x6UL
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT          1
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST      (0x0UL << 1)
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER          (0x1UL << 1)
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST      (0x2UL << 1)
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED    (0x3UL << 1)
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST          PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK       0x18UL
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT        3
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST    (0x0UL << 3)
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER        (0x1UL << 3)
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST    (0x2UL << 3)
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (0x3UL << 3)
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST        PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK          0xe0UL
         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT           5
         u8      unused_0[3];
 };

 /* hwrm_port_mac_cfg_output (size:128b/16B) */
 struct hwrm_port_mac_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  mru;
         __le16  mtu;
         u8      ipg;
         u8      lpbk;
         #define PORT_MAC_CFG_RESP_LPBK_NONE   0x0UL
         #define PORT_MAC_CFG_RESP_LPBK_LOCAL  0x1UL
         #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
         #define PORT_MAC_CFG_RESP_LPBK_LAST  PORT_MAC_CFG_RESP_LPBK_REMOTE
         u8      unused_0;
         u8      valid;
 };

 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
 struct hwrm_port_mac_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
 };

 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
 struct hwrm_port_mac_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  mru;
         __le16  mtu;
         u8      ipg;
         u8      lpbk;
         #define PORT_MAC_QCFG_RESP_LPBK_NONE   0x0UL
         #define PORT_MAC_QCFG_RESP_LPBK_LOCAL  0x1UL
         #define PORT_MAC_QCFG_RESP_LPBK_REMOTE 0x2UL
         #define PORT_MAC_QCFG_RESP_LPBK_LAST  PORT_MAC_QCFG_RESP_LPBK_REMOTE
         u8      vlan_pri2cos_map_pri;
         u8      flags;
         #define PORT_MAC_QCFG_RESP_FLAGS_VLAN_PRI2COS_ENABLE          0x1UL
         #define PORT_MAC_QCFG_RESP_FLAGS_TUNNEL_PRI2COS_ENABLE        0x2UL
         #define PORT_MAC_QCFG_RESP_FLAGS_IP_DSCP2COS_ENABLE           0x4UL
         #define PORT_MAC_QCFG_RESP_FLAGS_OOB_WOL_ENABLE               0x8UL
         #define PORT_MAC_QCFG_RESP_FLAGS_PTP_RX_TS_CAPTURE_ENABLE     0x10UL
         #define PORT_MAC_QCFG_RESP_FLAGS_PTP_TX_TS_CAPTURE_ENABLE     0x20UL
         u8      tunnel_pri2cos_map_pri;
         u8      dscp2pri_map_pri;
         __le16  rx_ts_capture_ptp_msg_type;
         __le16  tx_ts_capture_ptp_msg_type;
         u8      cos_field_cfg;
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_RSVD                      0x1UL
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_MASK         0x6UL
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_SFT          1
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST      (0x0UL << 1)
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER          (0x1UL << 1)
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST      (0x2UL << 1)
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED    (0x3UL << 1)
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_LAST          PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK       0x18UL
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT        3
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST    (0x0UL << 3)
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER        (0x1UL << 3)
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST    (0x2UL << 3)
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (0x3UL << 3)
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST        PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_MASK          0xe0UL
         #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_SFT           5
         u8      valid;
 };

 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
 struct hwrm_port_mac_ptp_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
 };

 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
 struct hwrm_port_mac_ptp_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      flags;
         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS     0x1UL
         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS       0x2UL
         u8      unused_0[3];
         __le32  rx_ts_reg_off_lower;
         __le32  rx_ts_reg_off_upper;
         __le32  rx_ts_reg_off_seq_id;
         __le32  rx_ts_reg_off_src_id_0;
         __le32  rx_ts_reg_off_src_id_1;
         __le32  rx_ts_reg_off_src_id_2;
         __le32  rx_ts_reg_off_domain_id;
         __le32  rx_ts_reg_off_fifo;
         __le32  rx_ts_reg_off_fifo_adv;
         __le32  rx_ts_reg_off_granularity;
         __le32  tx_ts_reg_off_lower;
         __le32  tx_ts_reg_off_upper;
         __le32  tx_ts_reg_off_seq_id;
         __le32  tx_ts_reg_off_fifo;
         __le32  tx_ts_reg_off_granularity;
         u8      unused_1[7];
         u8      valid;
 };

 /* tx_port_stats (size:3264b/408B) */
 struct tx_port_stats {
         __le64  tx_64b_frames;
         __le64  tx_65b_127b_frames;
         __le64  tx_128b_255b_frames;
         __le64  tx_256b_511b_frames;
         __le64  tx_512b_1023b_frames;
         __le64  tx_1024b_1518b_frames;
         __le64  tx_good_vlan_frames;
         __le64  tx_1519b_2047b_frames;
         __le64  tx_2048b_4095b_frames;
         __le64  tx_4096b_9216b_frames;
         __le64  tx_9217b_16383b_frames;
         __le64  tx_good_frames;
         __le64  tx_total_frames;
         __le64  tx_ucast_frames;
         __le64  tx_mcast_frames;
         __le64  tx_bcast_frames;
         __le64  tx_pause_frames;
         __le64  tx_pfc_frames;
         __le64  tx_jabber_frames;
         __le64  tx_fcs_err_frames;
         __le64  tx_control_frames;
         __le64  tx_oversz_frames;
         __le64  tx_single_dfrl_frames;
         __le64  tx_multi_dfrl_frames;
         __le64  tx_single_coll_frames;
         __le64  tx_multi_coll_frames;
         __le64  tx_late_coll_frames;
         __le64  tx_excessive_coll_frames;
         __le64  tx_frag_frames;
         __le64  tx_err;
         __le64  tx_tagged_frames;
         __le64  tx_dbl_tagged_frames;
         __le64  tx_runt_frames;
         __le64  tx_fifo_underruns;
         __le64  tx_pfc_ena_frames_pri0;
         __le64  tx_pfc_ena_frames_pri1;
         __le64  tx_pfc_ena_frames_pri2;
         __le64  tx_pfc_ena_frames_pri3;
         __le64  tx_pfc_ena_frames_pri4;
         __le64  tx_pfc_ena_frames_pri5;
         __le64  tx_pfc_ena_frames_pri6;
         __le64  tx_pfc_ena_frames_pri7;
         __le64  tx_eee_lpi_events;
         __le64  tx_eee_lpi_duration;
         __le64  tx_llfc_logical_msgs;
         __le64  tx_hcfc_msgs;
         __le64  tx_total_collisions;
         __le64  tx_bytes;
         __le64  tx_xthol_frames;
         __le64  tx_stat_discard;
         __le64  tx_stat_error;
 };

 /* rx_port_stats (size:4224b/528B) */
 struct rx_port_stats {
         __le64  rx_64b_frames;
         __le64  rx_65b_127b_frames;
         __le64  rx_128b_255b_frames;
         __le64  rx_256b_511b_frames;
         __le64  rx_512b_1023b_frames;
         __le64  rx_1024b_1518b_frames;
         __le64  rx_good_vlan_frames;
         __le64  rx_1519b_2047b_frames;
         __le64  rx_2048b_4095b_frames;
         __le64  rx_4096b_9216b_frames;
         __le64  rx_9217b_16383b_frames;
         __le64  rx_total_frames;
         __le64  rx_ucast_frames;
         __le64  rx_mcast_frames;
         __le64  rx_bcast_frames;
         __le64  rx_fcs_err_frames;
         __le64  rx_ctrl_frames;
         __le64  rx_pause_frames;
         __le64  rx_pfc_frames;
         __le64  rx_unsupported_opcode_frames;
         __le64  rx_unsupported_da_pausepfc_frames;
         __le64  rx_wrong_sa_frames;
         __le64  rx_align_err_frames;
         __le64  rx_oor_len_frames;
         __le64  rx_code_err_frames;
         __le64  rx_false_carrier_frames;
         __le64  rx_ovrsz_frames;
         __le64  rx_jbr_frames;
         __le64  rx_mtu_err_frames;
         __le64  rx_match_crc_frames;
         __le64  rx_promiscuous_frames;
         __le64  rx_tagged_frames;
         __le64  rx_double_tagged_frames;
         __le64  rx_trunc_frames;
         __le64  rx_good_frames;
         __le64  rx_pfc_xon2xoff_frames_pri0;
         __le64  rx_pfc_xon2xoff_frames_pri1;
         __le64  rx_pfc_xon2xoff_frames_pri2;
         __le64  rx_pfc_xon2xoff_frames_pri3;
         __le64  rx_pfc_xon2xoff_frames_pri4;
         __le64  rx_pfc_xon2xoff_frames_pri5;
         __le64  rx_pfc_xon2xoff_frames_pri6;
         __le64  rx_pfc_xon2xoff_frames_pri7;
         __le64  rx_pfc_ena_frames_pri0;
         __le64  rx_pfc_ena_frames_pri1;
         __le64  rx_pfc_ena_frames_pri2;
         __le64  rx_pfc_ena_frames_pri3;
         __le64  rx_pfc_ena_frames_pri4;
         __le64  rx_pfc_ena_frames_pri5;
         __le64  rx_pfc_ena_frames_pri6;
         __le64  rx_pfc_ena_frames_pri7;
         __le64  rx_sch_crc_err_frames;
         __le64  rx_undrsz_frames;
         __le64  rx_frag_frames;
         __le64  rx_eee_lpi_events;
         __le64  rx_eee_lpi_duration;
         __le64  rx_llfc_physical_msgs;
         __le64  rx_llfc_logical_msgs;
         __le64  rx_llfc_msgs_with_crc_err;
         __le64  rx_hcfc_msgs;
         __le64  rx_hcfc_msgs_with_crc_err;
         __le64  rx_bytes;
         __le64  rx_runt_bytes;
         __le64  rx_runt_frames;
         __le64  rx_stat_discard;
         __le64  rx_stat_err;
 };

 /* hwrm_port_qstats_input (size:320b/40B) */
 struct hwrm_port_qstats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
         __le64  tx_stat_host_addr;
         __le64  rx_stat_host_addr;
 };

 /* hwrm_port_qstats_output (size:128b/16B) */
 struct hwrm_port_qstats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  tx_stat_size;
         __le16  rx_stat_size;
         u8      unused_0[3];
         u8      valid;
 };

 /* tx_port_stats_ext (size:2048b/256B) */
 struct tx_port_stats_ext {
         __le64  tx_bytes_cos0;
         __le64  tx_bytes_cos1;
         __le64  tx_bytes_cos2;
         __le64  tx_bytes_cos3;
         __le64  tx_bytes_cos4;
         __le64  tx_bytes_cos5;
         __le64  tx_bytes_cos6;
         __le64  tx_bytes_cos7;
         __le64  tx_packets_cos0;
         __le64  tx_packets_cos1;
         __le64  tx_packets_cos2;
         __le64  tx_packets_cos3;
         __le64  tx_packets_cos4;
         __le64  tx_packets_cos5;
         __le64  tx_packets_cos6;
         __le64  tx_packets_cos7;
         __le64  pfc_pri0_tx_duration_us;
         __le64  pfc_pri0_tx_transitions;
         __le64  pfc_pri1_tx_duration_us;
         __le64  pfc_pri1_tx_transitions;
         __le64  pfc_pri2_tx_duration_us;
         __le64  pfc_pri2_tx_transitions;
         __le64  pfc_pri3_tx_duration_us;
         __le64  pfc_pri3_tx_transitions;
         __le64  pfc_pri4_tx_duration_us;
         __le64  pfc_pri4_tx_transitions;
         __le64  pfc_pri5_tx_duration_us;
         __le64  pfc_pri5_tx_transitions;
         __le64  pfc_pri6_tx_duration_us;
         __le64  pfc_pri6_tx_transitions;
         __le64  pfc_pri7_tx_duration_us;
         __le64  pfc_pri7_tx_transitions;
 };

 /* rx_port_stats_ext (size:2368b/296B) */
 struct rx_port_stats_ext {
         __le64  link_down_events;
         __le64  continuous_pause_events;
         __le64  resume_pause_events;
         __le64  continuous_roce_pause_events;
         __le64  resume_roce_pause_events;
         __le64  rx_bytes_cos0;
         __le64  rx_bytes_cos1;
         __le64  rx_bytes_cos2;
         __le64  rx_bytes_cos3;
         __le64  rx_bytes_cos4;
         __le64  rx_bytes_cos5;
         __le64  rx_bytes_cos6;
         __le64  rx_bytes_cos7;
         __le64  rx_packets_cos0;
         __le64  rx_packets_cos1;
         __le64  rx_packets_cos2;
         __le64  rx_packets_cos3;
         __le64  rx_packets_cos4;
         __le64  rx_packets_cos5;
         __le64  rx_packets_cos6;
         __le64  rx_packets_cos7;
         __le64  pfc_pri0_rx_duration_us;
         __le64  pfc_pri0_rx_transitions;
         __le64  pfc_pri1_rx_duration_us;
         __le64  pfc_pri1_rx_transitions;
         __le64  pfc_pri2_rx_duration_us;
         __le64  pfc_pri2_rx_transitions;
         __le64  pfc_pri3_rx_duration_us;
         __le64  pfc_pri3_rx_transitions;
         __le64  pfc_pri4_rx_duration_us;
         __le64  pfc_pri4_rx_transitions;
         __le64  pfc_pri5_rx_duration_us;
         __le64  pfc_pri5_rx_transitions;
         __le64  pfc_pri6_rx_duration_us;
         __le64  pfc_pri6_rx_transitions;
         __le64  pfc_pri7_rx_duration_us;
         __le64  pfc_pri7_rx_transitions;
 };

 /* hwrm_port_qstats_ext_input (size:320b/40B) */
 struct hwrm_port_qstats_ext_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         __le16  tx_stat_size;
         __le16  rx_stat_size;
         u8      unused_0[2];
         __le64  tx_stat_host_addr;
         __le64  rx_stat_host_addr;
 };

 /* hwrm_port_qstats_ext_output (size:128b/16B) */
 struct hwrm_port_qstats_ext_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  tx_stat_size;
         __le16  rx_stat_size;
         __le16  total_active_cos_queues;
         u8      flags;
         #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED     0x1UL
         u8      valid;
 };

 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
 struct hwrm_port_lpbk_qstats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
 struct hwrm_port_lpbk_qstats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  lpbk_ucast_frames;
         __le64  lpbk_mcast_frames;
         __le64  lpbk_bcast_frames;
         __le64  lpbk_ucast_bytes;
         __le64  lpbk_mcast_bytes;
         __le64  lpbk_bcast_bytes;
         __le64  tx_stat_discard;
         __le64  tx_stat_error;
         __le64  rx_stat_discard;
         __le64  rx_stat_error;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_port_clr_stats_input (size:192b/24B) */
 struct hwrm_port_clr_stats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      flags;
         #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS     0x1UL
         u8      unused_0[5];
 };

 /* hwrm_port_clr_stats_output (size:128b/16B) */
 struct hwrm_port_clr_stats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
 struct hwrm_port_lpbk_clr_stats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
 struct hwrm_port_lpbk_clr_stats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_port_ts_query_input (size:192b/24B) */
 struct hwrm_port_ts_query_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define PORT_TS_QUERY_REQ_FLAGS_PATH     0x1UL
         #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX    0x0UL
         #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX    0x1UL
         #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX
         __le16  port_id;
         u8      unused_0[2];
 };

 /* hwrm_port_ts_query_output (size:192b/24B) */
 struct hwrm_port_ts_query_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  ptp_msg_ts;
         __le16  ptp_msg_seqid;
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
 struct hwrm_port_phy_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
 };

 /* hwrm_port_phy_qcaps_output (size:320b/40B) */
 struct hwrm_port_phy_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      flags;
         #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED               0x1UL
         #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED     0x2UL
         #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK                  0xfcUL
         #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT                   2
         u8      port_cnt;
         #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
         #define PORT_PHY_QCAPS_RESP_PORT_CNT_1       0x1UL
         #define PORT_PHY_QCAPS_RESP_PORT_CNT_2       0x2UL
         #define PORT_PHY_QCAPS_RESP_PORT_CNT_3       0x3UL
         #define PORT_PHY_QCAPS_RESP_PORT_CNT_4       0x4UL
         #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST   PORT_PHY_QCAPS_RESP_PORT_CNT_4
         __le16  supported_speeds_force_mode;
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD     0x1UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB       0x2UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD       0x4UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB         0x8UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB         0x10UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB       0x20UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB        0x40UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB        0x80UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB        0x100UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB        0x200UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB        0x400UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB       0x800UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD      0x1000UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB        0x2000UL
         __le16  supported_speeds_auto_mode;
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD     0x1UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB       0x2UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD       0x4UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB         0x8UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB         0x10UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB       0x20UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB        0x40UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB        0x80UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB        0x100UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB        0x200UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB        0x400UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB       0x800UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD      0x1000UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB        0x2000UL
         __le16  supported_speeds_eee_mode;
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1     0x1UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB     0x2UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2     0x4UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB       0x8UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3     0x10UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4     0x20UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB      0x40UL
         __le32  tx_lpi_timer_low;
         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
         #define PORT_PHY_QCAPS_RESP_RSVD2_MASK           0xff000000UL
         #define PORT_PHY_QCAPS_RESP_RSVD2_SFT            24
         __le32  valid_tx_lpi_timer_high;
         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
         #define PORT_PHY_QCAPS_RESP_VALID_MASK            0xff000000UL
         #define PORT_PHY_QCAPS_RESP_VALID_SFT             24
         __le16  supported_pam4_speeds_auto_mode;
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G      0x1UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G     0x2UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G     0x4UL
         __le16  supported_pam4_speeds_force_mode;
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G      0x1UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G     0x2UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G     0x4UL
         __le16  flags2;
         #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED       0x1UL
         #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED         0x2UL
         #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED     0x4UL
         #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED       0x8UL
         u8      internal_port_cnt;
         u8      unused_0;
         __le16  supported_speeds2_force_mode;
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB                0x1UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB               0x2UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB               0x4UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB               0x8UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB               0x10UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB              0x20UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56       0x40UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56      0x80UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56      0x100UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56      0x200UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112     0x400UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112     0x800UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112     0x1000UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112     0x2000UL
         __le16  supported_speeds2_auto_mode;
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB                0x1UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB               0x2UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB               0x4UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB               0x8UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB               0x10UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB              0x20UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56       0x40UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56      0x80UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56      0x100UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56      0x200UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112     0x400UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112     0x800UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112     0x1000UL
         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112     0x2000UL
         u8      unused_1[3];
         u8      valid;
 };

 /* hwrm_port_phy_i2c_write_input (size:832b/104B) */
 struct hwrm_port_phy_i2c_write_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         __le32  enables;
         #define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET     0x1UL
         __le16  port_id;
         u8      i2c_slave_addr;
         u8      unused_0;
         __le16  page_number;
         __le16  page_offset;
         u8      data_length;
         u8      unused_1[7];
         __le32  data[16];
 };

 /* hwrm_port_phy_i2c_write_output (size:128b/16B) */
 struct hwrm_port_phy_i2c_write_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
 struct hwrm_port_phy_i2c_read_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         __le32  enables;
         #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET     0x1UL
         __le16  port_id;
         u8      i2c_slave_addr;
         u8      unused_0;
         __le16  page_number;
         __le16  page_offset;
         u8      data_length;
         u8      unused_1[7];
 };

 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
 struct hwrm_port_phy_i2c_read_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  data[16];
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_port_led_cfg_input (size:512b/64B) */
 struct hwrm_port_led_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define PORT_LED_CFG_REQ_ENABLES_LED0_ID            0x1UL
         #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE         0x2UL
         #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR         0x4UL
         #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON      0x8UL
         #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF     0x10UL
         #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID      0x20UL
         #define PORT_LED_CFG_REQ_ENABLES_LED1_ID            0x40UL
         #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE         0x80UL
         #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR         0x100UL
         #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON      0x200UL
         #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF     0x400UL
         #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID      0x800UL
         #define PORT_LED_CFG_REQ_ENABLES_LED2_ID            0x1000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE         0x2000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR         0x4000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON      0x8000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF     0x10000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID      0x20000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED3_ID            0x40000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE         0x80000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR         0x100000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON      0x200000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF     0x400000UL
         #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID      0x800000UL
         __le16  port_id;
         u8      num_leds;
         u8      rsvd;
         u8      led0_id;
         u8      led0_state;
         #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT  0x0UL
         #define PORT_LED_CFG_REQ_LED0_STATE_OFF      0x1UL
         #define PORT_LED_CFG_REQ_LED0_STATE_ON       0x2UL
         #define PORT_LED_CFG_REQ_LED0_STATE_BLINK    0x3UL
         #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
         #define PORT_LED_CFG_REQ_LED0_STATE_LAST    PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
         u8      led0_color;
         #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT    0x0UL
         #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER      0x1UL
         #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN      0x2UL
         #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
         #define PORT_LED_CFG_REQ_LED0_COLOR_LAST      PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
         u8      unused_0;
         __le16  led0_blink_on;
         __le16  led0_blink_off;
         u8      led0_group_id;
         u8      rsvd0;
         u8      led1_id;
         u8      led1_state;
         #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT  0x0UL
         #define PORT_LED_CFG_REQ_LED1_STATE_OFF      0x1UL
         #define PORT_LED_CFG_REQ_LED1_STATE_ON       0x2UL
         #define PORT_LED_CFG_REQ_LED1_STATE_BLINK    0x3UL
         #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
         #define PORT_LED_CFG_REQ_LED1_STATE_LAST    PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
         u8      led1_color;
         #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT    0x0UL
         #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER      0x1UL
         #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN      0x2UL
         #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
         #define PORT_LED_CFG_REQ_LED1_COLOR_LAST      PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
         u8      unused_1;
         __le16  led1_blink_on;
         __le16  led1_blink_off;
         u8      led1_group_id;
         u8      rsvd1;
         u8      led2_id;
         u8      led2_state;
         #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT  0x0UL
         #define PORT_LED_CFG_REQ_LED2_STATE_OFF      0x1UL
         #define PORT_LED_CFG_REQ_LED2_STATE_ON       0x2UL
         #define PORT_LED_CFG_REQ_LED2_STATE_BLINK    0x3UL
         #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
         #define PORT_LED_CFG_REQ_LED2_STATE_LAST    PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
         u8      led2_color;
         #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT    0x0UL
         #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER      0x1UL
         #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN      0x2UL
         #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
         #define PORT_LED_CFG_REQ_LED2_COLOR_LAST      PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
         u8      unused_2;
         __le16  led2_blink_on;
         __le16  led2_blink_off;
         u8      led2_group_id;
         u8      rsvd2;
         u8      led3_id;
         u8      led3_state;
         #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT  0x0UL
         #define PORT_LED_CFG_REQ_LED3_STATE_OFF      0x1UL
         #define PORT_LED_CFG_REQ_LED3_STATE_ON       0x2UL
         #define PORT_LED_CFG_REQ_LED3_STATE_BLINK    0x3UL
         #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
         #define PORT_LED_CFG_REQ_LED3_STATE_LAST    PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
         u8      led3_color;
         #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT    0x0UL
         #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER      0x1UL
         #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN      0x2UL
         #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
         #define PORT_LED_CFG_REQ_LED3_COLOR_LAST      PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
         u8      unused_3;
         __le16  led3_blink_on;
         __le16  led3_blink_off;
         u8      led3_group_id;
         u8      rsvd3;
 };

 /* hwrm_port_led_cfg_output (size:128b/16B) */
 struct hwrm_port_led_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_port_led_qcfg_input (size:192b/24B) */
 struct hwrm_port_led_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
 };

 /* hwrm_port_led_qcfg_output (size:448b/56B) */
 struct hwrm_port_led_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      num_leds;
         u8      led0_id;
         u8      led0_type;
         #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED    0x0UL
         #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
         #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID  0xffUL
         #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST    PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
         u8      led0_state;
         #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT  0x0UL
         #define PORT_LED_QCFG_RESP_LED0_STATE_OFF      0x1UL
         #define PORT_LED_QCFG_RESP_LED0_STATE_ON       0x2UL
         #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK    0x3UL
         #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
         #define PORT_LED_QCFG_RESP_LED0_STATE_LAST    PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
         u8      led0_color;
         #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT    0x0UL
         #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER      0x1UL
         #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN      0x2UL
         #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
         #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST      PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
         u8      unused_0;
         __le16  led0_blink_on;
         __le16  led0_blink_off;
         u8      led0_group_id;
         u8      led1_id;
         u8      led1_type;
         #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED    0x0UL
         #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
         #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID  0xffUL
         #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST    PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
         u8      led1_state;
         #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT  0x0UL
         #define PORT_LED_QCFG_RESP_LED1_STATE_OFF      0x1UL
         #define PORT_LED_QCFG_RESP_LED1_STATE_ON       0x2UL
         #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK    0x3UL
         #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
         #define PORT_LED_QCFG_RESP_LED1_STATE_LAST    PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
         u8      led1_color;
         #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT    0x0UL
         #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER      0x1UL
         #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN      0x2UL
         #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
         #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST      PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
         u8      unused_1;
         __le16  led1_blink_on;
         __le16  led1_blink_off;
         u8      led1_group_id;
         u8      led2_id;
         u8      led2_type;
         #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED    0x0UL
         #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
         #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID  0xffUL
         #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST    PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
         u8      led2_state;
         #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT  0x0UL
         #define PORT_LED_QCFG_RESP_LED2_STATE_OFF      0x1UL
         #define PORT_LED_QCFG_RESP_LED2_STATE_ON       0x2UL
         #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK    0x3UL
         #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
         #define PORT_LED_QCFG_RESP_LED2_STATE_LAST    PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
         u8      led2_color;
         #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT    0x0UL
         #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER      0x1UL
         #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN      0x2UL
         #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
         #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST      PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
         u8      unused_2;
         __le16  led2_blink_on;
         __le16  led2_blink_off;
         u8      led2_group_id;
         u8      led3_id;
         u8      led3_type;
         #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED    0x0UL
         #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
         #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID  0xffUL
         #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST    PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
         u8      led3_state;
         #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT  0x0UL
         #define PORT_LED_QCFG_RESP_LED3_STATE_OFF      0x1UL
         #define PORT_LED_QCFG_RESP_LED3_STATE_ON       0x2UL
         #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK    0x3UL
         #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
         #define PORT_LED_QCFG_RESP_LED3_STATE_LAST    PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
         u8      led3_color;
         #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT    0x0UL
         #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER      0x1UL
         #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN      0x2UL
         #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
         #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST      PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
         u8      unused_3;
         __le16  led3_blink_on;
         __le16  led3_blink_off;
         u8      led3_group_id;
         u8      unused_4[6];
         u8      valid;
 };

 /* hwrm_port_led_qcaps_input (size:192b/24B) */
 struct hwrm_port_led_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
 };

 /* hwrm_port_led_qcaps_output (size:384b/48B) */
 struct hwrm_port_led_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      num_leds;
         u8      unused[3];
         u8      led0_id;
         u8      led0_type;
         #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED    0x0UL
         #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
         #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID  0xffUL
         #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST    PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
         u8      led0_group_id;
         u8      unused_0;
         __le16  led0_state_caps;
         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED                 0x1UL
         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED           0x2UL
         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED            0x4UL
         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED         0x8UL
         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
         __le16  led0_color_caps;
         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD                0x1UL
         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
         u8      led1_id;
         u8      led1_type;
         #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED    0x0UL
         #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
         #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID  0xffUL
         #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST    PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
         u8      led1_group_id;
         u8      unused_1;
         __le16  led1_state_caps;
         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED                 0x1UL
         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED           0x2UL
         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED            0x4UL
         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED         0x8UL
         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
         __le16  led1_color_caps;
         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD                0x1UL
         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
         u8      led2_id;
         u8      led2_type;
         #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED    0x0UL
         #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
         #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID  0xffUL
         #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST    PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
         u8      led2_group_id;
         u8      unused_2;
         __le16  led2_state_caps;
         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED                 0x1UL
         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED           0x2UL
         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED            0x4UL
         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED         0x8UL
         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
         __le16  led2_color_caps;
         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD                0x1UL
         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
         u8      led3_id;
         u8      led3_type;
         #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED    0x0UL
         #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
         #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID  0xffUL
         #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST    PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
         u8      led3_group_id;
         u8      unused_3;
         __le16  led3_state_caps;
         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED                 0x1UL
         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED           0x2UL
         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED            0x4UL
         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED         0x8UL
         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
         __le16  led3_color_caps;
         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD                0x1UL
         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
         u8      unused_4[3];
         u8      valid;
 };

 /* hwrm_queue_qportcfg_input (size:192b/24B) */
 struct hwrm_queue_qportcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH     0x1UL
         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX    0x0UL
         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX    0x1UL
         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
         __le16  port_id;
         u8      drv_qmap_cap;
         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED  0x1UL
         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST    QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
         u8      unused_0;
 };

 /* hwrm_queue_qportcfg_output (size:256b/32B) */
 struct hwrm_queue_qportcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      max_configurable_queues;
         u8      max_configurable_lossless_queues;
         u8      queue_cfg_allowed;
         u8      queue_cfg_info;
         #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL
         u8      queue_pfcenable_cfg_allowed;
         u8      queue_pri2cos_cfg_allowed;
         u8      queue_cos2bw_cfg_allowed;
         u8      queue_id0;
         u8      queue_id0_service_profile;
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY          0x0UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS       0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN        0xffUL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
         u8      queue_id1;
         u8      queue_id1_service_profile;
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY          0x0UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS       0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN        0xffUL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
         u8      queue_id2;
         u8      queue_id2_service_profile;
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY          0x0UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS       0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN        0xffUL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
         u8      queue_id3;
         u8      queue_id3_service_profile;
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY          0x0UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS       0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN        0xffUL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
         u8      queue_id4;
         u8      queue_id4_service_profile;
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY          0x0UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS       0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN        0xffUL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
         u8      queue_id5;
         u8      queue_id5_service_profile;
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY          0x0UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS       0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN        0xffUL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
         u8      queue_id6;
         u8      queue_id6_service_profile;
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY          0x0UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS       0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN        0xffUL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
         u8      queue_id7;
         u8      queue_id7_service_profile;
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY          0x0UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS       0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN        0xffUL
         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
         u8      valid;
 };

 /* hwrm_queue_qcfg_input (size:192b/24B) */
 struct hwrm_queue_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define QUEUE_QCFG_REQ_FLAGS_PATH     0x1UL
         #define QUEUE_QCFG_REQ_FLAGS_PATH_TX    0x0UL
         #define QUEUE_QCFG_REQ_FLAGS_PATH_RX    0x1UL
         #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX
         __le32  queue_id;
 };

 /* hwrm_queue_qcfg_output (size:128b/16B) */
 struct hwrm_queue_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  queue_len;
         u8      service_profile;
         #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY    0x0UL
         #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL
         #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN  0xffUL
         #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST    QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN
         u8      queue_cfg_info;
         #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL
         u8      unused_0;
         u8      valid;
 };

 /* hwrm_queue_cfg_input (size:320b/40B) */
 struct hwrm_queue_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
         #define QUEUE_CFG_REQ_FLAGS_PATH_SFT  0
         #define QUEUE_CFG_REQ_FLAGS_PATH_TX     0x0UL
         #define QUEUE_CFG_REQ_FLAGS_PATH_RX     0x1UL
         #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL
         #define QUEUE_CFG_REQ_FLAGS_PATH_LAST  QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
         __le32  enables;
         #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN            0x1UL
         #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE     0x2UL
         __le32  queue_id;
         __le32  dflt_len;
         u8      service_profile;
         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY    0x0UL
         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
         #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN  0xffUL
         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST    QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
         u8      unused_0[7];
 };

 /* hwrm_queue_cfg_output (size:128b/16B) */
 struct hwrm_queue_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
 struct hwrm_queue_pfcenable_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
 };

 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
 struct hwrm_queue_pfcenable_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  flags;
         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED     0x1UL
         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED     0x2UL
         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED     0x4UL
         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED     0x8UL
         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED     0x10UL
         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED     0x20UL
         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED     0x40UL
         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED     0x80UL
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
 struct hwrm_queue_pfcenable_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED     0x1UL
         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED     0x2UL
         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED     0x4UL
         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED     0x8UL
         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED     0x10UL
         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED     0x20UL
         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED     0x40UL
         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED     0x80UL
         __le16  port_id;
         u8      unused_0[2];
 };

 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
 struct hwrm_queue_pfcenable_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
 struct hwrm_queue_pri2cos_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH      0x1UL
         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX     0x0UL
         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX     0x1UL
         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN     0x2UL
         u8      port_id;
         u8      unused_0[3];
 };

 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
 struct hwrm_queue_pri2cos_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      pri0_cos_queue_id;
         u8      pri1_cos_queue_id;
         u8      pri2_cos_queue_id;
         u8      pri3_cos_queue_id;
         u8      pri4_cos_queue_id;
         u8      pri5_cos_queue_id;
         u8      pri6_cos_queue_id;
         u8      pri7_cos_queue_id;
         u8      queue_cfg_info;
         #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL
         u8      unused_0[6];
         u8      valid;
 };

 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
 struct hwrm_queue_pri2cos_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT  0
         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX     0x0UL
         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX     0x1UL
         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL
         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN     0x4UL
         __le32  enables;
         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID     0x1UL
         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID     0x2UL
         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID     0x4UL
         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID     0x8UL
         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID     0x10UL
         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID     0x20UL
         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID     0x40UL
         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID     0x80UL
         u8      port_id;
         u8      pri0_cos_queue_id;
         u8      pri1_cos_queue_id;
         u8      pri2_cos_queue_id;
         u8      pri3_cos_queue_id;
         u8      pri4_cos_queue_id;
         u8      pri5_cos_queue_id;
         u8      pri6_cos_queue_id;
         u8      pri7_cos_queue_id;
         u8      unused_0[7];
 };

 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
 struct hwrm_queue_pri2cos_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
 struct hwrm_queue_cos2bw_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
 };

 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
 struct hwrm_queue_cos2bw_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      queue_id0;
         u8      unused_0;
         __le16  unused_1;
         __le32  queue_id0_min_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id0_max_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id0_tsa_assign;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id0_pri_lvl;
         u8      queue_id0_bw_weight;
         u8      queue_id1;
         __le32  queue_id1_min_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id1_max_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id1_tsa_assign;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id1_pri_lvl;
         u8      queue_id1_bw_weight;
         u8      queue_id2;
         __le32  queue_id2_min_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id2_max_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id2_tsa_assign;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id2_pri_lvl;
         u8      queue_id2_bw_weight;
         u8      queue_id3;
         __le32  queue_id3_min_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id3_max_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id3_tsa_assign;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id3_pri_lvl;
         u8      queue_id3_bw_weight;
         u8      queue_id4;
         __le32  queue_id4_min_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id4_max_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id4_tsa_assign;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id4_pri_lvl;
         u8      queue_id4_bw_weight;
         u8      queue_id5;
         __le32  queue_id5_min_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id5_max_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id5_tsa_assign;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id5_pri_lvl;
         u8      queue_id5_bw_weight;
         u8      queue_id6;
         __le32  queue_id6_min_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id6_max_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id6_tsa_assign;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id6_pri_lvl;
         u8      queue_id6_bw_weight;
         u8      queue_id7;
         __le32  queue_id7_min_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id7_max_bw;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id7_tsa_assign;
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id7_pri_lvl;
         u8      queue_id7_bw_weight;
         u8      unused_2[4];
         u8      valid;
 };

 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
 struct hwrm_queue_cos2bw_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         __le32  enables;
         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID     0x1UL
         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID     0x2UL
         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID     0x4UL
         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID     0x8UL
         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID     0x10UL
         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID     0x20UL
         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID     0x40UL
         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID     0x80UL
         __le16  port_id;
         u8      queue_id0;
         u8      unused_0;
         __le32  queue_id0_min_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id0_max_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id0_tsa_assign;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id0_pri_lvl;
         u8      queue_id0_bw_weight;
         u8      queue_id1;
         __le32  queue_id1_min_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id1_max_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id1_tsa_assign;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id1_pri_lvl;
         u8      queue_id1_bw_weight;
         u8      queue_id2;
         __le32  queue_id2_min_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id2_max_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id2_tsa_assign;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id2_pri_lvl;
         u8      queue_id2_bw_weight;
         u8      queue_id3;
         __le32  queue_id3_min_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id3_max_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id3_tsa_assign;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id3_pri_lvl;
         u8      queue_id3_bw_weight;
         u8      queue_id4;
         __le32  queue_id4_min_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id4_max_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id4_tsa_assign;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id4_pri_lvl;
         u8      queue_id4_bw_weight;
         u8      queue_id5;
         __le32  queue_id5_min_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id5_max_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id5_tsa_assign;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id5_pri_lvl;
         u8      queue_id5_bw_weight;
         u8      queue_id6;
         __le32  queue_id6_min_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id6_max_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id6_tsa_assign;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id6_pri_lvl;
         u8      queue_id6_bw_weight;
         u8      queue_id7;
         __le32  queue_id7_min_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
         __le32  queue_id7_max_bw;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT              0
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE                     0x10000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      queue_id7_tsa_assign;
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP             0x0UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS            0x1UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST  0xffUL
         u8      queue_id7_pri_lvl;
         u8      queue_id7_bw_weight;
         u8      unused_1[5];
 };

 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
 struct hwrm_queue_cos2bw_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
 struct hwrm_queue_dscp_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      port_id;
         u8      unused_0[7];
 };

 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
 struct hwrm_queue_dscp_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      num_dscp_bits;
         u8      unused_0;
         __le16  max_entries;
         u8      unused_1[3];
         u8      valid;
 };

 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
 struct hwrm_queue_dscp2pri_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  dest_data_addr;
         u8      port_id;
         u8      unused_0;
         __le16  dest_data_buffer_size;
         u8      unused_1[4];
 };

 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
 struct hwrm_queue_dscp2pri_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  entry_cnt;
         u8      default_pri;
         u8      unused_0[4];
         u8      valid;
 };

 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
 struct hwrm_queue_dscp2pri_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  src_data_addr;
         __le32  flags;
         #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI     0x1UL
         __le32  enables;
         #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI     0x1UL
         u8      port_id;
         u8      default_pri;
         __le16  entry_cnt;
         u8      unused_0[4];
 };

 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
 struct hwrm_queue_dscp2pri_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_vnic_alloc_input (size:192b/24B) */
 struct hwrm_vnic_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define VNIC_ALLOC_REQ_FLAGS_DEFAULT     0x1UL
         u8      unused_0[4];
 };

 /* hwrm_vnic_alloc_output (size:128b/16B) */
 struct hwrm_vnic_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  vnic_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_vnic_free_input (size:192b/24B) */
 struct hwrm_vnic_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  vnic_id;
         u8      unused_0[4];
 };

 /* hwrm_vnic_free_output (size:128b/16B) */
 struct hwrm_vnic_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_vnic_cfg_input (size:320b/40B) */
 struct hwrm_vnic_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define VNIC_CFG_REQ_FLAGS_DEFAULT                              0x1UL
         #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE                      0x2UL
         #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE                        0x4UL
         #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE                  0x8UL
         #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE                  0x10UL
         #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE                     0x20UL
         #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE     0x40UL
         __le32  enables;
         #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP            0x1UL
         #define VNIC_CFG_REQ_ENABLES_RSS_RULE                 0x2UL
         #define VNIC_CFG_REQ_ENABLES_COS_RULE                 0x4UL
         #define VNIC_CFG_REQ_ENABLES_LB_RULE                  0x8UL
         #define VNIC_CFG_REQ_ENABLES_MRU                      0x10UL
         #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID       0x20UL
         #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID     0x40UL
         __le16  vnic_id;
         __le16  dflt_ring_grp;
         __le16  rss_rule;
         __le16  cos_rule;
         __le16  lb_rule;
         __le16  mru;
         __le16  default_rx_ring_id;
         __le16  default_cmpl_ring_id;
 };

 /* hwrm_vnic_cfg_output (size:128b/16B) */
 struct hwrm_vnic_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_vnic_qcfg_input (size:256b/32B) */
 struct hwrm_vnic_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define VNIC_QCFG_REQ_ENABLES_VF_ID_VALID     0x1UL
         __le32  vnic_id;
         __le16  vf_id;
         u8      unused_0[6];
 };

 /* hwrm_vnic_qcfg_output (size:256b/32B) */
 struct hwrm_vnic_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  dflt_ring_grp;
         __le16  rss_rule;
         __le16  cos_rule;
         __le16  lb_rule;
         __le16  mru;
         u8      unused_0[2];
         __le32  flags;
         #define VNIC_QCFG_RESP_FLAGS_DEFAULT                              0x1UL
         #define VNIC_QCFG_RESP_FLAGS_VLAN_STRIP_MODE                      0x2UL
         #define VNIC_QCFG_RESP_FLAGS_BD_STALL_MODE                        0x4UL
         #define VNIC_QCFG_RESP_FLAGS_ROCE_DUAL_VNIC_MODE                  0x8UL
         #define VNIC_QCFG_RESP_FLAGS_ROCE_ONLY_VNIC_MODE                  0x10UL
         #define VNIC_QCFG_RESP_FLAGS_RSS_DFLT_CR_MODE                     0x20UL
         #define VNIC_QCFG_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE     0x40UL
         u8      unused_1[7];
         u8      valid;
 };

 /* hwrm_vnic_qcaps_input (size:192b/24B) */
 struct hwrm_vnic_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         u8      unused_0[4];
 };

 /* hwrm_vnic_qcaps_output (size:192b/24B) */
 struct hwrm_vnic_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  mru;
         u8      unused_0[2];
         __le32  flags;
         #define VNIC_QCAPS_RESP_FLAGS_UNUSED                              0x1UL
         #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP                      0x2UL
         #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP                        0x4UL
         #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP                  0x8UL
         #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP                  0x10UL
         #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP                     0x20UL
         #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP     0x40UL
         #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP                   0x80UL
         u8      unused_1[7];
         u8      valid;
 };

 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
 struct hwrm_vnic_tpa_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define VNIC_TPA_CFG_REQ_FLAGS_TPA                       0x1UL
         #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA                 0x2UL
         #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE            0x4UL
         #define VNIC_TPA_CFG_REQ_FLAGS_GRO                       0x8UL
         #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN              0x10UL
         #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL
         #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK            0x40UL
         #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK             0x80UL
         __le32  enables;
         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS      0x1UL
         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS          0x2UL
         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER     0x4UL
         #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN       0x8UL
         __le16  vnic_id;
         __le16  max_agg_segs;
         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1   0x0UL
         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2   0x1UL
         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4   0x2UL
         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8   0x3UL
         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
         __le16  max_aggs;
         #define VNIC_TPA_CFG_REQ_MAX_AGGS_1   0x0UL
         #define VNIC_TPA_CFG_REQ_MAX_AGGS_2   0x1UL
         #define VNIC_TPA_CFG_REQ_MAX_AGGS_4   0x2UL
         #define VNIC_TPA_CFG_REQ_MAX_AGGS_8   0x3UL
         #define VNIC_TPA_CFG_REQ_MAX_AGGS_16  0x4UL
         #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
         #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
         u8      unused_0[2];
         __le32  max_agg_timer;
         __le32  min_agg_len;
 };

 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
 struct hwrm_vnic_tpa_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
 struct hwrm_vnic_tpa_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  vnic_id;
         u8      unused_0[6];
 };

 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
 struct hwrm_vnic_tpa_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  flags;
         #define VNIC_TPA_QCFG_RESP_FLAGS_TPA                       0x1UL
         #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA                 0x2UL
         #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE            0x4UL
         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO                       0x8UL
         #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN              0x10UL
         #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL
         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK            0x40UL
         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK             0x80UL
         __le16  max_agg_segs;
         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1   0x0UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2   0x1UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4   0x2UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8   0x3UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
         __le16  max_aggs;
         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1   0x0UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2   0x1UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4   0x2UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8   0x3UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16  0x4UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
         __le32  max_agg_timer;
         __le32  min_agg_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
 struct hwrm_vnic_rss_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  hash_type;
         #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4         0x1UL
         #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4     0x2UL
         #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4     0x4UL
         #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6         0x8UL
         #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6     0x10UL
         #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6     0x20UL
         __le16  vnic_id;
         u8      ring_table_pair_index;
         u8      hash_mode_flags;
         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT         0x1UL
         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4     0x2UL
         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2     0x4UL
         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL
         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL
         __le64  ring_grp_tbl_addr;
         __le64  hash_key_tbl_addr;
         __le16  rss_ctx_idx;
         u8      unused_1[6];
 };

 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
 struct hwrm_vnic_rss_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
 struct hwrm_vnic_rss_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  rss_ctx_idx;
         u8      unused_0[6];
 };

 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
 struct hwrm_vnic_rss_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  hash_type;
         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4         0x1UL
         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4     0x2UL
         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4     0x4UL
         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6         0x8UL
         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6     0x10UL
         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6     0x20UL
         u8      unused_0[4];
         __le32  hash_key[10];
         u8      hash_mode_flags;
         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT         0x1UL
         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4     0x2UL
         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2     0x4UL
         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL
         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL
         u8      unused_1[6];
         u8      valid;
 };

 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
 struct hwrm_vnic_plcmodes_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT     0x1UL
         #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT       0x2UL
         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4              0x4UL
         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6              0x8UL
         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE              0x10UL
         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE              0x20UL
         __le32  enables;
         #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID      0x1UL
         #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID        0x2UL
         #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID     0x4UL
         __le32  vnic_id;
         __le16  jumbo_thresh;
         __le16  hds_offset;
         __le16  hds_threshold;
         u8      unused_0[6];
 };

 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
 struct hwrm_vnic_plcmodes_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
 struct hwrm_vnic_plcmodes_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  vnic_id;
         u8      unused_0[4];
 };

 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
 struct hwrm_vnic_plcmodes_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  flags;
         #define VNIC_PLCMODES_QCFG_RESP_FLAGS_REGULAR_PLACEMENT     0x1UL
         #define VNIC_PLCMODES_QCFG_RESP_FLAGS_JUMBO_PLACEMENT       0x2UL
         #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_IPV4              0x4UL
         #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_IPV6              0x8UL
         #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_FCOE              0x10UL
         #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_ROCE              0x20UL
         #define VNIC_PLCMODES_QCFG_RESP_FLAGS_DFLT_VNIC             0x40UL
         __le16  jumbo_thresh;
         __le16  hds_offset;
         __le16  hds_threshold;
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  rss_cos_lb_ctx_id;
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  rss_cos_lb_ctx_id;
         u8      unused_0[6];
 };

 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_ring_alloc_input (size:704b/88B) */
 struct hwrm_ring_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG          0x2UL
         #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID     0x8UL
         #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID          0x20UL
         #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID      0x40UL
         #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID      0x80UL
         #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID     0x100UL
         u8      ring_type;
         #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL   0x0UL
         #define RING_ALLOC_REQ_RING_TYPE_TX        0x1UL
         #define RING_ALLOC_REQ_RING_TYPE_RX        0x2UL
         #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
         #define RING_ALLOC_REQ_RING_TYPE_RX_AGG    0x4UL
         #define RING_ALLOC_REQ_RING_TYPE_NQ        0x5UL
         #define RING_ALLOC_REQ_RING_TYPE_LAST     RING_ALLOC_REQ_RING_TYPE_NQ
         u8      unused_0;
         __le16  flags;
         #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD     0x1UL
         __le64  page_tbl_addr;
         __le32  fbo;
         u8      page_size;
         u8      page_tbl_depth;
         u8      unused_1[2];
         __le32  length;
         __le16  logical_id;
         __le16  cmpl_ring_id;
         __le16  queue_id;
         __le16  rx_buf_size;
         __le16  rx_ring_id;
         __le16  nq_ring_id;
         __le16  ring_arb_cfg;
         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK      0xfUL
         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT       0
         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP          0x1UL
         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ         0x2UL
         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST       RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
         #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK            0xf0UL
         #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT             4
         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
         __le16  unused_3;
         __le32  reserved3;
         __le32  stat_ctx_id;
         __le32  reserved4;
         __le32  max_bw;
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT              0
         #define RING_ALLOC_REQ_MAX_BW_SCALE                     0x10000000UL
         #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)
         #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
         #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST                 RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST         RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
         u8      int_mode;
         #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
         #define RING_ALLOC_REQ_INT_MODE_RSVD   0x1UL
         #define RING_ALLOC_REQ_INT_MODE_MSIX   0x2UL
         #define RING_ALLOC_REQ_INT_MODE_POLL   0x3UL
         #define RING_ALLOC_REQ_INT_MODE_LAST  RING_ALLOC_REQ_INT_MODE_POLL
         u8      unused_4[3];
         __le64  cq_handle;
 };

 /* hwrm_ring_alloc_output (size:128b/16B) */
 struct hwrm_ring_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  ring_id;
         __le16  logical_ring_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_ring_free_input (size:192b/24B) */
 struct hwrm_ring_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      ring_type;
         #define RING_FREE_REQ_RING_TYPE_L2_CMPL   0x0UL
         #define RING_FREE_REQ_RING_TYPE_TX        0x1UL
         #define RING_FREE_REQ_RING_TYPE_RX        0x2UL
         #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
         #define RING_FREE_REQ_RING_TYPE_RX_AGG    0x4UL
         #define RING_FREE_REQ_RING_TYPE_NQ        0x5UL
         #define RING_FREE_REQ_RING_TYPE_LAST     RING_FREE_REQ_RING_TYPE_NQ
         u8      unused_0;
         __le16  ring_id;
         u8      unused_1[4];
 };

 /* hwrm_ring_free_output (size:128b/16B) */
 struct hwrm_ring_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_ring_reset_input (size:192b/24B) */
 struct hwrm_ring_reset_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      ring_type;
         #define RING_RESET_REQ_RING_TYPE_L2_CMPL   0x0UL
         #define RING_RESET_REQ_RING_TYPE_TX        0x1UL
         #define RING_RESET_REQ_RING_TYPE_RX        0x2UL
         #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
         #define RING_RESET_REQ_RING_TYPE_LAST     RING_RESET_REQ_RING_TYPE_ROCE_CMPL
         u8      unused_0;
         __le16  ring_id;
         u8      unused_1[4];
 };

 /* hwrm_ring_reset_output (size:128b/16B) */
 struct hwrm_ring_reset_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
 struct hwrm_ring_aggint_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
 struct hwrm_ring_aggint_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  cmpl_params;
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN                  0x1UL
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX                  0x2UL
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET                      0x4UL
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE                        0x8UL
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR                0x10UL
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT     0x20UL
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR                0x40UL
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT     0x80UL
         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT                0x100UL
         __le32  nq_params;
         #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN     0x1UL
         __le16  num_cmpl_dma_aggr_min;
         __le16  num_cmpl_dma_aggr_max;
         __le16  num_cmpl_dma_aggr_during_int_min;
         __le16  num_cmpl_dma_aggr_during_int_max;
         __le16  cmpl_aggr_dma_tmr_min;
         __le16  cmpl_aggr_dma_tmr_max;
         __le16  cmpl_aggr_dma_tmr_during_int_min;
         __le16  cmpl_aggr_dma_tmr_during_int_max;
         __le16  int_lat_tmr_min_min;
         __le16  int_lat_tmr_min_max;
         __le16  int_lat_tmr_max_min;
         __le16  int_lat_tmr_max_max;
         __le16  num_cmpl_aggr_int_min;
         __le16  num_cmpl_aggr_int_max;
         __le16  timer_units;
         u8      unused_0[1];
         u8      valid;
 };

 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
 struct hwrm_ring_cmpl_ring_qaggint_params_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  ring_id;
         u8      unused_0[6];
 };

 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
 struct hwrm_ring_cmpl_ring_qaggint_params_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  flags;
         #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET     0x1UL
         #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE       0x2UL
         __le16  num_cmpl_dma_aggr;
         __le16  num_cmpl_dma_aggr_during_int;
         __le16  cmpl_aggr_dma_tmr;
         __le16  cmpl_aggr_dma_tmr_during_int;
         __le16  int_lat_tmr_min;
         __le16  int_lat_tmr_max;
         __le16  num_cmpl_aggr_int;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  ring_id;
         __le16  flags;
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET     0x1UL
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE       0x2UL
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ           0x4UL
         __le16  num_cmpl_dma_aggr;
         __le16  num_cmpl_dma_aggr_during_int;
         __le16  cmpl_aggr_dma_tmr;
         __le16  cmpl_aggr_dma_tmr_during_int;
         __le16  int_lat_tmr_min;
         __le16  int_lat_tmr_max;
         __le16  num_cmpl_aggr_int;
         __le16  enables;
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR                0x1UL
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT     0x2UL
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR                0x4UL
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN                  0x8UL
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX                  0x10UL
         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT                0x20UL
         u8      unused_0[4];
 };

 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
 struct hwrm_ring_grp_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  cr;
         __le16  rr;
         __le16  ar;
         __le16  sc;
 };

 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
 struct hwrm_ring_grp_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  ring_group_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_ring_grp_free_input (size:192b/24B) */
 struct hwrm_ring_grp_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  ring_group_id;
         u8      unused_0[4];
 };

 /* hwrm_ring_grp_free_output (size:128b/16B) */
 struct hwrm_ring_grp_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
 struct hwrm_cfa_l2_filter_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH              0x1UL
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX             0x0UL
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX             0x1UL
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK          0x2UL
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP              0x4UL
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST         0x8UL
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK      0x30UL
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT       4
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 4)
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 4)
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 4)
         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
         __le32  enables;
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR             0x1UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK        0x2UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN            0x4UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK       0x8UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN            0x10UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK       0x20UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR           0x40UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK      0x80UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN          0x100UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK     0x200UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN          0x400UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK     0x800UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE            0x1000UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID              0x2000UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE         0x4000UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID              0x8000UL
         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID      0x10000UL
         u8      l2_addr[6];
         u8      unused_0[2];
         u8      l2_addr_mask[6];
         __le16  l2_ovlan;
         __le16  l2_ovlan_mask;
         __le16  l2_ivlan;
         __le16  l2_ivlan_mask;
         u8      unused_1[2];
         u8      t_l2_addr[6];
         u8      unused_2[2];
         u8      t_l2_addr_mask[6];
         __le16  t_l2_ovlan;
         __le16  t_l2_ovlan_mask;
         __le16  t_l2_ivlan;
         __le16  t_l2_ivlan_mask;
         u8      src_type;
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF    0x1UL
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF    0x2UL
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC  0x3UL
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG  0x4UL
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE   0x5UL
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO  0x6UL
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG  0x7UL
         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
         u8      unused_3;
         __le32  src_id;
         u8      tunnel_type;
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
         u8      unused_4;
         __le16  dst_id;
         __le16  mirror_vnic_id;
         u8      pri_hint;
         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER    0x0UL
         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX          0x3UL
         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN          0x4UL
         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST        CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
         u8      unused_5;
         __le32  unused_6;
         __le64  l2_filter_id_hint;
 };

 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
 struct hwrm_cfa_l2_filter_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  l2_filter_id;
         __le32  flow_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
 struct hwrm_cfa_l2_filter_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  l2_filter_id;
 };

 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
 struct hwrm_cfa_l2_filter_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
 struct hwrm_cfa_l2_filter_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH              0x1UL
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX             0x0UL
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX             0x1UL
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP              0x2UL
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK      0xcUL
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT       2
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 2)
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 2)
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 2)
         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
         __le32  enables;
         #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID                 0x1UL
         #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID     0x2UL
         __le64  l2_filter_id;
         __le32  dst_id;
         __le32  new_mirror_vnic_id;
 };

 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
 struct hwrm_cfa_l2_filter_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
 struct hwrm_cfa_l2_set_rx_mask_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  vnic_id;
         __le32  mask;
         #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST               0x2UL
         #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST           0x4UL
         #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST               0x8UL
         #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS         0x10UL
         #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST           0x20UL
         #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY            0x40UL
         #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN        0x80UL
         #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN     0x100UL
         __le64  mc_tbl_addr;
         __le32  num_mc_entries;
         u8      unused_0[4];
         __le64  vlan_tag_tbl_addr;
         __le32  num_vlan_tags;
         u8      unused_1[4];
 };

 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
 struct hwrm_cfa_l2_set_rx_mask_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
         u8      code;
         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN                    0x0UL
         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST                      CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
         u8      unused_0[7];
 };

 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
 struct hwrm_cfa_vlan_antispoof_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[2];
         __le32  num_vlan_entries;
         __le64  vlan_tag_mask_tbl_addr;
 };

 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
 struct hwrm_cfa_vlan_antispoof_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
 struct hwrm_cfa_vlan_antispoof_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  fid;
         u8      unused_0[2];
         __le32  max_vlan_entries;
         __le64  vlan_tag_mask_tbl_addr;
 };

 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
 struct hwrm_cfa_vlan_antispoof_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  num_vlan_entries;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
 struct hwrm_cfa_tunnel_filter_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL
         __le32  enables;
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID       0x1UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR            0x2UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN           0x4UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR            0x8UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE       0x10UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE     0x20UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR          0x40UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x80UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI                0x100UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID        0x200UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x400UL
         __le64  l2_filter_id;
         u8      l2_addr[6];
         __le16  l2_ivlan;
         __le32  l3_addr[4];
         __le32  t_l3_addr[4];
         u8      l3_addr_type;
         u8      t_l3_addr_type;
         u8      tunnel_type;
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
         u8      tunnel_flags;
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR     0x1UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1          0x2UL
         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0         0x4UL
         __le32  vni;
         __le32  dst_vnic_id;
         __le32  mirror_vnic_id;
 };

 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
 struct hwrm_cfa_tunnel_filter_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  tunnel_filter_id;
         __le32  flow_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
 struct hwrm_cfa_tunnel_filter_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  tunnel_filter_id;
 };

 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
 struct hwrm_cfa_tunnel_filter_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  dest_fid;
         u8      tunnel_type;
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
         u8      flags;
         #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_FLAGS_MODIFY_DST     0x1UL
         u8      unused_0[4];
 };

 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
 struct hwrm_cfa_redirect_tunnel_type_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  dest_fid;
         u8      tunnel_type;
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_LAST     CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL
         u8      unused_0[5];
 };

 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
 struct hwrm_cfa_redirect_tunnel_type_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
 struct hwrm_cfa_redirect_tunnel_type_info_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  src_fid;
         u8      tunnel_type;
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_LAST     CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_ANYTUNNEL
         u8      unused_0[5];
 };

 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
 struct hwrm_cfa_redirect_tunnel_type_info_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  dest_fid;
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
 struct hwrm_vxlan_ipv4_hdr {
         u8      ver_hlen;
         #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
         #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
         #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK      0xf0UL
         #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT       4
         u8      tos;
         __be16  ip_id;
         __be16  flags_frag_offset;
         u8      ttl;
         u8      protocol;
         __be32  src_ip_addr;
         __be32  dest_ip_addr;
 };

 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
 struct hwrm_vxlan_ipv6_hdr {
         __be32  ver_tc_flow_label;
         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT         0x1cUL
         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK        0xf0000000UL
         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT          0x14UL
         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK         0xff00000UL
         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT  0x0UL
         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST           VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
         __be16  payload_len;
         u8      next_hdr;
         u8      ttl;
         __be32  src_ip_addr[4];
         __be32  dest_ip_addr[4];
 };

 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
 struct hwrm_cfa_encap_data_vxlan {
         u8      src_mac_addr[6];
         __le16  unused_0;
         u8      dst_mac_addr[6];
         u8      num_vlan_tags;
         u8      unused_1;
         __be16  ovlan_tpid;
         __be16  ovlan_tci;
         __be16  ivlan_tpid;
         __be16  ivlan_tci;
         __le32  l3[10];
         #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
         #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
         #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
         #define CFA_ENCAP_DATA_VXLAN_L3_LAST    CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
         __be16  src_port;
         __be16  dst_port;
         __be32  vni;
         u8      hdr_rsvd0[3];
         u8      hdr_rsvd1;
         u8      hdr_flags;
         u8      unused[3];
 };

 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
 struct hwrm_cfa_encap_record_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL
         u8      encap_type;
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN    0x1UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE    0x2UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE    0x3UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP     0x4UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE   0x5UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS     0x6UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN     0x7UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE    0x8UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST    CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE
         u8      unused_0[3];
         __le32  encap_data[20];
 };

 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
 struct hwrm_cfa_encap_record_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  encap_record_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
 struct hwrm_cfa_encap_record_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  encap_record_id;
         u8      unused_0[4];
 };

 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
 struct hwrm_cfa_encap_record_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
 struct hwrm_cfa_ntuple_filter_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP         0x2UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER        0x4UL
         __le32  enables;
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID         0x1UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE            0x2UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE          0x4UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR          0x8UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE          0x10UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR           0x20UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK      0x40UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR           0x80UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK      0x100UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL          0x200UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT             0x400UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK        0x800UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT             0x1000UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK        0x2000UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT             0x4000UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID     0x8000UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID               0x10000UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID       0x20000UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR          0x40000UL
         __le64  l2_filter_id;
         u8      src_macaddr[6];
         __be16  ethertype;
         u8      ip_addr_type;
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
         u8      ip_protocol;
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
         __le16  dst_id;
         __le16  mirror_vnic_id;
         u8      tunnel_type;
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
         u8      pri_hint;
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE     0x1UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW     0x2UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST   0x3UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST    0x4UL
         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST     CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
         __be32  src_ipaddr[4];
         __be32  src_ipaddr_mask[4];
         __be32  dst_ipaddr[4];
         __be32  dst_ipaddr_mask[4];
         __be16  src_port;
         __be16  src_port_mask;
         __be16  dst_port;
         __be16  dst_port_mask;
         __le64  ntuple_filter_id_hint;
 };

 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
 struct hwrm_cfa_ntuple_filter_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  ntuple_filter_id;
         __le32  flow_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
         u8      code;
         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN                   0x0UL
         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST                     CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
         u8      unused_0[7];
 };

 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
 struct hwrm_cfa_ntuple_filter_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  ntuple_filter_id;
 };

 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
 struct hwrm_cfa_ntuple_filter_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
 struct hwrm_cfa_ntuple_filter_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID                0x1UL
         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID        0x2UL
         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID     0x4UL
         u8      unused_0[4];
         __le64  ntuple_filter_id;
         __le32  new_dst_id;
         __le32  new_mirror_vnic_id;
         __le16  new_meter_instance_id;
         #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
         #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST   CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
         u8      unused_1[6];
 };

 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
 struct hwrm_cfa_ntuple_filter_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
 struct hwrm_cfa_em_flow_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH         0x1UL
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_TX        0x0UL
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_RX        0x1UL
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_LAST     CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_RX
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_BYTE_CTR     0x2UL
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PKT_CTR      0x4UL
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_DECAP        0x8UL
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_ENCAP        0x10UL
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_DROP         0x20UL
         #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_METER        0x40UL
         __le32  enables;
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_L2_FILTER_ID          0x1UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_TUNNEL_TYPE           0x2UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_TUNNEL_ID             0x4UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_MACADDR           0x8UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_MACADDR           0x10UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_OVLAN_VID             0x20UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IVLAN_VID             0x40UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_ETHERTYPE             0x80UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_IPADDR            0x100UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_IPADDR            0x200UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IPADDR_TYPE           0x400UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IP_PROTOCOL           0x800UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_PORT              0x1000UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_PORT              0x2000UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_ID                0x4000UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID        0x8000UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_ENCAP_RECORD_ID       0x10000UL
         #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_METER_INSTANCE_ID     0x20000UL
         __le64  l2_filter_id;
         u8      tunnel_type;
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
         u8      unused_0[3];
         __le32  tunnel_id;
         u8      src_macaddr[6];
         __le16  meter_instance_id;
         #define CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_INVALID 0xffffUL
         #define CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_LAST   CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_INVALID
         u8      dst_macaddr[6];
         __le16  ovlan_vid;
         __le16  ivlan_vid;
         __be16  ethertype;
         u8      ip_addr_type;
         #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
         #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL
         #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL
         #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV6
         u8      ip_protocol;
         #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
         #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL
         #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL
         #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UDP
         u8      unused_1[2];
         __be32  src_ipaddr[4];
         __be32  dst_ipaddr[4];
         __be16  src_port;
         __be16  dst_port;
         __le16  dst_id;
         __le16  mirror_vnic_id;
         __le32  encap_record_id;
         u8      unused_2[4];
 };

 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
 struct hwrm_cfa_em_flow_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  em_filter_id;
         __le32  flow_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
 struct hwrm_cfa_em_flow_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  em_filter_id;
 };

 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
 struct hwrm_cfa_em_flow_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */
 struct hwrm_cfa_em_flow_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_DST_ID                0x1UL
         #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID        0x2UL
         #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID     0x4UL
         u8      unused_0[4];
         __le64  em_filter_id;
         __le32  new_dst_id;
         __le32  new_mirror_vnic_id;
         __le16  new_meter_instance_id;
         #define CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
         #define CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_LAST   CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
         u8      unused_1[6];
 };

 /* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */
 struct hwrm_cfa_em_flow_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
 struct hwrm_cfa_meter_profile_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH     0x1UL
         #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_TX    0x0UL
         #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_RX    0x1UL
         #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_RX
         u8      meter_type;
         #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC2697 0x0UL
         #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC2698 0x1UL
         #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC4115 0x2UL
         #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_LAST   CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC4115
         __le16  reserved1;
         __le32  reserved2;
         __le32  commit_rate;
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_MASK             0xfffffffUL
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_SFT              0
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE                     0x10000000UL
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BITS                  (0x0UL << 28)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BYTES                 (0x1UL << 28)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_LAST                 CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BYTES
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_SFT         29
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID
         __le32  commit_burst;
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_MASK             0xfffffffUL
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_SFT              0
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE                     0x10000000UL
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BITS                  (0x0UL << 28)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BYTES                 (0x1UL << 28)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_LAST                 CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BYTES
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_SFT         29
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID
         __le32  excess_peak_rate;
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_MASK             0xfffffffUL
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_SFT              0
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE                     0x10000000UL
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BITS                  (0x0UL << 28)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BYTES                 (0x1UL << 28)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_LAST                 CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BYTES
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT         29
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
         __le32  excess_peak_burst;
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_MASK             0xfffffffUL
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_SFT              0
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE                     0x10000000UL
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BITS                  (0x0UL << 28)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BYTES                 (0x1UL << 28)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_LAST                 CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BYTES
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT         29
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
 };

 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
 struct hwrm_cfa_meter_profile_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  meter_profile_id;
         #define CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_INVALID 0xffffUL
         #define CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_LAST   CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_INVALID
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
 struct hwrm_cfa_meter_profile_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH     0x1UL
         #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_TX    0x0UL
         #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_RX    0x1UL
         #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_RX
         u8      unused_0;
         __le16  meter_profile_id;
         #define CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_INVALID 0xffffUL
         #define CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_LAST   CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_INVALID
         u8      unused_1[4];
 };

 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
 struct hwrm_cfa_meter_profile_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
 struct hwrm_cfa_meter_profile_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH     0x1UL
         #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_TX    0x0UL
         #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_RX    0x1UL
         #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_RX
         u8      meter_type;
         #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC2697 0x0UL
         #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC2698 0x1UL
         #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC4115 0x2UL
         #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_LAST   CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC4115
         __le16  meter_profile_id;
         #define CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_INVALID 0xffffUL
         #define CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_LAST   CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_INVALID
         __le32  reserved;
         __le32  commit_rate;
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_MASK             0xfffffffUL
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_SFT              0
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE                     0x10000000UL
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BITS                  (0x0UL << 28)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BYTES                 (0x1UL << 28)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_LAST                 CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BYTES
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_SFT         29
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID
         __le32  commit_burst;
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_MASK             0xfffffffUL
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_SFT              0
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE                     0x10000000UL
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BITS                  (0x0UL << 28)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BYTES                 (0x1UL << 28)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_LAST                 CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BYTES
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_SFT         29
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID
         __le32  excess_peak_rate;
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_MASK             0xfffffffUL
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_SFT              0
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE                     0x10000000UL
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BITS                  (0x0UL << 28)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BYTES                 (0x1UL << 28)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_LAST                 CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BYTES
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT         29
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
         __le32  excess_peak_burst;
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_MASK             0xfffffffUL
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_SFT              0
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE                     0x10000000UL
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BITS                  (0x0UL << 28)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BYTES                 (0x1UL << 28)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_LAST                 CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BYTES
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK        0xe0000000UL
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT         29
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO          (0x2UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE          (0x4UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
         #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
 };

 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
 struct hwrm_cfa_meter_profile_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
 struct hwrm_cfa_meter_instance_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH     0x1UL
         #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_TX    0x0UL
         #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_RX    0x1UL
         #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_LAST CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_RX
         u8      unused_0;
         __le16  meter_profile_id;
         #define CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_INVALID 0xffffUL
         #define CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_LAST   CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_INVALID
         u8      unused_1[4];
 };

 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
 struct hwrm_cfa_meter_instance_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  meter_instance_id;
         #define CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_INVALID 0xffffUL
         #define CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_LAST   CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_INVALID
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
 struct hwrm_cfa_meter_instance_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH     0x1UL
         #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_TX    0x0UL
         #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_RX    0x1UL
         #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_LAST CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_RX
         u8      unused_0;
         __le16  meter_instance_id;
         #define CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_INVALID 0xffffUL
         #define CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_LAST   CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_INVALID
         u8      unused_1[4];
 };

 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
 struct hwrm_cfa_meter_instance_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
 struct hwrm_cfa_decap_filter_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL     0x1UL
         __le32  enables;
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x1UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID          0x2UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR        0x4UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR        0x8UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID          0x10UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID          0x20UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID        0x40UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID        0x80UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE          0x100UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR         0x200UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR         0x400UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE        0x800UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL        0x1000UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT           0x2000UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT           0x4000UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID             0x8000UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x10000UL
         __be32  tunnel_id;
         u8      tunnel_type;
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
         u8      unused_0;
         __le16  unused_1;
         u8      src_macaddr[6];
         u8      unused_2[2];
         u8      dst_macaddr[6];
         __be16  ovlan_vid;
         __be16  ivlan_vid;
         __be16  t_ovlan_vid;
         __be16  t_ivlan_vid;
         __be16  ethertype;
         u8      ip_addr_type;
         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
         u8      ip_protocol;
         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL
         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
         __le16  unused_3;
         __le32  unused_4;
         __be32  src_ipaddr[4];
         __be32  dst_ipaddr[4];
         __be16  src_port;
         __be16  dst_port;
         __le16  dst_id;
         __le16  l2_ctxt_ref_id;
 };

 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
 struct hwrm_cfa_decap_filter_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  decap_filter_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
 struct hwrm_cfa_decap_filter_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  decap_filter_id;
         u8      unused_0[4];
 };

 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
 struct hwrm_cfa_decap_filter_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
 struct hwrm_cfa_flow_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  flags;
         #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL                 0x1UL
         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK          0x6UL
         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT           1
         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE            (0x0UL << 1)
         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE             (0x1UL << 1)
         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO             (0x2UL << 1)
         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK          0x38UL
         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT           3
         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2              (0x0UL << 3)
         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4            (0x1UL << 3)
         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6            (0x2UL << 3)
         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
         #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX                0x40UL
         #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX                0x80UL
         #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI     0x100UL
         __le16  src_fid;
         __le32  tunnel_handle;
         __le16  action_flags;
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD                    0x1UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE                0x2UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP                   0x4UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER                  0x8UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL                 0x10UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC                0x20UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST               0x40UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS       0x80UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE      0x100UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT          0x200UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP              0x400UL
         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED     0x800UL
         __le16  dst_fid;
         __be16  l2_rewrite_vlan_tpid;
         __be16  l2_rewrite_vlan_tci;
         __le16  act_meter_id;
         __le16  ref_flow_handle;
         __be16  ethertype;
         __be16  outer_vlan_tci;
         __be16  dmac[3];
         __be16  inner_vlan_tci;
         __be16  smac[3];
         u8      ip_dst_mask_len;
         u8      ip_src_mask_len;
         __be32  ip_dst[4];
         __be32  ip_src[4];
         __be16  l4_src_port;
         __be16  l4_src_port_mask;
         __be16  l4_dst_port;
         __be16  l4_dst_port_mask;
         __be32  nat_ip_address[4];
         __be16  l2_rewrite_dmac[3];
         __be16  nat_port;
         __be16  l2_rewrite_smac[3];
         u8      ip_proto;
         u8      tunnel_type;
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
 };

 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
 struct hwrm_cfa_flow_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  flow_handle;
         u8      unused_0[2];
         __le32  flow_id;
         __le64  ext_flow_handle;
         u8      unused_1[7];
         u8      valid;
 };

 /* hwrm_cfa_flow_free_input (size:256b/32B) */
 struct hwrm_cfa_flow_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  flow_handle;
         u8      unused_0[6];
         __le64  ext_flow_handle;
 };

 /* hwrm_cfa_flow_free_output (size:256b/32B) */
 struct hwrm_cfa_flow_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  packet;
         __le64  byte;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_flow_info_input (size:256b/32B) */
 struct hwrm_cfa_flow_info_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  flow_handle;
         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK       0xfffUL
         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT        0
         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT        0x1000UL
         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT     0x2000UL
         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT     0x4000UL
         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX         0x8000UL
         u8      unused_0[6];
         __le64  ext_flow_handle;
 };

 /* hwrm_cfa_flow_info_output (size:448b/56B) */
 struct hwrm_cfa_flow_info_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      flags;
         u8      profile;
         __le16  src_fid;
         __le16  dst_fid;
         __le16  l2_ctxt_id;
         __le64  em_info;
         __le64  tcam_info;
         __le64  vfp_tcam_info;
         __le16  ar_id;
         __le16  flow_handle;
         __le32  tunnel_handle;
         __le16  flow_timer;
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_cfa_flow_flush_input (size:192b/24B) */
 struct hwrm_cfa_flow_flush_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         u8      unused_0[4];
 };

 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
 struct hwrm_cfa_flow_flush_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
 struct hwrm_cfa_flow_stats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  num_flows;
         __le16  flow_handle_0;
         __le16  flow_handle_1;
         __le16  flow_handle_2;
         __le16  flow_handle_3;
         __le16  flow_handle_4;
         __le16  flow_handle_5;
         __le16  flow_handle_6;
         __le16  flow_handle_7;
         __le16  flow_handle_8;
         __le16  flow_handle_9;
         u8      unused_0[2];
         __le32  flow_id_0;
         __le32  flow_id_1;
         __le32  flow_id_2;
         __le32  flow_id_3;
         __le32  flow_id_4;
         __le32  flow_id_5;
         __le32  flow_id_6;
         __le32  flow_id_7;
         __le32  flow_id_8;
         __le32  flow_id_9;
 };

 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
 struct hwrm_cfa_flow_stats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  packet_0;
         __le64  packet_1;
         __le64  packet_2;
         __le64  packet_3;
         __le64  packet_4;
         __le64  packet_5;
         __le64  packet_6;
         __le64  packet_7;
         __le64  packet_8;
         __le64  packet_9;
         __le64  byte_0;
         __le64  byte_1;
         __le64  byte_2;
         __le64  byte_3;
         __le64  byte_4;
         __le64  byte_5;
         __le64  byte_6;
         __le64  byte_7;
         __le64  byte_8;
         __le64  byte_9;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
 struct hwrm_cfa_flow_aging_timer_reset_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  flow_handle;
         u8      unused_0[6];
         __le64  ext_flow_handle;
 };

 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
 struct hwrm_cfa_flow_aging_timer_reset_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
 struct hwrm_cfa_flow_aging_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  enables;
         #define CFA_FLOW_AGING_CFG_REQ_ENABLES_TCP_FLOW_TIMER     0x1UL
         #define CFA_FLOW_AGING_CFG_REQ_ENABLES_TCP_FIN_TIMER      0x2UL
         #define CFA_FLOW_AGING_CFG_REQ_ENABLES_UDP_FLOW_TIMER     0x4UL
         u8      flags;
         #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH     0x1UL
         #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_TX    0x0UL
         #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_RX    0x1UL
         #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_RX
         u8      unused_0;
         __le32  tcp_flow_timer;
         __le32  tcp_fin_timer;
         __le32  udp_flow_timer;
 };

 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
 struct hwrm_cfa_flow_aging_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
 struct hwrm_cfa_flow_aging_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH     0x1UL
         #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_TX    0x0UL
         #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_RX    0x1UL
         #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_RX
         u8      unused_0[7];
 };

 /* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
 struct hwrm_cfa_flow_aging_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  tcp_flow_timer;
         __le32  tcp_fin_timer;
         __le32  udp_flow_timer;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
 struct hwrm_cfa_flow_aging_qcaps_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH     0x1UL
         #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_TX    0x0UL
         #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_RX    0x1UL
         #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_RX
         u8      unused_0[7];
 };

 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
 struct hwrm_cfa_flow_aging_qcaps_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  max_tcp_flow_timer;
         __le32  max_tcp_fin_timer;
         __le32  max_udp_flow_timer;
         __le32  max_aging_flows;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
 struct hwrm_cfa_vf_pair_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  vf_a_id;
         __le16  vf_b_id;
         u8      unused_0[4];
         char    pair_name[32];
 };

 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
 struct hwrm_cfa_vf_pair_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
 struct hwrm_cfa_vf_pair_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         char    pair_name[32];
 };

 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
 struct hwrm_cfa_vf_pair_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
 struct hwrm_cfa_vf_pair_info_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_VF_PAIR_INFO_REQ_FLAGS_LOOKUP_TYPE     0x1UL
         __le16  vf_pair_index;
         u8      unused_0[2];
         char    vf_pair_name[32];
 };

 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
 struct hwrm_cfa_vf_pair_info_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  next_vf_pair_index;
         __le16  vf_a_fid;
         __le16  vf_a_index;
         __le16  vf_b_fid;
         __le16  vf_b_index;
         u8      pair_state;
         #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ALLOCATED 0x1UL
         #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ACTIVE    0x2UL
         #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_LAST     CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ACTIVE
         u8      unused_0[5];
         char    pair_name[32];
         u8      unused_1[7];
         u8      valid;
 };

 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
 struct hwrm_cfa_pair_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      pair_mode;
         #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_VF2FN         0x0UL
         #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN        0x1UL
         #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2REP       0x2UL
         #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_PROXY         0x3UL
         #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_PFPAIR        0x4UL
         #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MOD    0x5UL
         #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MODALL 0x6UL
         #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_LAST         CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MODALL
         u8      unused_0;
         __le16  vf_a_id;
         u8      host_b_id;
         u8      pf_b_id;
         __le16  vf_b_id;
         u8      port_id;
         u8      pri;
         __le16  new_pf_fid;
         __le32  enables;
         #define CFA_PAIR_ALLOC_REQ_ENABLES_Q_AB_VALID      0x1UL
         #define CFA_PAIR_ALLOC_REQ_ENABLES_Q_BA_VALID      0x2UL
         #define CFA_PAIR_ALLOC_REQ_ENABLES_FC_AB_VALID     0x4UL
         #define CFA_PAIR_ALLOC_REQ_ENABLES_FC_BA_VALID     0x8UL
         char    pair_name[32];
         u8      q_ab;
         u8      q_ba;
         u8      fc_ab;
         u8      fc_ba;
         u8      unused_1[4];
 };

 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
 struct hwrm_cfa_pair_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  rx_cfa_code_a;
         __le16  tx_cfa_action_a;
         __le16  rx_cfa_code_b;
         __le16  tx_cfa_action_b;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_pair_free_input (size:384b/48B) */
 struct hwrm_cfa_pair_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         char    pair_name[32];
 };

 /* hwrm_cfa_pair_free_output (size:128b/16B) */
 struct hwrm_cfa_pair_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_pair_info_input (size:448b/56B) */
 struct hwrm_cfa_pair_info_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define CFA_PAIR_INFO_REQ_FLAGS_LOOKUP_TYPE      0x1UL
         #define CFA_PAIR_INFO_REQ_FLAGS_LOOKUP_REPRE     0x2UL
         __le16  pair_index;
         u8      pair_pfid;
         u8      pair_vfid;
         char    pair_name[32];
 };

 /* hwrm_cfa_pair_info_output (size:576b/72B) */
 struct hwrm_cfa_pair_info_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  next_pair_index;
         __le16  a_fid;
         u8      host_a_index;
         u8      pf_a_index;
         __le16  vf_a_index;
         __le16  rx_cfa_code_a;
         __le16  tx_cfa_action_a;
         __le16  b_fid;
         u8      host_b_index;
         u8      pf_b_index;
         __le16  vf_b_index;
         __le16  rx_cfa_code_b;
         __le16  tx_cfa_action_b;
         u8      pair_mode;
         #define CFA_PAIR_INFO_RESP_PAIR_MODE_VF2FN   0x0UL
         #define CFA_PAIR_INFO_RESP_PAIR_MODE_REP2FN  0x1UL
         #define CFA_PAIR_INFO_RESP_PAIR_MODE_REP2REP 0x2UL
         #define CFA_PAIR_INFO_RESP_PAIR_MODE_PROXY   0x3UL
         #define CFA_PAIR_INFO_RESP_PAIR_MODE_PFPAIR  0x4UL
         #define CFA_PAIR_INFO_RESP_PAIR_MODE_LAST   CFA_PAIR_INFO_RESP_PAIR_MODE_PFPAIR
         u8      pair_state;
         #define CFA_PAIR_INFO_RESP_PAIR_STATE_ALLOCATED 0x1UL
         #define CFA_PAIR_INFO_RESP_PAIR_STATE_ACTIVE    0x2UL
         #define CFA_PAIR_INFO_RESP_PAIR_STATE_LAST     CFA_PAIR_INFO_RESP_PAIR_STATE_ACTIVE
         char    pair_name[32];
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
 struct hwrm_cfa_vfr_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  vf_id;
         __le16  reserved;
         u8      unused_0[4];
         char    vfr_name[32];
 };

 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
 struct hwrm_cfa_vfr_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  rx_cfa_code;
         __le16  tx_cfa_action;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_cfa_vfr_free_input (size:384b/48B) */
 struct hwrm_cfa_vfr_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         char    vfr_name[32];
 };

 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
 struct hwrm_cfa_vfr_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
 struct hwrm_cfa_redirect_query_tunnel_type_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  src_fid;
         u8      unused_0[6];
 };

 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
 struct hwrm_cfa_redirect_query_tunnel_type_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  tunnel_mask;
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_NONTUNNEL     0x1UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_VXLAN         0x2UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_NVGRE         0x4UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_L2GRE         0x8UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPIP          0x10UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_GENEVE        0x20UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_MPLS          0x40UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_STT           0x80UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPGRE         0x100UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_VXLAN_V4      0x200UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPGRE_V1      0x400UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_ANYTUNNEL     0x800UL
         #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_L2_ETYPE      0x1000UL
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
 struct hwrm_tunnel_dst_port_query_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      tunnel_type;
         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN    0x1UL
         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE   0x5UL
         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST    TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE
         u8      unused_0[7];
 };

 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
 struct hwrm_tunnel_dst_port_query_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  tunnel_dst_port_id;
         __be16  tunnel_dst_port_val;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
 struct hwrm_tunnel_dst_port_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      tunnel_type;
         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN    0x1UL
         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE   0x5UL
         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST    TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE
         u8      unused_0;
         __be16  tunnel_dst_port_val;
         u8      unused_1[4];
 };

 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
 struct hwrm_tunnel_dst_port_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  tunnel_dst_port_id;
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
 struct hwrm_tunnel_dst_port_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      tunnel_type;
         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN    0x1UL
         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE   0x5UL
         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST    TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE
         u8      unused_0;
         __le16  tunnel_dst_port_id;
         u8      unused_1[4];
 };

 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
 struct hwrm_tunnel_dst_port_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_1[7];
         u8      valid;
 };

 /* ctx_hw_stats (size:1280b/160B) */
 struct ctx_hw_stats {
         __le64  rx_ucast_pkts;
         __le64  rx_mcast_pkts;
         __le64  rx_bcast_pkts;
         __le64  rx_discard_pkts;
         __le64  rx_drop_pkts;
         __le64  rx_ucast_bytes;
         __le64  rx_mcast_bytes;
         __le64  rx_bcast_bytes;
         __le64  tx_ucast_pkts;
         __le64  tx_mcast_pkts;
         __le64  tx_bcast_pkts;
         __le64  tx_discard_pkts;
         __le64  tx_drop_pkts;
         __le64  tx_ucast_bytes;
         __le64  tx_mcast_bytes;
         __le64  tx_bcast_bytes;
         __le64  tpa_pkts;
         __le64  tpa_bytes;
         __le64  tpa_events;
         __le64  tpa_aborts;
 };

 /* ctx_eng_stats (size:512b/64B) */
 struct ctx_eng_stats {
         __le64  eng_bytes_in;
         __le64  eng_bytes_out;
         __le64  aux_bytes_in;
         __le64  aux_bytes_out;
         __le64  commands;
         __le64  error_commands;
         __le64  cce_engine_usage;
         __le64  cdd_engine_usage;
 };

 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
 struct hwrm_stat_ctx_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  stats_dma_addr;
         __le32  update_period_ms;
         u8      stat_ctx_flags;
         #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE     0x1UL
         u8      unused_0[3];
 };

 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
 struct hwrm_stat_ctx_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  stat_ctx_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_stat_ctx_free_input (size:192b/24B) */
 struct hwrm_stat_ctx_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  stat_ctx_id;
         u8      unused_0[4];
 };

 /* hwrm_stat_ctx_free_output (size:128b/16B) */
 struct hwrm_stat_ctx_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  stat_ctx_id;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_stat_ctx_query_input (size:192b/24B) */
 struct hwrm_stat_ctx_query_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  stat_ctx_id;
         u8      unused_0[4];
 };

 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
 struct hwrm_stat_ctx_query_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  tx_ucast_pkts;
         __le64  tx_mcast_pkts;
         __le64  tx_bcast_pkts;
         __le64  tx_err_pkts;
         __le64  tx_drop_pkts;
         __le64  tx_ucast_bytes;
         __le64  tx_mcast_bytes;
         __le64  tx_bcast_bytes;
         __le64  rx_ucast_pkts;
         __le64  rx_mcast_pkts;
         __le64  rx_bcast_pkts;
         __le64  rx_err_pkts;
         __le64  rx_drop_pkts;
         __le64  rx_ucast_bytes;
         __le64  rx_mcast_bytes;
         __le64  rx_bcast_bytes;
         __le64  rx_agg_pkts;
         __le64  rx_agg_bytes;
         __le64  rx_agg_events;
         __le64  rx_agg_aborts;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
 struct hwrm_stat_ctx_eng_query_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  stat_ctx_id;
         u8      unused_0[4];
 };

 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
 struct hwrm_stat_ctx_eng_query_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  eng_bytes_in;
         __le64  eng_bytes_out;
         __le64  aux_bytes_in;
         __le64  aux_bytes_out;
         __le64  commands;
         __le64  error_commands;
         __le64  cce_engine_usage;
         __le64  cdd_engine_usage;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
 struct hwrm_stat_ctx_clr_stats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  stat_ctx_id;
         u8      unused_0[4];
 };

 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
 struct hwrm_stat_ctx_clr_stats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_pcie_qstats_input (size:256b/32B) */
 struct hwrm_pcie_qstats_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  pcie_stat_size;
         u8      unused_0[6];
         __le64  pcie_stat_host_addr;
 };

 /* hwrm_pcie_qstats_output (size:128b/16B) */
 struct hwrm_pcie_qstats_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  pcie_stat_size;
         u8      unused_0[5];
         u8      valid;
 };

 /* pcie_ctx_hw_stats (size:768b/96B) */
 struct pcie_ctx_hw_stats {
         __le64  pcie_pl_signal_integrity;
         __le64  pcie_dl_signal_integrity;
         __le64  pcie_tl_signal_integrity;
         __le64  pcie_link_integrity;
         __le64  pcie_tx_traffic_rate;
         __le64  pcie_rx_traffic_rate;
         __le64  pcie_tx_dllp_statistics;
         __le64  pcie_rx_dllp_statistics;
         __le64  pcie_equalization_time;
         __le32  pcie_ltssm_histogram[4];
         __le64  pcie_recovery_histogram;
 };

 /* hwrm_fw_reset_input (size:192b/24B) */
 struct hwrm_fw_reset_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      embedded_proc_type;
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT                 0x0UL
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT                 0x1UL
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL              0x2UL
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE                 0x3UL
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST                 0x4UL
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP                   0x5UL
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP                 0x6UL
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST                FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
         u8      selfrst_status;
         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE      0x0UL
         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP      0x1UL
         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST   0x2UL
         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
         #define FW_RESET_REQ_SELFRST_STATUS_LAST            FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
         u8      host_idx;
         u8      flags;
         #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL     0x1UL
         u8      unused_0[4];
 };

 /* hwrm_fw_reset_output (size:128b/16B) */
 struct hwrm_fw_reset_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      selfrst_status;
         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE      0x0UL
         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP      0x1UL
         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST   0x2UL
         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
         #define FW_RESET_RESP_SELFRST_STATUS_LAST            FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
         u8      unused_0[6];
         u8      valid;
 };

 /* hwrm_fw_qstatus_input (size:192b/24B) */
 struct hwrm_fw_qstatus_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      embedded_proc_type;
         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT    0x0UL
         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT    0x1UL
         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE    0x3UL
         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST    0x4UL
         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP      0x5UL
         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP    0x6UL
         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST   FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
         u8      unused_0[7];
 };

 /* hwrm_fw_qstatus_output (size:128b/16B) */
 struct hwrm_fw_qstatus_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      selfrst_status;
         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE    0x0UL
         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP    0x1UL
         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
         #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST          FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST
         u8      unused_0[6];
         u8      valid;
 };

 /* hwrm_fw_set_time_input (size:256b/32B) */
 struct hwrm_fw_set_time_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  year;
         #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
         #define FW_SET_TIME_REQ_YEAR_LAST   FW_SET_TIME_REQ_YEAR_UNKNOWN
         u8      month;
         u8      day;
         u8      hour;
         u8      minute;
         u8      second;
         u8      unused_0;
         __le16  millisecond;
         __le16  zone;
         #define FW_SET_TIME_REQ_ZONE_UTC     0x0UL
         #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL
         #define FW_SET_TIME_REQ_ZONE_LAST   FW_SET_TIME_REQ_ZONE_UNKNOWN
         u8      unused_1[4];
 };

 /* hwrm_fw_set_time_output (size:128b/16B) */
 struct hwrm_fw_set_time_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_fw_get_time_input (size:128b/16B) */
 struct hwrm_fw_get_time_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_fw_get_time_output (size:192b/24B) */
 struct hwrm_fw_get_time_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  year;
         #define FW_GET_TIME_RESP_YEAR_UNKNOWN 0x0UL
         #define FW_GET_TIME_RESP_YEAR_LAST   FW_GET_TIME_RESP_YEAR_UNKNOWN
         u8      month;
         u8      day;
         u8      hour;
         u8      minute;
         u8      second;
         u8      unused_0;
         __le16  millisecond;
         __le16  zone;
         #define FW_GET_TIME_RESP_ZONE_UTC     0x0UL
         #define FW_GET_TIME_RESP_ZONE_UNKNOWN 0xffffUL
         #define FW_GET_TIME_RESP_ZONE_LAST   FW_GET_TIME_RESP_ZONE_UNKNOWN
         u8      unused_1[3];
         u8      valid;
 };

 /* hwrm_struct_hdr (size:128b/16B) */
 struct hwrm_struct_hdr {
         __le16  struct_id;
         #define STRUCT_HDR_STRUCT_ID_LLDP_CFG           0x41bUL
         #define STRUCT_HDR_STRUCT_ID_DCBX_ETS           0x41dUL
         #define STRUCT_HDR_STRUCT_ID_DCBX_PFC           0x41fUL
         #define STRUCT_HDR_STRUCT_ID_DCBX_APP           0x421UL
         #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
         #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC       0x424UL
         #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE        0x426UL
         #define STRUCT_HDR_STRUCT_ID_POWER_BKUP         0x427UL
         #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE         0x1UL
         #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION   0xaUL
         #define STRUCT_HDR_STRUCT_ID_RSS_V2             0x64UL
         #define STRUCT_HDR_STRUCT_ID_LAST              STRUCT_HDR_STRUCT_ID_RSS_V2
         __le16  len;
         u8      version;
         u8      count;
         __le16  subtype;
         __le16  next_offset;
         #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
         u8      unused_0[6];
 };

 /* hwrm_struct_data_dcbx_ets (size:256b/32B) */
 struct hwrm_struct_data_dcbx_ets {
         u8      destination;
         #define STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION   0x1UL
         #define STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION 0x2UL
         #define STRUCT_DATA_DCBX_ETS_DESTINATION_LAST           STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION
         u8      max_tcs;
         __le16  unused1;
         u8      pri0_to_tc_map;
         u8      pri1_to_tc_map;
         u8      pri2_to_tc_map;
         u8      pri3_to_tc_map;
         u8      pri4_to_tc_map;
         u8      pri5_to_tc_map;
         u8      pri6_to_tc_map;
         u8      pri7_to_tc_map;
         u8      tc0_to_bw_map;
         u8      tc1_to_bw_map;
         u8      tc2_to_bw_map;
         u8      tc3_to_bw_map;
         u8      tc4_to_bw_map;
         u8      tc5_to_bw_map;
         u8      tc6_to_bw_map;
         u8      tc7_to_bw_map;
         u8      tc0_to_tsa_map;
         #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP              0x0UL
         #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS             0x1UL
         #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS             0x2UL
         #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC 0xffUL
         #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_LAST                    STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC
         u8      tc1_to_tsa_map;
         u8      tc2_to_tsa_map;
         u8      tc3_to_tsa_map;
         u8      tc4_to_tsa_map;
         u8      tc5_to_tsa_map;
         u8      tc6_to_tsa_map;
         u8      tc7_to_tsa_map;
         u8      unused_0[4];
 };

 /* hwrm_struct_data_dcbx_pfc (size:64b/8B) */
 struct hwrm_struct_data_dcbx_pfc {
         u8      pfc_priority_bitmap;
         u8      max_pfc_tcs;
         u8      mbc;
         u8      unused_0[5];
 };

 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
 struct hwrm_struct_data_dcbx_app {
         __be16  protocol_id;
         u8      protocol_selector;
         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE   0x1UL
         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT     0x2UL
         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT     0x3UL
         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST        STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
         u8      priority;
         u8      valid;
         u8      unused_0[3];
 };

 /* hwrm_struct_data_dcbx_feature_state (size:64b/8B) */
 struct hwrm_struct_data_dcbx_feature_state {
         u8      dcbx_mode;
         #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED 0x0UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE     0x1UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE      0x2UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_LAST         STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE
         u8      ets_state;
         u8      pfc_state;
         u8      app_state;
         #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS    0x7UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS   0x6UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS 0x5UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_LAST             STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS
         u8      unused[3];
         u8      resets;
         #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS   0x1UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC   0x2UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP   0x4UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE 0x8UL
         #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_LAST       STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE
 };

 /* hwrm_struct_data_lldp (size:64b/8B) */
 struct hwrm_struct_data_lldp {
         u8      admin_state;
         #define STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE 0x0UL
         #define STRUCT_DATA_LLDP_ADMIN_STATE_TX      0x1UL
         #define STRUCT_DATA_LLDP_ADMIN_STATE_RX      0x2UL
         #define STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE  0x3UL
         #define STRUCT_DATA_LLDP_ADMIN_STATE_LAST   STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE
         u8      port_description_state;
         #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE 0x0UL
         #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE  0x1UL
         #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_LAST   STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE
         u8      system_name_state;
         #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE 0x0UL
         #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE  0x1UL
         #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_LAST   STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE
         u8      system_desc_state;
         #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE 0x0UL
         #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE  0x1UL
         #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_LAST   STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE
         u8      system_cap_state;
         #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE 0x0UL
         #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE  0x1UL
         #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_LAST   STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE
         u8      mgmt_addr_state;
         #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE 0x0UL
         #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE  0x1UL
         #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_LAST   STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE
         u8      async_event_notification_state;
         #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE 0x0UL
         #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE  0x1UL
         #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_LAST   STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE
         u8      unused_0;
 };

 /* hwrm_struct_data_lldp_generic (size:2112b/264B) */
 struct hwrm_struct_data_lldp_generic {
         u8      tlv_type;
         #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS            0x1UL
         #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT               0x2UL
         #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME        0x3UL
         #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION 0x4UL
         #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME          0x5UL
         #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION   0x6UL
         #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_LAST              STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION
         u8      subtype;
         u8      length;
         u8      unused1[5];
         __le32  tlv_value[64];
 };

 /* hwrm_struct_data_lldp_device (size:1472b/184B) */
 struct hwrm_struct_data_lldp_device {
         __le16  ttl;
         u8      mgmt_addr_len;
         u8      mgmt_addr_type;
         u8      unused_3[4];
         __le32  mgmt_addr[8];
         __le32  system_caps;
         u8      intf_num_type;
         u8      mgmt_addr_oid_length;
         u8      unused_4[2];
         __le32  intf_num;
         u8      unused_5[4];
         __le32  mgmt_addr_oid[32];
 };

 /* hwrm_struct_data_port_description (size:64b/8B) */
 struct hwrm_struct_data_port_description {
         u8      port_id;
         u8      unused_0[7];
 };

 /* hwrm_struct_data_rss_v2 (size:128b/16B) */
 struct hwrm_struct_data_rss_v2 {
         __le16  flags;
         #define STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID     0x1UL
         __le16  rss_ctx_id;
         __le16  num_ring_groups;
         __le16  hash_type;
         #define STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4         0x1UL
         #define STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4     0x2UL
         #define STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4     0x4UL
         #define STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6         0x8UL
         #define STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6     0x10UL
         #define STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6     0x20UL
         __le64  hash_key_ring_group_ids;
 };

 /* hwrm_struct_data_power_information (size:192b/24B) */
 struct hwrm_struct_data_power_information {
         __le32  bkup_power_info_ver;
         __le32  platform_bkup_power_count;
         __le32  load_milli_watt;
         __le32  bkup_time_milli_seconds;
         __le32  bkup_power_status;
         __le32  bkup_power_charge_time;
 };

 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
 struct hwrm_fw_set_structured_data_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  src_data_addr;
         __le16  data_len;
         u8      hdr_cnt;
         u8      unused_0[5];
 };

 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
 struct hwrm_fw_set_structured_data_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
 struct hwrm_fw_set_structured_data_cmd_err {
         u8      code;
         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN     0x0UL
         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT     0x2UL
         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID      0x3UL
         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST       FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
         u8      unused_0[7];
 };

 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
 struct hwrm_fw_get_structured_data_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  dest_data_addr;
         __le16  data_len;
         __le16  structure_id;
         __le16  subtype;
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED                  0x0UL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL                     0xffffUL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN       0x100UL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER        0x101UL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN          0x200UL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER           0x201UL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL    0x202UL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL        0x300UL
         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST                   FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
         u8      count;
         u8      unused_0;
 };

 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
 struct hwrm_fw_get_structured_data_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      hdr_cnt;
         u8      unused_0[6];
         u8      valid;
 };

 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
 struct hwrm_fw_get_structured_data_cmd_err {
         u8      code;
         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID  0x3UL
         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST   FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
         u8      unused_0[7];
 };

 /* hwrm_fw_ipc_msg_input (size:320b/40B) */
 struct hwrm_fw_ipc_msg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define FW_IPC_MSG_REQ_ENABLES_COMMAND_ID        0x1UL
         #define FW_IPC_MSG_REQ_ENABLES_SRC_PROCESSOR     0x2UL
         #define FW_IPC_MSG_REQ_ENABLES_DATA_OFFSET       0x4UL
         #define FW_IPC_MSG_REQ_ENABLES_LENGTH            0x8UL
         __le16  command_id;
         #define FW_IPC_MSG_REQ_COMMAND_ID_ROCE_LAG 0x1UL
         #define FW_IPC_MSG_REQ_COMMAND_ID_LAST    FW_IPC_MSG_REQ_COMMAND_ID_ROCE_LAG
         u8      src_processor;
         #define FW_IPC_MSG_REQ_SRC_PROCESSOR_CFW  0x1UL
         #define FW_IPC_MSG_REQ_SRC_PROCESSOR_BONO 0x2UL
         #define FW_IPC_MSG_REQ_SRC_PROCESSOR_APE  0x3UL
         #define FW_IPC_MSG_REQ_SRC_PROCESSOR_KONG 0x4UL
         #define FW_IPC_MSG_REQ_SRC_PROCESSOR_LAST FW_IPC_MSG_REQ_SRC_PROCESSOR_KONG
         u8      unused_0;
         __le32  data_offset;
         __le16  length;
         u8      unused_1[2];
         __le64  opaque;
 };

 /* hwrm_fw_ipc_msg_output (size:128b/16B) */
 struct hwrm_fw_ipc_msg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_fw_ipc_mailbox_input (size:256b/32B) */
 struct hwrm_fw_ipc_mailbox_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         u8      unused;
         u8      event_id;
         u8      port_id;
         __le32  event_data1;
         __le32  event_data2;
         u8      unused_0[4];
 };

 /* hwrm_fw_ipc_mailbox_output (size:128b/16B) */
 struct hwrm_fw_ipc_mailbox_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_fw_ipc_mailbox_cmd_err (size:64b/8B) */
 struct hwrm_fw_ipc_mailbox_cmd_err {
         u8      code;
         #define FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN 0x0UL
         #define FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID  0x3UL
         #define FW_IPC_MAILBOX_CMD_ERR_CODE_LAST   FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID
         u8      unused_0[7];
 };

 /* hwrm_fw_health_check_input (size:128b/16B) */
 struct hwrm_fw_health_check_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_fw_health_check_output (size:128b/16B) */
 struct hwrm_fw_health_check_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  fw_status;
         #define FW_HEALTH_CHECK_RESP_FW_STATUS_SBI_BOOTED       0x1UL
         #define FW_HEALTH_CHECK_RESP_FW_STATUS_SBI_MISMATCH     0x2UL
         #define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT_BOOTED       0x4UL
         #define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT_MISMATCH     0x8UL
         #define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT_BOOTED       0x10UL
         #define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT_MISMATCH     0x20UL
         #define FW_HEALTH_CHECK_RESP_FW_STATUS_SECOND_RT        0x40UL
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_fw_sync_input (size:192b/24B) */
 struct hwrm_fw_sync_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  sync_action;
         #define FW_SYNC_REQ_SYNC_ACTION_SYNC_SBI     0x1UL
         #define FW_SYNC_REQ_SYNC_ACTION_SYNC_SRT     0x2UL
         #define FW_SYNC_REQ_SYNC_ACTION_SYNC_CRT     0x4UL
         #define FW_SYNC_REQ_SYNC_ACTION_ACTION       0x80000000UL
         u8      unused_0[4];
 };

 /* hwrm_fw_sync_output (size:128b/16B) */
 struct hwrm_fw_sync_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  sync_status;
         #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_MASK       0xffUL
         #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_SFT        0
         #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_SUCCESS      0x0UL
         #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_IN_PROGRESS  0x1UL
         #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_TIMEOUT      0x2UL
         #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_GENERAL      0x3UL
         #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_LAST        FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_GENERAL
         #define FW_SYNC_RESP_SYNC_STATUS_SYNC_ERR            0x40000000UL
         #define FW_SYNC_RESP_SYNC_STATUS_SYNC_COMPLETE       0x80000000UL
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
 struct hwrm_exec_fwd_resp_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  encap_request[26];
         __le16  encap_resp_target_id;
         u8      unused_0[6];
 };

 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
 struct hwrm_exec_fwd_resp_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
 struct hwrm_reject_fwd_resp_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  encap_request[26];
         __le16  encap_resp_target_id;
         u8      unused_0[6];
 };

 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
 struct hwrm_reject_fwd_resp_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_fwd_resp_input (size:1024b/128B) */
 struct hwrm_fwd_resp_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  encap_resp_target_id;
         __le16  encap_resp_cmpl_ring;
         __le16  encap_resp_len;
         u8      unused_0;
         u8      unused_1;
         __le64  encap_resp_addr;
         __le32  encap_resp[24];
 };

 /* hwrm_fwd_resp_output (size:128b/16B) */
 struct hwrm_fwd_resp_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
 struct hwrm_fwd_async_event_cmpl_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  encap_async_event_target_id;
         u8      unused_0[6];
         __le32  encap_async_event_cmpl[4];
 };

 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
 struct hwrm_fwd_async_event_cmpl_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_temp_monitor_query_input (size:128b/16B) */
 struct hwrm_temp_monitor_query_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_temp_monitor_query_output (size:128b/16B) */
 struct hwrm_temp_monitor_query_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      temp;
         u8      unused_0[6];
         u8      valid;
 };

 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
 struct hwrm_wol_filter_alloc_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         __le32  enables;
         #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS           0x1UL
         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET        0x2UL
         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE      0x4UL
         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR      0x8UL
         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR     0x10UL
         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE     0x20UL
         __le16  port_id;
         u8      wol_type;
         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP      0x1UL
         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID  0xffUL
         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST    WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
         u8      unused_0[5];
         u8      mac_address[6];
         __le16  pattern_offset;
         __le16  pattern_buf_size;
         __le16  pattern_mask_size;
         u8      unused_1[4];
         __le64  pattern_buf_addr;
         __le64  pattern_mask_addr;
 };

 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
 struct hwrm_wol_filter_alloc_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      wol_filter_id;
         u8      unused_0[6];
         u8      valid;
 };

 /* hwrm_wol_filter_free_input (size:256b/32B) */
 struct hwrm_wol_filter_free_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS     0x1UL
         __le32  enables;
         #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID     0x1UL
         __le16  port_id;
         u8      wol_filter_id;
         u8      unused_0[5];
 };

 /* hwrm_wol_filter_free_output (size:128b/16B) */
 struct hwrm_wol_filter_free_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
 struct hwrm_wol_filter_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         __le16  handle;
         u8      unused_0[4];
         __le64  pattern_buf_addr;
         __le16  pattern_buf_size;
         u8      unused_1[6];
         __le64  pattern_mask_addr;
         __le16  pattern_mask_size;
         u8      unused_2[6];
 };

 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
 struct hwrm_wol_filter_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  next_handle;
         u8      wol_filter_id;
         u8      wol_type;
         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP      0x1UL
         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID  0xffUL
         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST    WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
         __le32  unused_0;
         u8      mac_address[6];
         __le16  pattern_offset;
         __le16  pattern_size;
         __le16  pattern_mask_size;
         u8      unused_1[3];
         u8      valid;
 };

 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
 struct hwrm_wol_reason_qcfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  port_id;
         u8      unused_0[6];
         __le64  wol_pkt_buf_addr;
         __le16  wol_pkt_buf_size;
         u8      unused_1[6];
 };

 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
 struct hwrm_wol_reason_qcfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      wol_filter_id;
         u8      wol_reason;
         #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
         #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP      0x1UL
         #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID  0xffUL
         #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST    WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
         u8      wol_pkt_len;
         u8      unused_0[4];
         u8      valid;
 };

 /* hwrm_dbg_read_direct_input (size:256b/32B) */
 struct hwrm_dbg_read_direct_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
         __le32  read_addr;
         __le32  read_len32;
 };

 /* hwrm_dbg_read_direct_output (size:128b/16B) */
 struct hwrm_dbg_read_direct_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_dbg_write_direct_input (size:448b/56B) */
 struct hwrm_dbg_write_direct_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  write_addr;
         __le32  write_len32;
         __le32  write_data[8];
 };

 /* hwrm_dbg_write_direct_output (size:128b/16B) */
 struct hwrm_dbg_write_direct_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_dbg_read_indirect_input (size:320b/40B) */
 struct hwrm_dbg_read_indirect_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
         __le32  host_dest_addr_len;
         u8      indirect_access_type;
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2         0x0UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4       0x1UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2         0x2UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4       0x3UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_STAT_CTXS                  0x4UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM             0x5UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM             0x6UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM    0x7UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM    0x8UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM 0x9UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM 0xaUL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM        0xbUL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM 0xcUL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM 0xdUL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM         0xeUL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM         0xfUL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MHB                        0x10UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_PCIE_GBL                   0x11UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC             0x12UL
         #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_LAST                      DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC
         u8      unused_0[3];
         __le32  start_index;
         __le32  num_of_entries;
 };

 /* hwrm_dbg_read_indirect_output (size:128b/16B) */
 struct hwrm_dbg_read_indirect_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_dbg_write_indirect_input (size:512b/64B) */
 struct hwrm_dbg_write_indirect_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      indirect_access_type;
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2         0x0UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4       0x1UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2         0x2UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4       0x3UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_STAT_CTXS                  0x4UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM             0x5UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM             0x6UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM    0x7UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM    0x8UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM 0x9UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM 0xaUL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM        0xbUL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM 0xcUL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM 0xdUL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM         0xeUL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM         0xfUL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MHB                        0x10UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_PCIE_GBL                   0x11UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC             0x12UL
         #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_LAST                      DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC
         u8      unused_0[3];
         __le32  start_index;
         __le32  num_of_entries;
         u8      unused_1[4];
         __le32  write_data[8];
 };

 /* hwrm_dbg_write_indirect_output (size:128b/16B) */
 struct hwrm_dbg_write_indirect_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_dbg_dump_input (size:320b/40B) */
 struct hwrm_dbg_dump_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  handle;
         u8      unused_0[4];
         __le64  host_dbg_dump_addr;
         __le64  host_dbg_dump_addr_len;
 };

 /* hwrm_dbg_dump_output (size:192b/24B) */
 struct hwrm_dbg_dump_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  nexthandle;
         __le32  dbg_data_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_dbg_erase_nvm_input (size:192b/24B) */
 struct hwrm_dbg_erase_nvm_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  flags;
         #define DBG_ERASE_NVM_REQ_FLAGS_ERASE_ALL     0x1UL
         u8      unused_0[6];
 };

 /* hwrm_dbg_erase_nvm_output (size:128b/16B) */
 struct hwrm_dbg_erase_nvm_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_dbg_cfg_input (size:192b/24B) */
 struct hwrm_dbg_cfg_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  flags;
         #define DBG_CFG_REQ_FLAGS_UART_LOG               0x1UL
         #define DBG_CFG_REQ_FLAGS_UART_LOG_SECONDARY     0x2UL
         u8      unused_0[4];
 };

 /* hwrm_dbg_cfg_output (size:128b/16B) */
 struct hwrm_dbg_cfg_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* coredump_segment_record (size:128b/16B) */
 struct coredump_segment_record {
         __le16  component_id;
         __le16  segment_id;
         __le16  max_instances;
         u8      version_hi;
         u8      version_low;
         u8      seg_flags;
         u8      unused_0[7];
 };

 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
 struct hwrm_dbg_coredump_list_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
         __le32  host_buf_len;
         __le16  seq_no;
         u8      unused_0[2];
 };

 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
 struct hwrm_dbg_coredump_list_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      flags;
         #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE     0x1UL
         u8      unused_0;
         __le16  total_segments;
         __le16  data_len;
         u8      unused_1;
         u8      valid;
 };

 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
 struct hwrm_dbg_coredump_initiate_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  component_id;
         __le16  segment_id;
         __le16  instance;
         __le16  unused_0;
         u8      seg_flags;
         u8      unused_1[7];
 };

 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
 struct hwrm_dbg_coredump_initiate_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* coredump_data_hdr (size:128b/16B) */
 struct coredump_data_hdr {
         __le32  address;
         __le32  flags_length;
         __le32  instance;
         __le32  next_offset;
 };

 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
 struct hwrm_dbg_coredump_retrieve_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
         __le32  host_buf_len;
         __le32  unused_0;
         __le16  component_id;
         __le16  segment_id;
         __le16  instance;
         __le16  unused_1;
         u8      seg_flags;
         u8      unused_2;
         __le16  unused_3;
         __le32  unused_4;
         __le32  seq_no;
         __le32  unused_5;
 };

 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
 struct hwrm_dbg_coredump_retrieve_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      flags;
         #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE     0x1UL
         u8      unused_0;
         __le16  data_len;
         u8      unused_1[3];
         u8      valid;
 };

 /* hwrm_dbg_i2c_cmd_input (size:320b/40B) */
 struct hwrm_dbg_i2c_cmd_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
         __le16  read_size;
         __le16  write_size;
         u8      chnl_id;
         u8      options;
         #define DBG_I2C_CMD_REQ_OPTIONS_10_BIT_ADDRESSING     0x1UL
         #define DBG_I2C_CMD_REQ_OPTIONS_FAST_MODE             0x2UL
         __le16  slave_addr;
         u8      xfer_mode;
         #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_READ       0x0UL
         #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE      0x1UL
         #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE_READ 0x2UL
         #define DBG_I2C_CMD_REQ_XFER_MODE_LAST             DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE_READ
         u8      unused_1[7];
 };

 /* hwrm_dbg_i2c_cmd_output (size:128b/16B) */
 struct hwrm_dbg_i2c_cmd_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_dbg_fw_cli_input (size:1024b/128B) */
 struct hwrm_dbg_fw_cli_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
         __le32  host_buf_len;
         __le16  cli_cmd_len;
         u8      unused_0[2];
         u8      cli_cmd[96];
 };

 /* hwrm_dbg_fw_cli_output (size:128b/16B) */
 struct hwrm_dbg_fw_cli_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  cli_data_len;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */
 struct hwrm_dbg_ring_info_get_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      ring_type;
         #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
         #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX      0x1UL
         #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX      0x2UL
         #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST   DBG_RING_INFO_GET_REQ_RING_TYPE_RX
         u8      unused_0[3];
         __le32  fw_ring_id;
 };

 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */
 struct hwrm_dbg_ring_info_get_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  producer_index;
         __le32  consumer_index;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
 struct hwrm_nvm_raw_write_blk_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_src_addr;
         __le32  dest_addr;
         __le32  len;
 };

 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
 struct hwrm_nvm_raw_write_blk_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_read_input (size:320b/40B) */
 struct hwrm_nvm_read_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
         __le16  dir_idx;
         u8      unused_0[2];
         __le32  offset;
         __le32  len;
         u8      unused_1[4];
 };

 /* hwrm_nvm_read_output (size:128b/16B) */
 struct hwrm_nvm_read_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
 struct hwrm_nvm_raw_dump_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
         __le32  offset;
         __le32  len;
 };

 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
 struct hwrm_nvm_raw_dump_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
 struct hwrm_nvm_get_dir_entries_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_dest_addr;
 };

 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
 struct hwrm_nvm_get_dir_entries_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
 struct hwrm_nvm_get_dir_info_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
 struct hwrm_nvm_get_dir_info_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  entries;
         __le32  entry_length;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_write_input (size:384b/48B) */
 struct hwrm_nvm_write_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_src_addr;
         __le16  dir_type;
         __le16  dir_ordinal;
         __le16  dir_ext;
         __le16  dir_attr;
         __le32  dir_data_length;
         __le16  option;
         __le16  flags;
         #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG     0x1UL
         __le32  dir_item_length;
         __le32  unused_0;
 };

 /* hwrm_nvm_write_output (size:128b/16B) */
 struct hwrm_nvm_write_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  dir_item_length;
         __le16  dir_idx;
         u8      unused_0;
         u8      valid;
 };

 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
 struct hwrm_nvm_write_cmd_err {
         u8      code;
         #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN  0x0UL
         #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
         #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
         #define NVM_WRITE_CMD_ERR_CODE_LAST    NVM_WRITE_CMD_ERR_CODE_NO_SPACE
         u8      unused_0[7];
 };

 /* hwrm_nvm_modify_input (size:320b/40B) */
 struct hwrm_nvm_modify_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  host_src_addr;
         __le16  dir_idx;
         u8      unused_0[2];
         __le32  offset;
         __le32  len;
         u8      unused_1[4];
 };

 /* hwrm_nvm_modify_output (size:128b/16B) */
 struct hwrm_nvm_modify_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
 struct hwrm_nvm_find_dir_entry_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID     0x1UL
         __le16  dir_idx;
         __le16  dir_type;
         __le16  dir_ordinal;
         __le16  dir_ext;
         u8      opt_ordinal;
         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ    0x0UL
         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE    0x1UL
         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT    0x2UL
         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
         u8      unused_0[3];
 };

 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
 struct hwrm_nvm_find_dir_entry_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  dir_item_length;
         __le32  dir_data_length;
         __le32  fw_ver;
         __le16  dir_ordinal;
         __le16  dir_idx;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
 struct hwrm_nvm_erase_dir_entry_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  dir_idx;
         u8      unused_0[6];
 };

 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
 struct hwrm_nvm_erase_dir_entry_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
 struct hwrm_nvm_get_dev_info_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
 struct hwrm_nvm_get_dev_info_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  manufacturer_id;
         __le16  device_id;
         __le32  sector_size;
         __le32  nvram_size;
         __le32  reserved_size;
         __le32  available_size;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
 struct hwrm_nvm_mod_dir_entry_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  enables;
         #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM     0x1UL
         __le16  dir_idx;
         __le16  dir_ordinal;
         __le16  dir_ext;
         __le16  dir_attr;
         __le32  checksum;
 };

 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
 struct hwrm_nvm_mod_dir_entry_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_verify_update_input (size:192b/24B) */
 struct hwrm_nvm_verify_update_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le16  dir_type;
         __le16  dir_ordinal;
         __le16  dir_ext;
         u8      unused_0[2];
 };

 /* hwrm_nvm_verify_update_output (size:128b/16B) */
 struct hwrm_nvm_verify_update_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_install_update_input (size:192b/24B) */
 struct hwrm_nvm_install_update_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  install_type;
         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL    0xffffffffUL
         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST  NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
         __le16  flags;
         #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE     0x1UL
         #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG      0x2UL
         #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG      0x4UL
         u8      unused_0[2];
 };

 /* hwrm_nvm_install_update_output (size:192b/24B) */
 struct hwrm_nvm_install_update_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le64  installed_items;
         u8      result;
         #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
         #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST   NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
         u8      problem_item;
         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE    0x0UL
         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST   NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
         u8      reset_required;
         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE  0x0UL
         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI   0x1UL
         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
         u8      unused_0[4];
         u8      valid;
 };

 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
 struct hwrm_nvm_install_update_cmd_err {
         u8      code;
         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN  0x0UL
         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST    NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
         u8      unused_0[7];
 };

 /* hwrm_nvm_flush_input (size:128b/16B) */
 struct hwrm_nvm_flush_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_nvm_flush_output (size:128b/16B) */
 struct hwrm_nvm_flush_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
 struct hwrm_nvm_flush_cmd_err {
         u8      code;
         #define NVM_FLUSH_CMD_ERR_CODE_UNKNOWN 0x0UL
         #define NVM_FLUSH_CMD_ERR_CODE_FAIL    0x1UL
         #define NVM_FLUSH_CMD_ERR_CODE_LAST   NVM_FLUSH_CMD_ERR_CODE_FAIL
         u8      unused_0[7];
 };

 /* hwrm_nvm_get_variable_input (size:320b/40B) */
 struct hwrm_nvm_get_variable_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  dest_data_addr;
         __le16  data_len;
         __le16  option_num;
         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL
         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
         __le16  dimensions;
         __le16  index_0;
         __le16  index_1;
         __le16  index_2;
         __le16  index_3;
         u8      flags;
         #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT     0x1UL
         u8      unused_0;
 };

 /* hwrm_nvm_get_variable_output (size:128b/16B) */
 struct hwrm_nvm_get_variable_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  data_len;
         __le16  option_num;
         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0    0x0UL
         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST     NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
 struct hwrm_nvm_get_variable_cmd_err {
         u8      code;
         #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL
         #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
         #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL
         #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
         #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST         NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
         u8      unused_0[7];
 };

 /* hwrm_nvm_set_variable_input (size:320b/40B) */
 struct hwrm_nvm_set_variable_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  src_data_addr;
         __le16  data_len;
         __le16  option_num;
         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL
         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
         __le16  dimensions;
         __le16  index_0;
         __le16  index_1;
         __le16  index_2;
         __le16  index_3;
         u8      flags;
         #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH                0x1UL
         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK          0xeUL
         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT           1
         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE            (0x0UL << 1)
         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1       (0x1UL << 1)
         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256          (0x2UL << 1)
         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH  (0x3UL << 1)
         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST           NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
         u8      unused_0;
 };

 /* hwrm_nvm_set_variable_output (size:128b/16B) */
 struct hwrm_nvm_set_variable_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
 struct hwrm_nvm_set_variable_cmd_err {
         u8      code;
         #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL
         #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
         #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL
         #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST         NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
         u8      unused_0[7];
 };

 /* hwrm_nvm_validate_option_input (size:320b/40B) */
 struct hwrm_nvm_validate_option_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  src_data_addr;
         __le16  data_len;
         __le16  option_num;
         #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_0    0x0UL
         #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
         #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_LAST     NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_FFFF
         __le16  dimensions;
         __le16  index_0;
         __le16  index_1;
         __le16  index_2;
         __le16  index_3;
         u8      unused_0[2];
 };

 /* hwrm_nvm_validate_option_output (size:128b/16B) */
 struct hwrm_nvm_validate_option_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      result;
         #define NVM_VALIDATE_OPTION_RESP_RESULT_NOT_MATCH 0x0UL
         #define NVM_VALIDATE_OPTION_RESP_RESULT_MATCH     0x1UL
         #define NVM_VALIDATE_OPTION_RESP_RESULT_LAST     NVM_VALIDATE_OPTION_RESP_RESULT_MATCH
         u8      unused_0[6];
         u8      valid;
 };

 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
 struct hwrm_nvm_validate_option_cmd_err {
         u8      code;
         #define NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN 0x0UL
         #define NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST   NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
         u8      unused_0[7];
 };

 /* hwrm_nvm_factory_defaults_input (size:192b/24B) */
 struct hwrm_nvm_factory_defaults_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      mode;
         #define NVM_FACTORY_DEFAULTS_REQ_MODE_RESTORE 0x0UL
         #define NVM_FACTORY_DEFAULTS_REQ_MODE_CREATE  0x1UL
         #define NVM_FACTORY_DEFAULTS_REQ_MODE_LAST   NVM_FACTORY_DEFAULTS_REQ_MODE_CREATE
         u8      unused_0[7];
 };

 /* hwrm_nvm_factory_defaults_output (size:128b/16B) */
 struct hwrm_nvm_factory_defaults_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      result;
         #define NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_OK      0x0UL
         #define NVM_FACTORY_DEFAULTS_RESP_RESULT_RESTORE_OK     0x1UL
         #define NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_ALREADY 0x2UL
         #define NVM_FACTORY_DEFAULTS_RESP_RESULT_LAST          NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_ALREADY
         u8      unused_0[6];
         u8      valid;
 };

 /* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */
 struct hwrm_nvm_factory_defaults_cmd_err {
         u8      code;
         #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN      0x0UL
         #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG 0x1UL
         #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG 0x2UL
         #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST        NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG
         u8      unused_0[7];
 };

 /* hwrm_selftest_qlist_input (size:128b/16B) */
 struct hwrm_selftest_qlist_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_selftest_qlist_output (size:2240b/280B) */
 struct hwrm_selftest_qlist_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      num_tests;
         u8      available_tests;
         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST                 0x1UL
         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST                0x2UL
         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST            0x4UL
         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST              0x8UL
         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST         0x10UL
         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST     0x20UL
         u8      offline_tests;
         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST                 0x1UL
         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST                0x2UL
         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST            0x4UL
         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST              0x8UL
         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST         0x10UL
         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST     0x20UL
         u8      unused_0;
         __le16  test_timeout;
         u8      unused_1[2];
         char    test0_name[32];
         char    test1_name[32];
         char    test2_name[32];
         char    test3_name[32];
         char    test4_name[32];
         char    test5_name[32];
         char    test6_name[32];
         char    test7_name[32];
         u8      unused_2[7];
         u8      valid;
 };

 /* hwrm_selftest_exec_input (size:192b/24B) */
 struct hwrm_selftest_exec_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         u8      flags;
         #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST                 0x1UL
         #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST                0x2UL
         #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST            0x4UL
         #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST              0x8UL
         #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST         0x10UL
         #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST     0x20UL
         u8      unused_0[7];
 };

 /* hwrm_selftest_exec_output (size:128b/16B) */
 struct hwrm_selftest_exec_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      requested_tests;
         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST                 0x1UL
         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST                0x2UL
         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST            0x4UL
         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST              0x8UL
         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST         0x10UL
         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST     0x20UL
         u8      test_success;
         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST                 0x1UL
         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST                0x2UL
         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST            0x4UL
         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST              0x8UL
         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST         0x10UL
         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST     0x20UL
         u8      unused_0[5];
         u8      valid;
 };

 /* hwrm_selftest_irq_input (size:128b/16B) */
 struct hwrm_selftest_irq_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
 };

 /* hwrm_selftest_irq_output (size:128b/16B) */
 struct hwrm_selftest_irq_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         u8      unused_0[7];
         u8      valid;
 };

 /* hwrm_selftest_retrieve_serdes_data_input (size:256b/32B) */
 struct hwrm_selftest_retrieve_serdes_data_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le64  resp_data_addr;
         __le32  resp_data_offset;
         __le16  data_len;
         u8      flags;
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_MASK         0x7UL
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_SFT          0
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_EYE_PROJECTION           0x8UL
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_PCIE_SERDES_TEST         0x10UL
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_ETHERNET_SERDES_TEST     0x20UL
         u8      options;
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PCIE_LANE_NO_MASK     0xfUL
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PCIE_LANE_NO_SFT      0
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION             0x10UL
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_HORIZONTAL    (0x0UL << 4)
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_VERTICAL      (0x1UL << 4)
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_LAST         SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_VERTICAL
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE             0x20UL
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_LEFT_TOP      (0x0UL << 5)
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM  (0x1UL << 5)
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_LAST         SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_RSVD_MASK             0xc0UL
         #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_RSVD_SFT              6
 };

 /* hwrm_selftest_retrieve_serdes_data_output (size:128b/16B) */
 struct hwrm_selftest_retrieve_serdes_data_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le16  total_data_len;
         __le16  copied_data_len;
         u8      unused_0[3];
         u8      valid;
 };

 /* hwrm_oem_cmd_input (size:1024b/128B) */
 struct hwrm_oem_cmd_input {
         __le16  req_type;
         __le16  cmpl_ring;
         __le16  seq_id;
         __le16  target_id;
         __le64  resp_addr;
         __le32  IANA;
         __le32  unused_0;
         __le32  oem_data[26];
 };

 /* hwrm_oem_cmd_output (size:1344b/168B) */
 struct hwrm_oem_cmd_output {
         __le16  error_code;
         __le16  req_type;
         __le16  seq_id;
         __le16  resp_len;
         __le32  IANA;
         __le32  unused_0;
         __le32  oem_data[36];
         u8      unused_1[7];
         u8      valid;
 };

 #endif /* _BNXT_HSI_H_ */
hwrm_dbg_erase_nvm_input::flags
__le16 flags
Definition: bnxt_hsi.h:9677

hwrm_nvm_read_input::resp_addr
__le64 resp_addr
Definition: bnxt_hsi.h:9937

hwrm_port_led_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition: bnxt_hsi.h:4460

hwrm_async_event_cmpl_pf_vf_comm_status_change::event_id
__le16 event_id
Definition: bnxt_hsi.h:1015

hwrm_cfa_redirect_tunnel_type_alloc_input::resp_addr
__le64 resp_addr
Definition: bnxt_hsi.h:6853

hwrm_vnic_rss_cos_lb_ctx_alloc_input::resp_addr
__le64 resp_addr
Definition: bnxt_hsi.h:6164

hwrm_cfa_tunnel_filter_alloc_input::l2_ivlan
__le16 l2_ivlan
Definition: bnxt_hsi.h:6786

hwrm_queue_qcfg_output::queue_cfg_info
u8 queue_cfg_info
Definition: bnxt_hsi.h:4802

hwrm_cfa_l2_filter_cfg_output::valid
u8 valid
Definition: bnxt_hsi.h:6669

hwrm_async_event_cmpl_func_flr_proc_cmplt::timestamp_lo
u8 timestamp_lo
Definition: bnxt_hsi.h:907

hwrm_func_backing_store_cfg_input::tqm_ring1_pg_size_tqm_ring1_lvl
u8 tqm_ring1_pg_size_tqm_ring1_lvl
Definition: bnxt_hsi.h:2292

hwrm_func_buf_unrgtr_input::enables
__le32 enables
Definition: bnxt_hsi.h:1958

hwrm_func_qcfg_output::max_mtu_configured
__le16 max_mtu_configured
Definition: bnxt_hsi.h:1442

hwrm_func_drv_if_change_output
Definition: bnxt_hsi.h:3023

hwrm_port_led_qcfg_output::led0_color
u8 led0_color
Definition: bnxt_hsi.h:4488

hwrm_cfa_em_flow_cfg_output::valid
u8 valid
Definition: bnxt_hsi.h:7369

hwrm_func_drv_rgtr_input::vf_req_fwd
__le32 vf_req_fwd[8]
Definition: bnxt_hsi.h:1861

hwrm_selftest_retrieve_serdes_data_input::cmpl_ring
__le16 cmpl_ring
Definition: bnxt_hsi.h:10587

hwrm_wol_filter_qcfg_input::unused_2
u8 unused_2[6]
Definition: bnxt_hsi.h:9455

hwrm_nvm_read_output::seq_id
__le16 seq_id
Definition: bnxt_hsi.h:9950

hwrm_queue_cos2bw_qcfg_output::queue_id7_bw_weight
u8 queue_id7_bw_weight
Definition: bnxt_hsi.h:5326

hwrm_ring_grp_free_input::seq_id
__le16 seq_id
Definition: bnxt_hsi.h:6490

hwrm_queue_cos2bw_cfg_input
Definition: bnxt_hsi.h:5332

hwrm_func_vf_cfg_input::num_cmpl_rings
__le16 num_cmpl_rings
Definition: bnxt_hsi.h:1303

hwrm_nvm_find_dir_entry_input::resp_addr
__le64 resp_addr
Definition: bnxt_hsi.h:10092

hwrm_oem_cmd_output::oem_data
__le32 oem_data[36]
Definition: bnxt_hsi.h:10647

hwrm_queue_dscp_qcaps_output::unused_1
u8 unused_1[3]
Definition: bnxt_hsi.h:5703

hwrm_nvm_find_dir_entry_output::valid
u8 valid
Definition: bnxt_hsi.h:10121

hwrm_port_led_qcaps_output::led3_color_caps
__le16 led3_color_caps
Definition: bnxt_hsi.h:4658

hwrm_port_phy_cfg_input::lpbk
u8 lpbk
Definition: bnxt_hsi.h:3148

hwrm_port_mac_cfg_input::enables
__le32 enables
Definition: bnxt_hsi.h:3634

tx_port_stats::tx_eee_lpi_duration
__le64 tx_eee_lpi_duration
Definition: bnxt_hsi.h:3838

hwrm_port_phy_qcaps_output::valid
u8 valid
Definition: bnxt_hsi.h:4271

hwrm_selftest_qlist_output::num_tests
u8 num_tests
Definition: bnxt_hsi.h:10494

hwrm_vnic_tpa_qcfg_output::flags
__le32 flags
Definition: bnxt_hsi.h:5987

hwrm_ring_alloc_input::page_tbl_depth
u8 page_tbl_depth
Definition: bnxt_hsi.h:6227

hwrm_queue_cos2bw_cfg_output::req_type
__le16 req_type
Definition: bnxt_hsi.h:5676

hwrm_fw_health_check_input::req_type
__le16 req_type
Definition: bnxt_hsi.h:9200

hwrm_struct_data_dcbx_ets::tc3_to_bw_map
u8 tc3_to_bw_map
Definition: bnxt_hsi.h:8881

hwrm_vnic_qcfg_output::resp_len
__le16 resp_len
Definition: bnxt_hsi.h:5867

rx_port_stats::rx_llfc_physical_msgs
__le64 rx_llfc_physical_msgs
Definition: bnxt_hsi.h:3906

hwrm_port_led_cfg_input::rsvd1
u8 rsvd1
Definition: bnxt_hsi.h:4406

hwrm_cfa_pair_alloc_output::valid
u8 valid
Definition: bnxt_hsi.h:8238

hwrm_dbg_i2c_cmd_input::seq_id
__le16 seq_id
Definition: bnxt_hsi.h:9827

hwrm_cfa_decap_filter_alloc_input::dst_id
__le16 dst_id
Definition: bnxt_hsi.h:7726

hwrm_cfa_redirect_tunnel_type_free_output
Definition: bnxt_hsi.h:6912

hwrm_vnic_free_input::unused_0
u8 unused_0[4]
Definition: bnxt_hsi.h:5792

hwrm_port_clr_stats_input::unused_0
u8 unused_0[5]
Definition: bnxt_hsi.h:4088

hwrm_cfa_meter_profile_alloc_input::reserved2
__le32 reserved2
Definition: bnxt_hsi.h:7390

hwrm_fw_get_time_output
Definition: bnxt_hsi.h:8815

hwrm_cfa_flow_stats_input::target_id
__le16 target_id
Definition: bnxt_hsi.h:7945

hwrm_cfa_redirect_query_tunnel_type_output::tunnel_mask
__le32 tunnel_mask
Definition: bnxt_hsi.h:8374

hwrm_func_vlan_cfg_input::req_type
__le16 req_type
Definition: bnxt_hsi.h:2858

hwrm_cfa_l2_filter_alloc_input::mirror_vnic_id
__le16 mirror_vnic_id
Definition: bnxt_hsi.h:6590

hwrm_tunnel_dst_port_alloc_input::tunnel_dst_port_val
__be16 tunnel_dst_port_val
Definition: bnxt_hsi.h:8436

hwrm_func_vf_bw_cfg_input::seq_id
__le16 seq_id
Definition: bnxt_hsi.h:2923

hwrm_cfa_tunnel_filter_alloc_output::valid
u8 valid
Definition: bnxt_hsi.h:6824

hwrm_cfa_l2_filter_free_input::l2_filter_id
__le64 l2_filter_id
Definition: bnxt_hsi.h:6622

hwrm_vnic_plcmodes_cfg_input::vnic_id
__le32 vnic_id
Definition: bnxt_hsi.h:6109

hwrm_reject_fwd_resp_input::encap_request
__le32 encap_request[26]
Definition: bnxt_hsi.h:9289

hwrm_cfa_encap_data_vxlan::hdr_rsvd0
u8 hdr_rsvd0[3]
Definition: bnxt_hsi.h:7010

hwrm_cfa_decap_filter_alloc_input::unused_1
__le16 unused_1
Definition: bnxt_hsi.h:7701

hwrm_func_qcfg_output::alloc_rx_rings
__le16 alloc_rx_rings
Definition: bnxt_hsi.h:1424

tlv::tlv_type
__le16 tlv_type
Definition: bnxt_hsi.h:63

hwrm_cfa_tunnel_filter_alloc_output::flow_id
__le32 flow_id
Definition: bnxt_hsi.h:6822

hwrm_cfa_em_flow_free_input::resp_addr
__le64 resp_addr
Definition: bnxt_hsi.h:7327

hwrm_func_buf_rgtr_input::req_buf_len
__le16 req_buf_len
Definition: bnxt_hsi.h:1924

hwrm_vnic_rss_cfg_output::unused_0
u8 unused_0[7]
Definition: bnxt_hsi.h:6051

hwrm_dbg_coredump_list_input::host_dest_addr
__le64 host_dest_addr
Definition: bnxt_hsi.h:9733

hwrm_temp_monitor_query_output::error_code
__le16 error_code
Definition: bnxt_hsi.h:9363

hwrm_func_backing_store_qcfg_output::tqm_ring6_page_dir
__le64 tqm_ring6_page_dir
Definition: bnxt_hsi.h:2795

hwrm_cfa_vf_pair_free_output::error_code
__le16 error_code
Definition: bnxt_hsi.h:8147

hwrm_struct_data_rss_v2::rss_ctx_id
__le16 rss_ctx_id
Definition: bnxt_hsi.h:9024

hwrm_cfa_flow_info_output::valid
u8 valid
Definition: bnxt_hsi.h:7916

hwrm_fw_ipc_msg_input::opaque
__le64 opaque
Definition: bnxt_hsi.h:9150

hwrm_port_phy_cfg_input::tx_lpi_timer
__le32 tx_lpi_timer
Definition: bnxt_hsi.h:3172

hwrm_cfa_meter_profile_cfg_input
Definition: bnxt_hsi.h:7500

hwrm_fw_set_time_input::second
u8 second
Definition: bnxt_hsi.h:8785

hwrm_nvm_write_input::dir_attr
__le16 dir_attr
Definition: bnxt_hsi.h:10030

hwrm_fw_get_structured_data_cmd_err::code
u8 code
Definition: bnxt_hsi.h:9118

hwrm_queue_pri2cos_cfg_output::resp_len
__le16 resp_len
Definition: bnxt_hsi.h:4983

tx_port_stats::tx_late_coll_frames
__le64 tx_late_coll_frames
Definition: bnxt_hsi.h:3821

hwrm_cfa_em_flow_free_input::cmpl_ring
__le16 cmpl_ring
Definition: bnxt_hsi.h:7324

hwrm_func_drv_qver_output::valid
u8 valid
Definition: bnxt_hsi.h:2014

hwrm_dbg_read_indirect_input::resp_addr
__le64 resp_addr
Definition: bnxt_hsi.h:9561

hwrm_cfa_meter_profile_cfg_output::resp_len
__le16 resp_len
Definition: bnxt_hsi.h:7591

hwrm_func_vf_bw_qcfg_output::num_vfs
__le16 num_vfs
Definition: bnxt_hsi.h:2982

hwrm_dbg_fw_cli_output::unused_0
u8 unused_0[3]
Definition: bnxt_hsi.h:9877

hwrm_fwd_async_event_cmpl_input::target_id
__le16 target_id
Definition: bnxt_hsi.h:9335

hwrm_cfa_l2_set_rx_mask_output
Definition: bnxt_hsi.h:6698

hwrm_func_vf_vnic_ids_query_output::req_type
__le16 req_type
Definition: bnxt_hsi.h:2911

hwrm_func_vlan_qcfg_output::unused_0
__le64 unused_0
Definition: bnxt_hsi.h:2841

hwrm_cfa_em_flow_alloc_input::tunnel_type
u8 tunnel_type
Definition: bnxt_hsi.h:7263

hwrm_ring_grp_alloc_input::rr
__le16 rr
Definition: bnxt_hsi.h:6470

hwrm_port_lpbk_qstats_input
Definition: bnxt_hsi.h:4050

hwrm_dbg_coredump_list_output::unused_1
u8 unused_1
Definition: bnxt_hsi.h:9750

hwrm_vnic_alloc_input
Definition: bnxt_hsi.h:5762

hwrm_nvm_mod_dir_entry_input::dir_ext
__le16 dir_ext
Definition: bnxt_hsi.h:10181

hwrm_queue_cos2bw_qcfg_output::queue_id5
u8 queue_id5
Definition: bnxt_hsi.h:5207

hwrm_cfa_flow_info_output::tunnel_handle
__le32 tunnel_handle
Definition: bnxt_hsi.h:7913

hwrm_tunnel_dst_port_query_output::tunnel_dst_port_id
__le16 tunnel_dst_port_id
Definition: bnxt_hsi.h:8415

hwrm_wol_filter_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition: bnxt_hsi.h:9443

hwrm_cfa_meter_instance_free_output
Definition: bnxt_hsi.h:7648

hwrm_wol_filter_qcfg_input::handle
__le16 handle
Definition: bnxt_hsi.h:9448

hwrm_port_mac_cfg_input::dscp2pri_map_pri
u8 dscp2pri_map_pri
Definition: bnxt_hsi.h:3653

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__le32 event_data2
Definition: bnxt_hsi.h:634

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__le16 rss_ctx_idx
Definition: bnxt_hsi.h:6041

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__le16 target_id
Definition: bnxt_hsi.h:4153

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__le64 rx_packets_cos0
Definition: bnxt_hsi.h:3994

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Definition: bnxt_hsi.h:8999

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__le16 seq_id
Definition: bnxt_hsi.h:5335

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Definition: bnxt_hsi.h:1725

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Definition: bnxt_hsi.h:6588

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Definition: bnxt_hsi.h:9741

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__le16 resp_len
Definition: bnxt_hsi.h:10423

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Definition: bnxt_hsi.h:9926

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Definition: bnxt_hsi.h:7167

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__le16 vf_pair_index
Definition: bnxt_hsi.h:8164

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Definition: bnxt_hsi.h:8725

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Definition: bnxt_hsi.h:8344

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__le16 min_l2_ctxs
Definition: bnxt_hsi.h:2049

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Definition: bnxt_hsi.h:5914

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Definition: bnxt_hsi.h:1742

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Definition: bnxt_hsi.h:3013

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Definition: bnxt_hsi.h:9924

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Definition: bnxt_hsi.h:10262

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Definition: bnxt_hsi.h:6732

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Definition: bnxt_hsi.h:2128

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Definition: bnxt_hsi.h:732

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Definition: bnxt_hsi.h:8608

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Definition: bnxt_hsi.h:8061

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Definition: bnxt_hsi.h:10078

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Definition: bnxt_hsi.h:653

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Definition: bnxt_hsi.h:4544

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Definition: bnxt_hsi.h:6481

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__le64 tx_packets_cos0
Definition: bnxt_hsi.h:3953

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Definition: bnxt_hsi.h:406

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Definition: bnxt_hsi.h:8932

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Definition: bnxt_hsi.h:5833

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Definition: bnxt_hsi.h:8767

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__le64 vlan_tag_mask_tbl_addr
Definition: bnxt_hsi.h:6749

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__le64 byte_9
Definition: bnxt_hsi.h:7996

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Definition: bnxt_hsi.h:8667

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__le16 seq_id
Definition: bnxt_hsi.h:5755

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u8 hour
Definition: bnxt_hsi.h:8825

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Definition: bnxt_hsi.h:4567

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__le16 error_code
Definition: bnxt_hsi.h:3213

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Definition: bnxt_hsi.h:9882

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__be16 src_port_mask
Definition: bnxt_hsi.h:7147

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__le16 b_fid
Definition: bnxt_hsi.h:8290

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Definition: bnxt_hsi.h:9061

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__le32 queue_id4_min_bw
Definition: bnxt_hsi.h:5511

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__le16 min_l2_ctxs
Definition: bnxt_hsi.h:2081

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__le16 vlan
Definition: bnxt_hsi.h:1410

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Definition: bnxt_hsi.h:2848

__le32
uint32_t __le32
Definition: efx_common.h:30

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__le16 seq_id
Definition: bnxt_hsi.h:2889

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__le16 resp_len
Definition: bnxt_hsi.h:7220

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__le16 error_code
Definition: bnxt_hsi.h:10617

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Definition: bnxt_hsi.h:5349

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__le16 req_type
Definition: bnxt_hsi.h:8057

output
Definition: bnxt_hsi.h:77

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Definition: bnxt_hsi.h:10332

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__le32 install_type
Definition: bnxt_hsi.h:10226

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Definition: bnxt_hsi.h:10516

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__le16 req_type
Definition: bnxt_hsi.h:10457

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__le16 seq_id
Definition: bnxt_hsi.h:4298

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__le64 tx_fcs_err_frames
Definition: bnxt_hsi.h:3814

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__le32 enables
Definition: bnxt_hsi.h:9423

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Definition: bnxt_hsi.h:7851

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__le16 new_meter_instance_id
Definition: bnxt_hsi.h:7356

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Definition: bnxt_hsi.h:9736

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__le16 req_type
Definition: bnxt_hsi.h:5786

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__le16 resp_len
Definition: bnxt_hsi.h:5678

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__le64 error_buf_addr
Definition: bnxt_hsi.h:1937

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__le16 req_type
Definition: bnxt_hsi.h:3615

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__le64 resp_addr
Definition: bnxt_hsi.h:4126

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__le16 min_hw_ring_grps
Definition: bnxt_hsi.h:2055

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__le16 rx_cfa_code_b
Definition: bnxt_hsi.h:8294

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__le32 dst_id
Definition: bnxt_hsi.h:6658

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__le32 excess_peak_burst
Definition: bnxt_hsi.h:7439

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Definition: bnxt_hsi.h:4238

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__le64 host_dest_addr
Definition: bnxt_hsi.h:9518

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__le16 srq_num_l2_entries
Definition: bnxt_hsi.h:2803

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__le16 seq_id
Definition: bnxt_hsi.h:10023

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Definition: bnxt_hsi.h:7471

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__le16 req_type
Definition: bnxt_hsi.h:10642

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Definition: bnxt_hsi.h:7742

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__le16 seq_id
Definition: bnxt_hsi.h:8173

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Definition: bnxt_hsi.h:9256

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Definition: bnxt_hsi.h:8920

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__le16 resp_len
Definition: bnxt_hsi.h:10242

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__le16 cos_rule
Definition: bnxt_hsi.h:5870

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__le64 tx_dbl_tagged_frames
Definition: bnxt_hsi.h:3826

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Definition: bnxt_hsi.h:9852

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__le16 dst_id
Definition: bnxt_hsi.h:6589

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Definition: bnxt_hsi.h:3789

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Definition: bnxt_hsi.h:5978

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Definition: bnxt_hsi.h:4476

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__le64 tx_128b_255b_frames
Definition: bnxt_hsi.h:3797

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__le16 error_code
Definition: bnxt_hsi.h:10239

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u8 max_configurable_queues
Definition: bnxt_hsi.h:4692

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10482

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__le64 rx_pfc_ena_frames_pri5
Definition: bnxt_hsi.h:3898

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__le64 tx_1519b_2047b_frames
Definition: bnxt_hsi.h:3802

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__be16 ovlan_vid
Definition: bnxt_hsi.h:7705

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Definition: bnxt_hsi.h:6424

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__le16 flow_handle
Definition: bnxt_hsi.h:7912

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__le32 event_data1
Definition: bnxt_hsi.h:1046

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__le64 rx_bcast_pkts
Definition: bnxt_hsi.h:1672

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Definition: bnxt_hsi.h:3750

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__le16 req_type
Definition: bnxt_hsi.h:5841

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Definition: bnxt_hsi.h:6032

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__le16 hwrm_fw_major
Definition: bnxt_hsi.h:451

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__le16 encap_resp_target_id
Definition: bnxt_hsi.h:9290

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__le16 vf_a_id
Definition: bnxt_hsi.h:8207

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Definition: bnxt_hsi.h:9953

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Definition: bnxt_hsi.h:9222

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__le32 num_vlan_entries
Definition: bnxt_hsi.h:6758

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8244

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Definition: bnxt_hsi.h:7758

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6618

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__le64 continuous_roce_pause_events
Definition: bnxt_hsi.h:3984

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__le16 target_id
Definition: bnxt_hsi.h:7884

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__le64 resp_addr
Definition: bnxt_hsi.h:9698

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Definition: bnxt_hsi.h:4295

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__le64 tx_bytes_cos1
Definition: bnxt_hsi.h:3946

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u8 duplex_state
Definition: bnxt_hsi.h:3534

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__le32 event_data1
Definition: bnxt_hsi.h:702

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Definition: bnxt_hsi.h:8191

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__le16 seq_id
Definition: bnxt_hsi.h:1907

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__le16 resp_len
Definition: bnxt_hsi.h:7735

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__le64 resume_pause_events
Definition: bnxt_hsi.h:3983

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__le64 resp_addr
Definition: bnxt_hsi.h:2830

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__le16 max_stat_ctx
Definition: bnxt_hsi.h:1376

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__be16 dst_port
Definition: bnxt_hsi.h:7148

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__le32 mrav_num_entries
Definition: bnxt_hsi.h:2465

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__le32 enables
Definition: bnxt_hsi.h:1253

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Definition: bnxt_hsi.h:3770

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Definition: bnxt_hsi.h:4892

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__le16 req_type
Definition: bnxt_hsi.h:4990

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__le16 resp_len
Definition: bnxt_hsi.h:7872

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__le16 target_id
Definition: bnxt_hsi.h:9377

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__le16 seq_id
Definition: bnxt_hsi.h:1263

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Definition: bnxt_hsi.h:7466

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Definition: bnxt_hsi.h:4597

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__le64 rx_pfc_ena_frames_pri1
Definition: bnxt_hsi.h:3894

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__le32 reset_inprogress_reg_mask
Definition: bnxt_hsi.h:1792

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__le16 timer_units
Definition: bnxt_hsi.h:6387

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__le16 alloc_msix
Definition: bnxt_hsi.h:1499

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__le16 type
Definition: bnxt_hsi.h:792

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u8 evb_mode
Definition: bnxt_hsi.h:1613

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__le16 req_type
Definition: bnxt_hsi.h:10481

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__le16 req_type
Definition: bnxt_hsi.h:9911

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__le16 resp_len
Definition: bnxt_hsi.h:2488

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Definition: bnxt_hsi.h:8616

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Definition: bnxt_hsi.h:2963

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__be32 dst_ipaddr[4]
Definition: bnxt_hsi.h:7300

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u8 unused_0[2]
Definition: bnxt_hsi.h:2903

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Definition: bnxt_hsi.h:2953

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__le64 byte_7
Definition: bnxt_hsi.h:7994

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__le32 host_buf_len
Definition: bnxt_hsi.h:9734

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Definition: bnxt_hsi.h:4662

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Definition: bnxt_hsi.h:9989

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9757

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__le16 led3_blink_off
Definition: bnxt_hsi.h:4565

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Definition: bnxt_hsi.h:3329

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__le16 seq_id
Definition: bnxt_hsi.h:4451

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Definition: bnxt_hsi.h:10020

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__le16 vf_b_id
Definition: bnxt_hsi.h:8210

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__le16 led2_blink_on
Definition: bnxt_hsi.h:4541

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__be16 src_port
Definition: bnxt_hsi.h:7007

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__le16 req_type
Definition: bnxt_hsi.h:2838

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__le64 resp_addr
Definition: bnxt_hsi.h:10590

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Definition: bnxt_hsi.h:3790

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Definition: bnxt_hsi.h:9154

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__le16 seq_id
Definition: bnxt_hsi.h:4039

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__le16 resp_len
Definition: bnxt_hsi.h:9366

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Definition: bnxt_hsi.h:7972

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__le32 max_bailout_time
Definition: bnxt_hsi.h:1751

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Definition: bnxt_hsi.h:3007

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__le16 req_type
Definition: bnxt_hsi.h:4103

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__le16 req_type
Definition: bnxt_hsi.h:10324

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__le16 req_type
Definition: bnxt_hsi.h:6119

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__le64 resp_addr
Definition: bnxt_hsi.h:9760

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__le64 rx_agg_pkts
Definition: bnxt_hsi.h:8596

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__le16 seq_id
Definition: bnxt_hsi.h:9324

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__le32 flags
Definition: bnxt_hsi.h:6770

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__le64 tqm_sp_page_dir
Definition: bnxt_hsi.h:2788

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__le16 target_id
Definition: bnxt_hsi.h:7475

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__le16 req_type
Definition: bnxt_hsi.h:2921

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__le16 error_code
Definition: bnxt_hsi.h:6499

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Definition: bnxt_hsi.h:10167

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Definition: bnxt_hsi.h:6604

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__le32 next_offset
Definition: bnxt_hsi.h:9784

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__le16 error_code
Definition: bnxt_hsi.h:9242

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__le16 max_instances
Definition: bnxt_hsi.h:9719

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__le32 host_buf_len
Definition: bnxt_hsi.h:9795

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Definition: bnxt_hsi.h:1887

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Definition: bnxt_hsi.h:1392

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Definition: bnxt_hsi.h:9642

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Definition: bnxt_hsi.h:7190

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Definition: bnxt_hsi.h:7337

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__le16 lb_rule
Definition: bnxt_hsi.h:5871

hwrm_func_backing_store_cfg_input::vnic_entry_size
__le16 vnic_entry_size
Definition: bnxt_hsi.h:2476

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__le16 option_num
Definition: bnxt_hsi.h:10328

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__le16 seq_id
Definition: bnxt_hsi.h:1338

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Definition: bnxt_hsi.h:9775

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Definition: bnxt_hsi.h:4966

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__le16 alloc_stat_ctx
Definition: bnxt_hsi.h:1498

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__le64 resp_addr
Definition: bnxt_hsi.h:10485

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__le16 target_id
Definition: bnxt_hsi.h:8697

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__le32 new_mirror_vnic_id
Definition: bnxt_hsi.h:7355

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Definition: bnxt_hsi.h:8222

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__le64 rx_fcs_err_frames
Definition: bnxt_hsi.h:3865

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Definition: bnxt_hsi.h:1683

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Definition: bnxt_hsi.h:10480

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Definition: bnxt_hsi.h:9171

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__le16 target_id
Definition: bnxt_hsi.h:10024

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__le16 target_id
Definition: bnxt_hsi.h:5688

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__le32 write_data[8]
Definition: bnxt_hsi.h:9632

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__le16 error_code
Definition: bnxt_hsi.h:2954

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Definition: bnxt_hsi.h:5285

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Definition: bnxt_hsi.h:7603

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__le64 pfc_pri0_tx_transitions
Definition: bnxt_hsi.h:3962

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__le16 seq_id
Definition: bnxt_hsi.h:3710

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__le32 unused_3
Definition: bnxt_hsi.h:510

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10022

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__le16 seq_id
Definition: bnxt_hsi.h:10458

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Definition: bnxt_hsi.h:6743

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__le16 resp_len
Definition: bnxt_hsi.h:9528

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__le16 flow_timer
Definition: bnxt_hsi.h:7914

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__le16 port_id
Definition: bnxt_hsi.h:4464

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__le16 seq_id
Definition: bnxt_hsi.h:6280

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Definition: bnxt_hsi.h:7212

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Definition: bnxt_hsi.h:8228

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__le16 req_type
Definition: bnxt_hsi.h:9661

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__le64 resp_addr
Definition: bnxt_hsi.h:7505

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__le16 dir_idx
Definition: bnxt_hsi.h:10179

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__le16 req_type
Definition: bnxt_hsi.h:9262

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Definition: bnxt_hsi.h:8071

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__le32 rx_ts_reg_off_src_id_2
Definition: bnxt_hsi.h:3779

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__le16 min_cmpl_rings
Definition: bnxt_hsi.h:2043

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Definition: bnxt_hsi.h:6922

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__le16 error_code
Definition: bnxt_hsi.h:8758

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u8 src_processor
Definition: bnxt_hsi.h:9140

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__le16 error_code
Definition: bnxt_hsi.h:9405

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__le64 req_buf_page_addr5
Definition: bnxt_hsi.h:1932

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__le32 enables
Definition: bnxt_hsi.h:1836

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__le16 req_type
Definition: bnxt_hsi.h:8148

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__le64 pfc_pri7_rx_transitions
Definition: bnxt_hsi.h:4017

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__le16 auto_link_pam4_speed_mask
Definition: bnxt_hsi.h:3175

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__le16 error_code
Definition: bnxt_hsi.h:6047

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__le16 resp_len
Definition: bnxt_hsi.h:9245

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__le16 cmpl_ring
Definition: bnxt_hsi.h:2496

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8395

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Definition: bnxt_hsi.h:5708

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__le16 target_id
Definition: bnxt_hsi.h:1274

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__le16 target_id
Definition: bnxt_hsi.h:10632

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u8 result
Definition: bnxt_hsi.h:10244

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__le16 target_id
Definition: bnxt_hsi.h:5336

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__le16 led1_state_caps
Definition: bnxt_hsi.h:4616

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u8 unused_2[6]
Definition: bnxt_hsi.h:3208

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u8 flags
Definition: bnxt_hsi.h:7635

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__le16 tqm_entry_size
Definition: bnxt_hsi.h:2142

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__le16 error_code
Definition: bnxt_hsi.h:9344

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u8 timestamp_lo
Definition: bnxt_hsi.h:700

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__le16 flags
Definition: bnxt_hsi.h:6431

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__le16 error_code
Definition: bnxt_hsi.h:9970

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u8 unused[3]
Definition: bnxt_hsi.h:7013

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__le16 seq_id
Definition: bnxt_hsi.h:9276

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__le16 target_id
Definition: bnxt_hsi.h:4880

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__le16 hwrm_intf_minor
Definition: bnxt_hsi.h:448

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u8 queue_id1
Definition: bnxt_hsi.h:5047

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__le64 aux_bytes_out
Definition: bnxt_hsi.h:8624

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u8 unused_0[7]
Definition: bnxt_hsi.h:4901

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__le16 seq_id
Definition: bnxt_hsi.h:9444

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__le16 millisecond
Definition: bnxt_hsi.h:8787

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__le16 error_code
Definition: bnxt_hsi.h:8327

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__le32 stat_max_entries
Definition: bnxt_hsi.h:2140

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__be16 src_port
Definition: bnxt_hsi.h:7301

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u8 unused_1[4]
Definition: bnxt_hsi.h:7644

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__le64 resp_addr
Definition: bnxt_hsi.h:4154

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u8 led1_id
Definition: bnxt_hsi.h:4498

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__le16 flow_handle_7
Definition: bnxt_hsi.h:7955

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__le16 error_code
Definition: bnxt_hsi.h:6405

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__le16 req_type
Definition: bnxt_hsi.h:8518

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u8 unused_3
Definition: bnxt_hsi.h:4440

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__le16 seq_id
Definition: bnxt_hsi.h:29

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u8 unused_1[7]
Definition: bnxt_hsi.h:8186

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Definition: bnxt_hsi.h:1793

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__le16 data_len
Definition: bnxt_hsi.h:10327

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__le16 req_type
Definition: bnxt_hsi.h:1721

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u8 rsvd2
Definition: bnxt_hsi.h:4425

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__le32 max_hw_ring_grps
Definition: bnxt_hsi.h:1385

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__le16 dir_ordinal
Definition: bnxt_hsi.h:10028

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__le16 dest_fid
Definition: bnxt_hsi.h:6892

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__le16 total_segments
Definition: bnxt_hsi.h:9748

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__le64 resp_addr
Definition: bnxt_hsi.h:3016

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__le16 req_type
Definition: bnxt_hsi.h:6140

ret_codes::error_code
__le16 error_code
Definition: bnxt_hsi.h:330

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__le16 req_type
Definition: bnxt_hsi.h:4925

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u8 unused_0[2]
Definition: bnxt_hsi.h:7958

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__le64 cce_engine_usage
Definition: bnxt_hsi.h:8627

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__le16 error_code
Definition: bnxt_hsi.h:4470

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__le32 mask
Definition: bnxt_hsi.h:6680

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__le32 req_buf_addr_v[2]
Definition: bnxt_hsi.h:524

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Definition: bnxt_hsi.h:3932

hwrm_func_backing_store_qcfg_output::tqm_ring6_num_entries
__le32 tqm_ring6_num_entries
Definition: bnxt_hsi.h:2816

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__le32 fw_ver
Definition: bnxt_hsi.h:10117

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__le16 max_tx_rings
Definition: bnxt_hsi.h:2078

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__be16 l4_src_port
Definition: bnxt_hsi.h:7815

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__le16 target_id
Definition: bnxt_hsi.h:10175

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__le16 port_id
Definition: bnxt_hsi.h:3702

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__le16 seq_id
Definition: bnxt_hsi.h:9244

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__le16 num_stat_ctxs
Definition: bnxt_hsi.h:1308

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__le16 seq_id
Definition: bnxt_hsi.h:2828

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u8 unused_2
Definition: bnxt_hsi.h:9802

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__le16 resp_len
Definition: bnxt_hsi.h:7976

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u8 valid
Definition: bnxt_hsi.h:10216

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__le32 data_offset
Definition: bnxt_hsi.h:9147

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__le64 tx_pfc_ena_frames_pri0
Definition: bnxt_hsi.h:3829

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Definition: bnxt_hsi.h:7175

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__le64 pfc_pri5_tx_transitions
Definition: bnxt_hsi.h:3972

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Definition: bnxt_hsi.h:3926

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Definition: bnxt_hsi.h:10374

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Definition: bnxt_hsi.h:5469

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Definition: bnxt_hsi.h:1117

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__le16 page_offset
Definition: bnxt_hsi.h:4288

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__le16 cos_rule
Definition: bnxt_hsi.h:5831

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Definition: bnxt_hsi.h:4919

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__le64 lpbk_bcast_bytes
Definition: bnxt_hsi.h:4069

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__le16 error_code
Definition: bnxt_hsi.h:6169

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__le32 event_data2
Definition: bnxt_hsi.h:948

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u8 wol_filter_id
Definition: bnxt_hsi.h:9500

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__le32 cq_num_entries
Definition: bnxt_hsi.h:2454

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__le64 tx_drop_pkts
Definition: bnxt_hsi.h:8494

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Definition: bnxt_hsi.h:8338

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__le64 packet_0
Definition: bnxt_hsi.h:7977

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u8 queue_id5_tsa_assign
Definition: bnxt_hsi.h:5240

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__le16 fid
Definition: bnxt_hsi.h:1330

input::seq_id
__le16 seq_id
Definition: bnxt_hsi.h:71

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__le16 error_code
Definition: bnxt_hsi.h:8646

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__le16 num_cmpl_aggr_int_min
Definition: bnxt_hsi.h:6385

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__le16 error_code
Definition: bnxt_hsi.h:4296

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__le16 index_3
Definition: bnxt_hsi.h:10414

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u8 valid
Definition: bnxt_hsi.h:6918

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__le32 tqm_ring1_num_entries
Definition: bnxt_hsi.h:2458

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__be16 ivlan_vid
Definition: bnxt_hsi.h:7706

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8607

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u8 unused_0[6]
Definition: bnxt_hsi.h:6400

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__le64 resp_addr
Definition: bnxt_hsi.h:6324

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__le64 rx_mcast_bytes
Definition: bnxt_hsi.h:1676

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Definition: bnxt_hsi.h:6056

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7922

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__le16 seq_id
Definition: bnxt_hsi.h:6141

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u8 unused_0[6]
Definition: bnxt_hsi.h:4996

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__le32 flags
Definition: bnxt_hsi.h:5768

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u8 pri0_cos_queue_id
Definition: bnxt_hsi.h:4928

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__le16 target_id
Definition: bnxt_hsi.h:9886

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Definition: bnxt_hsi.h:10047

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Definition: bnxt_hsi.h:4979

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__le16 seq_id
Definition: bnxt_hsi.h:8775

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__le64 installed_items
Definition: bnxt_hsi.h:10243

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__le64 ptp_msg_ts
Definition: bnxt_hsi.h:4142

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__le16 target_id
Definition: bnxt_hsi.h:5810

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__le16 target_id
Definition: bnxt_hsi.h:1886

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Definition: bnxt_hsi.h:8919

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Definition: bnxt_hsi.h:9415

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__le16 seq_id
Definition: bnxt_hsi.h:7600

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u8 parallel_detect
Definition: bnxt_hsi.h:3464

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6020

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__le16 index_2
Definition: bnxt_hsi.h:10413

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Definition: bnxt_hsi.h:9273

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__le64 packet_3
Definition: bnxt_hsi.h:7980

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__le16 target_id
Definition: bnxt_hsi.h:6293

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__le16 seq_id
Definition: bnxt_hsi.h:1825

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u8 led0_color
Definition: bnxt_hsi.h:4377

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__le64 tx_stat_discard
Definition: bnxt_hsi.h:4070

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__le64 resp_addr
Definition: bnxt_hsi.h:2499

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char test3_name[32]
Definition: bnxt_hsi.h:10515

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__le16 error_code
Definition: bnxt_hsi.h:10456

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__le64 rx_bytes_cos5
Definition: bnxt_hsi.h:3991

rx_port_stats::rx_unsupported_opcode_frames
__le64 rx_unsupported_opcode_frames
Definition: bnxt_hsi.h:3869

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__le16 error_code
Definition: bnxt_hsi.h:5962

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__le16 force_link_speeds2
Definition: bnxt_hsi.h:3179

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8004

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Definition: bnxt_hsi.h:10511

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Definition: bnxt_hsi.h:10271

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__le16 os_type
Definition: bnxt_hsi.h:1992

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Definition: bnxt_hsi.h:3289

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Definition: bnxt_hsi.h:7823

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__le16 num_cmpl_dma_aggr_during_int_max
Definition: bnxt_hsi.h:6376

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Definition: bnxt_hsi.h:10146

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__le16 vnic_max_vnic_entries
Definition: bnxt_hsi.h:2137

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__le64 tx_discard_pkts
Definition: bnxt_hsi.h:1665

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Definition: bnxt_hsi.h:5509

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Definition: bnxt_hsi.h:8258

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__le16 seq_id
Definition: bnxt_hsi.h:9901

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__le16 force_link_speeds2
Definition: bnxt_hsi.h:3578

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Definition: bnxt_hsi.h:1971

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Definition: bnxt_hsi.h:9659

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__le64 resp_addr
Definition: bnxt_hsi.h:2925

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Definition: bnxt_hsi.h:10344

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Definition: bnxt_hsi.h:9204

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Definition: bnxt_hsi.h:1729

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Definition: bnxt_hsi.h:385

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__le16 req_type
Definition: bnxt_hsi.h:9638

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Definition: bnxt_hsi.h:6855

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Definition: bnxt_hsi.h:9918

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Definition: bnxt_hsi.h:10200

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Definition: bnxt_hsi.h:1094

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Definition: bnxt_hsi.h:1945

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Definition: bnxt_hsi.h:10113

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Definition: bnxt_hsi.h:6406

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Definition: bnxt_hsi.h:9781

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__le32 max_mcast_filters
Definition: bnxt_hsi.h:1383

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__le16 num_cmpl_rings
Definition: bnxt_hsi.h:1563

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__le32 decap_filter_id
Definition: bnxt_hsi.h:7736

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__le16 def_req_timeout
Definition: bnxt_hsi.h:441

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__le16 resp_len
Definition: bnxt_hsi.h:9325

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__le16 target_id
Definition: bnxt_hsi.h:3236

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__le16 req_type
Definition: bnxt_hsi.h:4297

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__le32 tqm_ring7_num_entries
Definition: bnxt_hsi.h:2464

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Definition: bnxt_hsi.h:1730

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Definition: bnxt_hsi.h:9563

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Definition: bnxt_hsi.h:8041

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Definition: bnxt_hsi.h:9367

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Definition: bnxt_hsi.h:7809

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Definition: bnxt_hsi.h:1304

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Definition: bnxt_hsi.h:5812

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Definition: bnxt_hsi.h:5770

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Definition: bnxt_hsi.h:495

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Definition: bnxt_hsi.h:8185

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__le16 req_type
Definition: bnxt_hsi.h:6160

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Definition: bnxt_hsi.h:9496

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__le64 rx_4096b_9216b_frames
Definition: bnxt_hsi.h:3859

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__le16 flow_handle_5
Definition: bnxt_hsi.h:7953

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__le16 seq_id
Definition: bnxt_hsi.h:6511

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Definition: bnxt_hsi.h:10455

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__le64 resp_addr
Definition: bnxt_hsi.h:10130

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__le16 req_type
Definition: bnxt_hsi.h:1224

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__le32 event_data1
Definition: bnxt_hsi.h:931

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Definition: bnxt_hsi.h:5690

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8340

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Definition: bnxt_hsi.h:4671

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Definition: bnxt_hsi.h:929

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Definition: bnxt_hsi.h:8610

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Definition: bnxt_hsi.h:4832

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__le16 cmpl_aggr_dma_tmr
Definition: bnxt_hsi.h:6414

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__le16 min_rx_rings
Definition: bnxt_hsi.h:2079

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Definition: bnxt_hsi.h:5967

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__le16 src_fid
Definition: bnxt_hsi.h:7786

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__le32 unused_5
Definition: bnxt_hsi.h:9806

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Definition: bnxt_hsi.h:2847

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Definition: bnxt_hsi.h:1882

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__le16 error_code
Definition: bnxt_hsi.h:2910

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__le16 req_type
Definition: bnxt_hsi.h:9971

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__le64 cq_page_dir
Definition: bnxt_hsi.h:2785

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__le64 tx_pfc_ena_frames_pri5
Definition: bnxt_hsi.h:3834

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__le16 millisecond
Definition: bnxt_hsi.h:8829

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__le64 pfc_pri2_tx_duration_us
Definition: bnxt_hsi.h:3965

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Definition: bnxt_hsi.h:3285

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__le16 max_vnics
Definition: bnxt_hsi.h:2052

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__le16 target_id
Definition: bnxt_hsi.h:8140

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__be16 l2_rewrite_smac[3]
Definition: bnxt_hsi.h:7822

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Definition: bnxt_hsi.h:6463

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__le64 rx_drop_pkts
Definition: bnxt_hsi.h:8592

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Definition: bnxt_hsi.h:7612

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Definition: bnxt_hsi.h:4772

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__le16 resp_len
Definition: bnxt_hsi.h:9110

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__le64 resp_addr
Definition: bnxt_hsi.h:6429

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__le16 target_id
Definition: bnxt_hsi.h:9650

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Definition: bnxt_hsi.h:8762

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Definition: bnxt_hsi.h:9716

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__le16 ovlan_vid
Definition: bnxt_hsi.h:7285

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__le16 event_id
Definition: bnxt_hsi.h:899

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Definition: bnxt_hsi.h:3703

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__le64 resp_addr
Definition: bnxt_hsi.h:9676

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u8 wol_filter_id
Definition: bnxt_hsi.h:9426

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__le16 req_type
Definition: bnxt_hsi.h:9433

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__le32 enables
Definition: bnxt_hsi.h:1229

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__le16 resp_len
Definition: bnxt_hsi.h:10140

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__le16 seq_id
Definition: bnxt_hsi.h:10158

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__le64 rx_err_pkts
Definition: bnxt_hsi.h:8591

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Definition: bnxt_hsi.h:8612

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Definition: bnxt_hsi.h:4426

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__le16 vnic_num_vnic_entries
Definition: bnxt_hsi.h:2474

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__le64 resp_addr
Definition: bnxt_hsi.h:5892

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__le32 event_data2
Definition: bnxt_hsi.h:1066

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__le16 req_type
Definition: bnxt_hsi.h:9557

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Definition: bnxt_hsi.h:6954

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Definition: bnxt_hsi.h:6127

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__le16 resp_len
Definition: bnxt_hsi.h:1216

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__le32 max_decap_records
Definition: bnxt_hsi.h:1378

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__le16 error_code
Definition: bnxt_hsi.h:78

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__le16 dst_id
Definition: bnxt_hsi.h:7303

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__le64 rx_65b_127b_frames
Definition: bnxt_hsi.h:3851

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u8 unused_1[7]
Definition: bnxt_hsi.h:2820

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u8 valid
Definition: bnxt_hsi.h:9820

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__le16 port_id
Definition: bnxt_hsi.h:5348

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u8 hwrm_intf_min_8b
Definition: bnxt_hsi.h:395

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__le32 commit_rate
Definition: bnxt_hsi.h:7520

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__le64 pcie_tl_signal_integrity
Definition: bnxt_hsi.h:8681

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__le16 target_id
Definition: bnxt_hsi.h:6163

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__le64 mrav_page_dir
Definition: bnxt_hsi.h:2450

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__le16 target_id
Definition: bnxt_hsi.h:10224

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__le16 resp_len
Definition: bnxt_hsi.h:6071

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__le32 enables
Definition: bnxt_hsi.h:9380

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Definition: bnxt_hsi.h:9394

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__le16 index_2
Definition: bnxt_hsi.h:10314

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__le16 cmpl_aggr_dma_tmr_min
Definition: bnxt_hsi.h:6377

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__le32 enables
Definition: bnxt_hsi.h:4957

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Definition: bnxt_hsi.h:9927

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__le16 error_code
Definition: bnxt_hsi.h:1261

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Definition: bnxt_hsi.h:5589

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__le64 rx_pfc_xon2xoff_frames_pri3
Definition: bnxt_hsi.h:3888

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__le16 target_id
Definition: bnxt_hsi.h:9914

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__be16 src_port
Definition: bnxt_hsi.h:7146

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__le16 req_type
Definition: bnxt_hsi.h:7374

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__le16 error_code
Definition: bnxt_hsi.h:10420

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__le64 req_buf_page_addr6
Definition: bnxt_hsi.h:1933

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__le32 event_data2
Definition: bnxt_hsi.h:725

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u8 valid
Definition: bnxt_hsi.h:1219

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__le32 dir_data_length
Definition: bnxt_hsi.h:10116

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__le16 error_code
Definition: bnxt_hsi.h:8668

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__le32 cq_num_entries
Definition: bnxt_hsi.h:2805

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Definition: bnxt_hsi.h:9866

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__le16 force_pam4_link_speed
Definition: bnxt_hsi.h:3167

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__le16 req_type
Definition: bnxt_hsi.h:10240

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__le64 packet
Definition: bnxt_hsi.h:7873

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u8 queue_id4
Definition: bnxt_hsi.h:5167

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Definition: bnxt_hsi.h:4305

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__le16 signature
Definition: bnxt_hsi.h:87

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__le16 error_code
Definition: bnxt_hsi.h:9107

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__le16 error_code
Definition: bnxt_hsi.h:8171

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Definition: bnxt_hsi.h:8109

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__le16 error_code
Definition: bnxt_hsi.h:5899

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u8 tc6_to_bw_map
Definition: bnxt_hsi.h:8884

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__le16 req_type
Definition: bnxt_hsi.h:7501

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__le16 error_code
Definition: bnxt_hsi.h:9899

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u8 dst_macaddr[6]
Definition: bnxt_hsi.h:7704

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u8 ring_type
Definition: bnxt_hsi.h:6325

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u8 pri1_cos_queue_id
Definition: bnxt_hsi.h:4929

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__le16 vf_reservation_strategy
Definition: bnxt_hsi.h:2036

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6395

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__le16 req_type
Definition: bnxt_hsi.h:7176

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__be32 src_ipaddr[4]
Definition: bnxt_hsi.h:7299

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__le16 int_lat_tmr_max
Definition: bnxt_hsi.h:6440

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__le16 resp_len
Definition: bnxt_hsi.h:6608

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__le16 req_type
Definition: bnxt_hsi.h:9374

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__le16 seq_id
Definition: bnxt_hsi.h:9202

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__le16 resp_len
Definition: bnxt_hsi.h:8726

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Definition: bnxt_hsi.h:4984

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__le16 target_id
Definition: bnxt_hsi.h:10402

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__le16 seq_id
Definition: bnxt_hsi.h:9850

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Definition: bnxt_hsi.h:9723

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__be32 src_ipaddr[4]
Definition: bnxt_hsi.h:7142

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u8 led1_id
Definition: bnxt_hsi.h:4388

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__le16 resp_len
Definition: bnxt_hsi.h:6820

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__le64 tim_page_dir
Definition: bnxt_hsi.h:2798

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__le16 seq_id
Definition: bnxt_hsi.h:8351

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__le16 error_code
Definition: bnxt_hsi.h:9637

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__le16 req_type
Definition: bnxt_hsi.h:5888

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__le16 error_code
Definition: bnxt_hsi.h:1699

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Definition: bnxt_hsi.h:10171

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u8 queue_id0_pri_lvl
Definition: bnxt_hsi.h:5045

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__le16 ptp_msg_seqid
Definition: bnxt_hsi.h:4143

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Definition: bnxt_hsi.h:1127

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__le16 vf_a_id
Definition: bnxt_hsi.h:8119

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__le16 seq_id
Definition: bnxt_hsi.h:1660

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Definition: bnxt_hsi.h:4701

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__le32 tim_num_entries
Definition: bnxt_hsi.h:2466

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7019

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Definition: bnxt_hsi.h:10502

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Definition: bnxt_hsi.h:1642

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__le32 unused_0
Definition: bnxt_hsi.h:10635

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Definition: bnxt_hsi.h:9601

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__le32 flags
Definition: bnxt_hsi.h:1888

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__le64 tx_err
Definition: bnxt_hsi.h:3824

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Definition: bnxt_hsi.h:10562

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__le16 unused_0[3]
Definition: bnxt_hsi.h:348

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Definition: bnxt_hsi.h:6616

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Definition: bnxt_hsi.h:2864

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Definition: bnxt_hsi.h:9060

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__le16 error_code
Definition: bnxt_hsi.h:6338

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Definition: bnxt_hsi.h:1270

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10350

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Definition: bnxt_hsi.h:8601

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__le16 port_id
Definition: bnxt_hsi.h:9487

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__le16 seq_id
Definition: bnxt_hsi.h:7632

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Definition: bnxt_hsi.h:9274

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Definition: bnxt_hsi.h:9559

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__le64 lpbk_mcast_bytes
Definition: bnxt_hsi.h:4068

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__le64 rx_agg_aborts
Definition: bnxt_hsi.h:1681

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Definition: bnxt_hsi.h:10354

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Definition: bnxt_hsi.h:1164

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Definition: bnxt_hsi.h:10518

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Definition: bnxt_hsi.h:8782

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Definition: bnxt_hsi.h:2849

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Definition: bnxt_hsi.h:4973

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Definition: bnxt_hsi.h:8904

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Definition: bnxt_hsi.h:10247

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Definition: bnxt_hsi.h:5623

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Definition: bnxt_hsi.h:8245

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Definition: bnxt_hsi.h:6291

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Definition: bnxt_hsi.h:10012

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Definition: bnxt_hsi.h:1682

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Definition: bnxt_hsi.h:7767

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Definition: bnxt_hsi.h:3674

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Definition: bnxt_hsi.h:10072

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Definition: bnxt_hsi.h:8141

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Definition: bnxt_hsi.h:9549

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Definition: bnxt_hsi.h:9762

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Definition: bnxt_hsi.h:5947

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Definition: bnxt_hsi.h:8121

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Definition: bnxt_hsi.h:6573

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Definition: bnxt_hsi.h:1097

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Definition: bnxt_hsi.h:7617

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Definition: bnxt_hsi.h:1677

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Definition: bnxt_hsi.h:6313

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Definition: bnxt_hsi.h:10010

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Definition: bnxt_hsi.h:8088

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Definition: bnxt_hsi.h:9203

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Definition: bnxt_hsi.h:2473

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Definition: bnxt_hsi.h:9317

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Definition: bnxt_hsi.h:1650

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Definition: bnxt_hsi.h:1712

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Definition: bnxt_hsi.h:6224

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Definition: bnxt_hsi.h:10191

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Definition: bnxt_hsi.h:6304

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Definition: bnxt_hsi.h:1743

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Definition: bnxt_hsi.h:4670

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Definition: bnxt_hsi.h:9558

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Definition: bnxt_hsi.h:10441

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Definition: bnxt_hsi.h:10087

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Definition: bnxt_hsi.h:4450

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Definition: bnxt_hsi.h:10150

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Definition: bnxt_hsi.h:9397

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Definition: bnxt_hsi.h:2504

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Definition: bnxt_hsi.h:10451

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Definition: bnxt_hsi.h:9157

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Definition: bnxt_hsi.h:3617

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Definition: bnxt_hsi.h:5756

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Definition: bnxt_hsi.h:3015

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Definition: bnxt_hsi.h:2497

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Definition: bnxt_hsi.h:4164

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Definition: bnxt_hsi.h:4330

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Definition: bnxt_hsi.h:9641

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Definition: bnxt_hsi.h:7764

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Definition: bnxt_hsi.h:5006

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Definition: bnxt_hsi.h:8265

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Definition: bnxt_hsi.h:3097

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Definition: bnxt_hsi.h:2096

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Definition: bnxt_hsi.h:7653

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__le32 queue_id3_max_bw
Definition: bnxt_hsi.h:5487

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__le64 resp_addr
Definition: bnxt_hsi.h:4881

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Definition: bnxt_hsi.h:7378

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__le16 mgmt_fw_major
Definition: bnxt_hsi.h:455

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Definition: bnxt_hsi.h:8278

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7660

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Definition: bnxt_hsi.h:6791

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Definition: bnxt_hsi.h:9646

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Definition: bnxt_hsi.h:8406

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__le16 rss_ctx_idx
Definition: bnxt_hsi.h:6062

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Definition: bnxt_hsi.h:6975

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Definition: bnxt_hsi.h:81

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Definition: bnxt_hsi.h:7725

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Definition: bnxt_hsi.h:2109

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Definition: bnxt_hsi.h:6817

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Definition: bnxt_hsi.h:4910

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Definition: bnxt_hsi.h:4697

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Definition: bnxt_hsi.h:1980

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__le32 new_mirror_vnic_id
Definition: bnxt_hsi.h:6659

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Definition: bnxt_hsi.h:4475

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__le16 req_type
Definition: bnxt_hsi.h:377

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Definition: bnxt_hsi.h:4444

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Definition: bnxt_hsi.h:4084

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Definition: bnxt_hsi.h:6612

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Definition: bnxt_hsi.h:9257

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__le64 cq_handle
Definition: bnxt_hsi.h:6273

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Definition: bnxt_hsi.h:6968

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__le16 seq_id
Definition: bnxt_hsi.h:6171

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__le16 resp_len
Definition: bnxt_hsi.h:7462

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Definition: bnxt_hsi.h:6058

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Definition: bnxt_hsi.h:3678

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__le64 resp_addr
Definition: bnxt_hsi.h:9862

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Definition: bnxt_hsi.h:5894

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Definition: bnxt_hsi.h:9940

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Definition: bnxt_hsi.h:10267

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Definition: bnxt_hsi.h:7482

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Definition: bnxt_hsi.h:6598

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Definition: bnxt_hsi.h:7658

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__le16 req_type
Definition: bnxt_hsi.h:9694

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Definition: bnxt_hsi.h:1722

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__le64 cq_page_dir
Definition: bnxt_hsi.h:2438

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__le64 tx_pfc_ena_frames_pri4
Definition: bnxt_hsi.h:3833

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Definition: bnxt_hsi.h:4579

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Definition: bnxt_hsi.h:9010

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Definition: bnxt_hsi.h:8856

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Definition: bnxt_hsi.h:8052

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__le32 tqm_max_entries_per_ring
Definition: bnxt_hsi.h:2144

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Definition: bnxt_hsi.h:5160

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__le64 rx_discard_pkts
Definition: bnxt_hsi.h:1673

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Definition: bnxt_hsi.h:10119

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__le16 error_code
Definition: bnxt_hsi.h:7491

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__le64 rx_9217b_16383b_frames
Definition: bnxt_hsi.h:3860

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__le64 resp_addr
Definition: bnxt_hsi.h:6641

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Definition: bnxt_hsi.h:10513

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__le32 tqm_ring2_num_entries
Definition: bnxt_hsi.h:2812

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Definition: bnxt_hsi.h:3709

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Definition: bnxt_hsi.h:7310

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__le32 enables
Definition: bnxt_hsi.h:5820

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Definition: bnxt_hsi.h:10197

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__le16 qp_entry_size
Definition: bnxt_hsi.h:2469

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Definition: bnxt_hsi.h:887

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Definition: bnxt_hsi.h:2308

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Definition: bnxt_hsi.h:10466

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Definition: bnxt_hsi.h:6347

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10127

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Definition: bnxt_hsi.h:9747

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Definition: bnxt_hsi.h:5855

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Definition: bnxt_hsi.h:1250

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Definition: bnxt_hsi.h:1953

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__le32 timestamp
Definition: bnxt_hsi.h:1859

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__le16 timestamp_hi
Definition: bnxt_hsi.h:640

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Definition: bnxt_hsi.h:7302

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__le16 error_code
Definition: bnxt_hsi.h:2485

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__le16 entry_cnt
Definition: bnxt_hsi.h:5747

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__le16 vf_id
Definition: bnxt_hsi.h:1714

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__le64 tx_pfc_ena_frames_pri7
Definition: bnxt_hsi.h:3836

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__le16 target_id
Definition: bnxt_hsi.h:4125

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__le16 dir_attr
Definition: bnxt_hsi.h:10182

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u8 timestamp_lo
Definition: bnxt_hsi.h:1044

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__le32 host_buf_len
Definition: bnxt_hsi.h:9864

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Definition: bnxt_hsi.h:6785

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__le64 resp_addr
Definition: bnxt_hsi.h:1827

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__le32 queue_id2_max_bw
Definition: bnxt_hsi.h:5447

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Definition: bnxt_hsi.h:8211

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__le32 IANA
Definition: bnxt_hsi.h:10634

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__le32 vnic_id
Definition: bnxt_hsi.h:5791

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__le16 seq_id
Definition: bnxt_hsi.h:1215

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Definition: bnxt_hsi.h:6631

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Definition: bnxt_hsi.h:8913

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Definition: bnxt_hsi.h:6965

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Definition: bnxt_hsi.h:8855

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Definition: bnxt_hsi.h:3940

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__le16 req_type
Definition: bnxt_hsi.h:9323

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__le64 req_buf_page_addr7
Definition: bnxt_hsi.h:1934

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Definition: bnxt_hsi.h:9300

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__le64 tx_good_frames
Definition: bnxt_hsi.h:3806

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__le16 resp_len
Definition: bnxt_hsi.h:9435

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__le16 srq_entry_size
Definition: bnxt_hsi.h:2471

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Definition: bnxt_hsi.h:8452

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Definition: bnxt_hsi.h:2060

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__be16 t_ovlan_vid
Definition: bnxt_hsi.h:7707

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Definition: bnxt_hsi.h:2920

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__le16 req_type
Definition: bnxt_hsi.h:8473

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Definition: bnxt_hsi.h:5125

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Definition: bnxt_hsi.h:4626

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__le64 ntuple_filter_id
Definition: bnxt_hsi.h:7206

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__le64 resp_addr
Definition: bnxt_hsi.h:9086

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Definition: bnxt_hsi.h:6742

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__le64 hash_key_ring_group_ids
Definition: bnxt_hsi.h:9033

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Definition: bnxt_hsi.h:9021

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__le16 index_1
Definition: bnxt_hsi.h:10362

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Definition: bnxt_hsi.h:8130

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__be16 outer_vlan_tci
Definition: bnxt_hsi.h:7807

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Definition: bnxt_hsi.h:1858

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Definition: bnxt_hsi.h:10398

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__le16 first_vf_id
Definition: bnxt_hsi.h:1231

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__le16 seq_id
Definition: bnxt_hsi.h:6701

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__le16 error_code
Definition: bnxt_hsi.h:5840

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Definition: bnxt_hsi.h:9688

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__le16 req_type
Definition: bnxt_hsi.h:6718

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Definition: bnxt_hsi.h:9002

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__le16 num_rsscos_ctxs
Definition: bnxt_hsi.h:1302

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Definition: bnxt_hsi.h:1310

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Definition: bnxt_hsi.h:86

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Definition: bnxt_hsi.h:7347

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Definition: bnxt_hsi.h:8533

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__le64 rx_oor_len_frames
Definition: bnxt_hsi.h:3873

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Definition: bnxt_hsi.h:7075

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__le16 stat_entry_size
Definition: bnxt_hsi.h:2141

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__le32 max_aging_flows
Definition: bnxt_hsi.h:8107

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__le16 error_code
Definition: bnxt_hsi.h:10641

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__le16 target_id
Definition: bnxt_hsi.h:8266

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Definition: bnxt_hsi.h:8955

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Definition: bnxt_hsi.h:9815

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Definition: bnxt_hsi.h:4568

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Definition: bnxt_hsi.h:3446

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Definition: bnxt_hsi.h:2042

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Definition: bnxt_hsi.h:2671

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__le32 event_data2
Definition: bnxt_hsi.h:656

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Definition: bnxt_hsi.h:4809

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__le32 event_data1
Definition: bnxt_hsi.h:641

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__le16 hwrm_fw_patch
Definition: bnxt_hsi.h:454

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__le64 resp_addr
Definition: bnxt_hsi.h:1329

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Definition: bnxt_hsi.h:6948

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__le32 oem_data[26]
Definition: bnxt_hsi.h:10636

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Definition: bnxt_hsi.h:8262

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__le32 stat_num_entries
Definition: bnxt_hsi.h:2455

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Definition: bnxt_hsi.h:4727

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4991

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Definition: bnxt_hsi.h:10471

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__le32 l3[10]
Definition: bnxt_hsi.h:7002

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Definition: bnxt_hsi.h:5630

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__le16 target_id
Definition: bnxt_hsi.h:9287

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__le16 vnic_id
Definition: bnxt_hsi.h:5977

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__le32 flags
Definition: bnxt_hsi.h:3017

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Definition: bnxt_hsi.h:4540

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Definition: bnxt_hsi.h:9358

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Definition: bnxt_hsi.h:7057

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__le16 req_type
Definition: bnxt_hsi.h:1944

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Definition: bnxt_hsi.h:7000

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__le16 num_mcast_filters
Definition: bnxt_hsi.h:1632

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Definition: bnxt_hsi.h:1674

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Definition: bnxt_hsi.h:6121

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Definition: bnxt_hsi.h:6204

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Definition: bnxt_hsi.h:5087

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__le16 max_vfs
Definition: bnxt_hsi.h:2034

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Definition: bnxt_hsi.h:7043

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__le16 rx_ts_capture_ptp_msg_type
Definition: bnxt_hsi.h:3730

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Definition: bnxt_hsi.h:1030

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__le64 byte_0
Definition: bnxt_hsi.h:7987

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__le16 max_tx_scheduler_inputs
Definition: bnxt_hsi.h:2057

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__le16 target_id
Definition: bnxt_hsi.h:21

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Definition: bnxt_hsi.h:9418

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Definition: bnxt_hsi.h:5778

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Definition: bnxt_hsi.h:9113

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Definition: bnxt_hsi.h:9008

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Definition: bnxt_hsi.h:3212

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__le16 target_id
Definition: bnxt_hsi.h:7633

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__le16 req_type
Definition: bnxt_hsi.h:5709

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__le16 fec_cfg
Definition: bnxt_hsi.h:3518

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Definition: bnxt_hsi.h:9860

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Definition: bnxt_hsi.h:8114

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Definition: bnxt_hsi.h:8733

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Definition: bnxt_hsi.h:9070

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__le64 ext_flow_handle
Definition: bnxt_hsi.h:8010

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__le32 rsvd1
Definition: bnxt_hsi.h:2880

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__le16 flow_handle_0
Definition: bnxt_hsi.h:7948

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__le64 req_buf_page_addr1
Definition: bnxt_hsi.h:1928

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__le32 reset_inprogress_reg
Definition: bnxt_hsi.h:1782

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__le16 dir_ext
Definition: bnxt_hsi.h:10029

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__le16 qp_num_l2_entries
Definition: bnxt_hsi.h:2800

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__le16 req_len_type
Definition: bnxt_hsi.h:515

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Definition: bnxt_hsi.h:80

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Definition: bnxt_hsi.h:4938

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Definition: bnxt_hsi.h:5758

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__le16 auto_link_speeds2
Definition: bnxt_hsi.h:3594

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__le64 pfc_pri3_rx_duration_us
Definition: bnxt_hsi.h:4008

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__le32 event_data2
Definition: bnxt_hsi.h:9175

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__le64 host_src_addr
Definition: bnxt_hsi.h:10068

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__le16 req_type
Definition: bnxt_hsi.h:6093

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__le64 tx_packets_cos2
Definition: bnxt_hsi.h:3955

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__le16 jumbo_thresh
Definition: bnxt_hsi.h:6151

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Definition: bnxt_hsi.h:8880

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__le16 req_type
Definition: bnxt_hsi.h:1883

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__le64 src_data_addr
Definition: bnxt_hsi.h:10404

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Definition: bnxt_hsi.h:8753

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__le16 req_type
Definition: bnxt_hsi.h:9526

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__le16 link_partner_adv_eee_link_speed_mask
Definition: bnxt_hsi.h:3499

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__le16 target_id
Definition: bnxt_hsi.h:9445

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Definition: bnxt_hsi.h:1952

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Definition: bnxt_hsi.h:10624

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Definition: bnxt_hsi.h:6960

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Definition: bnxt_hsi.h:8467

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__le16 req_type
Definition: bnxt_hsi.h:7598

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__le64 resp_addr
Definition: bnxt_hsi.h:10225

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u8 default_pri
Definition: bnxt_hsi.h:5746

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__le32 event_data2
Definition: bnxt_hsi.h:776

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Definition: bnxt_hsi.h:8006

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__le64 rx_pfc_xon2xoff_frames_pri1
Definition: bnxt_hsi.h:3886

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__le16 max_agg_segs
Definition: bnxt_hsi.h:5996

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__le64 tqm_ring0_page_dir
Definition: bnxt_hsi.h:2789

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__le16 seq_id
Definition: bnxt_hsi.h:4849

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Definition: bnxt_hsi.h:2030

input
Definition: bnxt_hsi.h:68

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Definition: bnxt_hsi.h:8465

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Definition: bnxt_hsi.h:9261

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__le16 target_id
Definition: bnxt_hsi.h:4279

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Definition: bnxt_hsi.h:5715

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Definition: bnxt_hsi.h:9706

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__le64 rx_stat_err
Definition: bnxt_hsi.h:3915

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__le16 resp_len
Definition: bnxt_hsi.h:9993

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__le16 req_type
Definition: bnxt_hsi.h:7755

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__le16 ring_id
Definition: bnxt_hsi.h:6332

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__le16 seq_id
Definition: bnxt_hsi.h:9365

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Definition: bnxt_hsi.h:8772

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__le16 req_type
Definition: bnxt_hsi.h:8048

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Definition: bnxt_hsi.h:1019

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Definition: bnxt_hsi.h:9409

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Definition: bnxt_hsi.h:8863

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__le32 flow_id_4
Definition: bnxt_hsi.h:7963

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Definition: bnxt_hsi.h:4815

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Definition: bnxt_hsi.h:5684

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__le16 cmpl_ring
Definition: bnxt_hsi.h:2859

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Definition: bnxt_hsi.h:2751

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__le64 resp_addr
Definition: bnxt_hsi.h:4948

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Definition: bnxt_hsi.h:6510

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Definition: bnxt_hsi.h:1733

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Definition: bnxt_hsi.h:4036

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Definition: bnxt_hsi.h:9081

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__le16 req_type
Definition: bnxt_hsi.h:10088

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__le16 req_type
Definition: bnxt_hsi.h:5776

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Definition: bnxt_hsi.h:9071

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u8 roce_fw_min_8b
Definition: bnxt_hsi.h:422

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__le16 error_code
Definition: bnxt_hsi.h:5775

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8193

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Definition: bnxt_hsi.h:3011

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__le16 error_code
Definition: bnxt_hsi.h:10156

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Definition: bnxt_hsi.h:6555

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Definition: bnxt_hsi.h:10383

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Definition: bnxt_hsi.h:4285

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Definition: bnxt_hsi.h:9631

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Definition: bnxt_hsi.h:973

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__le16 dir_ext
Definition: bnxt_hsi.h:10205

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__le16 hds_threshold
Definition: bnxt_hsi.h:6112

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__le16 target_id
Definition: bnxt_hsi.h:9230

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__le16 seq_id
Definition: bnxt_hsi.h:7188

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__le16 meter_profile_id
Definition: bnxt_hsi.h:7463

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__le16 req_buf_page_size
Definition: bnxt_hsi.h:1915

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__le16 resp_len
Definition: bnxt_hsi.h:10644

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4151

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__le16 resp_len
Definition: bnxt_hsi.h:9347

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__le32 rx_ts_reg_off_domain_id
Definition: bnxt_hsi.h:3780

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__le16 num_cmpl_dma_aggr_during_int_min
Definition: bnxt_hsi.h:6375

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u8 pri5_to_tc_map
Definition: bnxt_hsi.h:8875

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7077

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__le16 error_code
Definition: bnxt_hsi.h:8047

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Definition: bnxt_hsi.h:7070

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4945

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__le16 resp_len
Definition: bnxt_hsi.h:10044

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Definition: bnxt_hsi.h:4943

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__le16 error_code
Definition: bnxt_hsi.h:9181

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Definition: bnxt_hsi.h:1331

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__le16 srq_max_l2_entries
Definition: bnxt_hsi.h:2131

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__le16 error_code
Definition: bnxt_hsi.h:3244

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__le16 vnic_entry_size
Definition: bnxt_hsi.h:2139

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__le16 adv_eee_link_speed_mask
Definition: bnxt_hsi.h:3491

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__le32 qp_max_entries
Definition: bnxt_hsi.h:2127

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__le16 timestamp_hi
Definition: bnxt_hsi.h:662

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__le64 resp_addr
Definition: bnxt_hsi.h:9052

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__le16 link_partner_adv_speeds
Definition: bnxt_hsi.h:3466

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Definition: bnxt_hsi.h:635

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__le32 queue_id1_min_bw
Definition: bnxt_hsi.h:5391

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Definition: bnxt_hsi.h:2836

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__le64 resp_addr
Definition: bnxt_hsi.h:8029

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Definition: bnxt_hsi.h:4667

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__le16 min_hw_ring_grps
Definition: bnxt_hsi.h:2087

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__le16 req_type
Definition: bnxt_hsi.h:4459

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__le32 tqm_sp_num_entries
Definition: bnxt_hsi.h:2456

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__le16 req_type
Definition: bnxt_hsi.h:1325

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__le64 pattern_mask_addr
Definition: bnxt_hsi.h:9453

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__le64 commands
Definition: bnxt_hsi.h:8625

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__le16 seq_id
Definition: bnxt_hsi.h:7376

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__le32 nq_params
Definition: bnxt_hsi.h:6371

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__le16 link_speed
Definition: bnxt_hsi.h:3270

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Definition: bnxt_hsi.h:8358

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Definition: bnxt_hsi.h:5730

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__le16 resp_len
Definition: bnxt_hsi.h:6757

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__le16 resp_len
Definition: bnxt_hsi.h:8174

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__le16 cq_max_l2_entries
Definition: bnxt_hsi.h:2134

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__le16 seq_id
Definition: bnxt_hsi.h:4779

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__le64 resp_addr
Definition: bnxt_hsi.h:5924

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__le32 cmpl_params
Definition: bnxt_hsi.h:6361

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Definition: bnxt_hsi.h:7473

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u8 queue_id4_tsa_assign
Definition: bnxt_hsi.h:5200

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__le64 resp_addr
Definition: bnxt_hsi.h:10571

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Definition: bnxt_hsi.h:997

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u8 tc1_to_tsa_map
Definition: bnxt_hsi.h:8892

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Definition: bnxt_hsi.h:8727

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__le64 resp_addr
Definition: bnxt_hsi.h:4994

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Definition: bnxt_hsi.h:885

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Definition: bnxt_hsi.h:5423

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__le16 req_type
Definition: bnxt_hsi.h:4689

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Definition: bnxt_hsi.h:2844

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__le16 seq_id
Definition: bnxt_hsi.h:9649

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__le64 tx_ucast_pkts
Definition: bnxt_hsi.h:8580

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Definition: bnxt_hsi.h:9933

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Definition: bnxt_hsi.h:10058

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Definition: bnxt_hsi.h:9310

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Definition: bnxt_hsi.h:8638

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Definition: bnxt_hsi.h:9452

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Definition: bnxt_hsi.h:1264

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Definition: bnxt_hsi.h:9883

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Definition: bnxt_hsi.h:6382

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Definition: bnxt_hsi.h:7079

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Definition: bnxt_hsi.h:2916

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Definition: bnxt_hsi.h:3900

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Definition: bnxt_hsi.h:8471

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__le16 fid
Definition: bnxt_hsi.h:1652

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Definition: bnxt_hsi.h:6048

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Definition: bnxt_hsi.h:9985

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Definition: bnxt_hsi.h:9176

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__le32 tqm_ring4_num_entries
Definition: bnxt_hsi.h:2814

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Definition: bnxt_hsi.h:4981

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Definition: bnxt_hsi.h:3854

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Definition: bnxt_hsi.h:3786

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__le64 tx_packets_cos5
Definition: bnxt_hsi.h:3958

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Definition: bnxt_hsi.h:2091

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Definition: bnxt_hsi.h:1203

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Definition: bnxt_hsi.h:7899

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__le32 reserved_size
Definition: bnxt_hsi.h:10164

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__le16 tx_stat_size
Definition: bnxt_hsi.h:4028

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Definition: bnxt_hsi.h:10618

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Definition: bnxt_hsi.h:5905

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Definition: bnxt_hsi.h:6455

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__le16 src_fid
Definition: bnxt_hsi.h:6928

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Definition: bnxt_hsi.h:2887

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Definition: bnxt_hsi.h:8156

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Definition: bnxt_hsi.h:10424

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__le64 tx_xthol_frames
Definition: bnxt_hsi.h:3843

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Definition: bnxt_hsi.h:1262

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Definition: bnxt_hsi.h:8698

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Definition: bnxt_hsi.h:7703

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__le16 seq_id
Definition: bnxt_hsi.h:1406

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Definition: bnxt_hsi.h:5127

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Definition: bnxt_hsi.h:1961

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__le64 host_src_addr
Definition: bnxt_hsi.h:10026

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__le16 req_type
Definition: bnxt_hsi.h:8453

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Definition: bnxt_hsi.h:8162

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__le16 event_id
Definition: bnxt_hsi.h:689

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__le16 rx_cfa_code_a
Definition: bnxt_hsi.h:8288

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__le16 reserved_tx_rings
Definition: bnxt_hsi.h:2102

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__le32 data[16]
Definition: bnxt_hsi.h:4291

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__be32 ip_dst[4]
Definition: bnxt_hsi.h:7813

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__le16 data_len
Definition: bnxt_hsi.h:9749

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Definition: bnxt_hsi.h:8095

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__le16 req_type
Definition: bnxt_hsi.h:6311

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__le64 resp_addr
Definition: bnxt_hsi.h:10446

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__le16 default_rx_ring_id
Definition: bnxt_hsi.h:5834

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__le16 seq_id
Definition: bnxt_hsi.h:4308

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__le16 l2_ovlan
Definition: bnxt_hsi.h:6549

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u8 pri1_cos_queue_id
Definition: bnxt_hsi.h:4968

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__le16 req_type
Definition: bnxt_hsi.h:391

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__le16 seq_id
Definition: bnxt_hsi.h:7871

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__le16 resp_len
Definition: bnxt_hsi.h:10159

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Definition: bnxt_hsi.h:10132

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__le16 req_type
Definition: bnxt_hsi.h:6339

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Definition: bnxt_hsi.h:4972

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Definition: bnxt_hsi.h:5669

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__le16 target_id
Definition: bnxt_hsi.h:7860

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Definition: bnxt_hsi.h:759

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Definition: bnxt_hsi.h:10141

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Definition: bnxt_hsi.h:4511

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Definition: bnxt_hsi.h:10388

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u8 pri1_to_tc_map
Definition: bnxt_hsi.h:8871

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__le16 error_code
Definition: bnxt_hsi.h:10137

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Definition: bnxt_hsi.h:830

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Definition: bnxt_hsi.h:7216

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u8 ip_src_mask_len
Definition: bnxt_hsi.h:7812

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4574

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__le16 max_ext_req_len
Definition: bnxt_hsi.h:467

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__le32 event_data1
Definition: bnxt_hsi.h:761

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Definition: bnxt_hsi.h:4448

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__le16 t_l2_ivlan
Definition: bnxt_hsi.h:6559

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__le16 seq_id
Definition: bnxt_hsi.h:6312

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__le32 flags
Definition: bnxt_hsi.h:4782

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__le16 pattern_mask_size
Definition: bnxt_hsi.h:9475

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__le16 vf_id
Definition: bnxt_hsi.h:1913

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Definition: bnxt_hsi.h:4644

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Definition: bnxt_hsi.h:1055

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Definition: bnxt_hsi.h:425

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__le16 req_type
Definition: bnxt_hsi.h:6923

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__le16 length
Definition: bnxt_hsi.h:64

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__le16 hds_offset
Definition: bnxt_hsi.h:6111

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Definition: bnxt_hsi.h:6611

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__le16 resp_len
Definition: bnxt_hsi.h:8620

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Definition: bnxt_hsi.h:7065

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__le16 seq_id
Definition: bnxt_hsi.h:1955

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Definition: bnxt_hsi.h:2503

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__le16 target_id
Definition: bnxt_hsi.h:10303

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__le16 support_speeds
Definition: bnxt_hsi.h:3292

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__le16 num_l2_ctxs
Definition: bnxt_hsi.h:1566

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__le64 resp_addr
Definition: bnxt_hsi.h:3924

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__le16 reserved_stat_ctx
Definition: bnxt_hsi.h:2106

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Definition: bnxt_hsi.h:4853

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Definition: bnxt_hsi.h:8303

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Definition: bnxt_hsi.h:7856

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__le16 port_id
Definition: bnxt_hsi.h:4852

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__le16 num_vfs
Definition: bnxt_hsi.h:2969

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Definition: bnxt_hsi.h:402

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__le32 enables
Definition: bnxt_hsi.h:5934

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Definition: bnxt_hsi.h:10542

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Definition: bnxt_hsi.h:3488

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__le32 stat_ctx_id
Definition: bnxt_hsi.h:6248

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__le32 stat_ctx_id
Definition: bnxt_hsi.h:8548

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__le16 resp_len
Definition: bnxt_hsi.h:7620

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Definition: bnxt_hsi.h:8322

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__le64 rx_bytes_cos1
Definition: bnxt_hsi.h:3987

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__le16 seq_id
Definition: bnxt_hsi.h:8361

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__le16 l2_ctxt_id
Definition: bnxt_hsi.h:7907

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Definition: bnxt_hsi.h:8781

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Definition: bnxt_hsi.h:3041

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Definition: bnxt_hsi.h:1228

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Definition: bnxt_hsi.h:10241

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Definition: bnxt_hsi.h:10527

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Definition: bnxt_hsi.h:1817

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Definition: bnxt_hsi.h:10129

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Definition: bnxt_hsi.h:4165

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__le64 tx_pause_frames
Definition: bnxt_hsi.h:3811

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__le16 vnic_num_vnic_entries
Definition: bnxt_hsi.h:2806

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Definition: bnxt_hsi.h:10001

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__le64 rx_ucast_bytes
Definition: bnxt_hsi.h:8593

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Definition: bnxt_hsi.h:4934

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Definition: bnxt_hsi.h:8214

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Definition: bnxt_hsi.h:5583

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__le16 meter_profile_id
Definition: bnxt_hsi.h:7483

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Definition: bnxt_hsi.h:9308

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Definition: bnxt_hsi.h:2180

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__le32 min_agg_len
Definition: bnxt_hsi.h:5957

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Definition: bnxt_hsi.h:9159

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Definition: bnxt_hsi.h:3620

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Definition: bnxt_hsi.h:9343

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Definition: bnxt_hsi.h:4424

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Definition: bnxt_hsi.h:2873

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__le16 error_code
Definition: bnxt_hsi.h:6664

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__le16 mtu
Definition: bnxt_hsi.h:3684

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Definition: bnxt_hsi.h:2033

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Definition: bnxt_hsi.h:10512

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9912

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Definition: bnxt_hsi.h:6893

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Definition: bnxt_hsi.h:8027

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Definition: bnxt_hsi.h:2276

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Definition: bnxt_hsi.h:9326

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__le16 seq_id
Definition: bnxt_hsi.h:6676

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Definition: bnxt_hsi.h:9228

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Definition: bnxt_hsi.h:9697

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Definition: bnxt_hsi.h:4947

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__le64 tx_drop_pkts
Definition: bnxt_hsi.h:8584

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__le16 seq_id
Definition: bnxt_hsi.h:7198

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__le64 eng_bytes_out
Definition: bnxt_hsi.h:8622

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Definition: bnxt_hsi.h:6229

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Definition: bnxt_hsi.h:8002

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__le64 rx_llfc_msgs_with_crc_err
Definition: bnxt_hsi.h:3908

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Definition: bnxt_hsi.h:5005

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__le32 qp_num_entries
Definition: bnxt_hsi.h:2452

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__le32 max_encap_records
Definition: bnxt_hsi.h:1377

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__le64 rx_pause_frames
Definition: bnxt_hsi.h:3867

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__le16 error_code
Definition: bnxt_hsi.h:9322

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Definition: bnxt_hsi.h:6754

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Definition: bnxt_hsi.h:8115

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Definition: bnxt_hsi.h:9602

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Definition: bnxt_hsi.h:404

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Definition: bnxt_hsi.h:8722

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__le32 flow_id_2
Definition: bnxt_hsi.h:7961

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Definition: bnxt_hsi.h:877

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__le16 target_id
Definition: bnxt_hsi.h:8117

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Definition: bnxt_hsi.h:4155

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Definition: bnxt_hsi.h:6222

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__le16 error_code
Definition: bnxt_hsi.h:4858

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__le16 resp_len
Definition: bnxt_hsi.h:6194

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Definition: bnxt_hsi.h:6046

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__le16 target_id
Definition: bnxt_hsi.h:9983

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Definition: bnxt_hsi.h:5675

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__le16 seq_id
Definition: bnxt_hsi.h:10090

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Definition: bnxt_hsi.h:1906

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Definition: bnxt_hsi.h:1740

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Definition: bnxt_hsi.h:9015

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__le16 num_cmpl_dma_aggr
Definition: bnxt_hsi.h:6412

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Definition: bnxt_hsi.h:7025

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Definition: bnxt_hsi.h:4627

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Definition: bnxt_hsi.h:9301

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Definition: bnxt_hsi.h:6357

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__le16 led2_blink_on
Definition: bnxt_hsi.h:4422

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Definition: bnxt_hsi.h:3109

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Definition: bnxt_hsi.h:8149

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Definition: bnxt_hsi.h:9542

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Definition: bnxt_hsi.h:10445

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Definition: bnxt_hsi.h:3082

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Definition: bnxt_hsi.h:7332

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Definition: bnxt_hsi.h:601

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Definition: bnxt_hsi.h:10645

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Definition: bnxt_hsi.h:2388

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Definition: bnxt_hsi.h:9539

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Definition: bnxt_hsi.h:2149

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Definition: bnxt_hsi.h:6050

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Definition: bnxt_hsi.h:3644

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Definition: bnxt_hsi.h:7461

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Definition: bnxt_hsi.h:10035

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Definition: bnxt_hsi.h:9887

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Definition: bnxt_hsi.h:5383

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Definition: bnxt_hsi.h:5080

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Definition: bnxt_hsi.h:9900

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Definition: bnxt_hsi.h:8192

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Definition: bnxt_hsi.h:7936

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Definition: bnxt_hsi.h:7624

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Definition: bnxt_hsi.h:6096

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Definition: bnxt_hsi.h:717

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Definition: bnxt_hsi.h:6638

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Definition: bnxt_hsi.h:1515

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Definition: bnxt_hsi.h:6310

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Definition: bnxt_hsi.h:5790

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Definition: bnxt_hsi.h:10291

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Definition: bnxt_hsi.h:1981

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Definition: bnxt_hsi.h:3901

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Definition: bnxt_hsi.h:2964

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Definition: bnxt_hsi.h:10381

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Definition: bnxt_hsi.h:10139

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Definition: bnxt_hsi.h:9003

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Definition: bnxt_hsi.h:3975

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Definition: bnxt_hsi.h:9586

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Definition: bnxt_hsi.h:6666

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__le32 dst_vnic_id
Definition: bnxt_hsi.h:6811

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Definition: bnxt_hsi.h:2099

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Definition: bnxt_hsi.h:4970

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Definition: bnxt_hsi.h:7315

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Definition: bnxt_hsi.h:1317

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Definition: bnxt_hsi.h:9513

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Definition: bnxt_hsi.h:5739

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Definition: bnxt_hsi.h:8271

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Definition: bnxt_hsi.h:10062

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__le16 encap_resp_target_id
Definition: bnxt_hsi.h:9311

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Definition: bnxt_hsi.h:5468

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Definition: bnxt_hsi.h:9231

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Definition: bnxt_hsi.h:6315

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Definition: bnxt_hsi.h:2978

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Definition: bnxt_hsi.h:2484

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Definition: bnxt_hsi.h:8319

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Definition: bnxt_hsi.h:4645

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Definition: bnxt_hsi.h:9863

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Definition: bnxt_hsi.h:6929

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Definition: bnxt_hsi.h:4577

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Definition: bnxt_hsi.h:3679

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Definition: bnxt_hsi.h:6693

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Definition: bnxt_hsi.h:5857

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Definition: bnxt_hsi.h:8896

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Definition: bnxt_hsi.h:6458

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Definition: bnxt_hsi.h:6283

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Definition: bnxt_hsi.h:5774

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__le16 vf_id
Definition: bnxt_hsi.h:2902

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Definition: bnxt_hsi.h:10349

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Definition: bnxt_hsi.h:7927

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Definition: bnxt_hsi.h:7293

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Definition: bnxt_hsi.h:6917

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Definition: bnxt_hsi.h:6063

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Definition: bnxt_hsi.h:8291

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__le16 hwrm_fw_minor
Definition: bnxt_hsi.h:452

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Definition: bnxt_hsi.h:8253

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Definition: bnxt_hsi.h:10447

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Definition: bnxt_hsi.h:4163

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Definition: bnxt_hsi.h:4718

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Definition: bnxt_hsi.h:9828

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Definition: bnxt_hsi.h:6882

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__le64 pfc_pri1_rx_transitions
Definition: bnxt_hsi.h:4005

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Definition: bnxt_hsi.h:8131

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Definition: bnxt_hsi.h:8318

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__le16 force_link_speed
Definition: bnxt_hsi.h:3308

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__le64 tqm_ring5_page_dir
Definition: bnxt_hsi.h:2794

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Definition: bnxt_hsi.h:8569

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Definition: bnxt_hsi.h:9745

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Definition: bnxt_hsi.h:8879

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Definition: bnxt_hsi.h:3154

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Definition: bnxt_hsi.h:409

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Definition: bnxt_hsi.h:7882

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Definition: bnxt_hsi.h:10136

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__le16 resp_len
Definition: bnxt_hsi.h:4473

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Definition: bnxt_hsi.h:8546

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Definition: bnxt_hsi.h:3711

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__le16 error_code
Definition: bnxt_hsi.h:6949

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Definition: bnxt_hsi.h:8456

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Definition: bnxt_hsi.h:8062

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Definition: bnxt_hsi.h:8316

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Definition: bnxt_hsi.h:6889

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Definition: bnxt_hsi.h:10514

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__le32 tcp_flow_timer
Definition: bnxt_hsi.h:8040

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__le32 tqm_ring3_num_entries
Definition: bnxt_hsi.h:2460

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Definition: bnxt_hsi.h:581

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Definition: bnxt_hsi.h:9981

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Definition: bnxt_hsi.h:4930

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Definition: bnxt_hsi.h:1967

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Definition: bnxt_hsi.h:859

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Definition: bnxt_hsi.h:797

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__le64 pcie_rx_traffic_rate
Definition: bnxt_hsi.h:8684

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Definition: bnxt_hsi.h:7038

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Definition: bnxt_hsi.h:5046

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Definition: bnxt_hsi.h:10311

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Definition: bnxt_hsi.h:2837

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Definition: bnxt_hsi.h:663

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Definition: bnxt_hsi.h:10322

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6766

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__le64 tcam_info
Definition: bnxt_hsi.h:7909

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Definition: bnxt_hsi.h:5677

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Definition: bnxt_hsi.h:2150

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__le16 mru
Definition: bnxt_hsi.h:3683

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Definition: bnxt_hsi.h:8009

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Definition: bnxt_hsi.h:9348

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__le32 tqm_ring1_num_entries
Definition: bnxt_hsi.h:2811

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Definition: bnxt_hsi.h:701

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Definition: bnxt_hsi.h:7178

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Definition: bnxt_hsi.h:10460

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Definition: bnxt_hsi.h:8543

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Definition: bnxt_hsi.h:4027

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__le16 t_l2_ivlan_mask
Definition: bnxt_hsi.h:6560

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Definition: bnxt_hsi.h:9471

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Definition: bnxt_hsi.h:7496

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__le64 rx_eee_lpi_events
Definition: bnxt_hsi.h:3904

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Definition: bnxt_hsi.h:4408

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Definition: bnxt_hsi.h:9999

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__le64 resp_addr
Definition: bnxt_hsi.h:3759

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Definition: bnxt_hsi.h:1968

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Definition: bnxt_hsi.h:6118

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Definition: bnxt_hsi.h:5550

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__le16 req_type
Definition: bnxt_hsi.h:8350

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__le16 hds_offset
Definition: bnxt_hsi.h:6152

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Definition: bnxt_hsi.h:1708

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Definition: bnxt_hsi.h:7054

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__le16 next_offset
Definition: bnxt_hsi.h:8857

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Definition: bnxt_hsi.h:7806

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Definition: bnxt_hsi.h:329

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__le64 tx_bytes_cos6
Definition: bnxt_hsi.h:3951

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__le32 bkup_power_status
Definition: bnxt_hsi.h:9042

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Definition: bnxt_hsi.h:8005

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Definition: bnxt_hsi.h:10326

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__le16 req_type
Definition: bnxt_hsi.h:1510

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Definition: bnxt_hsi.h:850

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__le64 rx_wrong_sa_frames
Definition: bnxt_hsi.h:3871

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Definition: bnxt_hsi.h:2968

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Definition: bnxt_hsi.h:8864

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__le16 rx_cfa_code_a
Definition: bnxt_hsi.h:8233

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Definition: bnxt_hsi.h:7158

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Definition: bnxt_hsi.h:7166

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__le16 eee_link_speed_mask
Definition: bnxt_hsi.h:3159

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__le16 req_type
Definition: bnxt_hsi.h:4038

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__le16 resp_len
Definition: bnxt_hsi.h:2507

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Definition: bnxt_hsi.h:609

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Definition: bnxt_hsi.h:6772

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Definition: bnxt_hsi.h:5964

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Definition: bnxt_hsi.h:5548

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Definition: bnxt_hsi.h:3217

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__le16 req_type
Definition: bnxt_hsi.h:7196

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Definition: bnxt_hsi.h:988

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Definition: bnxt_hsi.h:4926

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Definition: bnxt_hsi.h:10285

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__le16 encap_async_event_target_id
Definition: bnxt_hsi.h:9337

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__le16 led2_color_caps
Definition: bnxt_hsi.h:4640

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__le16 pci_id
Definition: bnxt_hsi.h:1207

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__le16 led1_blink_off
Definition: bnxt_hsi.h:4404

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__le64 rx_pfc_ena_frames_pri0
Definition: bnxt_hsi.h:3893

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Definition: bnxt_hsi.h:6061

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Definition: bnxt_hsi.h:10421

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Definition: bnxt_hsi.h:7323

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__le64 tx_mcast_bytes
Definition: bnxt_hsi.h:8586

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Definition: bnxt_hsi.h:2065

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__le32 queue_id4_max_bw
Definition: bnxt_hsi.h:5527

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Definition: bnxt_hsi.h:9387

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Definition: bnxt_hsi.h:1131

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__le64 resp_addr
Definition: bnxt_hsi.h:6927

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Definition: bnxt_hsi.h:8567

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__le16 num_cmpl_dma_aggr_min
Definition: bnxt_hsi.h:6373

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__le32 valid_tx_lpi_timer_high
Definition: bnxt_hsi.h:4220

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Definition: bnxt_hsi.h:8657

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Definition: bnxt_hsi.h:1732

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Definition: bnxt_hsi.h:9763

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__le64 tpa_bytes
Definition: bnxt_hsi.h:8499

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Definition: bnxt_hsi.h:6843

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Definition: bnxt_hsi.h:90

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Definition: bnxt_hsi.h:6966

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Definition: bnxt_hsi.h:9501

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Definition: bnxt_hsi.h:9083

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Definition: bnxt_hsi.h:4598

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Definition: bnxt_hsi.h:3852

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Definition: bnxt_hsi.h:8560

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Definition: bnxt_hsi.h:8151

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Definition: bnxt_hsi.h:8365

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Definition: bnxt_hsi.h:9731

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Definition: bnxt_hsi.h:4851

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Definition: bnxt_hsi.h:9089

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Definition: bnxt_hsi.h:2799

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Definition: bnxt_hsi.h:2767

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Definition: bnxt_hsi.h:1036

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Definition: bnxt_hsi.h:8743

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Definition: bnxt_hsi.h:1087

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Definition: bnxt_hsi.h:7227

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Definition: bnxt_hsi.h:10351

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Definition: bnxt_hsi.h:5798

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Definition: bnxt_hsi.h:1192

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Definition: bnxt_hsi.h:1988

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Definition: bnxt_hsi.h:10437

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Definition: bnxt_hsi.h:6503

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Definition: bnxt_hsi.h:1255

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Definition: bnxt_hsi.h:6725

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Definition: bnxt_hsi.h:5685

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Definition: bnxt_hsi.h:7845

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Definition: bnxt_hsi.h:10063

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Definition: bnxt_hsi.h:10036

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Definition: bnxt_hsi.h:3758

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Definition: bnxt_hsi.h:3026

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Definition: bnxt_hsi.h:8492

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Definition: bnxt_hsi.h:19

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Definition: bnxt_hsi.h:10483

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Definition: bnxt_hsi.h:8535

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Definition: bnxt_hsi.h:7588

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Definition: bnxt_hsi.h:7023

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Definition: bnxt_hsi.h:1874

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Definition: bnxt_hsi.h:6994

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Definition: bnxt_hsi.h:3234

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Definition: bnxt_hsi.h:9853

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Definition: bnxt_hsi.h:7861

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Definition: bnxt_hsi.h:9039

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Definition: bnxt_hsi.h:3774

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Definition: bnxt_hsi.h:8992

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Definition: bnxt_hsi.h:2145

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Definition: bnxt_hsi.h:9782

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Definition: bnxt_hsi.h:8598

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Definition: bnxt_hsi.h:10215

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Definition: bnxt_hsi.h:8487

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Definition: bnxt_hsi.h:10378

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Definition: bnxt_hsi.h:9550

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Definition: bnxt_hsi.h:2977

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__le32 fw_heartbeat_reg
Definition: bnxt_hsi.h:1762

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Definition: bnxt_hsi.h:8854

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__le64 tx_llfc_logical_msgs
Definition: bnxt_hsi.h:3839

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Definition: bnxt_hsi.h:54

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Definition: bnxt_hsi.h:9943

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__le64 rx_pfc_ena_frames_pri6
Definition: bnxt_hsi.h:3899

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Definition: bnxt_hsi.h:8570

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Definition: bnxt_hsi.h:1877

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__le64 tx_pfc_ena_frames_pri2
Definition: bnxt_hsi.h:3831

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__le16 min_rsscos_ctx
Definition: bnxt_hsi.h:2041

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__le16 max_vnics
Definition: bnxt_hsi.h:2084

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Definition: bnxt_hsi.h:1513

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Definition: bnxt_hsi.h:6059

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__le32 udp_flow_timer
Definition: bnxt_hsi.h:8042

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Definition: bnxt_hsi.h:6182

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Definition: bnxt_hsi.h:1368

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Definition: bnxt_hsi.h:3114

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Definition: bnxt_hsi.h:9111

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Definition: bnxt_hsi.h:8229

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Definition: bnxt_hsi.h:8565

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Definition: bnxt_hsi.h:886

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Definition: bnxt_hsi.h:4918

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Definition: bnxt_hsi.h:924

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Definition: bnxt_hsi.h:9925

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Definition: bnxt_hsi.h:1744

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Definition: bnxt_hsi.h:8585

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Definition: bnxt_hsi.h:8255

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Definition: bnxt_hsi.h:1407

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Definition: bnxt_hsi.h:6466

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Definition: bnxt_hsi.h:8777

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Definition: bnxt_hsi.h:4094

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Definition: bnxt_hsi.h:456

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Definition: bnxt_hsi.h:7989

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Definition: bnxt_hsi.h:10025

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Definition: bnxt_hsi.h:7733

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Definition: bnxt_hsi.h:8289

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Definition: bnxt_hsi.h:6349

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Definition: bnxt_hsi.h:5828

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Definition: bnxt_hsi.h:2132

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Definition: bnxt_hsi.h:6667

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Definition: bnxt_hsi.h:1144

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Definition: bnxt_hsi.h:5866

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Definition: bnxt_hsi.h:4898

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Definition: bnxt_hsi.h:2790

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Definition: bnxt_hsi.h:7818

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Definition: bnxt_hsi.h:2074

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Definition: bnxt_hsi.h:8898

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Definition: bnxt_hsi.h:8498

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Definition: bnxt_hsi.h:751

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__le64 pfc_pri1_tx_duration_us
Definition: bnxt_hsi.h:3963

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Definition: bnxt_hsi.h:1884

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Definition: bnxt_hsi.h:2129

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Definition: bnxt_hsi.h:5983

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Definition: bnxt_hsi.h:10318

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Definition: bnxt_hsi.h:10048

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Definition: bnxt_hsi.h:5780

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__le32 event_data1
Definition: bnxt_hsi.h:587

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Definition: bnxt_hsi.h:8905

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Definition: bnxt_hsi.h:6342

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Definition: bnxt_hsi.h:7942

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Definition: bnxt_hsi.h:6689

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Definition: bnxt_hsi.h:10623

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Definition: bnxt_hsi.h:8348

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__le16 req_type
Definition: bnxt_hsi.h:5850

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Definition: bnxt_hsi.h:6694

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Definition: bnxt_hsi.h:8372

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__le16 reserved_vnics
Definition: bnxt_hsi.h:2105

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Definition: bnxt_hsi.h:9708

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__le64 tqm_ring0_page_dir
Definition: bnxt_hsi.h:2442

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__le16 req_type
Definition: bnxt_hsi.h:10042

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__le16 mru
Definition: bnxt_hsi.h:5903

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Definition: bnxt_hsi.h:9593

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Definition: bnxt_hsi.h:4861

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Definition: bnxt_hsi.h:4075

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Definition: bnxt_hsi.h:6756

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Definition: bnxt_hsi.h:432

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8360

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Definition: bnxt_hsi.h:6759

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Definition: bnxt_hsi.h:8993

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__le64 tx_frag_frames
Definition: bnxt_hsi.h:3823

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__le16 unused[3]
Definition: bnxt_hsi.h:2983

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Definition: bnxt_hsi.h:3104

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Definition: bnxt_hsi.h:10400

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Definition: bnxt_hsi.h:4694

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__le16 netctrl_fw_patch
Definition: bnxt_hsi.h:462

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__le16 wol_pkt_buf_size
Definition: bnxt_hsi.h:9490

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Definition: bnxt_hsi.h:7738

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__le16 req_type
Definition: bnxt_hsi.h:4162

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__le16 flow_handle_2
Definition: bnxt_hsi.h:7950

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__le16 flags
Definition: bnxt_hsi.h:1411

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Definition: bnxt_hsi.h:6741

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__le32 tqm_sp_num_entries
Definition: bnxt_hsi.h:2809

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Definition: bnxt_hsi.h:8975

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Definition: bnxt_hsi.h:2898

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Definition: bnxt_hsi.h:9484

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Definition: bnxt_hsi.h:6174

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Definition: bnxt_hsi.h:9128

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__le16 target_id
Definition: bnxt_hsi.h:4576

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Definition: bnxt_hsi.h:1570

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Definition: bnxt_hsi.h:8039

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Definition: bnxt_hsi.h:4578

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Definition: bnxt_hsi.h:10443

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Definition: bnxt_hsi.h:1565

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Definition: bnxt_hsi.h:8317

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Definition: bnxt_hsi.h:6887

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Definition: bnxt_hsi.h:2857

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__le16 resp_len
Definition: bnxt_hsi.h:8761

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Definition: bnxt_hsi.h:4061

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Definition: bnxt_hsi.h:4683

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__le64 l2_filter_id
Definition: bnxt_hsi.h:6609

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__le64 rx_mtu_err_frames
Definition: bnxt_hsi.h:3878

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__le16 pattern_buf_size
Definition: bnxt_hsi.h:9451

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__le64 resp_addr
Definition: bnxt_hsi.h:7747

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__le16 tqm_entry_size
Definition: bnxt_hsi.h:2478

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u8 unused_0[7]
Definition: bnxt_hsi.h:4975

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__le32 tqm_ring7_num_entries
Definition: bnxt_hsi.h:2817

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__le16 seq_id
Definition: bnxt_hsi.h:9696

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u8 tunnel_type
Definition: bnxt_hsi.h:8458

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Definition: bnxt_hsi.h:3222

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__le16 seq_id
Definition: bnxt_hsi.h:9129

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__le64 ntuple_filter_id
Definition: bnxt_hsi.h:7159

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__le16 vnic_id
Definition: bnxt_hsi.h:6031

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__le16 support_speeds2
Definition: bnxt_hsi.h:3563

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Definition: bnxt_hsi.h:6482

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Definition: bnxt_hsi.h:4755

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__be32 dflt_ip_addr[4]
Definition: bnxt_hsi.h:1572

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Definition: bnxt_hsi.h:8126

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Definition: bnxt_hsi.h:2958

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Definition: bnxt_hsi.h:5325

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__le16 zone
Definition: bnxt_hsi.h:8788

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Definition: bnxt_hsi.h:6459

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__le16 req_type
Definition: bnxt_hsi.h:7921

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Definition: bnxt_hsi.h:2832

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Definition: bnxt_hsi.h:4405

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Definition: bnxt_hsi.h:10594

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__le16 error_code
Definition: bnxt_hsi.h:10323

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__le16 req_type
Definition: bnxt_hsi.h:2124

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__le64 pcie_recovery_histogram
Definition: bnxt_hsi.h:8689

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Definition: bnxt_hsi.h:6753

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__le16 dest_fid
Definition: bnxt_hsi.h:6854

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__le64 resp_addr
Definition: bnxt_hsi.h:6352

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Definition: bnxt_hsi.h:5629

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Definition: bnxt_hsi.h:5508

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Definition: bnxt_hsi.h:2878

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Definition: bnxt_hsi.h:1926

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__le32 flags
Definition: bnxt_hsi.h:4912

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Definition: bnxt_hsi.h:7616

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u8 unused_0[6]
Definition: bnxt_hsi.h:9112

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__le16 seq_id
Definition: bnxt_hsi.h:8578

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4081

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Definition: bnxt_hsi.h:9398

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__le16 error_code
Definition: bnxt_hsi.h:7754

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__le16 mgmt_fw_build
Definition: bnxt_hsi.h:457

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__le16 target_id
Definition: bnxt_hsi.h:7662

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__le32 num_mc_entries
Definition: bnxt_hsi.h:6690

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__le64 resp_addr
Definition: bnxt_hsi.h:10530

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7599

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u8 unused_1[4]
Definition: bnxt_hsi.h:6305

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__le32 driver_polling_freq
Definition: bnxt_hsi.h:1747

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__le16 resp_len
Definition: bnxt_hsi.h:6880

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__le16 error_code
Definition: bnxt_hsi.h:6454

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__le32 min_bw
Definition: bnxt_hsi.h:1443

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__le64 tx_packets_cos4
Definition: bnxt_hsi.h:3957

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__le16 seq_id
Definition: bnxt_hsi.h:10223

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u8 unused_0[3]
Definition: bnxt_hsi.h:7278

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__le16 seq_id
Definition: bnxt_hsi.h:8017

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__le16 nq_ring_id
Definition: bnxt_hsi.h:6235

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Definition: bnxt_hsi.h:8313

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u8 hwrm_intf_maj_8b
Definition: bnxt_hsi.h:394

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__be32 dst_ipaddr_mask[4]
Definition: bnxt_hsi.h:7145

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u8 unused_1[7]
Definition: bnxt_hsi.h:4290

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u8 meter_type
Definition: bnxt_hsi.h:7511

hwrm_ring_free_input::ring_type
u8 ring_type
Definition: bnxt_hsi.h:6295

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u8 unused_0[4]
Definition: bnxt_hsi.h:7205

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__le16 seq_id
Definition: bnxt_hsi.h:6193

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__le16 force_link_speed
Definition: bnxt_hsi.h:3083

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__le16 seq_id
Definition: bnxt_hsi.h:9885

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__le16 resp_len
Definition: bnxt_hsi.h:9744

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6719

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__le16 vnic_num_ring_table_entries
Definition: bnxt_hsi.h:2475

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u8 valid
Definition: bnxt_hsi.h:8674

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__le64 resp_addr
Definition: bnxt_hsi.h:7768

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u8 stat_pg_size_stat_lvl
Definition: bnxt_hsi.h:2244

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__le16 seq_id
Definition: bnxt_hsi.h:1690

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__le16 seq_id
Definition: bnxt_hsi.h:7901

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__le32 flags
Definition: bnxt_hsi.h:6642

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__le16 max_resp_len
Definition: bnxt_hsi.h:440

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u8 unused_0[7]
Definition: bnxt_hsi.h:9195

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u8 options
Definition: bnxt_hsi.h:1618

hwrm_ring_grp_alloc_output::seq_id
__le16 seq_id
Definition: bnxt_hsi.h:6479

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__le16 target_id
Definition: bnxt_hsi.h:1396

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__le16 req_type
Definition: bnxt_hsi.h:6425

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u8 port_cnt
Definition: bnxt_hsi.h:4170

hwrm_dbg_coredump_retrieve_output::data_len
__le16 data_len
Definition: bnxt_hsi.h:9818

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6489

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__le16 resp_len
Definition: bnxt_hsi.h:4063

hwrm_fwd_resp_cmpl
Definition: bnxt_hsi.h:531

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__le16 supported_speeds_auto_mode
Definition: bnxt_hsi.h:4192

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__be16 dmac[3]
Definition: bnxt_hsi.h:7808

tx_port_stats::tx_1024b_1518b_frames
__le64 tx_1024b_1518b_frames
Definition: bnxt_hsi.h:3800

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__le16 seq_id
Definition: bnxt_hsi.h:4114

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__le64 tqm_ring3_page_dir
Definition: bnxt_hsi.h:2445

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Definition: bnxt_hsi.h:1965

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__le64 resp_addr
Definition: bnxt_hsi.h:5767

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u8 valid
Definition: bnxt_hsi.h:10649

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__le16 error_code
Definition: bnxt_hsi.h:7066

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__le16 resp_len
Definition: bnxt_hsi.h:1640

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__le16 seq_id
Definition: bnxt_hsi.h:9356

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__le16 req_type
Definition: bnxt_hsi.h:9182

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__le16 req_type
Definition: bnxt_hsi.h:3233

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__le16 resp_len
Definition: bnxt_hsi.h:4141

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__le32 udp_flow_timer
Definition: bnxt_hsi.h:8078

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Definition: bnxt_hsi.h:5887

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Definition: bnxt_hsi.h:7467

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Definition: bnxt_hsi.h:9843

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u8 valid
Definition: bnxt_hsi.h:7050

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char test7_name[32]
Definition: bnxt_hsi.h:10519

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u8 queue_id6
Definition: bnxt_hsi.h:5247

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__le16 error_code
Definition: bnxt_hsi.h:7311

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__le16 error_code
Definition: bnxt_hsi.h:6839

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u8 led2_color
Definition: bnxt_hsi.h:4415

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__le16 seq_id
Definition: bnxt_hsi.h:7975

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Definition: bnxt_hsi.h:4137

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__le64 resp_addr
Definition: bnxt_hsi.h:10176

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u8 unused_0[7]
Definition: bnxt_hsi.h:5757

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Definition: bnxt_hsi.h:1818

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Definition: bnxt_hsi.h:3610

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u8 cos_field_cfg
Definition: bnxt_hsi.h:3656

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__le64 resume_roce_pause_events
Definition: bnxt_hsi.h:3985

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__le64 rx_bytes
Definition: bnxt_hsi.h:3911

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Definition: bnxt_hsi.h:6881

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__le16 req_type
Definition: bnxt_hsi.h:9958

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Definition: bnxt_hsi.h:8184

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__le16 cmpl_ring
Definition: bnxt_hsi.h:2922

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__le16 netctrl_fw_minor
Definition: bnxt_hsi.h:460

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__le64 resp_addr
Definition: bnxt_hsi.h:9732

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__le64 tx_ucast_bytes
Definition: bnxt_hsi.h:1667

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u8 unused_0[7]
Definition: bnxt_hsi.h:6419

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__le16 seq_id
Definition: bnxt_hsi.h:4879

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__le16 seq_id
Definition: bnxt_hsi.h:9773

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__le16 target_id
Definition: bnxt_hsi.h:9130

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Definition: bnxt_hsi.h:9847

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u8 unused_0[3]
Definition: bnxt_hsi.h:3773

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__le16 error_code
Definition: bnxt_hsi.h:4584

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Definition: bnxt_hsi.h:514

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__le32 bkup_time_milli_seconds
Definition: bnxt_hsi.h:9041

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__le16 event_id
Definition: bnxt_hsi.h:945

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__le16 num_stat_ctxs
Definition: bnxt_hsi.h:1568

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Definition: bnxt_hsi.h:9871

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__be16 dst_port_mask
Definition: bnxt_hsi.h:7149

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__le64 rx_good_frames
Definition: bnxt_hsi.h:3884

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__le16 subtype
Definition: bnxt_hsi.h:9090

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u8 unused_1[6]
Definition: bnxt_hsi.h:6087

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Definition: bnxt_hsi.h:9507

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__be16 ovlan_tci
Definition: bnxt_hsi.h:6999

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__le32 alloc_hw_ring_grps
Definition: bnxt_hsi.h:1496

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Definition: bnxt_hsi.h:1223

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u8 meter_type
Definition: bnxt_hsi.h:7384

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__le16 seq_id
Definition: bnxt_hsi.h:1649

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u8 timestamp_lo
Definition: bnxt_hsi.h:1001

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__le16 led0_blink_off
Definition: bnxt_hsi.h:4496

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Definition: bnxt_hsi.h:6626

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u8 unused_3[4]
Definition: bnxt_hsi.h:2882

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__le16 req_type
Definition: bnxt_hsi.h:1271

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__le32 instance
Definition: bnxt_hsi.h:9783

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8566

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__le16 req_type
Definition: bnxt_hsi.h:7472

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__le32 queue_id7_min_bw
Definition: bnxt_hsi.h:5288

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__le16 t_l2_ovlan
Definition: bnxt_hsi.h:6557

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Definition: bnxt_hsi.h:9368

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Definition: bnxt_hsi.h:6703

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Definition: bnxt_hsi.h:647

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__le32 preemphasis
Definition: bnxt_hsi.h:3384

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u8 unused_3[3]
Definition: bnxt_hsi.h:2852

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__le16 component_id
Definition: bnxt_hsi.h:9761

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Definition: bnxt_hsi.h:1403

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__le64 resp_addr
Definition: bnxt_hsi.h:9793

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__le64 rx_pfc_ena_frames_pri2
Definition: bnxt_hsi.h:3895

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__le32 encap_data[20]
Definition: bnxt_hsi.h:7039

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__le32 write_addr
Definition: bnxt_hsi.h:9540

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__le16 led0_blink_on
Definition: bnxt_hsi.h:4384

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__le16 seq_id
Definition: bnxt_hsi.h:9992

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u8 hwrm_fw_maj_8b
Definition: bnxt_hsi.h:398

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__le16 error_code
Definition: bnxt_hsi.h:9592

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__le64 tx_ucast_frames
Definition: bnxt_hsi.h:3808

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u8 valid
Definition: bnxt_hsi.h:8418

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u8 queue_id1_pri_lvl
Definition: bnxt_hsi.h:5085

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u8 num_leds
Definition: bnxt_hsi.h:4367

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8544

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__le64 tx_4096b_9216b_frames
Definition: bnxt_hsi.h:3804

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__le64 byte_6
Definition: bnxt_hsi.h:7993

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__le16 unused_0[3]
Definition: bnxt_hsi.h:325

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Definition: bnxt_hsi.h:8575

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__le32 tx_lpi_timer_low
Definition: bnxt_hsi.h:4215

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__le16 num_msix
Definition: bnxt_hsi.h:1516

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__le16 req_type
Definition: bnxt_hsi.h:1872

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__le16 seq_id
Definition: bnxt_hsi.h:1512

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__le16 type
Definition: bnxt_hsi.h:1031

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__le16 error_code
Definition: bnxt_hsi.h:4060

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__le64 rx_pfc_ena_frames_pri4
Definition: bnxt_hsi.h:3897

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u8 unused_0[7]
Definition: bnxt_hsi.h:1641

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__le64 aux_bytes_out
Definition: bnxt_hsi.h:8509

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__le16 target_id
Definition: bnxt_hsi.h:6832

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Definition: bnxt_hsi.h:6122

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__be16 nat_port
Definition: bnxt_hsi.h:7821

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__le16 vf_id
Definition: bnxt_hsi.h:5858

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__le16 next_pair_index
Definition: bnxt_hsi.h:8283

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__le16 dir_type
Definition: bnxt_hsi.h:10096

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Definition: bnxt_hsi.h:3935

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Definition: bnxt_hsi.h:6745

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Definition: bnxt_hsi.h:7608

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Definition: bnxt_hsi.h:5691

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Definition: bnxt_hsi.h:7801

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Definition: bnxt_hsi.h:6279

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Definition: bnxt_hsi.h:6042

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Definition: bnxt_hsi.h:4122

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Definition: bnxt_hsi.h:1639

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Definition: bnxt_hsi.h:8349

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Definition: bnxt_hsi.h:626

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Definition: bnxt_hsi.h:1748

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Definition: bnxt_hsi.h:4902

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Definition: bnxt_hsi.h:1337

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Definition: bnxt_hsi.h:6607

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Definition: bnxt_hsi.h:10014

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Definition: bnxt_hsi.h:3039

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Definition: bnxt_hsi.h:5208

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Definition: bnxt_hsi.h:7232

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Definition: bnxt_hsi.h:949

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__le64 tx_packets_cos6
Definition: bnxt_hsi.h:3959

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Definition: bnxt_hsi.h:3720

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Definition: bnxt_hsi.h:9525

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Definition: bnxt_hsi.h:6266

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Definition: bnxt_hsi.h:6098

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Definition: bnxt_hsi.h:3803

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Definition: bnxt_hsi.h:1252

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Definition: bnxt_hsi.h:9903

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Definition: bnxt_hsi.h:7618

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Definition: bnxt_hsi.h:6692

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Definition: bnxt_hsi.h:10306

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Definition: bnxt_hsi.h:9375

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Definition: bnxt_hsi.h:408

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Definition: bnxt_hsi.h:2792

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Definition: bnxt_hsi.h:3760

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Definition: bnxt_hsi.h:7506

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Definition: bnxt_hsi.h:5713

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Definition: bnxt_hsi.h:10489

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Definition: bnxt_hsi.h:8826

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Definition: bnxt_hsi.h:4737

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Definition: bnxt_hsi.h:4935

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Definition: bnxt_hsi.h:1806

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Definition: bnxt_hsi.h:4233

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Definition: bnxt_hsi.h:9137

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Definition: bnxt_hsi.h:4672

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Definition: bnxt_hsi.h:8508

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Definition: bnxt_hsi.h:5788

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Definition: bnxt_hsi.h:3712

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Definition: bnxt_hsi.h:1975

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__le16 dir_idx
Definition: bnxt_hsi.h:10131

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Definition: bnxt_hsi.h:434

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Definition: bnxt_hsi.h:2045

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__le16 req_type
Definition: bnxt_hsi.h:1709

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Definition: bnxt_hsi.h:4564

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Definition: bnxt_hsi.h:10422

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Definition: bnxt_hsi.h:1149

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Definition: bnxt_hsi.h:2467

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Definition: bnxt_hsi.h:9221

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Definition: bnxt_hsi.h:6246

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__le64 rx_eee_lpi_duration
Definition: bnxt_hsi.h:3905

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Definition: bnxt_hsi.h:2439

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Definition: bnxt_hsi.h:7998

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Definition: bnxt_hsi.h:7333

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Definition: bnxt_hsi.h:1200

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Definition: bnxt_hsi.h:9535

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Definition: bnxt_hsi.h:6278

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__le64 resp_addr
Definition: bnxt_hsi.h:381

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__le32 read_addr
Definition: bnxt_hsi.h:9519

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Definition: bnxt_hsi.h:9191

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__le16 error_code
Definition: bnxt_hsi.h:1213

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__le32 flags
Definition: bnxt_hsi.h:4882

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__le32 normal_wait_period
Definition: bnxt_hsi.h:1749

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Definition: bnxt_hsi.h:8326

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Definition: bnxt_hsi.h:7373

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__le16 seq_id
Definition: bnxt_hsi.h:4992

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__le16 error_code
Definition: bnxt_hsi.h:8411

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Definition: bnxt_hsi.h:10394

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__le16 flags
Definition: bnxt_hsi.h:9022

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Definition: bnxt_hsi.h:10528

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__le32 dir_item_length
Definition: bnxt_hsi.h:10115

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__le64 packet_2
Definition: bnxt_hsi.h:7979

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__le32 max_bw
Definition: bnxt_hsi.h:1459

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Definition: bnxt_hsi.h:8273

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Definition: bnxt_hsi.h:7368

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__le16 fid
Definition: bnxt_hsi.h:1217

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__le32 event_data2
Definition: bnxt_hsi.h:902

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__le16 seq_id
Definition: bnxt_hsi.h:6733

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__le16 target_id
Definition: bnxt_hsi.h:3700

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__le16 req_type
Definition: bnxt_hsi.h:2505

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Definition: bnxt_hsi.h:9122

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Definition: bnxt_hsi.h:5741

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Definition: bnxt_hsi.h:3934

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__le32 fw_ring_id
Definition: bnxt_hsi.h:9894

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__le64 ring_grp_tbl_addr
Definition: bnxt_hsi.h:6039

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__le64 tx_single_coll_frames
Definition: bnxt_hsi.h:3819

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__le16 first_vf_id
Definition: bnxt_hsi.h:1241

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Definition: bnxt_hsi.h:6849

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Definition: bnxt_hsi.h:7848

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__le64 rx_packets_cos1
Definition: bnxt_hsi.h:3995

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Definition: bnxt_hsi.h:7715

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Definition: bnxt_hsi.h:8309

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Definition: bnxt_hsi.h:8073

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Definition: bnxt_hsi.h:9515

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Definition: bnxt_hsi.h:2890

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__le32 tqm_ring4_num_entries
Definition: bnxt_hsi.h:2461

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__le16 vf_b_index
Definition: bnxt_hsi.h:8293

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__le16 seq_id
Definition: bnxt_hsi.h:10283

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Definition: bnxt_hsi.h:5868

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__le64 tqm_ring7_page_dir
Definition: bnxt_hsi.h:2796

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__le64 rx_agg_events
Definition: bnxt_hsi.h:1680

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Definition: bnxt_hsi.h:6184

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Definition: bnxt_hsi.h:7199

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Definition: bnxt_hsi.h:1715

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Definition: bnxt_hsi.h:5785

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Definition: bnxt_hsi.h:5716

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Definition: bnxt_hsi.h:5754

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Definition: bnxt_hsi.h:6494

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Definition: bnxt_hsi.h:1408

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Definition: bnxt_hsi.h:10257

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Definition: bnxt_hsi.h:9026

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Definition: bnxt_hsi.h:5327

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Definition: bnxt_hsi.h:9404

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__le16 target_id
Definition: bnxt_hsi.h:6512

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Definition: bnxt_hsi.h:4591

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__le16 dir_ext
Definition: bnxt_hsi.h:10098

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Definition: bnxt_hsi.h:4527

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Definition: bnxt_hsi.h:5781

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Definition: bnxt_hsi.h:9865

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__le32 enables
Definition: bnxt_hsi.h:6206

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Definition: bnxt_hsi.h:1384

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Definition: bnxt_hsi.h:2156

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Definition: bnxt_hsi.h:7345

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Definition: bnxt_hsi.h:8074

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__le64 ntuple_filter_id
Definition: bnxt_hsi.h:7181

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__le64 packet_9
Definition: bnxt_hsi.h:7986

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__le16 dst_fid
Definition: bnxt_hsi.h:7906

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Definition: bnxt_hsi.h:10360

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Definition: bnxt_hsi.h:903

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Definition: bnxt_hsi.h:996

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__le64 resp_addr
Definition: bnxt_hsi.h:8457

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Definition: bnxt_hsi.h:8118

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Definition: bnxt_hsi.h:2955

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Definition: bnxt_hsi.h:1637

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Definition: bnxt_hsi.h:9548

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Definition: bnxt_hsi.h:1409

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Definition: bnxt_hsi.h:4370

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Definition: bnxt_hsi.h:7078

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Definition: bnxt_hsi.h:908

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Definition: bnxt_hsi.h:4763

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__le64 pfc_pri4_rx_duration_us
Definition: bnxt_hsi.h:4010

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Definition: bnxt_hsi.h:8166

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__le64 tx_ucast_pkts
Definition: bnxt_hsi.h:1662

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Definition: bnxt_hsi.h:6674

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Definition: bnxt_hsi.h:865

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Definition: bnxt_hsi.h:8223

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__le16 min_cmpl_rings
Definition: bnxt_hsi.h:2075

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Definition: bnxt_hsi.h:4085

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__le64 rx_packets_cos6
Definition: bnxt_hsi.h:4000

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__le16 read_size
Definition: bnxt_hsi.h:9831

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__le32 xcvr_identifier_type_tx_lpi_timer
Definition: bnxt_hsi.h:3507

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__le16 roce_fw_build
Definition: bnxt_hsi.h:465

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Definition: bnxt_hsi.h:7978

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Definition: bnxt_hsi.h:6678

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__le16 data_len
Definition: bnxt_hsi.h:9088

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Definition: bnxt_hsi.h:8519

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Definition: bnxt_hsi.h:8286

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__le64 resp_addr
Definition: bnxt_hsi.h:1713

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Definition: bnxt_hsi.h:4534

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__le64 tpa_aborts
Definition: bnxt_hsi.h:8501

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Definition: bnxt_hsi.h:5811

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Definition: bnxt_hsi.h:4907

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__le32 rx_ts_reg_off_fifo_adv
Definition: bnxt_hsi.h:3782

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__le64 rx_pfc_xon2xoff_frames_pri2
Definition: bnxt_hsi.h:3887

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Definition: bnxt_hsi.h:4545

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Definition: bnxt_hsi.h:1256

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__le16 dflt_vlan
Definition: bnxt_hsi.h:1571

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Definition: bnxt_hsi.h:4695

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__be32 dest_ip_addr[4]
Definition: bnxt_hsi.h:6988

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Definition: bnxt_hsi.h:8617

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Definition: bnxt_hsi.h:730

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__le64 ext_flow_handle
Definition: bnxt_hsi.h:7864

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__le16 dflt_vnic_id
Definition: bnxt_hsi.h:1441

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__le64 tx_bytes
Definition: bnxt_hsi.h:3842

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Definition: bnxt_hsi.h:2073

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Definition: bnxt_hsi.h:2404

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Definition: bnxt_hsi.h:2095

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__le16 lb_rule
Definition: bnxt_hsi.h:5832

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Definition: bnxt_hsi.h:1698

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Definition: bnxt_hsi.h:2490

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Definition: bnxt_hsi.h:4145

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Definition: bnxt_hsi.h:3025

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Definition: bnxt_hsi.h:8979

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Definition: bnxt_hsi.h:6323

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Definition: bnxt_hsi.h:7874

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Definition: bnxt_hsi.h:9529

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__le16 req_type
Definition: bnxt_hsi.h:10112

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Definition: bnxt_hsi.h:1723

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Definition: bnxt_hsi.h:8839

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__le32 excess_peak_rate
Definition: bnxt_hsi.h:7423

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Definition: bnxt_hsi.h:5607

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Definition: bnxt_hsi.h:6556

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__le16 seq_id
Definition: bnxt_hsi.h:8637

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Definition: bnxt_hsi.h:2356

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Definition: bnxt_hsi.h:8807

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Definition: bnxt_hsi.h:9674

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Definition: bnxt_hsi.h:5883

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Definition: bnxt_hsi.h:8740

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Definition: bnxt_hsi.h:9246

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Definition: bnxt_hsi.h:7059

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Definition: bnxt_hsi.h:3841

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Definition: bnxt_hsi.h:1194

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Definition: bnxt_hsi.h:4309

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Definition: bnxt_hsi.h:9722

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Definition: bnxt_hsi.h:3452

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Definition: bnxt_hsi.h:9630

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Definition: bnxt_hsi.h:9333

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Definition: bnxt_hsi.h:8224

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Definition: bnxt_hsi.h:10066

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Definition: bnxt_hsi.h:1340

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Definition: bnxt_hsi.h:1589

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Definition: bnxt_hsi.h:9183

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Definition: bnxt_hsi.h:7519

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Definition: bnxt_hsi.h:5735

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__le32 event_data1
Definition: bnxt_hsi.h:909

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__le16 option
Definition: bnxt_hsi.h:10032

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Definition: bnxt_hsi.h:6129

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__le16 resp_len
Definition: bnxt_hsi.h:8018

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Definition: bnxt_hsi.h:4614

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Definition: bnxt_hsi.h:4557

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__le16 req_type
Definition: bnxt_hsi.h:1905

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__le32 event_data1
Definition: bnxt_hsi.h:1104

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__le32 srq_num_entries
Definition: bnxt_hsi.h:2453

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__le16 resp_len
Definition: bnxt_hsi.h:9973

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__le16 seq_id
Definition: bnxt_hsi.h:9604

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__le32 enables
Definition: bnxt_hsi.h:10093

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Definition: bnxt_hsi.h:4315

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__le16 resp_len
Definition: bnxt_hsi.h:30

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__le16 req_type
Definition: bnxt_hsi.h:10629

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Definition: bnxt_hsi.h:2024

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__le64 tx_256b_511b_frames
Definition: bnxt_hsi.h:3798

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Definition: bnxt_hsi.h:10052

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__le32 fw_reset_cnt_reg
Definition: bnxt_hsi.h:1772

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Definition: bnxt_hsi.h:9979

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__le16 led3_blink_off
Definition: bnxt_hsi.h:4442

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__le16 type
Definition: bnxt_hsi.h:964

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__le16 ref_flow_handle
Definition: bnxt_hsi.h:7805

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__le32 max_tx_wm_flows
Definition: bnxt_hsi.h:1380

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__le16 target_id
Definition: bnxt_hsi.h:2069

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__le16 target_id
Definition: bnxt_hsi.h:3923

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__le16 unused_1
Definition: bnxt_hsi.h:9800

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__le64 tx_bytes_cos4
Definition: bnxt_hsi.h:3949

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Definition: bnxt_hsi.h:1822

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__le16 error_code
Definition: bnxt_hsi.h:8015

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u8 mgmt_addr_len
Definition: bnxt_hsi.h:9001

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__le16 req_type
Definition: bnxt_hsi.h:1700

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Definition: bnxt_hsi.h:10011

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Definition: bnxt_hsi.h:9017

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__le16 seq_id
Definition: bnxt_hsi.h:6639

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Definition: bnxt_hsi.h:5859

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__le64 tx_runt_frames
Definition: bnxt_hsi.h:3827

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__le16 seq_id
Definition: bnxt_hsi.h:2966

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__le16 cmd_discr
Definition: bnxt_hsi.h:53

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__le16 vnic_max_ring_table_entries
Definition: bnxt_hsi.h:2138

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__le16 seq_id
Definition: bnxt_hsi.h:3235

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Definition: bnxt_hsi.h:6154

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Definition: bnxt_hsi.h:8874

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__le16 target_id
Definition: bnxt_hsi.h:6852

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u8 tunnel_type
Definition: bnxt_hsi.h:7824

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__le16 error_code
Definition: bnxt_hsi.h:5864

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Definition: bnxt_hsi.h:4804

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Definition: bnxt_hsi.h:8046

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Definition: bnxt_hsi.h:4116

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__le16 mru
Definition: bnxt_hsi.h:1428

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__le16 tim_entry_size
Definition: bnxt_hsi.h:2480

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__le16 resp_len
Definition: bnxt_hsi.h:7494

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__le64 pfc_pri2_rx_transitions
Definition: bnxt_hsi.h:4007

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__le64 dest_data_addr
Definition: bnxt_hsi.h:5714

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__le32 tcp_fin_timer
Definition: bnxt_hsi.h:8077

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__le16 resp_len
Definition: bnxt_hsi.h:2840

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__le16 req_type
Definition: bnxt_hsi.h:9461

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__le32 min_bw
Definition: bnxt_hsi.h:1573

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__le16 mtu
Definition: bnxt_hsi.h:3713

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__le16 target_id
Definition: bnxt_hsi.h:10091

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__le16 flow_handle
Definition: bnxt_hsi.h:7862

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__le32 tim_max_entries
Definition: bnxt_hsi.h:2148

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__le16 target_id
Definition: bnxt_hsi.h:9861

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u8 ver_maj_8b
Definition: bnxt_hsi.h:1855

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__le16 seq_id
Definition: bnxt_hsi.h:1327

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__le16 timestamp_hi
Definition: bnxt_hsi.h:760

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__le16 error_code
Definition: bnxt_hsi.h:10281

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__le32 offset
Definition: bnxt_hsi.h:10071

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__le16 target_id
Definition: bnxt_hsi.h:10003

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__le64 tqm_ring5_page_dir
Definition: bnxt_hsi.h:2447

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__le16 target_id
Definition: bnxt_hsi.h:9605

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u8 wol_filter_id
Definition: bnxt_hsi.h:9465

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Definition: bnxt_hsi.h:2008

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__le16 cmpl_ring
Definition: bnxt_hsi.h:5851

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__le16 seq_id
Definition: bnxt_hsi.h:10578

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__le16 req_type
Definition: bnxt_hsi.h:9406

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__le16 req_type
Definition: bnxt_hsi.h:6464

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7631

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__le64 pcie_stat_host_addr
Definition: bnxt_hsi.h:8663

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__le32 flags
Definition: bnxt_hsi.h:6514

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u8 queue_id3_pri_lvl
Definition: bnxt_hsi.h:5165

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__le16 max_tx_rings
Definition: bnxt_hsi.h:1370

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__le16 seq_id
Definition: bnxt_hsi.h:8741

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__le16 seq_id
Definition: bnxt_hsi.h:9639

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__le16 req_type
Definition: bnxt_hsi.h:9275

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__le64 resp_addr
Definition: bnxt_hsi.h:10276

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__le64 rx_bcast_bytes
Definition: bnxt_hsi.h:8489

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Definition: bnxt_hsi.h:10429

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__le16 timestamp_hi
Definition: bnxt_hsi.h:806

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__le16 error_code
Definition: bnxt_hsi.h:1190

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__le16 seq_id
Definition: bnxt_hsi.h:4899

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__le64 resp_addr
Definition: bnxt_hsi.h:9169

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__le16 error_code
Definition: bnxt_hsi.h:8576

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__le16 resp_len
Definition: bnxt_hsi.h:4452

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Definition: bnxt_hsi.h:4383

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Definition: bnxt_hsi.h:7379

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Definition: bnxt_hsi.h:6309

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__le64 byte_4
Definition: bnxt_hsi.h:7991

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__le16 seq_id
Definition: bnxt_hsi.h:5890

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__le64 pfc_pri6_tx_transitions
Definition: bnxt_hsi.h:3974

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Definition: bnxt_hsi.h:893

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__le32 flags
Definition: bnxt_hsi.h:5338

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__le16 qp_entry_size
Definition: bnxt_hsi.h:2130

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char pair_name[32]
Definition: bnxt_hsi.h:8248

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u8 unused_1[6]
Definition: bnxt_hsi.h:7359

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__le16 encap_resp_cmpl_ring
Definition: bnxt_hsi.h:9312

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__le16 seq_id
Definition: bnxt_hsi.h:2839

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__le64 host_dbg_dump_addr_len
Definition: bnxt_hsi.h:9655

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Definition: bnxt_hsi.h:605

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Definition: bnxt_hsi.h:8051

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__le16 seq_id
Definition: bnxt_hsi.h:6501

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__le16 max_l2_ctxs
Definition: bnxt_hsi.h:1372

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Definition: bnxt_hsi.h:85

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__le64 rx_stat_host_addr
Definition: bnxt_hsi.h:4032

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__le16 resp_len
Definition: bnxt_hsi.h:8256

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__le16 cmpl_ring
Definition: bnxt_hsi.h:378

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__le16 seq_id
Definition: bnxt_hsi.h:8520

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Definition: bnxt_hsi.h:3157

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__le16 error_code
Definition: bnxt_hsi.h:10490

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Definition: bnxt_hsi.h:1319

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__le64 resp_addr
Definition: bnxt_hsi.h:1734

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Definition: bnxt_hsi.h:10125

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Definition: bnxt_hsi.h:816

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__le16 seq_id
Definition: bnxt_hsi.h:6130

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Definition: bnxt_hsi.h:4857

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__le16 req_type
Definition: bnxt_hsi.h:8656

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u8 valid
Definition: bnxt_hsi.h:5802

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__le32 flags
Definition: bnxt_hsi.h:9699

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__le16 req_type
Definition: bnxt_hsi.h:10212

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__le64 tx_ucast_pkts
Definition: bnxt_hsi.h:8490

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Definition: bnxt_hsi.h:5971

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6202

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Definition: bnxt_hsi.h:6221

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__le64 resp_addr
Definition: bnxt_hsi.h:6492

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__le16 seq_id
Definition: bnxt_hsi.h:8102

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__le64 l2_filter_id
Definition: bnxt_hsi.h:7262

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__le64 resp_addr
Definition: bnxt_hsi.h:6833

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__le16 error_code
Definition: bnxt_hsi.h:3933

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7344

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Definition: bnxt_hsi.h:6052

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__le16 timestamp_hi
Definition: bnxt_hsi.h:864

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__le16 req_type
Definition: bnxt_hsi.h:9772

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__le64 tx_eee_lpi_events
Definition: bnxt_hsi.h:3837

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__le16 cmpl_ring
Definition: bnxt_hsi.h:3616

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__le16 target_id
Definition: bnxt_hsi.h:9485

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__le32 queue_id7_max_bw
Definition: bnxt_hsi.h:5304

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4052

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__le16 cmpl_ring
Definition: bnxt_hsi.h:1394

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__le16 data_len
Definition: bnxt_hsi.h:10355

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Definition: bnxt_hsi.h:9190

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__le16 target_id
Definition: bnxt_hsi.h:8776

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__le16 req_type
Definition: bnxt_hsi.h:7630

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Definition: bnxt_hsi.h:5891

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__le32 tqm_min_entries_per_ring
Definition: bnxt_hsi.h:2143

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__le64 tunnel_filter_id
Definition: bnxt_hsi.h:6834

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__le64 resp_addr
Definition: bnxt_hsi.h:2160

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Definition: bnxt_hsi.h:1711

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Definition: bnxt_hsi.h:6679

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Definition: bnxt_hsi.h:4650

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Definition: bnxt_hsi.h:4521

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Definition: bnxt_hsi.h:7788

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Definition: bnxt_hsi.h:1990

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Definition: bnxt_hsi.h:6456

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Definition: bnxt_hsi.h:3947

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Definition: bnxt_hsi.h:3939

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Definition: bnxt_hsi.h:6138

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Definition: bnxt_hsi.h:10002

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Definition: bnxt_hsi.h:6360

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Definition: bnxt_hsi.h:7593

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Definition: bnxt_hsi.h:1970

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Definition: bnxt_hsi.h:9420

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Definition: bnxt_hsi.h:3686

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Definition: bnxt_hsi.h:496

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Definition: bnxt_hsi.h:4911

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Definition: bnxt_hsi.h:6493

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Definition: bnxt_hsi.h:10593

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Definition: bnxt_hsi.h:5001

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Definition: bnxt_hsi.h:9653

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Definition: bnxt_hsi.h:8523

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Definition: bnxt_hsi.h:6748

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Definition: bnxt_hsi.h:6552

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Definition: bnxt_hsi.h:1175

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Definition: bnxt_hsi.h:9718

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Definition: bnxt_hsi.h:9295

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__le16 req_type
Definition: bnxt_hsi.h:6170

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Definition: bnxt_hsi.h:6153

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Definition: bnxt_hsi.h:9400

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Definition: bnxt_hsi.h:10097

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Definition: bnxt_hsi.h:10648

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Definition: bnxt_hsi.h:1960

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Definition: bnxt_hsi.h:858

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Definition: bnxt_hsi.h:2879

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Definition: bnxt_hsi.h:3239

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Definition: bnxt_hsi.h:7045

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Definition: bnxt_hsi.h:5503

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Definition: bnxt_hsi.h:3144

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Definition: bnxt_hsi.h:1386

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Definition: bnxt_hsi.h:2888

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Definition: bnxt_hsi.h:8868

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__le16 min_stat_ctx
Definition: bnxt_hsi.h:2085

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Definition: bnxt_hsi.h:2035

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Definition: bnxt_hsi.h:1320

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Definition: bnxt_hsi.h:9728

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Definition: bnxt_hsi.h:8287

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Definition: bnxt_hsi.h:5920

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Definition: bnxt_hsi.h:3817

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Definition: bnxt_hsi.h:7925

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Definition: bnxt_hsi.h:8268

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Definition: bnxt_hsi.h:7765

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Definition: bnxt_hsi.h:10015

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__le16 req_type
Definition: bnxt_hsi.h:4326

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Definition: bnxt_hsi.h:6471

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Definition: bnxt_hsi.h:2818

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Definition: bnxt_hsi.h:595

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__le32 flow_id_8
Definition: bnxt_hsi.h:7967

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__le32 event_data1
Definition: bnxt_hsi.h:979

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__le16 seq_id
Definition: bnxt_hsi.h:9434

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__le16 req_type
Definition: bnxt_hsi.h:9332

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Definition: bnxt_hsi.h:7107

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__le64 resp_addr
Definition: bnxt_hsi.h:6769

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__be16 ovlan_tpid
Definition: bnxt_hsi.h:6998

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Definition: bnxt_hsi.h:1947

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Definition: bnxt_hsi.h:5801

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__le16 error_code
Definition: bnxt_hsi.h:10009

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Definition: bnxt_hsi.h:3697

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Definition: bnxt_hsi.h:9284

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Definition: bnxt_hsi.h:7177

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Definition: bnxt_hsi.h:6848

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__le32 enables
Definition: bnxt_hsi.h:5339

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__le16 resp_len
Definition: bnxt_hsi.h:9902

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Definition: bnxt_hsi.h:755

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__le16 int_lat_tmr_max_max
Definition: bnxt_hsi.h:6384

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__le16 error_code
Definition: bnxt_hsi.h:4161

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__le64 rx_bytes_cos7
Definition: bnxt_hsi.h:3993

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Definition: bnxt_hsi.h:10251

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Definition: bnxt_hsi.h:2909

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__le16 target_id
Definition: bnxt_hsi.h:6022

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Definition: bnxt_hsi.h:8830

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Definition: bnxt_hsi.h:8527

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__le16 seq_id
Definition: bnxt_hsi.h:8231

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__le64 rx_jbr_frames
Definition: bnxt_hsi.h:3877

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Definition: bnxt_hsi.h:684

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Definition: bnxt_hsi.h:10187

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__le16 req_type
Definition: bnxt_hsi.h:3214

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__le16 resp_len
Definition: bnxt_hsi.h:9710

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__le16 seq_id
Definition: bnxt_hsi.h:7229

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Definition: bnxt_hsi.h:10586

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__le64 pattern_buf_addr
Definition: bnxt_hsi.h:9399

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Definition: bnxt_hsi.h:9790

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Definition: bnxt_hsi.h:8243

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Definition: bnxt_hsi.h:1987

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__le64 resp_addr
Definition: bnxt_hsi.h:22

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Definition: bnxt_hsi.h:8208

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__le64 rx_llfc_logical_msgs
Definition: bnxt_hsi.h:3907

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Definition: bnxt_hsi.h:7852

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Definition: bnxt_hsi.h:8099

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Definition: bnxt_hsi.h:6186

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__le32 event_data1
Definition: bnxt_hsi.h:9174

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Definition: bnxt_hsi.h:8049

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Definition: bnxt_hsi.h:2066

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Definition: bnxt_hsi.h:6924

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Definition: bnxt_hsi.h:1265

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Definition: bnxt_hsi.h:8933

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Definition: bnxt_hsi.h:8394

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Definition: bnxt_hsi.h:1719

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Definition: bnxt_hsi.h:6561

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Definition: bnxt_hsi.h:6358

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Definition: bnxt_hsi.h:2468

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Definition: bnxt_hsi.h:6314

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__le16 resp_len
Definition: bnxt_hsi.h:4795

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Definition: bnxt_hsi.h:7731

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Definition: bnxt_hsi.h:1979

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Definition: bnxt_hsi.h:9486

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Definition: bnxt_hsi.h:8500

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Definition: bnxt_hsi.h:8912

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Definition: bnxt_hsi.h:9449

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Definition: bnxt_hsi.h:8178

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Definition: bnxt_hsi.h:8314

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Definition: bnxt_hsi.h:6249

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Definition: bnxt_hsi.h:1072

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Definition: bnxt_hsi.h:9209

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Definition: bnxt_hsi.h:5351

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Definition: bnxt_hsi.h:2862

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Definition: bnxt_hsi.h:3699

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Definition: bnxt_hsi.h:3881

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Definition: bnxt_hsi.h:9729

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Definition: bnxt_hsi.h:1899

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Definition: bnxt_hsi.h:8307

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Definition: bnxt_hsi.h:4462

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Definition: bnxt_hsi.h:1395

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Definition: bnxt_hsi.h:70

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Definition: bnxt_hsi.h:9165

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__le64 tx_drop_pkts
Definition: bnxt_hsi.h:1666

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__le32 tim_num_entries
Definition: bnxt_hsi.h:2819

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__le32 stat_ctx_id
Definition: bnxt_hsi.h:8536

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Definition: bnxt_hsi.h:1132

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Definition: bnxt_hsi.h:9898

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__le16 enables
Definition: bnxt_hsi.h:8030

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__le32 tx_ts_reg_off_fifo
Definition: bnxt_hsi.h:3787

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__le16 req_type
Definition: bnxt_hsi.h:97

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__le32 system_caps
Definition: bnxt_hsi.h:9005

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Definition: bnxt_hsi.h:10554

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Definition: bnxt_hsi.h:6343

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__le64 l2_filter_id
Definition: bnxt_hsi.h:6784

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Definition: bnxt_hsi.h:7135

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__le16 rx_cfa_code_b
Definition: bnxt_hsi.h:8235

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Definition: bnxt_hsi.h:7287

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Definition: bnxt_hsi.h:8869

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Definition: bnxt_hsi.h:6120

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__le16 reserved_cmpl_rings
Definition: bnxt_hsi.h:2101

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__le16 unused_3
Definition: bnxt_hsi.h:9803

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__le16 resp_len
Definition: bnxt_hsi.h:3682

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__le16 num_rsscos_ctxs
Definition: bnxt_hsi.h:1562

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Definition: bnxt_hsi.h:7601

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Definition: bnxt_hsi.h:9607

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Definition: bnxt_hsi.h:9812

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Definition: bnxt_hsi.h:9170

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__le16 seq_id
Definition: bnxt_hsi.h:10274

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Definition: bnxt_hsi.h:4812

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Definition: bnxt_hsi.h:1201

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Definition: bnxt_hsi.h:8618

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Definition: bnxt_hsi.h:7298

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Definition: bnxt_hsi.h:4105

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Definition: bnxt_hsi.h:4053

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Definition: bnxt_hsi.h:4337

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Definition: bnxt_hsi.h:7721

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Definition: bnxt_hsi.h:1500

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Definition: bnxt_hsi.h:8895

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__le16 seq_id
Definition: bnxt_hsi.h:2506

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Definition: bnxt_hsi.h:1842

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Definition: bnxt_hsi.h:1430

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__le32 queue_id2_min_bw
Definition: bnxt_hsi.h:5088

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Definition: bnxt_hsi.h:4454

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Definition: bnxt_hsi.h:8872

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Definition: bnxt_hsi.h:8159

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Definition: bnxt_hsi.h:6491

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Definition: bnxt_hsi.h:2007

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Definition: bnxt_hsi.h:8906

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Definition: bnxt_hsi.h:8137

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Definition: bnxt_hsi.h:10188

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Definition: bnxt_hsi.h:7869

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Definition: bnxt_hsi.h:1501

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Definition: bnxt_hsi.h:930

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Definition: bnxt_hsi.h:5915

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Definition: bnxt_hsi.h:1276

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Definition: bnxt_hsi.h:9664

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Definition: bnxt_hsi.h:5806

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Definition: bnxt_hsi.h:6760

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__le64 hash_key_tbl_addr
Definition: bnxt_hsi.h:6040

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Definition: bnxt_hsi.h:7684

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Definition: bnxt_hsi.h:5007

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Definition: bnxt_hsi.h:8014

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__le16 seq_id
Definition: bnxt_hsi.h:9063

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Definition: bnxt_hsi.h:7061

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Definition: bnxt_hsi.h:4504

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Definition: bnxt_hsi.h:8353

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__le16 req_type
Definition: bnxt_hsi.h:9416

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Definition: bnxt_hsi.h:3223

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Definition: bnxt_hsi.h:10561

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__le32 bkup_power_info_ver
Definition: bnxt_hsi.h:9038

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Definition: bnxt_hsi.h:3728

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__le64 req_addr
Definition: bnxt_hsi.h:92

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Definition: bnxt_hsi.h:9720

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__le64 tx_pfc_frames
Definition: bnxt_hsi.h:3812

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Definition: bnxt_hsi.h:6019

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Definition: bnxt_hsi.h:8641

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Definition: bnxt_hsi.h:1668

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__le16 tx_cfa_action_b
Definition: bnxt_hsi.h:8236

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__le16 req_type
Definition: bnxt_hsi.h:8172

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__le16 resp_len
Definition: bnxt_hsi.h:7314

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Definition: bnxt_hsi.h:7847

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Definition: bnxt_hsi.h:7474

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6850

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Definition: bnxt_hsi.h:9675

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Definition: bnxt_hsi.h:9564

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Definition: bnxt_hsi.h:4822

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Definition: bnxt_hsi.h:10206

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Definition: bnxt_hsi.h:10081

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Definition: bnxt_hsi.h:9766

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Definition: bnxt_hsi.h:5845

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Definition: bnxt_hsi.h:6713

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__le32 flow_id_6
Definition: bnxt_hsi.h:7965

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__le32 max_agg_timer
Definition: bnxt_hsi.h:6011

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Definition: bnxt_hsi.h:6449

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__le16 req_type
Definition: bnxt_hsi.h:6057

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Definition: bnxt_hsi.h:4115

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Definition: bnxt_hsi.h:872

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Definition: bnxt_hsi.h:8883

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__le64 pfc_pri0_tx_duration_us
Definition: bnxt_hsi.h:3961

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__le16 req_type
Definition: bnxt_hsi.h:3920

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__le32 queue_id0_min_bw
Definition: bnxt_hsi.h:5008

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Definition: bnxt_hsi.h:4458

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__le16 req_type
Definition: bnxt_hsi.h:5807

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Definition: bnxt_hsi.h:6790

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__le32 queue_id7_min_bw
Definition: bnxt_hsi.h:5631

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Definition: bnxt_hsi.h:3707

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Definition: bnxt_hsi.h:2340

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Definition: bnxt_hsi.h:8285

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__le16 seq_id
Definition: bnxt_hsi.h:9498

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Definition: bnxt_hsi.h:9537

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Definition: bnxt_hsi.h:5670

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__le16 cmpl_ring
Definition: bnxt_hsi.h:1824

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Definition: bnxt_hsi.h:4443

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__le64 tx_err_pkts
Definition: bnxt_hsi.h:8583

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__le64 cdd_engine_usage
Definition: bnxt_hsi.h:8513

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__le16 rx_stat_size
Definition: bnxt_hsi.h:3938

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Definition: bnxt_hsi.h:10419

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__le16 req_type
Definition: bnxt_hsi.h:5865

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__le32 queue_id0_max_bw
Definition: bnxt_hsi.h:5024

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__le32 tqm_ring0_num_entries
Definition: bnxt_hsi.h:2810

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__le16 error_code
Definition: bnxt_hsi.h:9460

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__le16 vf_id
Definition: bnxt_hsi.h:1178

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__le16 seq_id
Definition: bnxt_hsi.h:6831

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__le16 error_code
Definition: bnxt_hsi.h:9660

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__le64 rx_bcast_pkts
Definition: bnxt_hsi.h:8590

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__le64 resp_addr
Definition: bnxt_hsi.h:4310

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__le16 hwrm_intf_patch
Definition: bnxt_hsi.h:450

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__le16 alloc_vfs
Definition: bnxt_hsi.h:1494

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Definition: bnxt_hsi.h:8963

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Definition: bnxt_hsi.h:8658

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__le64 byte_1
Definition: bnxt_hsi.h:7988

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u8 tc0_to_tsa_map
Definition: bnxt_hsi.h:8886

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__le16 resp_len
Definition: bnxt_hsi.h:3936

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Definition: bnxt_hsi.h:1208

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__le32 event_data1
Definition: bnxt_hsi.h:1073

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u8 tc2_to_tsa_map
Definition: bnxt_hsi.h:8893

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__le16 target_id
Definition: bnxt_hsi.h:5975

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Definition: bnxt_hsi.h:7352

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Definition: bnxt_hsi.h:4699

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__le16 seq_id
Definition: bnxt_hsi.h:5765

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__le64 resp_data_addr
Definition: bnxt_hsi.h:10591

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Definition: bnxt_hsi.h:9516

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__le32 dest_addr
Definition: bnxt_hsi.h:9917

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__le64 rx_bcast_bytes
Definition: bnxt_hsi.h:8595

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__le64 resp_addr
Definition: bnxt_hsi.h:5854

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9826

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__le64 resp_addr
Definition: bnxt_hsi.h:7946

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4848

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4104

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__le32 len
Definition: bnxt_hsi.h:9942

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Definition: bnxt_hsi.h:7753

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__le64 rx_ucast_pkts
Definition: bnxt_hsi.h:8588

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Definition: bnxt_hsi.h:5246

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__le16 event_id
Definition: bnxt_hsi.h:553

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Definition: bnxt_hsi.h:7819

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10273

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Definition: bnxt_hsi.h:7366

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Definition: bnxt_hsi.h:2735

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Definition: bnxt_hsi.h:9629

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Definition: bnxt_hsi.h:9011

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Definition: bnxt_hsi.h:8165

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Definition: bnxt_hsi.h:4632

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__le16 req_type
Definition: bnxt_hsi.h:6069

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Definition: bnxt_hsi.h:4287

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Definition: bnxt_hsi.h:3218

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Definition: bnxt_hsi.h:7875

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__le32 event_data2
Definition: bnxt_hsi.h:580

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__le16 req_type
Definition: bnxt_hsi.h:7900

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__le64 rx_bytes_cos6
Definition: bnxt_hsi.h:3992

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Definition: bnxt_hsi.h:801

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__le16 seq_id
Definition: bnxt_hsi.h:4152

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Definition: bnxt_hsi.h:7893

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__le16 req_type
Definition: bnxt_hsi.h:5972

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__le16 num_cmpl_dma_aggr_during_int
Definition: bnxt_hsi.h:6436

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Definition: bnxt_hsi.h:9213

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Definition: bnxt_hsi.h:4073

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__le32 enables
Definition: bnxt_hsi.h:1910

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Definition: bnxt_hsi.h:1133

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9648

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__le64 resp_addr
Definition: bnxt_hsi.h:7602

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__le16 resp_len
Definition: bnxt_hsi.h:4040

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__le16 cq_num_l2_entries
Definition: bnxt_hsi.h:2472

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Definition: bnxt_hsi.h:7338

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Definition: bnxt_hsi.h:4407

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__le16 seq_id
Definition: bnxt_hsi.h:7325

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Definition: bnxt_hsi.h:4805

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__le16 manufacturer_id
Definition: bnxt_hsi.h:10160

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Definition: bnxt_hsi.h:2155

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__le64 host_dest_addr
Definition: bnxt_hsi.h:9562

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__le64 resp_addr
Definition: bnxt_hsi.h:6513

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__le64 tx_multi_dfrl_frames
Definition: bnxt_hsi.h:3818

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Definition: bnxt_hsi.h:6453

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Definition: bnxt_hsi.h:4494

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__le16 req_type
Definition: bnxt_hsi.h:8647

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Definition: bnxt_hsi.h:8553

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__le16 port_id
Definition: bnxt_hsi.h:1341

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Definition: bnxt_hsi.h:4314

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Definition: bnxt_hsi.h:2826

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Definition: bnxt_hsi.h:8393

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__le16 seq_id
Definition: bnxt_hsi.h:1273

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Definition: bnxt_hsi.h:7654

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Definition: bnxt_hsi.h:7723

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__le16 seq_id
Definition: bnxt_hsi.h:2980

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Definition: bnxt_hsi.h:8237

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__le64 resp_addr
Definition: bnxt_hsi.h:10633

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Definition: bnxt_hsi.h:6095

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__le32 preemphasis
Definition: bnxt_hsi.h:3158

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Definition: bnxt_hsi.h:1688

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__le16 req_type
Definition: bnxt_hsi.h:6700

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Definition: bnxt_hsi.h:1199

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__le16 event_id
Definition: bnxt_hsi.h:1063

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__le64 tqm_ring1_page_dir
Definition: bnxt_hsi.h:2443

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__le16 resp_len
Definition: bnxt_hsi.h:10284

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Definition: bnxt_hsi.h:9534

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__le64 resp_addr
Definition: bnxt_hsi.h:4026

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Definition: bnxt_hsi.h:4700

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__le16 unused_1
Definition: bnxt_hsi.h:539

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__le16 num_cmpl_aggr_int_max
Definition: bnxt_hsi.h:6386

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__le16 default_cmpl_ring_id
Definition: bnxt_hsi.h:5835

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__le16 resp_len
Definition: bnxt_hsi.h:7935

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__le16 target_id
Definition: bnxt_hsi.h:1328

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Definition: bnxt_hsi.h:10484

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Definition: bnxt_hsi.h:722

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__le16 resp_len
Definition: bnxt_hsi.h:4927

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__le32 dflt_len
Definition: bnxt_hsi.h:4826

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__le32 event_data1
Definition: bnxt_hsi.h:1003

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Definition: bnxt_hsi.h:7592

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__le16 cmpl_ring
Definition: bnxt_hsi.h:5889

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__be16 tunnel_dst_port_val
Definition: bnxt_hsi.h:8416

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__le64 resp_addr
Definition: bnxt_hsi.h:10151

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__le64 tx_bcast_bytes
Definition: bnxt_hsi.h:1669

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__le64 resp_addr
Definition: bnxt_hsi.h:9378

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__le16 error_code
Definition: bnxt_hsi.h:7732

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__le16 reserved1
Definition: bnxt_hsi.h:7389

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__le32 unused_6
Definition: bnxt_hsi.h:6599

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Definition: bnxt_hsi.h:6175

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__le16 async_event_cr
Definition: bnxt_hsi.h:1605

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Definition: bnxt_hsi.h:7759

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Definition: bnxt_hsi.h:9148

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Definition: bnxt_hsi.h:4900

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Definition: bnxt_hsi.h:1387

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__le16 cmpl_ring
Definition: bnxt_hsi.h:5736

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__le16 page_offset
Definition: bnxt_hsi.h:4318

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Definition: bnxt_hsi.h:5921

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Definition: bnxt_hsi.h:5752

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__le16 req_type
Definition: bnxt_hsi.h:1316

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Definition: bnxt_hsi.h:8122

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Definition: bnxt_hsi.h:3538

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__le32 unused_0
Definition: bnxt_hsi.h:10646

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__le16 seq_id
Definition: bnxt_hsi.h:1226

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Definition: bnxt_hsi.h:7709

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Definition: bnxt_hsi.h:6657

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__le64 resp_addr
Definition: bnxt_hsi.h:7180

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__le64 rx_good_vlan_frames
Definition: bnxt_hsi.h:3856

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Definition: bnxt_hsi.h:9952

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Definition: bnxt_hsi.h:3976

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__le16 target_id
Definition: bnxt_hsi.h:6721

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Definition: bnxt_hsi.h:484

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__le16 resp_len
Definition: bnxt_hsi.h:6630

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Definition: bnxt_hsi.h:5470

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Definition: bnxt_hsi.h:8152

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__le16 mirror_vnic_id
Definition: bnxt_hsi.h:7119

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Definition: bnxt_hsi.h:1860

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__le16 req_type
Definition: bnxt_hsi.h:1214

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Definition: bnxt_hsi.h:9355

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__le16 resp_len
Definition: bnxt_hsi.h:6341

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__le16 slave_addr
Definition: bnxt_hsi.h:9837

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__le16 target_id
Definition: bnxt_hsi.h:5923

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__le16 tx_cfa_action_b
Definition: bnxt_hsi.h:8295

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__le32 excess_peak_burst
Definition: bnxt_hsi.h:7568

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Definition: bnxt_hsi.h:3757

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Definition: bnxt_hsi.h:10428

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__le16 target_id
Definition: bnxt_hsi.h:9309

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Definition: bnxt_hsi.h:4566

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__le64 eng_bytes_in
Definition: bnxt_hsi.h:8621

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Definition: bnxt_hsi.h:2114

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Definition: bnxt_hsi.h:8308

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__le32 rx_ts_reg_off_src_id_1
Definition: bnxt_hsi.h:3778

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__le16 req_type
Definition: bnxt_hsi.h:8328

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Definition: bnxt_hsi.h:5674

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__le16 error_code
Definition: bnxt_hsi.h:9684

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__le16 req_type
Definition: bnxt_hsi.h:9789

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__le16 req_type
Definition: bnxt_hsi.h:10544

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4778

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__le16 resp_len
Definition: bnxt_hsi.h:8819

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__le64 ntuple_filter_id_hint
Definition: bnxt_hsi.h:7150

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__le16 target_id
Definition: bnxt_hsi.h:4993

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__le64 req_buf_page_addr4
Definition: bnxt_hsi.h:1931

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__le16 req_type
Definition: bnxt_hsi.h:7460

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__le32 vnic_id
Definition: bnxt_hsi.h:6133

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__le32 data[16]
Definition: bnxt_hsi.h:4329

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__le64 resp_addr
Definition: bnxt_hsi.h:6398

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u8 valid
Definition: bnxt_hsi.h:4301

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__le64 pfc_pri3_tx_transitions
Definition: bnxt_hsi.h:3968

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Definition: bnxt_hsi.h:6553

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Definition: bnxt_hsi.h:10616

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__le16 ver_upd
Definition: bnxt_hsi.h:1865

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__le16 seq_id
Definition: bnxt_hsi.h:10619

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__le16 rx_stat_size
Definition: bnxt_hsi.h:4029

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__le16 supported_speeds2_auto_mode
Definition: bnxt_hsi.h:4255

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Definition: bnxt_hsi.h:8447

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__le16 req_type
Definition: bnxt_hsi.h:6840

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__le64 tx_mcast_frames
Definition: bnxt_hsi.h:3809

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Definition: bnxt_hsi.h:4316

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__le64 resp_addr
Definition: bnxt_hsi.h:9829

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__le16 resp_len
Definition: bnxt_hsi.h:1661

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u8 hwrm_fw_rsvd_8b
Definition: bnxt_hsi.h:401

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__le16 total_active_cos_queues
Definition: bnxt_hsi.h:4043

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__le16 req_type
Definition: bnxt_hsi.h:7857

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__le64 tx_stat_host_addr
Definition: bnxt_hsi.h:4031

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__le16 seq_id
Definition: bnxt_hsi.h:8413

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__le16 source_id
Definition: bnxt_hsi.h:537

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__le64 rx_agg_pkts
Definition: bnxt_hsi.h:1678

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Definition: bnxt_hsi.h:8899

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__le16 req_type
Definition: bnxt_hsi.h:4080

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__le16 error_code
Definition: bnxt_hsi.h:4325

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__le64 host_dbg_dump_addr
Definition: bnxt_hsi.h:9654

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Definition: bnxt_hsi.h:1942

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Definition: bnxt_hsi.h:9185

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__le64 src_data_addr
Definition: bnxt_hsi.h:9053

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__le16 index_1
Definition: bnxt_hsi.h:10412

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__le16 alloc_cmpl_rings
Definition: bnxt_hsi.h:1422

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__le16 error_code
Definition: bnxt_hsi.h:6191

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u8 unused_3
Definition: bnxt_hsi.h:4563

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__le16 req_type
Definition: bnxt_hsi.h:6478

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__le16 segment_id
Definition: bnxt_hsi.h:9798

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__le16 option_num
Definition: bnxt_hsi.h:10406

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Definition: bnxt_hsi.h:10110

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__le16 error_code
Definition: bnxt_hsi.h:7649

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__le16 max_rx_rings
Definition: bnxt_hsi.h:1371

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__le16 reserved
Definition: bnxt_hsi.h:8320

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__le32 queue_id2_min_bw
Definition: bnxt_hsi.h:5431

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__le32 event_data1
Definition: bnxt_hsi.h:1165

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u8 opaque_v
Definition: bnxt_hsi.h:881

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__le16 req_type
Definition: bnxt_hsi.h:1976

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__le64 resp_addr
Definition: bnxt_hsi.h:10202

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Definition: bnxt_hsi.h:10525

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__le16 cmpl_ring
Definition: bnxt_hsi.h:1954

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__le16 min_vnics
Definition: bnxt_hsi.h:2083

hwrm_async_event_cmpl_hwrm_error::event_data2
__le32 event_data2
Definition: bnxt_hsi.h:1152

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Definition: bnxt_hsi.h:8441

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__le16 req_type
Definition: bnxt_hsi.h:5333

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u8 ip_protocol
Definition: bnxt_hsi.h:7113

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__le64 rx_256b_511b_frames
Definition: bnxt_hsi.h:3853

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__le16 unused_0
Definition: bnxt_hsi.h:9764

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Definition: bnxt_hsi.h:7597

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__le16 resp_len
Definition: bnxt_hsi.h:5800

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Definition: bnxt_hsi.h:9186

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__le16 fid
Definition: bnxt_hsi.h:1693

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__le64 vlan_tag_mask_tbl_addr
Definition: bnxt_hsi.h:6726

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Definition: bnxt_hsi.h:2891

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__le16 seq_id
Definition: bnxt_hsi.h:6720

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__le16 event_id
Definition: bnxt_hsi.h:773

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__le16 error_code
Definition: bnxt_hsi.h:8554

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__le32 sector_size
Definition: bnxt_hsi.h:10162

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__le16 target_id
Definition: bnxt_hsi.h:9168

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__le32 flags
Definition: bnxt_hsi.h:1293

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Definition: bnxt_hsi.h:9321

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u8 unused_0[7]
Definition: bnxt_hsi.h:9596

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u8 hdr_cnt
Definition: bnxt_hsi.h:9055

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__le64 rx_bytes_cos0
Definition: bnxt_hsi.h:3986

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__le64 error_commands
Definition: bnxt_hsi.h:8511

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u8 phy_type
Definition: bnxt_hsi.h:3388

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__le16 resp_len
Definition: bnxt_hsi.h:6457

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__le64 resp_addr
Definition: bnxt_hsi.h:6023

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__le64 tx_good_vlan_frames
Definition: bnxt_hsi.h:3801

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__le16 resp_len
Definition: bnxt_hsi.h:9774

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Definition: bnxt_hsi.h:9740

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__le64 tx_fifo_underruns
Definition: bnxt_hsi.h:3828

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__le16 seq_id
Definition: bnxt_hsi.h:2098

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__le16 target_id
Definition: bnxt_hsi.h:1227

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__le16 resp_len
Definition: bnxt_hsi.h:10620

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__le16 resp_len
Definition: bnxt_hsi.h:8800

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__le16 req_type
Definition: bnxt_hsi.h:10172

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u8 queue_id2_bw_weight
Definition: bnxt_hsi.h:5126

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6888

input::req_type
__le16 req_type
Definition: bnxt_hsi.h:69

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__le16 seq_id
Definition: bnxt_hsi.h:10325

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__le16 req_type
Definition: bnxt_hsi.h:4585

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__le64 tqm_ring6_page_dir
Definition: bnxt_hsi.h:2448

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__le16 type
Definition: bnxt_hsi.h:1118

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u8 unused_0[2]
Definition: bnxt_hsi.h:6547

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__le16 flags
Definition: bnxt_hsi.h:10033

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u8 queue_id5_service_profile
Definition: bnxt_hsi.h:4746

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__le16 seq_id
Definition: bnxt_hsi.h:9407

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__le32 enables
Definition: bnxt_hsi.h:7348

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u8 reserved1
Definition: bnxt_hsi.h:3651

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__le32 enables
Definition: bnxt_hsi.h:6654

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u8 queue_id0_bw_weight
Definition: bnxt_hsi.h:5389

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4307

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__le64 tx_tagged_frames
Definition: bnxt_hsi.h:3825

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u8 unused_0[5]
Definition: bnxt_hsi.h:9056

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u8 pri
Definition: bnxt_hsi.h:8212

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Definition: bnxt_hsi.h:10520

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__le16 error_code
Definition: bnxt_hsi.h:7843

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__be16 src_port
Definition: bnxt_hsi.h:7724

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__le16 timestamp_hi
Definition: bnxt_hsi.h:610

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u8 queue_pri2cos_cfg_allowed
Definition: bnxt_hsi.h:4698

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Definition: bnxt_hsi.h:6498

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Definition: bnxt_hsi.h:1739

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__le16 ver_patch
Definition: bnxt_hsi.h:2012

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__le16 resp_len
Definition: bnxt_hsi.h:6734

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u8 num_dscp_bits
Definition: bnxt_hsi.h:5700

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__le64 tx_total_frames
Definition: bnxt_hsi.h:3807

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char pair_name[32]
Definition: bnxt_hsi.h:8142

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__le64 resp_addr
Definition: bnxt_hsi.h:6294

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__le64 resp_addr
Definition: bnxt_hsi.h:8639

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Definition: bnxt_hsi.h:2151

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Definition: bnxt_hsi.h:10070

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Definition: bnxt_hsi.h:9628

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u8 led1_color
Definition: bnxt_hsi.h:4396

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9859

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u8 flags
Definition: bnxt_hsi.h:8090

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__be32 src_ip_addr
Definition: bnxt_hsi.h:6970

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__le16 error_code
Definition: bnxt_hsi.h:6913

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Definition: bnxt_hsi.h:9546

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__le16 target_id
Definition: bnxt_hsi.h:9560

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Definition: bnxt_hsi.h:4872

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__le16 resp_len
Definition: bnxt_hsi.h:3769

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__le16 seq_id
Definition: bnxt_hsi.h:2956

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__le32 fw_health_status_reg
Definition: bnxt_hsi.h:1752

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Definition: bnxt_hsi.h:6736

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Definition: bnxt_hsi.h:3387

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Definition: bnxt_hsi.h:9552

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__le16 req_type
Definition: bnxt_hsi.h:8016

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__le16 error_code
Definition: bnxt_hsi.h:7155

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__le16 req_type
Definition: bnxt_hsi.h:10282

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u8 tqm_ring4_pg_size_tqm_ring4_lvl
Definition: bnxt_hsi.h:2687

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Definition: bnxt_hsi.h:3849

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__le64 tqm_ring2_page_dir
Definition: bnxt_hsi.h:2791

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__le16 max_stat_ctx
Definition: bnxt_hsi.h:2054

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10630

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__le64 rx_mcast_pkts
Definition: bnxt_hsi.h:8589

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__le32 hash_type
Definition: bnxt_hsi.h:6024

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__le32 flow_id_9
Definition: bnxt_hsi.h:7968

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Definition: bnxt_hsi.h:9396

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__le32 sync_action
Definition: bnxt_hsi.h:9232

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__le16 type
Definition: bnxt_hsi.h:532

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Definition: bnxt_hsi.h:6890

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Definition: bnxt_hsi.h:3862

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Definition: bnxt_hsi.h:18

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Definition: bnxt_hsi.h:10459

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Definition: bnxt_hsi.h:8446

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Definition: bnxt_hsi.h:10382

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Definition: bnxt_hsi.h:3855

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Definition: bnxt_hsi.h:4810

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Definition: bnxt_hsi.h:10095

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Definition: bnxt_hsi.h:7745

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Definition: bnxt_hsi.h:4787

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Definition: bnxt_hsi.h:1929

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Definition: bnxt_hsi.h:8482

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Definition: bnxt_hsi.h:397

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Definition: bnxt_hsi.h:5663

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Definition: bnxt_hsi.h:6744

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Definition: bnxt_hsi.h:6467

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Definition: bnxt_hsi.h:1935

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Definition: bnxt_hsi.h:463

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Definition: bnxt_hsi.h:9875

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Definition: bnxt_hsi.h:9227

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Definition: bnxt_hsi.h:10065

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Definition: bnxt_hsi.h:6665

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Definition: bnxt_hsi.h:9538

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Definition: bnxt_hsi.h:6971

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Definition: bnxt_hsi.h:8398

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Definition: bnxt_hsi.h:6201

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Definition: bnxt_hsi.h:4590

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Definition: bnxt_hsi.h:7902

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Definition: bnxt_hsi.h:2802

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__le16 size
Definition: bnxt_hsi.h:91

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__le16 max_tx_rings
Definition: bnxt_hsi.h:2046

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Definition: bnxt_hsi.h:8175

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Definition: bnxt_hsi.h:9671

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Definition: bnxt_hsi.h:10106

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Definition: bnxt_hsi.h:9229

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Definition: bnxt_hsi.h:8086

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Definition: bnxt_hsi.h:3652

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Definition: bnxt_hsi.h:8475

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Definition: bnxt_hsi.h:2860

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Definition: bnxt_hsi.h:2019

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Definition: bnxt_hsi.h:4144

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Definition: bnxt_hsi.h:5003

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Definition: bnxt_hsi.h:4423

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__le16 resp_len
Definition: bnxt_hsi.h:6281

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Definition: bnxt_hsi.h:4327

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Definition: bnxt_hsi.h:5206

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__le16 error_code
Definition: bnxt_hsi.h:4138

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Definition: bnxt_hsi.h:1948

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Definition: bnxt_hsi.h:8577

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Definition: bnxt_hsi.h:7046

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Definition: bnxt_hsi.h:501

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Definition: bnxt_hsi.h:6131

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__le64 src_data_addr
Definition: bnxt_hsi.h:5740

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__le16 device_id
Definition: bnxt_hsi.h:10161

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Definition: bnxt_hsi.h:1315

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Definition: bnxt_hsi.h:6155

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Definition: bnxt_hsi.h:9606

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Definition: bnxt_hsi.h:1218

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Definition: bnxt_hsi.h:5697

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Definition: bnxt_hsi.h:4690

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Definition: bnxt_hsi.h:1741

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Definition: bnxt_hsi.h:8412

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Definition: bnxt_hsi.h:4932

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__le64 rx_ovrsz_frames
Definition: bnxt_hsi.h:3876

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Definition: bnxt_hsi.h:916

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Definition: bnxt_hsi.h:9016

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Definition: bnxt_hsi.h:7984

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Definition: bnxt_hsi.h:8410

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10301

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Definition: bnxt_hsi.h:7219

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__le64 resp_addr
Definition: bnxt_hsi.h:10067

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__le32 queue_id5_min_bw
Definition: bnxt_hsi.h:5551

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Definition: bnxt_hsi.h:7934

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Definition: bnxt_hsi.h:6986

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Definition: bnxt_hsi.h:6233

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Definition: bnxt_hsi.h:3944

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__le16 req_type
Definition: bnxt_hsi.h:2097

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Definition: bnxt_hsi.h:9466

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Definition: bnxt_hsi.h:3645

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__le16 target_id
Definition: bnxt_hsi.h:2861

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Definition: bnxt_hsi.h:6952

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Definition: bnxt_hsi.h:2372

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7228

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__le16 year
Definition: bnxt_hsi.h:8820

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__le16 total_data_len
Definition: bnxt_hsi.h:10621

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Definition: bnxt_hsi.h:6142

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__le64 mrav_page_dir
Definition: bnxt_hsi.h:2797

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Definition: bnxt_hsi.h:5904

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Definition: bnxt_hsi.h:2719

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__le16 async_event_cr
Definition: bnxt_hsi.h:1291

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Definition: bnxt_hsi.h:6033

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Definition: bnxt_hsi.h:5004

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Definition: bnxt_hsi.h:9961

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Definition: bnxt_hsi.h:10016

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Definition: bnxt_hsi.h:7923

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__le16 ver_maj
Definition: bnxt_hsi.h:2009

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__le16 dimensions
Definition: bnxt_hsi.h:10410

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__le64 pcie_tx_traffic_rate
Definition: bnxt_hsi.h:8683

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__le64 pfc_pri2_rx_duration_us
Definition: bnxt_hsi.h:4006

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Definition: bnxt_hsi.h:4796

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Definition: bnxt_hsi.h:4841

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Definition: bnxt_hsi.h:4946

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Definition: bnxt_hsi.h:10546

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Definition: bnxt_hsi.h:7171

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Definition: bnxt_hsi.h:10295

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__le64 resp_addr
Definition: bnxt_hsi.h:9915

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__be16 l2_rewrite_vlan_tpid
Definition: bnxt_hsi.h:7802

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__le16 seq_id
Definition: bnxt_hsi.h:9935

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__le16 target_id
Definition: bnxt_hsi.h:7746

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Definition: bnxt_hsi.h:8801

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__le16 seq_id
Definition: bnxt_hsi.h:379

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u8 tc3_to_tsa_map
Definition: bnxt_hsi.h:8894

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Definition: bnxt_hsi.h:7811

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__le64 tx_bytes_cos5
Definition: bnxt_hsi.h:3950

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__le16 resp_len
Definition: bnxt_hsi.h:6702

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__le32 rsvd2
Definition: bnxt_hsi.h:2881

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Definition: bnxt_hsi.h:4335

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u8 rsvd
Definition: bnxt_hsi.h:4368

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Definition: bnxt_hsi.h:9765

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__le64 tx_packets_cos1
Definition: bnxt_hsi.h:3954

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__le16 mgmt_fw_patch
Definition: bnxt_hsi.h:458

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Definition: bnxt_hsi.h:1646

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__le16 target_id
Definition: bnxt_hsi.h:1251

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8138

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__le64 tx_mcast_pkts
Definition: bnxt_hsi.h:1663

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__le16 seq_id
Definition: bnxt_hsi.h:6162

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Definition: bnxt_hsi.h:1978

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__le32 rsvd2
Definition: bnxt_hsi.h:2850

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__le16 src_fid
Definition: bnxt_hsi.h:7905

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__le16 max_aggs
Definition: bnxt_hsi.h:6003

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__le32 resp_buf_addr_v[2]
Definition: bnxt_hsi.h:540

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__le16 req_type
Definition: bnxt_hsi.h:9306

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Definition: bnxt_hsi.h:4156

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Definition: bnxt_hsi.h:5844

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Definition: bnxt_hsi.h:6996

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6830

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__le16 tunnel_dst_port_id
Definition: bnxt_hsi.h:8466

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__le16 resp_len
Definition: bnxt_hsi.h:8579

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Definition: bnxt_hsi.h:7842

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__le32 flags
Definition: bnxt_hsi.h:2508

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Definition: bnxt_hsi.h:6747

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Definition: bnxt_hsi.h:9132

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__le64 resp_addr
Definition: bnxt_hsi.h:10004

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__le16 dir_type
Definition: bnxt_hsi.h:10027

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Definition: bnxt_hsi.h:10177

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Definition: bnxt_hsi.h:7640

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Definition: bnxt_hsi.h:10570

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Definition: bnxt_hsi.h:6487

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__le16 write_size
Definition: bnxt_hsi.h:9832

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__le64 dest_data_addr
Definition: bnxt_hsi.h:9087

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Definition: bnxt_hsi.h:2006

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__le64 rx_mcast_frames
Definition: bnxt_hsi.h:3863

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Definition: bnxt_hsi.h:4282

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Definition: bnxt_hsi.h:8792

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Definition: bnxt_hsi.h:2957

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Definition: bnxt_hsi.h:8626

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Definition: bnxt_hsi.h:3066

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__le16 seq_id
Definition: bnxt_hsi.h:10492

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8058

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6321

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Definition: bnxt_hsi.h:9838

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__le16 resp_len
Definition: bnxt_hsi.h:8352

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__le64 tx_bcast_pkts
Definition: bnxt_hsi.h:8582

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__le16 type
Definition: bnxt_hsi.h:940

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__le32 flow_id_5
Definition: bnxt_hsi.h:7964

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__le16 resp_len
Definition: bnxt_hsi.h:7069

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Definition: bnxt_hsi.h:894

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Definition: bnxt_hsi.h:2912

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Definition: bnxt_hsi.h:8257

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__le16 cr
Definition: bnxt_hsi.h:6469

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__le16 target_id
Definition: bnxt_hsi.h:4054

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__le32 vnic_id_cnt
Definition: bnxt_hsi.h:2914

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Definition: bnxt_hsi.h:7476

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Definition: bnxt_hsi.h:10312

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Definition: bnxt_hsi.h:7490

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Definition: bnxt_hsi.h:10379

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Definition: bnxt_hsi.h:5668

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__le64 rx_false_carrier_frames
Definition: bnxt_hsi.h:3875

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Definition: bnxt_hsi.h:9651

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__le16 pci_id
Definition: bnxt_hsi.h:1420

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__le32 nvram_size
Definition: bnxt_hsi.h:10163

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__le16 req_type
Definition: bnxt_hsi.h:8025

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__le16 seq_id
Definition: bnxt_hsi.h:2899

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__le16 led0_blink_on
Definition: bnxt_hsi.h:4495

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__le16 auto_link_speed_mask
Definition: bnxt_hsi.h:3347

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Definition: bnxt_hsi.h:5337

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Definition: bnxt_hsi.h:692

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__le16 error_code
Definition: bnxt_hsi.h:8072

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__le16 target_id
Definition: bnxt_hsi.h:5789

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Definition: bnxt_hsi.h:6628

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Definition: bnxt_hsi.h:1324

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__le16 meter_profile_id
Definition: bnxt_hsi.h:7516

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Definition: bnxt_hsi.h:4465

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__le16 reserved_l2_ctxs
Definition: bnxt_hsi.h:2104

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Definition: bnxt_hsi.h:4336

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Definition: bnxt_hsi.h:10356

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Definition: bnxt_hsi.h:10495

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Definition: bnxt_hsi.h:6886

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Definition: bnxt_hsi.h:9506

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Definition: bnxt_hsi.h:2123

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Definition: bnxt_hsi.h:2044

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Definition: bnxt_hsi.h:10592

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Definition: bnxt_hsi.h:1163

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Definition: bnxt_hsi.h:10403

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Definition: bnxt_hsi.h:9647

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Definition: bnxt_hsi.h:6955

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Definition: bnxt_hsi.h:10082

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Definition: bnxt_hsi.h:9727

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__le16 error_code
Definition: bnxt_hsi.h:9155

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Definition: bnxt_hsi.h:8709

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__le16 flags
Definition: bnxt_hsi.h:7769

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Definition: bnxt_hsi.h:6709

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Definition: bnxt_hsi.h:6113

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__le32 queue_id5_max_bw
Definition: bnxt_hsi.h:5224

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Definition: bnxt_hsi.h:9427

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Definition: bnxt_hsi.h:8823

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Definition: bnxt_hsi.h:8079

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__le64 resp_addr
Definition: bnxt_hsi.h:6097

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u8 hwrm_intf_upd_8b
Definition: bnxt_hsi.h:396

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Definition: bnxt_hsi.h:2543

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Definition: bnxt_hsi.h:5849

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u8 port_id
Definition: bnxt_hsi.h:9173

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__le16 seq_id
Definition: bnxt_hsi.h:7651

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__le16 req_type
Definition: bnxt_hsi.h:6950

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__le16 seq_id
Definition: bnxt_hsi.h:8760

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__le16 target_id
Definition: bnxt_hsi.h:1691

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u8 queue_id7_tsa_assign
Definition: bnxt_hsi.h:5320

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u8 pri4_cos_queue_id
Definition: bnxt_hsi.h:4971

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__le32 flow_id_3
Definition: bnxt_hsi.h:7962

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__le16 resp_len
Definition: bnxt_hsi.h:10493

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__le16 req_type
Definition: bnxt_hsi.h:7933

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__le16 led1_blink_off
Definition: bnxt_hsi.h:4519

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Definition: bnxt_hsi.h:10220

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__le64 tqm_ring4_page_dir
Definition: bnxt_hsi.h:2793

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__le16 req_type
Definition: bnxt_hsi.h:6500

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Definition: bnxt_hsi.h:427

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10199

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__le16 req_type
Definition: bnxt_hsi.h:9442

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__le16 seq_id
Definition: bnxt_hsi.h:2068

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__le16 req_type
Definition: bnxt_hsi.h:8773

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Definition: bnxt_hsi.h:4092

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__le16 req_type
Definition: bnxt_hsi.h:6765

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__le64 rx_promiscuous_frames
Definition: bnxt_hsi.h:3880

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__le16 seq_id
Definition: bnxt_hsi.h:10643

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Definition: bnxt_hsi.h:6393

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u8 unused_0[7]
Definition: bnxt_hsi.h:6668

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u8 valid
Definition: bnxt_hsi.h:9279

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__le16 int_lat_tmr_min_min
Definition: bnxt_hsi.h:6381

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__le64 tx_pfc_ena_frames_pri3
Definition: bnxt_hsi.h:3832

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__le16 error_code
Definition: bnxt_hsi.h:3024

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__be16 l2_rewrite_dmac[3]
Definition: bnxt_hsi.h:7820

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__le64 rx_packets_cos3
Definition: bnxt_hsi.h:3997

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__le16 resp_len
Definition: bnxt_hsi.h:1318

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__le64 resp_addr
Definition: bnxt_hsi.h:6722

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__le16 target_id
Definition: bnxt_hsi.h:4813

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Definition: bnxt_hsi.h:3542

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__le16 l2_ctxt_ref_id
Definition: bnxt_hsi.h:7727

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u8 valid
Definition: bnxt_hsi.h:9411

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__le64 rx_mcast_bytes
Definition: bnxt_hsi.h:8488

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Definition: bnxt_hsi.h:4074

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9514

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__le32 flags
Definition: bnxt_hsi.h:4862

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__le16 error_code
Definition: bnxt_hsi.h:9707

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Definition: bnxt_hsi.h:9269

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__le16 req_type
Definition: bnxt_hsi.h:8694

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__le16 resp_len
Definition: bnxt_hsi.h:6480

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__le32 commit_rate
Definition: bnxt_hsi.h:7391

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__le32 event_data2
Definition: bnxt_hsi.h:800

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__le16 req_type
Definition: bnxt_hsi.h:9082

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__le64 resp_addr
Definition: bnxt_hsi.h:7080

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__le16 port_id
Definition: bnxt_hsi.h:9447

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__le16 port_id
Definition: bnxt_hsi.h:4366

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__le64 resp_addr
Definition: bnxt_hsi.h:7885

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__le16 target_id
Definition: bnxt_hsi.h:6351

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__le32 enables
Definition: bnxt_hsi.h:6528

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__le16 resp_len
Definition: bnxt_hsi.h:4840

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__le16 req_type
Definition: bnxt_hsi.h:9991

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__le16 num_vnics
Definition: bnxt_hsi.h:1307

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u8 vlan_antispoof_mode
Definition: bnxt_hsi.h:1606

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__le16 seq_id
Definition: bnxt_hsi.h:9084

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Definition: bnxt_hsi.h:9893

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Definition: bnxt_hsi.h:4609

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Definition: bnxt_hsi.h:4633

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Definition: bnxt_hsi.h:4939

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__le16 jumbo_thresh
Definition: bnxt_hsi.h:6110

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__le16 seq_id
Definition: bnxt_hsi.h:9527

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__le16 new_meter_instance_id
Definition: bnxt_hsi.h:7209

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__le16 req_type
Definition: bnxt_hsi.h:1171

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__le16 src_fid
Definition: bnxt_hsi.h:8364

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__le16 seq_id
Definition: bnxt_hsi.h:5698

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__le16 target_id
Definition: bnxt_hsi.h:2829

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Definition: bnxt_hsi.h:7012

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Definition: bnxt_hsi.h:4339

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__le32 flags
Definition: bnxt_hsi.h:7926

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Definition: bnxt_hsi.h:2117

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Definition: bnxt_hsi.h:6092

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Definition: bnxt_hsi.h:9393

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__le16 flow_handle_8
Definition: bnxt_hsi.h:7956

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Definition: bnxt_hsi.h:1612

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__le16 seq_id
Definition: bnxt_hsi.h:6629

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__le32 event_data1
Definition: bnxt_hsi.h:1025

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__le16 error_code
Definition: bnxt_hsi.h:9990

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__le16 req_type
Definition: bnxt_hsi.h:9062

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__le16 req_type
Definition: bnxt_hsi.h:6320

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Definition: bnxt_hsi.h:2018

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Definition: bnxt_hsi.h:10210

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__le16 target_id
Definition: bnxt_hsi.h:7504

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__le64 resp_addr
Definition: bnxt_hsi.h:2070

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Definition: bnxt_hsi.h:8549

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__le64 rx_pfc_xon2xoff_frames_pri4
Definition: bnxt_hsi.h:3889

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__le32 dir_item_length
Definition: bnxt_hsi.h:10045

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Definition: bnxt_hsi.h:10157

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Definition: bnxt_hsi.h:9226

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__le16 data_len
Definition: bnxt_hsi.h:10405

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__le16 led3_blink_on
Definition: bnxt_hsi.h:4441

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9285

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Definition: bnxt_hsi.h:8828

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Definition: bnxt_hsi.h:6959

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__le32 max_rx_wm_flows
Definition: bnxt_hsi.h:1382

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__le16 seq_id
Definition: bnxt_hsi.h:1202

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Definition: bnxt_hsi.h:9349

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__be16 stag_tpid
Definition: bnxt_hsi.h:2875

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__le32 max_udp_flow_timer
Definition: bnxt_hsi.h:8106

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__le16 resp_len
Definition: bnxt_hsi.h:7367

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__le64 host_dest_addr
Definition: bnxt_hsi.h:9794

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Definition: bnxt_hsi.h:7974

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Definition: bnxt_hsi.h:7863

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u8 tunnel_type
Definition: bnxt_hsi.h:7120

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Definition: bnxt_hsi.h:9459

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Definition: bnxt_hsi.h:96

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Definition: bnxt_hsi.h:683

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__le64 resp_addr
Definition: bnxt_hsi.h:4463

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__le16 error_code
Definition: bnxt_hsi.h:5797

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__le16 seq_id
Definition: bnxt_hsi.h:7734

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__le16 port_id
Definition: bnxt_hsi.h:9425

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Definition: bnxt_hsi.h:5680

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__le16 cmpl_ring_id
Definition: bnxt_hsi.h:6231

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u8 hwrm_fw_bld_8b
Definition: bnxt_hsi.h:400

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Definition: bnxt_hsi.h:9947

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__le64 pfc_pri3_rx_transitions
Definition: bnxt_hsi.h:4009

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__le64 tx_stat_host_addr
Definition: bnxt_hsi.h:3927

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u8 hwrm_intf_min
Definition: bnxt_hsi.h:383

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__le64 pcie_pl_signal_integrity
Definition: bnxt_hsi.h:8679

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__le16 seq_id
Definition: bnxt_hsi.h:10302

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__le16 req_type
Definition: bnxt_hsi.h:4877

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__le16 seq_id
Definition: bnxt_hsi.h:3014

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__le64 rx_pfc_xon2xoff_frames_pri5
Definition: bnxt_hsi.h:3890

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u8 mgmt_fw_min_8b
Definition: bnxt_hsi.h:403

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Definition: bnxt_hsi.h:9369

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Definition: bnxt_hsi.h:1687

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__le16 req_type
Definition: bnxt_hsi.h:9825

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__le32 queue_id3_max_bw
Definition: bnxt_hsi.h:5144

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__le16 seq_id
Definition: bnxt_hsi.h:4095

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Definition: bnxt_hsi.h:8824

tlv
Definition: bnxt_hsi.h:52

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Definition: bnxt_hsi.h:6844

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__be16 flags_frag_offset
Definition: bnxt_hsi.h:6967

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__le32 tqm_ring3_num_entries
Definition: bnxt_hsi.h:2813

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Definition: bnxt_hsi.h:7195

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Definition: bnxt_hsi.h:6190

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Definition: bnxt_hsi.h:8718

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Definition: bnxt_hsi.h:6014

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10173

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__le64 rx_bytes_cos2
Definition: bnxt_hsi.h:3988

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__le64 resp_addr
Definition: bnxt_hsi.h:9517

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__le16 t_l2_ovlan_mask
Definition: bnxt_hsi.h:6558

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__le16 resp_len
Definition: bnxt_hsi.h:8232

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__le16 seq_id
Definition: bnxt_hsi.h:4024

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__le32 queue_id0_max_bw
Definition: bnxt_hsi.h:5367

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Definition: bnxt_hsi.h:4497

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8158

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Definition: bnxt_hsi.h:8885

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Definition: bnxt_hsi.h:7910

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Definition: bnxt_hsi.h:6380

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Definition: bnxt_hsi.h:8521

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Definition: bnxt_hsi.h:1943

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Definition: bnxt_hsi.h:5723

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Definition: bnxt_hsi.h:8532

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Definition: bnxt_hsi.h:8811

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Definition: bnxt_hsi.h:9541

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Definition: bnxt_hsi.h:3879

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Definition: bnxt_hsi.h:10304

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Definition: bnxt_hsi.h:9296

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Definition: bnxt_hsi.h:6088

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Definition: bnxt_hsi.h:9594

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Definition: bnxt_hsi.h:6359

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Definition: bnxt_hsi.h:4082

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Definition: bnxt_hsi.h:10529

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Definition: bnxt_hsi.h:9354

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Definition: bnxt_hsi.h:8695

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Definition: bnxt_hsi.h:410

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Definition: bnxt_hsi.h:522

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Definition: bnxt_hsi.h:4794

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Definition: bnxt_hsi.h:1388

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Definition: bnxt_hsi.h:9667

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Definition: bnxt_hsi.h:8085

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Definition: bnxt_hsi.h:5280

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Definition: bnxt_hsi.h:4270

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Definition: bnxt_hsi.h:2067

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Definition: bnxt_hsi.h:1828

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Definition: bnxt_hsi.h:1807

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Definition: bnxt_hsi.h:1103

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Definition: bnxt_hsi.h:4669

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Definition: bnxt_hsi.h:8196

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Definition: bnxt_hsi.h:1429

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Definition: bnxt_hsi.h:6472

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Definition: bnxt_hsi.h:8505

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Definition: bnxt_hsi.h:7318

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Definition: bnxt_hsi.h:9064

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Definition: bnxt_hsi.h:3194

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Definition: bnxt_hsi.h:807

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Definition: bnxt_hsi.h:9951

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Definition: bnxt_hsi.h:9872

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Definition: bnxt_hsi.h:2863

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Definition: bnxt_hsi.h:9980

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Definition: bnxt_hsi.h:7179

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Definition: bnxt_hsi.h:831

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Definition: bnxt_hsi.h:3928

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Definition: bnxt_hsi.h:8160

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Definition: bnxt_hsi.h:6225

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Definition: bnxt_hsi.h:1237

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Definition: bnxt_hsi.h:5982

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Definition: bnxt_hsi.h:8744

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Definition: bnxt_hsi.h:8661

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Definition: bnxt_hsi.h:5686

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Definition: bnxt_hsi.h:1957

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Definition: bnxt_hsi.h:10442

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Definition: bnxt_hsi.h:4016

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Definition: bnxt_hsi.h:393

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Definition: bnxt_hsi.h:2498

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Definition: bnxt_hsi.h:2163

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Definition: bnxt_hsi.h:10300

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Definition: bnxt_hsi.h:4980

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Definition: bnxt_hsi.h:8907

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Definition: bnxt_hsi.h:8280

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Definition: bnxt_hsi.h:2900

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Definition: bnxt_hsi.h:4280

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Definition: bnxt_hsi.h:7876

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Definition: bnxt_hsi.h:6755

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Definition: bnxt_hsi.h:6509

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Definition: bnxt_hsi.h:4300

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Definition: bnxt_hsi.h:9316

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Definition: bnxt_hsi.h:6468

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Definition: bnxt_hsi.h:426

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Definition: bnxt_hsi.h:5852

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Definition: bnxt_hsi.h:469

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Definition: bnxt_hsi.h:9266

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Definition: bnxt_hsi.h:9454

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Definition: bnxt_hsi.h:4149

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Definition: bnxt_hsi.h:8282

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Definition: bnxt_hsi.h:1404

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Definition: bnxt_hsi.h:6117

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Definition: bnxt_hsi.h:9101

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Definition: bnxt_hsi.h:8315

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Definition: bnxt_hsi.h:8263

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Definition: bnxt_hsi.h:9679

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Definition: bnxt_hsi.h:6704

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Definition: bnxt_hsi.h:2845

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Definition: bnxt_hsi.h:4046

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Definition: bnxt_hsi.h:2050

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Definition: bnxt_hsi.h:8254

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Definition: bnxt_hsi.h:10352

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Definition: bnxt_hsi.h:7492

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Definition: bnxt_hsi.h:9959

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Definition: bnxt_hsi.h:6985

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Definition: bnxt_hsi.h:7477

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Definition: bnxt_hsi.h:4693

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Definition: bnxt_hsi.h:2495

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Definition: bnxt_hsi.h:1704

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Definition: bnxt_hsi.h:8926

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Definition: bnxt_hsi.h:9127

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Definition: bnxt_hsi.h:9801

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Definition: bnxt_hsi.h:7883

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Definition: bnxt_hsi.h:10180

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Definition: bnxt_hsi.h:431

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Definition: bnxt_hsi.h:5799

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Definition: bnxt_hsi.h:1679

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Definition: bnxt_hsi.h:2158

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Definition: bnxt_hsi.h:1495

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Definition: bnxt_hsi.h:1189

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Definition: bnxt_hsi.h:10149

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Definition: bnxt_hsi.h:4573

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Definition: bnxt_hsi.h:3761

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Definition: bnxt_hsi.h:10069

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Definition: bnxt_hsi.h:9941

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Definition: bnxt_hsi.h:1657

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__le32 tqm_ring5_num_entries
Definition: bnxt_hsi.h:2462

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Definition: bnxt_hsi.h:2494

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Definition: bnxt_hsi.h:8108

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Definition: bnxt_hsi.h:1805

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Definition: bnxt_hsi.h:4814

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Definition: bnxt_hsi.h:9910

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Definition: bnxt_hsi.h:8220

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Definition: bnxt_hsi.h:9419

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Definition: bnxt_hsi.h:10230

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Definition: bnxt_hsi.h:9201

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Definition: bnxt_hsi.h:6192

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Definition: bnxt_hsi.h:1504

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Definition: bnxt_hsi.h:863

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Definition: bnxt_hsi.h:3030

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__le16 req_type
Definition: bnxt_hsi.h:2897

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Definition: bnxt_hsi.h:449

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Definition: bnxt_hsi.h:4317

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Definition: bnxt_hsi.h:548

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Definition: bnxt_hsi.h:2082

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Definition: bnxt_hsi.h:2815

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Definition: bnxt_hsi.h:9742

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Definition: bnxt_hsi.h:5120

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Definition: bnxt_hsi.h:1179

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Definition: bnxt_hsi.h:4338

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Definition: bnxt_hsi.h:8802

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Definition: bnxt_hsi.h:10126

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Definition: bnxt_hsi.h:8806

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Definition: bnxt_hsi.h:7652

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Definition: bnxt_hsi.h:5711

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Definition: bnxt_hsi.h:7191

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Definition: bnxt_hsi.h:3028

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Definition: bnxt_hsi.h:7743

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Definition: bnxt_hsi.h:8105

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Definition: bnxt_hsi.h:4277

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Definition: bnxt_hsi.h:8568

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Definition: bnxt_hsi.h:8662

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__le16 max_stat_ctx
Definition: bnxt_hsi.h:2086

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__le32 queue_id6_max_bw
Definition: bnxt_hsi.h:5264

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Definition: bnxt_hsi.h:8784

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Definition: bnxt_hsi.h:8716

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7375

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__le16 target_id
Definition: bnxt_hsi.h:7326

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Definition: bnxt_hsi.h:9949

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Definition: bnxt_hsi.h:4071

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Definition: bnxt_hsi.h:7663

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Definition: bnxt_hsi.h:1272

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Definition: bnxt_hsi.h:9693

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Definition: bnxt_hsi.h:8835

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Definition: bnxt_hsi.h:10580

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Definition: bnxt_hsi.h:10444

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__le32 tqm_ring0_num_entries
Definition: bnxt_hsi.h:2457

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__le16 req_type
Definition: bnxt_hsi.h:7187

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Definition: bnxt_hsi.h:1475

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__le64 ext_flow_handle
Definition: bnxt_hsi.h:7850

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Definition: bnxt_hsi.h:3232

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__le64 tx_512b_1023b_frames
Definition: bnxt_hsi.h:3799

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__le16 mtu
Definition: bnxt_hsi.h:1289

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__le16 vfn[48]
Definition: bnxt_hsi.h:2928

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Definition: bnxt_hsi.h:9421

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Definition: bnxt_hsi.h:1240

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Definition: bnxt_hsi.h:9585

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Definition: bnxt_hsi.h:507

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Definition: bnxt_hsi.h:1658

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Definition: bnxt_hsi.h:9489

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Definition: bnxt_hsi.h:4754

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Definition: bnxt_hsi.h:3019

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Definition: bnxt_hsi.h:1170

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Definition: bnxt_hsi.h:5549

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Definition: bnxt_hsi.h:8180

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Definition: bnxt_hsi.h:596

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Definition: bnxt_hsi.h:7804

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Definition: bnxt_hsi.h:4728

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Definition: bnxt_hsi.h:79

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Definition: bnxt_hsi.h:10008

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__le16 min_vnics
Definition: bnxt_hsi.h:2051

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Definition: bnxt_hsi.h:389

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__le32 flags
Definition: bnxt_hsi.h:7664

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Definition: bnxt_hsi.h:5743

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Definition: bnxt_hsi.h:10166

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Definition: bnxt_hsi.h:4522

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Definition: bnxt_hsi.h:1897

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Definition: bnxt_hsi.h:9811

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Definition: bnxt_hsi.h:6049

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Definition: bnxt_hsi.h:8786

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Definition: bnxt_hsi.h:9849

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Definition: bnxt_hsi.h:3896

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Definition: bnxt_hsi.h:9662

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Definition: bnxt_hsi.h:3989

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Definition: bnxt_hsi.h:3681

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Definition: bnxt_hsi.h:6488

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Definition: bnxt_hsi.h:8840

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Definition: bnxt_hsi.h:8321

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Definition: bnxt_hsi.h:2122

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__le16 resp_len
Definition: bnxt_hsi.h:5902

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Definition: bnxt_hsi.h:2126

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Definition: bnxt_hsi.h:8696

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Definition: bnxt_hsi.h:10600

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Definition: bnxt_hsi.h:6819

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Definition: bnxt_hsi.h:6891

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Definition: bnxt_hsi.h:7328

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Definition: bnxt_hsi.h:9672

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Definition: bnxt_hsi.h:4764

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Definition: bnxt_hsi.h:8834

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Definition: bnxt_hsi.h:9488

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Definition: bnxt_hsi.h:4023

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Definition: bnxt_hsi.h:4780

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Definition: bnxt_hsi.h:9065

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__le32 flow_id
Definition: bnxt_hsi.h:7160

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Definition: bnxt_hsi.h:4710

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__le64 dest_data_addr
Definition: bnxt_hsi.h:10305

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Definition: bnxt_hsi.h:3037

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Definition: bnxt_hsi.h:1648

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Definition: bnxt_hsi.h:9066

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Definition: bnxt_hsi.h:1009

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__le64 pfc_pri0_rx_transitions
Definition: bnxt_hsi.h:4003

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Definition: bnxt_hsi.h:9102

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__le16 req_type
Definition: bnxt_hsi.h:5763

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Definition: bnxt_hsi.h:3543

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Definition: bnxt_hsi.h:5510

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__le16 req_type
Definition: bnxt_hsi.h:4944

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Definition: bnxt_hsi.h:10193

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__le16 test_timeout
Definition: bnxt_hsi.h:10510

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Definition: bnxt_hsi.h:9884

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Definition: bnxt_hsi.h:9164

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__le32 queue_id
Definition: bnxt_hsi.h:4825

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Definition: bnxt_hsi.h:10631

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Definition: bnxt_hsi.h:5901

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Definition: bnxt_hsi.h:8783

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__le64 commands
Definition: bnxt_hsi.h:8510

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__le16 seq_id
Definition: bnxt_hsi.h:7335

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__le16 error_code
Definition: bnxt_hsi.h:6627

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__le16 req_type
Definition: bnxt_hsi.h:9497

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__le32 enables
Definition: bnxt_hsi.h:4312

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Definition: bnxt_hsi.h:953

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Definition: bnxt_hsi.h:6997

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__le16 req_type
Definition: bnxt_hsi.h:10221

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Definition: bnxt_hsi.h:7017

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Definition: bnxt_hsi.h:8571

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__le16 roce_fw_minor
Definition: bnxt_hsi.h:464

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8636

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__le16 seq_id
Definition: bnxt_hsi.h:7756

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Definition: bnxt_hsi.h:7317

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__le64 resp_addr
Definition: bnxt_hsi.h:8547

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Definition: bnxt_hsi.h:9776

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Definition: bnxt_hsi.h:3363

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__le16 error_code
Definition: bnxt_hsi.h:10111

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__le16 cmpl_aggr_dma_tmr_during_int
Definition: bnxt_hsi.h:6438

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__le16 req_type
Definition: bnxt_hsi.h:10198

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__le16 error_code
Definition: bnxt_hsi.h:8370

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__le16 resp_len
Definition: bnxt_hsi.h:7189

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Definition: bnxt_hsi.h:10077

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__le16 dir_idx
Definition: bnxt_hsi.h:10046

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__le16 seq_id
Definition: bnxt_hsi.h:6203

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__le16 req_type
Definition: bnxt_hsi.h:8157

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__le16 seq_id
Definition: bnxt_hsi.h:9334

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Definition: bnxt_hsi.h:8296

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Definition: bnxt_hsi.h:5695

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Definition: bnxt_hsi.h:10261

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u8 tunnel_type
Definition: bnxt_hsi.h:8428

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Definition: bnxt_hsi.h:10192

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Definition: bnxt_hsi.h:7931

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__le32 enables
Definition: bnxt_hsi.h:7666

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__le16 ver_min
Definition: bnxt_hsi.h:2010

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Definition: bnxt_hsi.h:9441

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__le32 queue_id7_max_bw
Definition: bnxt_hsi.h:5647

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__le64 rx_packets_cos5
Definition: bnxt_hsi.h:3999

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Definition: bnxt_hsi.h:1367

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__le16 stag_vid
Definition: bnxt_hsi.h:2872

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__le16 req_type
Definition: bnxt_hsi.h:8635

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__le64 link_down_events
Definition: bnxt_hsi.h:3981

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Definition: bnxt_hsi.h:5590

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Definition: bnxt_hsi.h:3696

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Definition: bnxt_hsi.h:10509

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__le16 target_id
Definition: bnxt_hsi.h:10201

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__le32 enables
Definition: bnxt_hsi.h:1205

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Definition: bnxt_hsi.h:7920

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__le16 min_stat_ctx
Definition: bnxt_hsi.h:2053

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Definition: bnxt_hsi.h:500

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9603

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Definition: bnxt_hsi.h:7280

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Definition: bnxt_hsi.h:5961

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Definition: bnxt_hsi.h:4453

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__le16 led0_blink_off
Definition: bnxt_hsi.h:4385

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__le64 resp_addr
Definition: bnxt_hsi.h:1204

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__le16 flow_handle
Definition: bnxt_hsi.h:8008

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__le32 excess_peak_rate
Definition: bnxt_hsi.h:7552

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__le16 target_id
Definition: bnxt_hsi.h:6397

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Definition: bnxt_hsi.h:6995

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__le16 force_pam4_link_speed
Definition: bnxt_hsi.h:3548

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Definition: bnxt_hsi.h:1731

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Definition: bnxt_hsi.h:10521

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Definition: bnxt_hsi.h:4421

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Definition: bnxt_hsi.h:3031

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__le64 resp_addr
Definition: bnxt_hsi.h:9984

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__le64 resp_addr
Definition: bnxt_hsi.h:1651

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__le16 alloc_sp_tx_rings
Definition: bnxt_hsi.h:1497

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Definition: bnxt_hsi.h:4286

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__le64 packet_6
Definition: bnxt_hsi.h:7983

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__le32 tqm_ring2_num_entries
Definition: bnxt_hsi.h:2459

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__le16 error_code
Definition: bnxt_hsi.h:390

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u8 ver_min_8b
Definition: bnxt_hsi.h:1856

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Definition: bnxt_hsi.h:2025

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__le16 target_id
Definition: bnxt_hsi.h:4025

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Definition: bnxt_hsi.h:6969

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Definition: bnxt_hsi.h:2575

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__le16 req_type
Definition: bnxt_hsi.h:8443

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Definition: bnxt_hsi.h:7924

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__le64 ext_flow_handle
Definition: bnxt_hsi.h:7894

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Definition: bnxt_hsi.h:10476

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__le32 vni
Definition: bnxt_hsi.h:6810

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Definition: bnxt_hsi.h:10465

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u8 qpc_pg_size_qpc_lvl
Definition: bnxt_hsi.h:2527

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__le32 queue_id3_min_bw
Definition: bnxt_hsi.h:5471

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__le64 pfc_pri3_tx_duration_us
Definition: bnxt_hsi.h:3967

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Definition: bnxt_hsi.h:10581

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__le16 resp_len
Definition: bnxt_hsi.h:4328

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__le16 seq_id
Definition: bnxt_hsi.h:5809

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__le16 roce_fw_patch
Definition: bnxt_hsi.h:466

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6094

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__le32 queue_id3_min_bw
Definition: bnxt_hsi.h:5128

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Definition: bnxt_hsi.h:9551

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__le16 resp_len
Definition: bnxt_hsi.h:9499

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__le64 resp_addr
Definition: bnxt_hsi.h:7022

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Definition: bnxt_hsi.h:8476

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__le16 seq_id
Definition: bnxt_hsi.h:7503

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Definition: bnxt_hsi.h:5898

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__le16 req_type
Definition: bnxt_hsi.h:10491

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Definition: bnxt_hsi.h:10234

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__le16 error_code
Definition: bnxt_hsi.h:4792

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Definition: bnxt_hsi.h:2853

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__le16 target_id
Definition: bnxt_hsi.h:8195

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__le16 resp_len
Definition: bnxt_hsi.h:10214

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__le16 seq_id
Definition: bnxt_hsi.h:9709

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__le16 req_type
Definition: bnxt_hsi.h:4306

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Definition: bnxt_hsi.h:2892

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__le16 seq_id
Definition: bnxt_hsi.h:9972

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Definition: bnxt_hsi.h:1225

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Definition: bnxt_hsi.h:9867

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__le16 req_type
Definition: bnxt_hsi.h:6290

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Definition: bnxt_hsi.h:6677

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Definition: bnxt_hsi.h:4160

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Definition: bnxt_hsi.h:3228

__be32
uint32_t __be32
Definition: CIB_PRM.h:26

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__le16 resp_len
Definition: bnxt_hsi.h:9687

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__le16 seq_id
Definition: bnxt_hsi.h:6407

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Definition: bnxt_hsi.h:1991

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Definition: bnxt_hsi.h:5428

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__le16 target_id
Definition: bnxt_hsi.h:6620

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u8 pri0_cos_queue_id
Definition: bnxt_hsi.h:4967

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__le16 req_type
Definition: bnxt_hsi.h:1393

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Definition: bnxt_hsi.h:8435

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Definition: bnxt_hsi.h:6926

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__le16 tx_ts_capture_ptp_msg_type
Definition: bnxt_hsi.h:3655

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Definition: bnxt_hsi.h:5718

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Definition: bnxt_hsi.h:4499

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Definition: bnxt_hsi.h:8630

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__le32 tcp_flow_timer
Definition: bnxt_hsi.h:8076

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Definition: bnxt_hsi.h:7700

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__le16 tim_entry_size
Definition: bnxt_hsi.h:2147

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__le16 req_type
Definition: bnxt_hsi.h:9108

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__le16 resp_len
Definition: bnxt_hsi.h:6172

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Definition: bnxt_hsi.h:8983

hwrm_nvm_raw_dump_input::seq_id
__le16 seq_id
Definition: bnxt_hsi.h:9960

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Definition: bnxt_hsi.h:5722

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__le16 opaque_1
Definition: bnxt_hsi.h:358

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__le64 resp_addr
Definition: bnxt_hsi.h:9446

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Definition: bnxt_hsi.h:1086

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u8 valid
Definition: bnxt_hsi.h:8080

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__le16 timestamp_hi
Definition: bnxt_hsi.h:1002

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__le16 seq_id
Definition: bnxt_hsi.h:2125

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__le16 req_type
Definition: bnxt_hsi.h:7650

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u8 page_size
Definition: bnxt_hsi.h:6226

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__le64 tx_65b_127b_frames
Definition: bnxt_hsi.h:3796

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__le32 enables
Definition: bnxt_hsi.h:6105

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7056

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Definition: bnxt_hsi.h:8878

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__le64 rx_agg_aborts
Definition: bnxt_hsi.h:8599

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__le16 seq_id
Definition: bnxt_hsi.h:9874

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__le16 target_id
Definition: bnxt_hsi.h:7058

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__le16 event_id
Definition: bnxt_hsi.h:822

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Definition: bnxt_hsi.h:7106

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__le32 event_data1
Definition: bnxt_hsi.h:832

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__le32 bkup_power_charge_time
Definition: bnxt_hsi.h:9043

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__le32 reset_reg[16]
Definition: bnxt_hsi.h:1795

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__be16 payload_len
Definition: bnxt_hsi.h:6984

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Definition: bnxt_hsi.h:4842

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__le64 host_src_addr
Definition: bnxt_hsi.h:9916

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Definition: bnxt_hsi.h:8818

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Definition: bnxt_hsi.h:8333

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__le16 target_id
Definition: bnxt_hsi.h:1174

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__le16 seq_id
Definition: bnxt_hsi.h:7020

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__le16 cmpl_ring
Definition: bnxt_hsi.h:5710

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__le16 req_type
Definition: bnxt_hsi.h:4859

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__le32 opaque
Definition: bnxt_hsi.h:483

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Definition: bnxt_hsi.h:6823

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__le16 resp_len
Definition: bnxt_hsi.h:3247

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u8 pri3_to_tc_map
Definition: bnxt_hsi.h:8873

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__le16 resp_len
Definition: bnxt_hsi.h:1969

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Definition: bnxt_hsi.h:9436

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__le64 pfc_pri2_tx_transitions
Definition: bnxt_hsi.h:3966

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__be32 src_ipaddr[4]
Definition: bnxt_hsi.h:7722

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__le16 seq_id
Definition: bnxt_hsi.h:3768

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__le16 req_type
Definition: bnxt_hsi.h:7659

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__le64 tx_bytes_cos7
Definition: bnxt_hsi.h:3952

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__le64 resp_addr
Definition: bnxt_hsi.h:3619

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__le16 seq_id
Definition: bnxt_hsi.h:6350

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__be32 dst_ipaddr[4]
Definition: bnxt_hsi.h:7144

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__le64 tx_ucast_bytes
Definition: bnxt_hsi.h:8495

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Definition: bnxt_hsi.h:9805

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__le16 target_id
Definition: bnxt_hsi.h:6640

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__le16 index_0
Definition: bnxt_hsi.h:10411

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Definition: bnxt_hsi.h:6337

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u8 valid
Definition: bnxt_hsi.h:6483

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__le64 pcie_tx_dllp_statistics
Definition: bnxt_hsi.h:8685

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__le64 pfc_pri5_tx_duration_us
Definition: bnxt_hsi.h:3971

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__le16 vfn[48]
Definition: bnxt_hsi.h:2984

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__le64 tx_hcfc_msgs
Definition: bnxt_hsi.h:3840

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char pair_name[32]
Definition: bnxt_hsi.h:8219

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__le32 flags
Definition: bnxt_hsi.h:4949

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__le16 req_type
Definition: bnxt_hsi.h:28

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__le32 stat_ctx_id
Definition: bnxt_hsi.h:8611

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__le16 error_code
Definition: bnxt_hsi.h:7217

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__le16 cmpl_ring
Definition: bnxt_hsi.h:2020

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Definition: bnxt_hsi.h:6632

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Definition: bnxt_hsi.h:5679

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__le16 resp_len
Definition: bnxt_hsi.h:9408

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__le16 target_id
Definition: bnxt_hsi.h:8362

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__le16 l2_ovlan_mask
Definition: bnxt_hsi.h:6550

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__le16 error_code
Definition: bnxt_hsi.h:8127

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u8 system_name_state
Definition: bnxt_hsi.h:8959

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__le32 update_period_ms
Definition: bnxt_hsi.h:8524

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Definition: bnxt_hsi.h:5873

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__le16 led2_state_caps
Definition: bnxt_hsi.h:4634

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__le16 req_type
Definition: bnxt_hsi.h:1647

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__le16 resp_len
Definition: bnxt_hsi.h:8150

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__le16 dflt_ring_grp
Definition: bnxt_hsi.h:5829

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__le32 enables
Definition: bnxt_hsi.h:7243

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__le16 seq_id
Definition: bnxt_hsi.h:10213

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u8 roce_fw_bld_8b
Definition: bnxt_hsi.h:423

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u8 pf_b_index
Definition: bnxt_hsi.h:8292

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__le64 tx_mcast_bytes
Definition: bnxt_hsi.h:8496

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Definition: bnxt_hsi.h:1236

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__le16 req_type
Definition: bnxt_hsi.h:7589

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__le16 req_type
Definition: bnxt_hsi.h:7844

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__le16 resp_len
Definition: bnxt_hsi.h:5843

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__le32 tlv_value[64]
Definition: bnxt_hsi.h:8995

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__le32 flags
Definition: bnxt_hsi.h:9379

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u8 unused_1[7]
Definition: bnxt_hsi.h:2013

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__le16 error_code
Definition: bnxt_hsi.h:7044

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__le16 seq_id
Definition: bnxt_hsi.h:9264

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u8 valid
Definition: bnxt_hsi.h:8538

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u8 queue_id3_bw_weight
Definition: bnxt_hsi.h:5166

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__le64 tx_packets_cos7
Definition: bnxt_hsi.h:3960

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__le16 seq_id
Definition: bnxt_hsi.h:8670

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__le32 rx_ts_reg_off_upper
Definition: bnxt_hsi.h:3775

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u8 led3_state
Definition: bnxt_hsi.h:4427

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__le64 tx_64b_frames
Definition: bnxt_hsi.h:3795

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u8 queue_id6_bw_weight
Definition: bnxt_hsi.h:5286

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u8 system_cap_state
Definition: bnxt_hsi.h:8967

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__le16 led1_blink_on
Definition: bnxt_hsi.h:4518

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__le16 mrav_entry_size
Definition: bnxt_hsi.h:2146

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__le64 req_buf_page_addr9
Definition: bnxt_hsi.h:1936

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__le16 target_id
Definition: bnxt_hsi.h:7230

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__le32 flags
Definition: bnxt_hsi.h:5925

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__le16 resp_len
Definition: bnxt_hsi.h:9277

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Definition: bnxt_hsi.h:4687

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__le16 error_code
Definition: bnxt_hsi.h:1966

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__le16 target_id
Definition: bnxt_hsi.h:10275

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9263

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__le16 req_type
Definition: bnxt_hsi.h:8101

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__le64 pfc_pri4_tx_transitions
Definition: bnxt_hsi.h:3970

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u8 unused_4[3]
Definition: bnxt_hsi.h:6272

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Definition: bnxt_hsi.h:9689

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__le16 target_id
Definition: bnxt_hsi.h:8426

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u8 unused_0[4]
Definition: bnxt_hsi.h:9237

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__le16 error_code
Definition: bnxt_hsi.h:8797

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u8 t_l2_addr[6]
Definition: bnxt_hsi.h:6554

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__le16 seq_id
Definition: bnxt_hsi.h:6340

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__le16 num_hw_ring_grps
Definition: bnxt_hsi.h:1569

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__le64 resp_addr
Definition: bnxt_hsi.h:3237

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Definition: bnxt_hsi.h:4776

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__le32 src_id
Definition: bnxt_hsi.h:6572

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Definition: bnxt_hsi.h:9975

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Definition: bnxt_hsi.h:547

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Definition: bnxt_hsi.h:7749

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__le16 led2_blink_off
Definition: bnxt_hsi.h:4542

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Definition: bnxt_hsi.h:8715

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Definition: bnxt_hsi.h:9172

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__le16 ring_arb_cfg
Definition: bnxt_hsi.h:6236

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__le16 req_type
Definition: bnxt_hsi.h:4838

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__le16 seq_id
Definition: bnxt_hsi.h:1885

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__le16 timestamp_hi
Definition: bnxt_hsi.h:1045

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u8 code
Definition: bnxt_hsi.h:10053

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Definition: bnxt_hsi.h:3691

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6465

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u8 unused_1[2]
Definition: bnxt_hsi.h:6228

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Definition: bnxt_hsi.h:5205

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Definition: bnxt_hsi.h:1419

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__le64 continuous_pause_events
Definition: bnxt_hsi.h:3982

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__le16 option_num
Definition: bnxt_hsi.h:10307

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__le16 req_type
Definition: bnxt_hsi.h:6617

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u8 pair_mode
Definition: bnxt_hsi.h:8197

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__le16 event_id
Definition: bnxt_hsi.h:1123

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__le16 error_code
Definition: bnxt_hsi.h:6068

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Definition: bnxt_hsi.h:9146

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__le64 resp_addr
Definition: bnxt_hsi.h:2023

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__le16 resp_len
Definition: bnxt_hsi.h:6408

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__le32 event_data2
Definition: bnxt_hsi.h:825

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__le32 vnic_id
Definition: bnxt_hsi.h:5779

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__le16 req_type
Definition: bnxt_hsi.h:1823

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Definition: bnxt_hsi.h:7937

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u8 tqm_ring1_pg_size_tqm_ring1_lvl
Definition: bnxt_hsi.h:2639

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__le16 dir_ordinal
Definition: bnxt_hsi.h:10204

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__le16 dst_id
Definition: bnxt_hsi.h:7118

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__le16 cmpl_ring
Definition: bnxt_hsi.h:2827

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u8 reg_array_cnt
Definition: bnxt_hsi.h:1794

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__le64 pcie_rx_dllp_statistics
Definition: bnxt_hsi.h:8686

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__le16 num_cmpl_dma_aggr_during_int
Definition: bnxt_hsi.h:6413

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Definition: bnxt_hsi.h:1314

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__le16 dir_ordinal
Definition: bnxt_hsi.h:10118

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__le32 flags
Definition: bnxt_hsi.h:4127

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__le16 error_code
Definition: bnxt_hsi.h:8723

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__le16 ring_id
Definition: bnxt_hsi.h:6399

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__le64 packet_8
Definition: bnxt_hsi.h:7985

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__le16 seq_id
Definition: bnxt_hsi.h:7766

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Definition: bnxt_hsi.h:6872

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Definition: bnxt_hsi.h:6285

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__le16 pcie_stat_size
Definition: bnxt_hsi.h:8672

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7502

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__le32 enables
Definition: bnxt_hsi.h:5893

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__le16 target_id
Definition: bnxt_hsi.h:8810

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u8 pf_b_id
Definition: bnxt_hsi.h:8209

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Definition: bnxt_hsi.h:7915

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Definition: bnxt_hsi.h:6179

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__le16 seq_id
Definition: bnxt_hsi.h:4586

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__le16 type
Definition: bnxt_hsi.h:474

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__le16 seq_id
Definition: bnxt_hsi.h:4461

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Definition: bnxt_hsi.h:4989

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__le16 max_rx_rings
Definition: bnxt_hsi.h:2080

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Definition: bnxt_hsi.h:10120

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Definition: bnxt_hsi.h:2821

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__le16 dest_data_buffer_size
Definition: bnxt_hsi.h:5717

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__le16 cmpl_ring
Definition: bnxt_hsi.h:2157

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u8 tunnel_type
Definition: bnxt_hsi.h:8399

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Definition: bnxt_hsi.h:4923

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__le16 seq_id
Definition: bnxt_hsi.h:3246

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__le16 target_id
Definition: bnxt_hsi.h:8397

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__le16 resp_len
Definition: bnxt_hsi.h:3216

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__le32 event_data2
Definition: bnxt_hsi.h:1018

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u8 tlv_type
Definition: bnxt_hsi.h:8984

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__le16 req_type
Definition: bnxt_hsi.h:7881

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Definition: bnxt_hsi.h:1502

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__le16 target_id
Definition: bnxt_hsi.h:6428

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__le64 tx_mcast_pkts
Definition: bnxt_hsi.h:8581

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Definition: bnxt_hsi.h:8537

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__le64 resp_addr
Definition: bnxt_hsi.h:8007

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__le16 max_cmpl_rings
Definition: bnxt_hsi.h:1369

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Definition: bnxt_hsi.h:3253

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Definition: bnxt_hsi.h:9652

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Definition: bnxt_hsi.h:6067

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__le64 lpbk_ucast_frames
Definition: bnxt_hsi.h:4064

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Definition: bnxt_hsi.h:6292

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Definition: bnxt_hsi.h:6870

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Definition: bnxt_hsi.h:2783

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Definition: bnxt_hsi.h:8388

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__le16 error_code
Definition: bnxt_hsi.h:4037

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__le16 target_id
Definition: bnxt_hsi.h:72

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Definition: bnxt_hsi.h:1239

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Definition: bnxt_hsi.h:2623

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Definition: bnxt_hsi.h:2607

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__le16 req_type
Definition: bnxt_hsi.h:1405

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Definition: bnxt_hsi.h:7279

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Definition: bnxt_hsi.h:5350

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Definition: bnxt_hsi.h:9211

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Definition: bnxt_hsi.h:7161

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__le64 tx_bcast_frames
Definition: bnxt_hsi.h:3810

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Definition: bnxt_hsi.h:6205

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__le32 reset_addr_poll
Definition: bnxt_hsi.h:1503

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Definition: bnxt_hsi.h:7200

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Definition: bnxt_hsi.h:6426

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Definition: bnxt_hsi.h:5919

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Definition: bnxt_hsi.h:6915

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Definition: bnxt_hsi.h:7304

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Definition: bnxt_hsi.h:10089

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Definition: bnxt_hsi.h:8113

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Definition: bnxt_hsi.h:7162

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Definition: bnxt_hsi.h:4278

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Definition: bnxt_hsi.h:7049

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Definition: bnxt_hsi.h:1305

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Definition: bnxt_hsi.h:4239

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Definition: bnxt_hsi.h:6303

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Definition: bnxt_hsi.h:9530

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Definition: bnxt_hsi.h:4575

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__le16 req_type
Definition: bnxt_hsi.h:6637

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Definition: bnxt_hsi.h:6396

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Definition: bnxt_hsi.h:445

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__le16 resp_len
Definition: bnxt_hsi.h:4691

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__le64 pfc_pri1_tx_transitions
Definition: bnxt_hsi.h:3964

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__le64 resp_addr
Definition: bnxt_hsi.h:10353

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Definition: bnxt_hsi.h:6139

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Definition: bnxt_hsi.h:7486

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Definition: bnxt_hsi.h:9314

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Definition: bnxt_hsi.h:9711

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__le64 em_filter_id
Definition: bnxt_hsi.h:7353

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Definition: bnxt_hsi.h:2851

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Definition: bnxt_hsi.h:6070

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Definition: bnxt_hsi.h:9117

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__le64 resp_addr
Definition: bnxt_hsi.h:3701

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Definition: bnxt_hsi.h:4389

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__le64 rx_packets_cos7
Definition: bnxt_hsi.h:4001

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Definition: bnxt_hsi.h:726

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Definition: bnxt_hsi.h:4097

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__le16 seq_id
Definition: bnxt_hsi.h:1873

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Definition: bnxt_hsi.h:5777

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Definition: bnxt_hsi.h:9364

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__le32 tx_ts_reg_off_upper
Definition: bnxt_hsi.h:3785

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__le16 seq_id
Definition: bnxt_hsi.h:9050

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Definition: bnxt_hsi.h:2031

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__le16 l2_ivlan
Definition: bnxt_hsi.h:6551

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Definition: bnxt_hsi.h:9788

hwrm_fw_ipc_mailbox_output::resp_len
__le16 resp_len
Definition: bnxt_hsi.h:9184

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Definition: bnxt_hsi.h:7363

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__le16 seq_id
Definition: bnxt_hsi.h:4909

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__le16 error_code
Definition: bnxt_hsi.h:3766

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__le16 resp_len
Definition: bnxt_hsi.h:7047

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__le32 rx_ts_reg_off_fifo
Definition: bnxt_hsi.h:3781

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Definition: bnxt_hsi.h:8600

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__le16 req_type
Definition: bnxt_hsi.h:1248

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__le16 req_type
Definition: bnxt_hsi.h:7055

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10222

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u8 profile
Definition: bnxt_hsi.h:7904

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__le16 seq_id
Definition: bnxt_hsi.h:355

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__le16 req_type
Definition: bnxt_hsi.h:8606

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__le64 lpbk_mcast_frames
Definition: bnxt_hsi.h:4065

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__le32 reserved3
Definition: bnxt_hsi.h:6247

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__le16 req_type
Definition: bnxt_hsi.h:6180

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__le16 seq_id
Definition: bnxt_hsi.h:6767

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__le32 queue_id4_max_bw
Definition: bnxt_hsi.h:5184

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__le16 index_0
Definition: bnxt_hsi.h:10361

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Definition: bnxt_hsi.h:9410

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__le16 error_code
Definition: bnxt_hsi.h:10211

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__le32 commit_burst
Definition: bnxt_hsi.h:7536

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__le16 error_code
Definition: bnxt_hsi.h:4688

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__le16 ver_maj
Definition: bnxt_hsi.h:1863

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__le32 encap_request[26]
Definition: bnxt_hsi.h:9267

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__le16 flow_handle_6
Definition: bnxt_hsi.h:7954

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Definition: bnxt_hsi.h:871

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__le64 tx_packets_cos3
Definition: bnxt_hsi.h:3956

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__le16 req_type
Definition: bnxt_hsi.h:9297

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__le16 ver_min
Definition: bnxt_hsi.h:1864

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__le16 instance
Definition: bnxt_hsi.h:9799

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Definition: bnxt_hsi.h:6816

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__le32 checksum
Definition: bnxt_hsi.h:10183

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__le16 req_type
Definition: bnxt_hsi.h:354

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Definition: bnxt_hsi.h:8903

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__le16 resp_len
Definition: bnxt_hsi.h:9663

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__le16 seq_id
Definition: bnxt_hsi.h:392

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__le64 resp_addr
Definition: bnxt_hsi.h:73

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__le16 req_type
Definition: bnxt_hsi.h:3245

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Definition: bnxt_hsi.h:8477

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__le16 error_code
Definition: bnxt_hsi.h:8279

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__le64 resp_addr
Definition: bnxt_hsi.h:6621

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Definition: bnxt_hsi.h:9477

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__le16 tx_stat_size
Definition: bnxt_hsi.h:4041

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__le32 unused0
Definition: bnxt_hsi.h:523

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__le16 req_type
Definition: bnxt_hsi.h:6394

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__le16 target_id
Definition: bnxt_hsi.h:380

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__le16 error_code
Definition: bnxt_hsi.h:5753

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Definition: bnxt_hsi.h:1653

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__le16 mtu
Definition: bnxt_hsi.h:1427

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Definition: bnxt_hsi.h:424

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__le16 target_id
Definition: bnxt_hsi.h:7377

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__le64 rx_trunc_frames
Definition: bnxt_hsi.h:3883

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9695

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__le32 commit_burst
Definition: bnxt_hsi.h:7407

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__le16 seq_id
Definition: bnxt_hsi.h:9109

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u8 timestamp_lo
Definition: bnxt_hsi.h:781

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__le32 rx_ts_reg_off_src_id_0
Definition: bnxt_hsi.h:3777

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Definition: bnxt_hsi.h:7737

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__le64 rx_align_err_frames
Definition: bnxt_hsi.h:3872

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__le64 rx_double_tagged_frames
Definition: bnxt_hsi.h:3882

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u8 unused_1[4]
Definition: bnxt_hsi.h:6333

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__le64 resp_addr
Definition: bnxt_hsi.h:9131

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__le16 req_type
Definition: bnxt_hsi.h:6128

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__le16 seq_id
Definition: bnxt_hsi.h:7944

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__le16 error_code
Definition: bnxt_hsi.h:7973

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Definition: bnxt_hsi.h:8242

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__le16 pattern_offset
Definition: bnxt_hsi.h:9473

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u8 dst_macaddr[6]
Definition: bnxt_hsi.h:7284

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__le16 req_type
Definition: bnxt_hsi.h:5002

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__le16 resp_len
Definition: bnxt_hsi.h:8330

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Definition: bnxt_hsi.h:1703

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__le64 pfc_pri0_rx_duration_us
Definition: bnxt_hsi.h:4002

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u8 valid
Definition: bnxt_hsi.h:8132

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u8 queue_id5_pri_lvl
Definition: bnxt_hsi.h:5245

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__le16 target_id
Definition: bnxt_hsi.h:8246

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__le16 error_code
Definition: bnxt_hsi.h:4449

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__le64 rx_1519b_2047b_frames
Definition: bnxt_hsi.h:3857

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Definition: bnxt_hsi.h:9994

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__le16 target_id
Definition: bnxt_hsi.h:8742

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__le16 resp_len
Definition: bnxt_hsi.h:5726

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__le32 max_bw
Definition: bnxt_hsi.h:6250

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__le16 req_type
Definition: bnxt_hsi.h:4139

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Definition: bnxt_hsi.h:1505

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u8 pri2_cos_queue_id
Definition: bnxt_hsi.h:4969

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u8 valid
Definition: bnxt_hsi.h:10286

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__le64 resp_addr
Definition: bnxt_hsi.h:7634

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9307

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__le64 stat_page_dir
Definition: bnxt_hsi.h:2787

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__le16 cmpl_ring
Definition: bnxt_hsi.h:5764

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__le16 seq_id
Definition: bnxt_hsi.h:10174

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__le32 new_dst_id
Definition: bnxt_hsi.h:7354

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char roce_fw_name[16]
Definition: bnxt_hsi.h:429

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__le16 seq_id
Definition: bnxt_hsi.h:6925

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__le64 resp_addr
Definition: bnxt_hsi.h:6132

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9673

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__le64 pcie_dl_signal_integrity
Definition: bnxt_hsi.h:8680

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u8 flags
Definition: bnxt_hsi.h:10316

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__le32 flags
Definition: bnxt_hsi.h:6143

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__le16 rx_ts_capture_ptp_msg_type
Definition: bnxt_hsi.h:3654

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__le16 auto_link_speed
Definition: bnxt_hsi.h:3333

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Definition: bnxt_hsi.h:2915

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__le32 dbg_data_len
Definition: bnxt_hsi.h:9665

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__le16 meter_instance_id
Definition: bnxt_hsi.h:7621

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__le16 req_type
Definition: bnxt_hsi.h:1638

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Definition: bnxt_hsi.h:4021

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__le16 req_type
Definition: bnxt_hsi.h:5900

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Definition: bnxt_hsi.h:4651

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u8 srq_pg_size_srq_lvl
Definition: bnxt_hsi.h:2196

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__le64 tx_bytes_cos0
Definition: bnxt_hsi.h:3945

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u8 options
Definition: bnxt_hsi.h:1480

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u8 vnic_pg_size_vnic_lvl
Definition: bnxt_hsi.h:2228

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__le16 fid
Definition: bnxt_hsi.h:1398

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Definition: bnxt_hsi.h:8559

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__le32 flow_id_1
Definition: bnxt_hsi.h:7960

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__le16 num_hw_ring_grps
Definition: bnxt_hsi.h:1309

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__le16 rx_ring_id
Definition: bnxt_hsi.h:6234

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Definition: bnxt_hsi.h:8655

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__le64 pfc_pri4_tx_duration_us
Definition: bnxt_hsi.h:3969

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__le16 req_type
Definition: bnxt_hsi.h:8230

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__le64 byte_3
Definition: bnxt_hsi.h:7990

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__le64 resp_addr
Definition: bnxt_hsi.h:4781

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__le64 tx_9217b_16383b_frames
Definition: bnxt_hsi.h:3805

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Definition: bnxt_hsi.h:6735

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__le16 alloc_rsscos_ctx
Definition: bnxt_hsi.h:1421

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__le64 tx_pfc_ena_frames_pri1
Definition: bnxt_hsi.h:3830

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__le16 target_id
Definition: bnxt_hsi.h:9051

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Definition: bnxt_hsi.h:8938

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Definition: bnxt_hsi.h:1143

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__le64 tx_bytes_cos3
Definition: bnxt_hsi.h:3948

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Definition: bnxt_hsi.h:6993

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__le64 rx_unsupported_da_pausepfc_frames
Definition: bnxt_hsi.h:3870

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Definition: bnxt_hsi.h:5839

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Definition: bnxt_hsi.h:1977

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__le16 new_pf_fid
Definition: bnxt_hsi.h:8213

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Definition: bnxt_hsi.h:7590

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Definition: bnxt_hsi.h:1982

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__le32 len
Definition: bnxt_hsi.h:9965

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Definition: bnxt_hsi.h:5724

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Definition: bnxt_hsi.h:9771

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Definition: bnxt_hsi.h:6018

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__le16 error_code
Definition: bnxt_hsi.h:10576

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Definition: bnxt_hsi.h:8597

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Definition: bnxt_hsi.h:3708

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Definition: bnxt_hsi.h:6080

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Definition: bnxt_hsi.h:5687

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Definition: bnxt_hsi.h:8534

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Definition: bnxt_hsi.h:10013

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__le64 tx_multi_coll_frames
Definition: bnxt_hsi.h:3820

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Definition: bnxt_hsi.h:6183

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Definition: bnxt_hsi.h:8525

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Definition: bnxt_hsi.h:9830

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Definition: bnxt_hsi.h:8921

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Definition: bnxt_hsi.h:6842

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Definition: bnxt_hsi.h:5729

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Definition: bnxt_hsi.h:5086

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Definition: bnxt_hsi.h:1710

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Definition: bnxt_hsi.h:442

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Definition: bnxt_hsi.h:7081

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Definition: bnxt_hsi.h:9462

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Definition: bnxt_hsi.h:5248

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__le16 req_type
Definition: bnxt_hsi.h:8739

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Definition: bnxt_hsi.h:855

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Definition: bnxt_hsi.h:8629

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Definition: bnxt_hsi.h:7495

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__le16 error_code
Definition: bnxt_hsi.h:10041

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Definition: bnxt_hsi.h:1946

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Definition: bnxt_hsi.h:7459

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Definition: bnxt_hsi.h:4240

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Definition: bnxt_hsi.h:8020

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Definition: bnxt_hsi.h:9156

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Definition: bnxt_hsi.h:2071

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__le64 l2_filter_id
Definition: bnxt_hsi.h:7105

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__le64 pcie_link_integrity
Definition: bnxt_hsi.h:8682

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__le32 flags
Definition: bnxt_hsi.h:5874

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Definition: bnxt_hsi.h:7001

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Definition: bnxt_hsi.h:4589

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Definition: bnxt_hsi.h:10021

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Definition: bnxt_hsi.h:9819

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Definition: bnxt_hsi.h:4995

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Definition: bnxt_hsi.h:7810

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__le64 rx_drop_pkts
Definition: bnxt_hsi.h:8486

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Definition: bnxt_hsi.h:2876

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__le32 encap_async_event_cmpl[4]
Definition: bnxt_hsi.h:9339

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Definition: bnxt_hsi.h:9792

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Definition: bnxt_hsi.h:4745

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Definition: bnxt_hsi.h:9437

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__le16 num_flows
Definition: bnxt_hsi.h:7947

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__le32 queue_id6_min_bw
Definition: bnxt_hsi.h:5591

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__le32 event_data1
Definition: bnxt_hsi.h:955

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__le16 pattern_size
Definition: bnxt_hsi.h:9474

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Definition: bnxt_hsi.h:3721

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__le16 support_pam4_speeds
Definition: bnxt_hsi.h:3544

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Definition: bnxt_hsi.h:10083

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Definition: bnxt_hsi.h:399

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__le16 chip_num
Definition: bnxt_hsi.h:430

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Definition: bnxt_hsi.h:6764

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__le16 flow_handle_4
Definition: bnxt_hsi.h:7952

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Definition: bnxt_hsi.h:1894

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Definition: bnxt_hsi.h:5863

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__le16 seq_id
Definition: bnxt_hsi.h:9298

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Definition: bnxt_hsi.h:777

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Definition: bnxt_hsi.h:2089

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Definition: bnxt_hsi.h:4793

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__le32 max_tcp_flow_timer
Definition: bnxt_hsi.h:8104

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__le16 seq_id
Definition: bnxt_hsi.h:4124

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Definition: bnxt_hsi.h:9054

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Definition: bnxt_hsi.h:6404

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Definition: bnxt_hsi.h:4517

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Definition: bnxt_hsi.h:8796

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__le16 error_code
Definition: bnxt_hsi.h:4924

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__be32 vni
Definition: bnxt_hsi.h:7009

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Definition: bnxt_hsi.h:9817

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__le16 seq_id
Definition: bnxt_hsi.h:9913

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__le64 tx_stat_discard
Definition: bnxt_hsi.h:3844

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Definition: bnxt_hsi.h:468

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Definition: bnxt_hsi.h:10073

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Definition: bnxt_hsi.h:10128

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Definition: bnxt_hsi.h:9482

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__le16 req_type
Definition: bnxt_hsi.h:4113

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Definition: bnxt_hsi.h:7941

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__le16 cq_entry_size
Definition: bnxt_hsi.h:2136

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Definition: bnxt_hsi.h:6571

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Definition: bnxt_hsi.h:7625

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Definition: bnxt_hsi.h:5388

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__le16 seq_id
Definition: bnxt_hsi.h:4472

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Definition: bnxt_hsi.h:3767

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Definition: bnxt_hsi.h:9858

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Definition: bnxt_hsi.h:4062

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Definition: bnxt_hsi.h:2108

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Definition: bnxt_hsi.h:8994

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Definition: bnxt_hsi.h:6079

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Definition: bnxt_hsi.h:7312

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Definition: bnxt_hsi.h:1193

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Definition: bnxt_hsi.h:9939

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Definition: bnxt_hsi.h:2260

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Definition: bnxt_hsi.h:4982

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Definition: bnxt_hsi.h:9158

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__le64 packet_4
Definition: bnxt_hsi.h:7981

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__le64 vnic_id_tbl_addr
Definition: bnxt_hsi.h:2905

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__le32 v
Definition: bnxt_hsi.h:508

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__le64 rx_bytes_cos4
Definition: bnxt_hsi.h:3990

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__le16 seq_id
Definition: bnxt_hsi.h:3215

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__le16 num_l2_ctxs
Definition: bnxt_hsi.h:1306

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__le16 cmpl_ring
Definition: bnxt_hsi.h:5808

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Definition: bnxt_hsi.h:4596

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__le16 cmpl_aggr_dma_tmr_max
Definition: bnxt_hsi.h:6378

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__le16 req_type
Definition: bnxt_hsi.h:2979

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Definition: bnxt_hsi.h:1720

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Definition: bnxt_hsi.h:9964

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__le64 pfc_pri6_rx_duration_us
Definition: bnxt_hsi.h:4014

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__le16 cmpl_aggr_dma_tmr_during_int_min
Definition: bnxt_hsi.h:6379

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Definition: bnxt_hsi.h:7085

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__le64 resp_addr
Definition: bnxt_hsi.h:4107

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Definition: bnxt_hsi.h:4284

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__le16 error_code
Definition: bnxt_hsi.h:8100

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Definition: bnxt_hsi.h:9730

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Definition: bnxt_hsi.h:5000

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u8 led0_group_id
Definition: bnxt_hsi.h:4386

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Definition: bnxt_hsi.h:7629

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__le16 srq_num_l2_entries
Definition: bnxt_hsi.h:2470

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__le16 resp_len
Definition: bnxt_hsi.h:356

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__le16 entry_cnt
Definition: bnxt_hsi.h:5727

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Definition: bnxt_hsi.h:8809

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Definition: bnxt_hsi.h:7068

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Definition: bnxt_hsi.h:4311

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__le16 mtu
Definition: bnxt_hsi.h:1560

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__le64 pfc_pri6_tx_duration_us
Definition: bnxt_hsi.h:3973

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Definition: bnxt_hsi.h:9743

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Definition: bnxt_hsi.h:8187

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Definition: bnxt_hsi.h:3038

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Definition: bnxt_hsi.h:9683

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__le16 req_type
Definition: bnxt_hsi.h:10380

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Definition: bnxt_hsi.h:9922

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Definition: bnxt_hsi.h:5328

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Definition: bnxt_hsi.h:538

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Definition: bnxt_hsi.h:4319

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Definition: bnxt_hsi.h:8194

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Definition: bnxt_hsi.h:9048

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Definition: bnxt_hsi.h:8103

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Definition: bnxt_hsi.h:9006

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Definition: bnxt_hsi.h:9305

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__le16 target_id
Definition: bnxt_hsi.h:9759

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Definition: bnxt_hsi.h:9595

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Definition: bnxt_hsi.h:1983

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__le16 alloc_l2_ctx
Definition: bnxt_hsi.h:1425

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Definition: bnxt_hsi.h:9338

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Definition: bnxt_hsi.h:6908

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__le32 rx_ts_reg_off_seq_id
Definition: bnxt_hsi.h:3776

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Definition: bnxt_hsi.h:10165

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Definition: bnxt_hsi.h:9712

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Definition: bnxt_hsi.h:731

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Definition: bnxt_hsi.h:9508

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__le64 resp_addr
Definition: bnxt_hsi.h:8660

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Definition: bnxt_hsi.h:2115

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__le16 ivlan_vid
Definition: bnxt_hsi.h:7286

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Definition: bnxt_hsi.h:7322

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__le16 req_type
Definition: bnxt_hsi.h:10079

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Definition: bnxt_hsi.h:6879

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Definition: bnxt_hsi.h:5429

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Definition: bnxt_hsi.h:3715

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__le32 cq_max_entries
Definition: bnxt_hsi.h:2135

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Definition: bnxt_hsi.h:1102

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__le16 dest_fid
Definition: bnxt_hsi.h:6953

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__le64 tx_discard_pkts
Definition: bnxt_hsi.h:8493

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Definition: bnxt_hsi.h:3481

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Definition: bnxt_hsi.h:9878

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Definition: bnxt_hsi.h:7222

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__le32 stat_ctx_id
Definition: bnxt_hsi.h:8640

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Definition: bnxt_hsi.h:2005

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Definition: bnxt_hsi.h:1724

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Definition: bnxt_hsi.h:8678

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Definition: bnxt_hsi.h:4797

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Definition: bnxt_hsi.h:4543

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__le64 rx_pfc_xon2xoff_frames_pri0
Definition: bnxt_hsi.h:3885

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Definition: bnxt_hsi.h:10142

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__le16 error_code
Definition: bnxt_hsi.h:4093

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Definition: bnxt_hsi.h:4777

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Definition: bnxt_hsi.h:10384

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Definition: bnxt_hsi.h:8897

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__le64 tx_bcast_pkts
Definition: bnxt_hsi.h:1664

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__le16 target_id
Definition: bnxt_hsi.h:2967

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__le16 req_type
Definition: bnxt_hsi.h:4022

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Definition: bnxt_hsi.h:8971

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__le16 req_type
Definition: bnxt_hsi.h:4150

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Definition: bnxt_hsi.h:6548

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__le32 num_of_entries
Definition: bnxt_hsi.h:9587

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8454

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Definition: bnxt_hsi.h:9888

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__le32 encap_record_id
Definition: bnxt_hsi.h:7305

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Definition: bnxt_hsi.h:969

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Definition: bnxt_hsi.h:8067

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Definition: bnxt_hsi.h:6591

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Definition: bnxt_hsi.h:3006

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__le16 vfn[48]
Definition: bnxt_hsi.h:2971

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Definition: bnxt_hsi.h:2808

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Definition: bnxt_hsi.h:6196

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Definition: bnxt_hsi.h:9106

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__le16 cq_num_l2_entries
Definition: bnxt_hsi.h:2804

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Definition: bnxt_hsi.h:6213

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Definition: bnxt_hsi.h:10364

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Definition: bnxt_hsi.h:8542

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Definition: bnxt_hsi.h:9007

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__le32 tx_ts_reg_off_granularity
Definition: bnxt_hsi.h:3788

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__le16 max_vfs
Definition: bnxt_hsi.h:1375

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__le16 netctrl_fw_build
Definition: bnxt_hsi.h:461

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Definition: bnxt_hsi.h:9268

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Definition: bnxt_hsi.h:6021

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Definition: bnxt_hsi.h:2022

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Definition: bnxt_hsi.h:3618

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Definition: bnxt_hsi.h:9025

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Definition: bnxt_hsi.h:4471

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Definition: bnxt_hsi.h:3921

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Definition: bnxt_hsi.h:407

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__le64 pcie_equalization_time
Definition: bnxt_hsi.h:8687

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Definition: bnxt_hsi.h:8609

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Definition: bnxt_hsi.h:1342

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Definition: bnxt_hsi.h:9824

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Definition: bnxt_hsi.h:3909

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Definition: bnxt_hsi.h:2926

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__le16 reserved_rsscos_ctx
Definition: bnxt_hsi.h:2100

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Definition: bnxt_hsi.h:8882

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__le64 resp_addr
Definition: bnxt_hsi.h:8089

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__le32 new_dst_id
Definition: bnxt_hsi.h:7207

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Definition: bnxt_hsi.h:8272

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__le16 seq_id
Definition: bnxt_hsi.h:5974

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__le16 resp_len
Definition: bnxt_hsi.h:8557

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__le32 mgmt_addr[8]
Definition: bnxt_hsi.h:9004

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__le64 resp_addr
Definition: bnxt_hsi.h:9336

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__le16 seq_id
Definition: bnxt_hsi.h:1173

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Definition: bnxt_hsi.h:954

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Definition: bnxt_hsi.h:9291

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__le16 resp_buf_len
Definition: bnxt_hsi.h:1925

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__le16 error_code
Definition: bnxt_hsi.h:7932

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Definition: bnxt_hsi.h:2807

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Definition: bnxt_hsi.h:6168

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u8 queue_id2_service_profile
Definition: bnxt_hsi.h:4719

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__le64 rx_total_frames
Definition: bnxt_hsi.h:3861

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Definition: bnxt_hsi.h:8084

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__le16 seq_id
Definition: bnxt_hsi.h:8455

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Definition: bnxt_hsi.h:5588

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__le16 req_type
Definition: bnxt_hsi.h:10567

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Definition: bnxt_hsi.h:1191

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__le64 resp_addr
Definition: bnxt_hsi.h:2118

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__le16 rss_cos_lb_ctx_id
Definition: bnxt_hsi.h:6185

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__le64 resp_addr
Definition: bnxt_hsi.h:5689

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__le64 tx_pfc_ena_frames_pri6
Definition: bnxt_hsi.h:3835

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__le16 num_vfs
Definition: bnxt_hsi.h:1232

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Definition: bnxt_hsi.h:7685

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Definition: bnxt_hsi.h:7903

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__le64 resp_addr
Definition: bnxt_hsi.h:1397

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__le16 seq_id
Definition: bnxt_hsi.h:8329

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__le16 seq_id
Definition: bnxt_hsi.h:8116

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Definition: bnxt_hsi.h:1511

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Definition: bnxt_hsi.h:9702

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Definition: bnxt_hsi.h:9597

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Definition: bnxt_hsi.h:8651

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Definition: bnxt_hsi.h:473

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8774

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__le16 seq_id
Definition: bnxt_hsi.h:6427

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Definition: bnxt_hsi.h:5882

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__le16 len
Definition: bnxt_hsi.h:8853

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Definition: bnxt_hsi.h:421

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__le16 ar_id
Definition: bnxt_hsi.h:7911

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Definition: bnxt_hsi.h:6388

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__le16 seq_id
Definition: bnxt_hsi.h:8396

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Definition: bnxt_hsi.h:9928

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__le16 target_id
Definition: bnxt_hsi.h:4850

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Definition: bnxt_hsi.h:1056

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Definition: bnxt_hsi.h:9126

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8808

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__le16 target_id
Definition: bnxt_hsi.h:5738

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Definition: bnxt_hsi.h:631

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__le16 error_code
Definition: bnxt_hsi.h:7364

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__le16 seq_id
Definition: bnxt_hsi.h:5985

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Definition: bnxt_hsi.h:4985

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Definition: bnxt_hsi.h:9481

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__le16 min_tx_rings
Definition: bnxt_hsi.h:2077

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Definition: bnxt_hsi.h:8252

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Definition: bnxt_hsi.h:7859

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Definition: bnxt_hsi.h:6319

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Definition: bnxt_hsi.h:8354

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__le16 req_type
Definition: bnxt_hsi.h:9243

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Definition: bnxt_hsi.h:978

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Definition: bnxt_hsi.h:6060

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Definition: bnxt_hsi.h:6876

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__le16 error_code
Definition: bnxt_hsi.h:6605

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__le64 rx_bcast_frames
Definition: bnxt_hsi.h:3864

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Definition: bnxt_hsi.h:9472

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__le16 req_type
Definition: bnxt_hsi.h:7018

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__le64 tqm_ring2_page_dir
Definition: bnxt_hsi.h:2444

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Definition: bnxt_hsi.h:2959

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Definition: bnxt_hsi.h:7156

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Definition: bnxt_hsi.h:6699

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Definition: bnxt_hsi.h:9873

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Definition: bnxt_hsi.h:3027

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Definition: bnxt_hsi.h:4340

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Definition: bnxt_hsi.h:6230

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Definition: bnxt_hsi.h:9149

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__le32 min_agg_len
Definition: bnxt_hsi.h:6012

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__le16 flags
Definition: bnxt_hsi.h:2058

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__le16 seq_id
Definition: bnxt_hsi.h:10545

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__le16 flow_handle_9
Definition: bnxt_hsi.h:7957

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__le16 resp_len
Definition: bnxt_hsi.h:4299

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Definition: bnxt_hsi.h:3692

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Definition: bnxt_hsi.h:428

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__le16 rx_cfa_code
Definition: bnxt_hsi.h:8331

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__le16 req_type
Definition: bnxt_hsi.h:10000

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__le64 rx_pfc_xon2xoff_frames_pri7
Definition: bnxt_hsi.h:3892

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__le16 seq_id
Definition: bnxt_hsi.h:9286

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Definition: bnxt_hsi.h:9047

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Definition: bnxt_hsi.h:4588

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__le64 tx_excessive_coll_frames
Definition: bnxt_hsi.h:3822

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__le16 port_id
Definition: bnxt_hsi.h:4678

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__le32 event_data2
Definition: bnxt_hsi.h:604

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__le16 seq_id
Definition: bnxt_hsi.h:8087

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__le16 encap_resp_len
Definition: bnxt_hsi.h:9313

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__le16 req_type
Definition: bnxt_hsi.h:7334

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__le16 resp_len
Definition: bnxt_hsi.h:9851

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u8 vlan_pri2cos_map_pri
Definition: bnxt_hsi.h:3650

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__le16 target_id
Definition: bnxt_hsi.h:8659

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__le64 rx_undrsz_frames
Definition: bnxt_hsi.h:3902

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Definition: bnxt_hsi.h:433

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Definition: bnxt_hsi.h:6636

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Definition: bnxt_hsi.h:4736

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Definition: bnxt_hsi.h:585

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__le16 req_type
Definition: bnxt_hsi.h:4276

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__le16 req_type
Definition: bnxt_hsi.h:3755

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Definition: bnxt_hsi.h:2874

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7197

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Definition: bnxt_hsi.h:6663

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4811

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Definition: bnxt_hsi.h:4668

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Definition: bnxt_hsi.h:446

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Definition: bnxt_hsi.h:2113

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__le16 target_id
Definition: bnxt_hsi.h:7021

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__le16 index_2
Definition: bnxt_hsi.h:10363

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__le16 component_id
Definition: bnxt_hsi.h:9797

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Definition: bnxt_hsi.h:7221

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Definition: bnxt_hsi.h:10517

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Definition: bnxt_hsi.h:382

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__le16 target_id
Definition: bnxt_hsi.h:1956

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__le16 port_id
Definition: bnxt_hsi.h:3643

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__le16 rss_cos_lb_ctx_id
Definition: bnxt_hsi.h:6173

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__le64 req_buf_page_addr0
Definition: bnxt_hsi.h:1927

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__le16 resp_len
Definition: bnxt_hsi.h:8445

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Definition: bnxt_hsi.h:10256

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__le16 tx_cfa_action
Definition: bnxt_hsi.h:8332

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__le64 rx_mcast_pkts
Definition: bnxt_hsi.h:8483

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__le64 resp_addr
Definition: bnxt_hsi.h:1514

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__le16 seq_id
Definition: bnxt_hsi.h:10190

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__le64 resp_addr
Definition: bnxt_hsi.h:1275

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__le16 error_code
Definition: bnxt_hsi.h:27

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__be16 l2_rewrite_vlan_tci
Definition: bnxt_hsi.h:7803

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10148

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__le16 seq_id
Definition: bnxt_hsi.h:7661

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__le32 queue_id4_min_bw
Definition: bnxt_hsi.h:5168

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__le32 consumer_index
Definition: bnxt_hsi.h:9904

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__le32 rx_ts_reg_off_granularity
Definition: bnxt_hsi.h:3783

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__le16 req_type
Definition: bnxt_hsi.h:7343

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Definition: bnxt_hsi.h:4663

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Definition: bnxt_hsi.h:2843

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__le16 req_type
Definition: bnxt_hsi.h:7218

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Definition: bnxt_hsi.h:5287

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Definition: bnxt_hsi.h:4871

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__le32 event_data2
Definition: bnxt_hsi.h:754

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__le16 seq_id
Definition: bnxt_hsi.h:8129

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Definition: bnxt_hsi.h:8555

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Definition: bnxt_hsi.h:7880

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Definition: bnxt_hsi.h:9160

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Definition: bnxt_hsi.h:10389

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__le16 event_id
Definition: bnxt_hsi.h:921

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Definition: bnxt_hsi.h:482

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Definition: bnxt_hsi.h:7313

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Definition: bnxt_hsi.h:9524

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Definition: bnxt_hsi.h:7226

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Definition: bnxt_hsi.h:4177

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Definition: bnxt_hsi.h:4550

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Definition: bnxt_hsi.h:8724

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Definition: bnxt_hsi.h:2161

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Definition: bnxt_hsi.h:2076

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Definition: bnxt_hsi.h:5737

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Definition: bnxt_hsi.h:3937

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Definition: bnxt_hsi.h:611

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Definition: bnxt_hsi.h:9796

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Definition: bnxt_hsi.h:3998

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Definition: bnxt_hsi.h:1862

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Definition: bnxt_hsi.h:9814

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Definition: bnxt_hsi.h:8558

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Definition: bnxt_hsi.h:7186

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Definition: bnxt_hsi.h:6841

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Definition: bnxt_hsi.h:8587

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Definition: bnxt_hsi.h:9049

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Definition: bnxt_hsi.h:648

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Definition: bnxt_hsi.h:8623

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Definition: bnxt_hsi.h:3891

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Definition: bnxt_hsi.h:2133

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Definition: bnxt_hsi.h:10531

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Definition: bnxt_hsi.h:9934

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Definition: bnxt_hsi.h:8034

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Definition: bnxt_hsi.h:2441

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Definition: bnxt_hsi.h:8628

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Definition: bnxt_hsi.h:2107

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Definition: bnxt_hsi.h:9963

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Definition: bnxt_hsi.h:353

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Definition: bnxt_hsi.h:6476

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Definition: bnxt_hsi.h:1857

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Definition: bnxt_hsi.h:1561

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Definition: bnxt_hsi.h:2801

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Definition: bnxt_hsi.h:4791

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Definition: bnxt_hsi.h:9686

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Definition: bnxt_hsi.h:8545

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Definition: bnxt_hsi.h:8564

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Definition: bnxt_hsi.h:2477

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Definition: bnxt_hsi.h:4281

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Definition: bnxt_hsi.h:3903

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Definition: bnxt_hsi.h:2784

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Definition: bnxt_hsi.h:1938

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Definition: bnxt_hsi.h:4229

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Definition: bnxt_hsi.h:2159

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Definition: bnxt_hsi.h:9464

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Definition: bnxt_hsi.h:8472

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Definition: bnxt_hsi.h:6914

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Definition: bnxt_hsi.h:6789

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Definition: bnxt_hsi.h:5869

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Definition: bnxt_hsi.h:3035

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__le32 master_wait_post_reset
Definition: bnxt_hsi.h:1750

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Definition: bnxt_hsi.h:7846

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__le64 pfc_pri5_rx_transitions
Definition: bnxt_hsi.h:4013

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Definition: bnxt_hsi.h:3373

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Definition: bnxt_hsi.h:4140

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Definition: bnxt_hsi.h:826

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Definition: bnxt_hsi.h:4086

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Definition: bnxt_hsi.h:6123

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Definition: bnxt_hsi.h:405

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__le64 eng_bytes_out
Definition: bnxt_hsi.h:8507

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Definition: bnxt_hsi.h:7817

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Definition: bnxt_hsi.h:972

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Definition: bnxt_hsi.h:4387

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Definition: bnxt_hsi.h:9373

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Definition: bnxt_hsi.h:10433

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__le32 flow_id
Definition: bnxt_hsi.h:7849

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Definition: bnxt_hsi.h:7493

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Definition: bnxt_hsi.h:3614

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__le16 meter_profile_id
Definition: bnxt_hsi.h:7609

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Definition: bnxt_hsi.h:5048

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Definition: bnxt_hsi.h:9721

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Definition: bnxt_hsi.h:4876

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Definition: bnxt_hsi.h:9327

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Definition: bnxt_hsi.h:6232

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Definition: bnxt_hsi.h:7365

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Definition: bnxt_hsi.h:9085

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Definition: bnxt_hsi.h:8274

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Definition: bnxt_hsi.h:7458

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__le16 resp_len
Definition: bnxt_hsi.h:9640

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Definition: bnxt_hsi.h:6409

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__le64 pattern_buf_addr
Definition: bnxt_hsi.h:9450

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Definition: bnxt_hsi.h:4066

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Definition: bnxt_hsi.h:2981

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Definition: bnxt_hsi.h:8389

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Definition: bnxt_hsi.h:4520

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__le64 tx_stat_error
Definition: bnxt_hsi.h:3845

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Definition: bnxt_hsi.h:782

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Definition: bnxt_hsi.h:1694

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Definition: bnxt_hsi.h:625

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Definition: bnxt_hsi.h:4123

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Definition: bnxt_hsi.h:9948

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Definition: bnxt_hsi.h:10080

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Definition: bnxt_hsi.h:7208

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Definition: bnxt_hsi.h:8605

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Definition: bnxt_hsi.h:20

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Definition: bnxt_hsi.h:4106

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Definition: bnxt_hsi.h:10189

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Definition: bnxt_hsi.h:4207

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Definition: bnxt_hsi.h:9995

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__le16 ver_patch
Definition: bnxt_hsi.h:1866

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Definition: bnxt_hsi.h:9376

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Definition: bnxt_hsi.h:6976

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Definition: bnxt_hsi.h:5986

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Definition: bnxt_hsi.h:5955

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Definition: bnxt_hsi.h:8373

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__le32 encap_record_id
Definition: bnxt_hsi.h:7060

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Definition: bnxt_hsi.h:3561

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Definition: bnxt_hsi.h:10588

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Definition: bnxt_hsi.h:10569

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Definition: bnxt_hsi.h:9936

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Definition: bnxt_hsi.h:1659

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Definition: bnxt_hsi.h:2913

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Definition: bnxt_hsi.h:9751

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Definition: bnxt_hsi.h:2970

__le16
uint16_t __le16
Definition: efx_common.h:29

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__le64 rx_packets_cos2
Definition: bnxt_hsi.h:3996

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Definition: bnxt_hsi.h:2021

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__le64 rx_runt_frames
Definition: bnxt_hsi.h:3913

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Definition: bnxt_hsi.h:1238

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Definition: bnxt_hsi.h:8669

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__le16 int_lat_tmr_max
Definition: bnxt_hsi.h:6417

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Definition: bnxt_hsi.h:8075

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Definition: bnxt_hsi.h:3714

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Definition: bnxt_hsi.h:9906

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Definition: bnxt_hsi.h:1071

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__le16 req_type
Definition: bnxt_hsi.h:9685

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Definition: bnxt_hsi.h:10313

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Definition: bnxt_hsi.h:5956

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__le16 target_id
Definition: bnxt_hsi.h:5712

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__le32 flags
Definition: bnxt_hsi.h:1517

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__le16 error_code
Definition: bnxt_hsi.h:9848

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__le16 req_type
Definition: bnxt_hsi.h:3036

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Definition: bnxt_hsi.h:9357

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Definition: bnxt_hsi.h:8284

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Definition: bnxt_hsi.h:4673

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Definition: bnxt_hsi.h:1242

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__le64 em_info
Definition: bnxt_hsi.h:7908

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Definition: bnxt_hsi.h:5728

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__le16 seq_id
Definition: bnxt_hsi.h:4839

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Definition: bnxt_hsi.h:1195

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__le16 tx_ts_capture_ptp_msg_type
Definition: bnxt_hsi.h:3731

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__le32 queue_id1_max_bw
Definition: bnxt_hsi.h:5407

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8026

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Definition: bnxt_hsi.h:6723

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Definition: bnxt_hsi.h:4030

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__le16 cmpl_ring
Definition: bnxt_hsi.h:10064

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Definition: bnxt_hsi.h:8556

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__le16 resp_len
Definition: bnxt_hsi.h:8050

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Definition: bnxt_hsi.h:5853

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Definition: bnxt_hsi.h:6691

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__le64 resp_addr
Definition: bnxt_hsi.h:8161

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Definition: bnxt_hsi.h:5745

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__le16 rx_stat_size
Definition: bnxt_hsi.h:4042

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__le16 cmpl_ring
Definition: bnxt_hsi.h:4908

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Definition: bnxt_hsi.h:8870

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__le64 resp_addr
Definition: bnxt_hsi.h:9288

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Definition: bnxt_hsi.h:7959

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Definition: bnxt_hsi.h:9666

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Definition: bnxt_hsi.h:8369

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__le16 req_type
Definition: bnxt_hsi.h:10577

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Definition: bnxt_hsi.h:7076

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Definition: bnxt_hsi.h:6951

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__le64 tx_control_frames
Definition: bnxt_hsi.h:3815

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Definition: bnxt_hsi.h:4615

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Definition: bnxt_hsi.h:5543

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Definition: bnxt_hsi.h:6546

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__le64 host_dest_addr
Definition: bnxt_hsi.h:9938

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__le16 vf_a_index
Definition: bnxt_hsi.h:8177

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__le16 seq_id
Definition: bnxt_hsi.h:6851

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__le32 decap_filter_id
Definition: bnxt_hsi.h:7748

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__le32 dir_data_length
Definition: bnxt_hsi.h:10031

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__le64 rx_pfc_frames
Definition: bnxt_hsi.h:3868

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__le32 tunnel_handle
Definition: bnxt_hsi.h:7787

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Definition: bnxt_hsi.h:3367

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Definition: bnxt_hsi.h:9476

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Definition: bnxt_hsi.h:7201

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Definition: bnxt_hsi.h:1126

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Definition: bnxt_hsi.h:6877

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Definition: bnxt_hsi.h:1336

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Definition: bnxt_hsi.h:5963

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Definition: bnxt_hsi.h:5696

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Definition: bnxt_hsi.h:9346

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Definition: bnxt_hsi.h:8778

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Definition: bnxt_hsi.h:3238

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Definition: bnxt_hsi.h:6134

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Definition: bnxt_hsi.h:3040

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Definition: bnxt_hsi.h:9395

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Definition: bnxt_hsi.h:6746

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Definition: bnxt_hsi.h:8414

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Definition: bnxt_hsi.h:8939

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Definition: bnxt_hsi.h:5984

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Definition: bnxt_hsi.h:4133

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Definition: bnxt_hsi.h:6610

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Definition: bnxt_hsi.h:9547

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Definition: bnxt_hsi.h:2440

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Definition: bnxt_hsi.h:5976

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__le64 tunnel_filter_id
Definition: bnxt_hsi.h:6821

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Definition: bnxt_hsi.h:459

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Definition: bnxt_hsi.h:4320

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Definition: bnxt_hsi.h:3128

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Definition: bnxt_hsi.h:5922

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__le16 supported_pam4_speeds_auto_mode
Definition: bnxt_hsi.h:4225

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Definition: bnxt_hsi.h:1670

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Definition: bnxt_hsi.h:7858

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__le16 max_req_win_len
Definition: bnxt_hsi.h:439

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__le16 rss_rule
Definition: bnxt_hsi.h:5830

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__le64 pfc_pri6_rx_transitions
Definition: bnxt_hsi.h:4015

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Definition: bnxt_hsi.h:7316

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Definition: bnxt_hsi.h:7157

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Definition: bnxt_hsi.h:6013

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__le16 flow_handle_3
Definition: bnxt_hsi.h:7951

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Definition: bnxt_hsi.h:657

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Definition: bnxt_hsi.h:10280

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Definition: bnxt_hsi.h:2865

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Definition: bnxt_hsi.h:7966

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Definition: bnxt_hsi.h:6356

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Definition: bnxt_hsi.h:1098

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Definition: bnxt_hsi.h:10138

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__le16 max_entries
Definition: bnxt_hsi.h:5702

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Definition: bnxt_hsi.h:4403

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Definition: bnxt_hsi.h:9974

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Definition: bnxt_hsi.h:5973

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Definition: bnxt_hsi.h:8699

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Definition: bnxt_hsi.h:6675

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__le16 error_code
Definition: bnxt_hsi.h:9923

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Definition: bnxt_hsi.h:8423

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Definition: bnxt_hsi.h:4860

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Definition: bnxt_hsi.h:10526

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__le64 packet_5
Definition: bnxt_hsi.h:7982

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Definition: bnxt_hsi.h:7702

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Definition: bnxt_hsi.h:2420

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__le32 encap_record_id
Definition: bnxt_hsi.h:7048

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Definition: bnxt_hsi.h:817

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Definition: bnxt_hsi.h:9210

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Definition: bnxt_hsi.h:8264

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__le16 first_vf_id
Definition: bnxt_hsi.h:1374

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__le32 mirror_vnic_id
Definition: bnxt_hsi.h:6812

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__le16 target_id
Definition: bnxt_hsi.h:1826

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__le16 hwrm_fw_build
Definition: bnxt_hsi.h:453

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__le16 target_id
Definition: bnxt_hsi.h:10589

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Definition: bnxt_hsi.h:10114

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__le64 byte_8
Definition: bnxt_hsi.h:7995

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Definition: bnxt_hsi.h:7071

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Definition: bnxt_hsi.h:2324

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Definition: bnxt_hsi.h:8417

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7744

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Definition: bnxt_hsi.h:6724

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__le16 port_id
Definition: bnxt_hsi.h:4132

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Definition: bnxt_hsi.h:8128

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__le32 t_l3_addr[4]
Definition: bnxt_hsi.h:6788

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__le64 resp_addr
Definition: bnxt_hsi.h:8343

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Definition: bnxt_hsi.h:746

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Definition: bnxt_hsi.h:1185

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Definition: bnxt_hsi.h:6731

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Definition: bnxt_hsi.h:6322

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Definition: bnxt_hsi.h:2032

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Definition: bnxt_hsi.h:1898

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Definition: bnxt_hsi.h:4096

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Definition: bnxt_hsi.h:5463

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Definition: bnxt_hsi.h:5704

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__le64 rx_2048b_4095b_frames
Definition: bnxt_hsi.h:3858

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Definition: bnxt_hsi.h:8060

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Definition: bnxt_hsi.h:7067

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__le16 num_cmpl_aggr_int
Definition: bnxt_hsi.h:6441

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Definition: bnxt_hsi.h:1735

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__le64 rx_bcast_pkts
Definition: bnxt_hsi.h:8484

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Definition: bnxt_hsi.h:9299

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Definition: bnxt_hsi.h:8339

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__le16 num_cmpl_dma_aggr
Definition: bnxt_hsi.h:6435

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Definition: bnxt_hsi.h:2831

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Definition: bnxt_hsi.h:4324

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__le16 vf_b_id
Definition: bnxt_hsi.h:8120

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__be32 src_ip_addr[4]
Definition: bnxt_hsi.h:6987

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Definition: bnxt_hsi.h:6730

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__le16 seq_id
Definition: bnxt_hsi.h:8619

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__le16 error_code
Definition: bnxt_hsi.h:8442

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__le16 int_lat_tmr_min
Definition: bnxt_hsi.h:6416

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__le16 index_3
Definition: bnxt_hsi.h:10315

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Definition: bnxt_hsi.h:6348

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__le64 pfc_pri1_rx_duration_us
Definition: bnxt_hsi.h:4004

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Definition: bnxt_hsi.h:7710

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Definition: bnxt_hsi.h:5701

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__le16 seq_id
Definition: bnxt_hsi.h:8139

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__le64 tx_mcast_pkts
Definition: bnxt_hsi.h:8491

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u8 service_profile
Definition: bnxt_hsi.h:4827

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__le16 resp_len
Definition: bnxt_hsi.h:5965

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__le64 resp_addr
Definition: bnxt_hsi.h:7231

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__le16 resp_len
Definition: bnxt_hsi.h:10579

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__le16 dir_type
Definition: bnxt_hsi.h:10203

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__le16 guest_vlan
Definition: bnxt_hsi.h:1290

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__le64 pfc_pri4_rx_transitions
Definition: bnxt_hsi.h:4011

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Definition: bnxt_hsi.h:2896

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__le16 seq_id
Definition: bnxt_hsi.h:9758

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__le16 req_type
Definition: bnxt_hsi.h:6606

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__le64 resp_addr
Definition: bnxt_hsi.h:8427

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__le16 resp_len
Definition: bnxt_hsi.h:5699

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Definition: bnxt_hsi.h:3922

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Definition: bnxt_hsi.h:1266

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__le16 seq_id
Definition: bnxt_hsi.h:9813

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9536

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__le16 ver_upd
Definition: bnxt_hsi.h:2011

u8
uint8_t u8
Definition: stdint.h:19

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__le16 num_cmpl_dma_aggr_max
Definition: bnxt_hsi.h:6374

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Definition: bnxt_hsi.h:1909

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Definition: bnxt_hsi.h:9717

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__le32 event_data2
Definition: bnxt_hsi.h:1039

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__le16 error_code
Definition: bnxt_hsi.h:6477

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Definition: bnxt_hsi.h:3680

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Definition: bnxt_hsi.h:9982

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Definition: bnxt_hsi.h:10043

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Definition: bnxt_hsi.h:1895

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Definition: bnxt_hsi.h:8359

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Definition: bnxt_hsi.h:7708

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Definition: bnxt_hsi.h:5430

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__le16 unused_3
Definition: bnxt_hsi.h:7720

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Definition: bnxt_hsi.h:6944

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__le16 led1_color_caps
Definition: bnxt_hsi.h:4622

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__le16 flow_handle
Definition: bnxt_hsi.h:7886

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Definition: bnxt_hsi.h:7870

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Definition: bnxt_hsi.h:9735

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__le16 resp_len
Definition: bnxt_hsi.h:7757

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6161

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__le16 cmpl_ring
Definition: bnxt_hsi.h:9417

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Definition: bnxt_hsi.h:8799

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Definition: bnxt_hsi.h:1989

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Definition: bnxt_hsi.h:9905

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Definition: bnxt_hsi.h:1423

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__le32 tx_ts_reg_off_lower
Definition: bnxt_hsi.h:3784

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Definition: bnxt_hsi.h:2487

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Definition: bnxt_hsi.h:7619

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__le64 eng_bytes_in
Definition: bnxt_hsi.h:8506

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__le64 cce_engine_usage
Definition: bnxt_hsi.h:8512

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Definition: bnxt_hsi.h:4369

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Definition: bnxt_hsi.h:8267

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Definition: bnxt_hsi.h:8734

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Definition: bnxt_hsi.h:9756

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Definition: bnxt_hsi.h:2056

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Definition: bnxt_hsi.h:5796

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__le16 resp_len
Definition: bnxt_hsi.h:1339

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__le16 cmpl_ring
Definition: bnxt_hsi.h:1689

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__le16 vf_b_index
Definition: bnxt_hsi.h:8179

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__le16 max_hw_ring_grps
Definition: bnxt_hsi.h:2088

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u8 unused_0[7]
Definition: bnxt_hsi.h:5966

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__le16 type
Definition: bnxt_hsi.h:1010

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Definition: bnxt_hsi.h:4933

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__le64 tx_jabber_frames
Definition: bnxt_hsi.h:3813

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__le16 max_rx_rings
Definition: bnxt_hsi.h:2048

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__le16 ctag_vid
Definition: bnxt_hsi.h:2846

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Definition: bnxt_hsi.h:2510

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__le64 l2_filter_id_hint
Definition: bnxt_hsi.h:6600

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__le64 rx_code_err_frames
Definition: bnxt_hsi.h:3874

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Definition: bnxt_hsi.h:1896

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Definition: bnxt_hsi.h:1260

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__le16 max_vnics
Definition: bnxt_hsi.h:1373

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__le16 seq_id
Definition: bnxt_hsi.h:8425

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Definition: bnxt_hsi.h:8059

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Definition: bnxt_hsi.h:10566

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__le16 error_code
Definition: bnxt_hsi.h:4897

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Definition: bnxt_hsi.h:639

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__le32 load_milli_watt
Definition: bnxt_hsi.h:9040

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Definition: bnxt_hsi.h:2116

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__le64 req_buf_page_addr3
Definition: bnxt_hsi.h:1930

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__le16 alloc_vnics
Definition: bnxt_hsi.h:1426

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Definition: bnxt_hsi.h:9315

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__le32 cli_data_len
Definition: bnxt_hsi.h:9876

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Definition: bnxt_hsi.h:2965

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__le32 queue_id5_max_bw
Definition: bnxt_hsi.h:5567

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Definition: bnxt_hsi.h:10147

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Definition: bnxt_hsi.h:8448

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__le16 led0_color_caps
Definition: bnxt_hsi.h:4604

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__le16 stag_vid
Definition: bnxt_hsi.h:2842

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__le16 cmpl_aggr_dma_tmr
Definition: bnxt_hsi.h:6437

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__le16 seq_id
Definition: bnxt_hsi.h:8281

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__le16 int_lat_tmr_min
Definition: bnxt_hsi.h:6439

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Definition: bnxt_hsi.h:360

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__le16 resp_len
Definition: bnxt_hsi.h:9212

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__le16 copied_data_len
Definition: bnxt_hsi.h:10622

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__le64 resp_addr
Definition: bnxt_hsi.h:9962

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__le16 target_id
Definition: bnxt_hsi.h:6768

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Definition: bnxt_hsi.h:6717

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Definition: bnxt_hsi.h:4331

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__le32 opaque_0
Definition: bnxt_hsi.h:357

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__le64 resp_addr
Definition: bnxt_hsi.h:4055

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u8 unused_2[4]
Definition: bnxt_hsi.h:7306

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__le16 error_code
Definition: bnxt_hsi.h:4837

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u8 queue_id1
Definition: bnxt_hsi.h:4709

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__le16 seq_id
Definition: bnxt_hsi.h:6619

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u8 valid
Definition: bnxt_hsi.h:8768

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__le16 resp_len
Definition: bnxt_hsi.h:6916

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__le16 reserved_rx_rings
Definition: bnxt_hsi.h:2103

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__le64 rx_stat_discard
Definition: bnxt_hsi.h:3914

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__le32 enables
Definition: bnxt_hsi.h:1176

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u8 code
Definition: bnxt_hsi.h:10434

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__le16 req_type
Definition: bnxt_hsi.h:10272

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__le64 rx_stat_discard
Definition: bnxt_hsi.h:4072

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__le16 cmpl_ring
Definition: bnxt_hsi.h:1172

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__le16 seq_id
Definition: bnxt_hsi.h:8444

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__le16 cmpl_ring
Definition: bnxt_hsi.h:5334

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u8 ets_state
Definition: bnxt_hsi.h:8931

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__le64 rx_ctrl_frames
Definition: bnxt_hsi.h:3866

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__le16 ring_id
Definition: bnxt_hsi.h:6282

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__le16 port_id
Definition: bnxt_hsi.h:4891

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u8 opaque_v
Definition: bnxt_hsi.h:925

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u8 ip_addr_type
Definition: bnxt_hsi.h:7288

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u8 opaque_v
Definition: bnxt_hsi.h:1159

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__le16 sequence_id
Definition: bnxt_hsi.h:506

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__le16 cmpl_ring
Definition: bnxt_hsi.h:1326

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__le16 timestamp_hi
Definition: bnxt_hsi.h:1024

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u8 unused_0[7]
Definition: bnxt_hsi.h:8650

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__le16 cmpl_ring
Definition: bnxt_hsi.h:5787

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__le32 tqm_ring6_num_entries
Definition: bnxt_hsi.h:2463

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__le16 req_type
Definition: bnxt_hsi.h:8759

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__le32 hash_type
Definition: bnxt_hsi.h:6072

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Definition: bnxt_hsi.h:5748

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__le16 req_type
Definition: bnxt_hsi.h:4051

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__le16 resp_len
Definition: bnxt_hsi.h:4587

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__le32 l3_addr[4]
Definition: bnxt_hsi.h:6787

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__le16 target_id
Definition: bnxt_hsi.h:2924

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__le16 req_type
Definition: bnxt_hsi.h:6829

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__le16 req_type
Definition: bnxt_hsi.h:3012

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Definition: bnxt_hsi.h:2886

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__le16 resp_len
Definition: bnxt_hsi.h:8649

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__le16 ring_id
Definition: bnxt_hsi.h:6430

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__le16 num_cmpl_aggr_int
Definition: bnxt_hsi.h:6418

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Definition: bnxt_hsi.h:1890

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u8 drv_qmap_cap
Definition: bnxt_hsi.h:4679

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Definition: bnxt_hsi.h:9491

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__le16 max_msix
Definition: bnxt_hsi.h:2072

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Definition: bnxt_hsi.h:8019

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__le64 tim_page_dir
Definition: bnxt_hsi.h:2451

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__le32 unused_4
Definition: bnxt_hsi.h:9804

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__le64 rx_runt_bytes
Definition: bnxt_hsi.h:3912

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__le16 meter_instance_id
Definition: bnxt_hsi.h:7281

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__le32 event_data2
Definition: bnxt_hsi.h:880

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__le32 enables
Definition: bnxt_hsi.h:4341

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__le32 max_rx_em_flows
Definition: bnxt_hsi.h:1381

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__le64 pfc_pri5_rx_duration_us
Definition: bnxt_hsi.h:4012

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__le16 timestamp_hi
Definition: bnxt_hsi.h:586

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__le16 num_tx_rings
Definition: bnxt_hsi.h:1564

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__le16 port_id
Definition: bnxt_hsi.h:3925

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__le16 seq_id
Definition: bnxt_hsi.h:10401

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__le16 cmpl_ring
Definition: bnxt_hsi.h:3698

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__le32 queue_id2_max_bw
Definition: bnxt_hsi.h:5104

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__le64 rx_mcast_pkts
Definition: bnxt_hsi.h:1671

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__le16 meter_instance_id
Definition: bnxt_hsi.h:7641

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__le64 vnic_page_dir
Definition: bnxt_hsi.h:2786

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__le64 lpbk_ucast_bytes
Definition: bnxt_hsi.h:4067

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__le64 rx_ucast_bytes
Definition: bnxt_hsi.h:1675

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__le16 num_vnics
Definition: bnxt_hsi.h:1567

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__le16 resp_len
Definition: bnxt_hsi.h:8671

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__le16 target_id
Definition: bnxt_hsi.h:8028

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Definition: bnxt_hsi.h:4121

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u8 tqm_ring2_pg_size_tqm_ring2_lvl
Definition: bnxt_hsi.h:2655

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__le64 byte_5
Definition: bnxt_hsi.h:7992

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u8 active_lanes
Definition: bnxt_hsi.h:3609

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u8 link
Definition: bnxt_hsi.h:3248

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u8 cmd_err
Definition: bnxt_hsi.h:359

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__le16 cmpl_ring
Definition: bnxt_hsi.h:3756

__be16
uint16_t __be16
Definition: CIB_PRM.h:27

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__le64 qpc_page_dir
Definition: bnxt_hsi.h:2436

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__le64 rx_mcast_bytes
Definition: bnxt_hsi.h:8594

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__le16 cmpl_aggr_dma_tmr_during_int
Definition: bnxt_hsi.h:6415

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u8 pri6_to_tc_map
Definition: bnxt_hsi.h:8876

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Definition: bnxt_hsi.h:4402

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u8 dscp2pri_map_pri
Definition: bnxt_hsi.h:3729

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__le16 auto_pam4_link_speed_mask
Definition: bnxt_hsi.h:3553

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__le64 rx_64b_frames
Definition: bnxt_hsi.h:3850

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u8 timestamp_lo
Definition: bnxt_hsi.h:661

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__le16 hwrm_intf_major
Definition: bnxt_hsi.h:447

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__le16 target_id
Definition: bnxt_hsi.h:9265

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__le16 cmpl_ring
Definition: bnxt_hsi.h:1249

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u8 valid
Definition: bnxt_hsi.h:6389

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__le64 rx_discard_pkts
Definition: bnxt_hsi.h:8485

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__le16 resp_len
Definition: bnxt_hsi.h:7336

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__le16 event_id
Definition: bnxt_hsi.h:993

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__le16 seq_id
Definition: bnxt_hsi.h:8341

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u8 unused_0[7]
Definition: bnxt_hsi.h:9278

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__le16 mru
Definition: bnxt_hsi.h:5872

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u8 unused_0[3]
Definition: bnxt_hsi.h:6284

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__le16 tx_cfa_action_a
Definition: bnxt_hsi.h:8234

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__le16 min_rx_rings
Definition: bnxt_hsi.h:2047

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__le16 target_id
Definition: bnxt_hsi.h:5766

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u8 pri7_cos_queue_id
Definition: bnxt_hsi.h:4974

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__le16 seq_id
Definition: bnxt_hsi.h:9791

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Definition: bnxt_hsi.h:6195

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__le16 led3_state_caps
Definition: bnxt_hsi.h:4652

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__le16 seq_id
Definition: bnxt_hsi.h:5842

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__le16 req_type
Definition: bnxt_hsi.h:9345

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__le16 error_code
Definition: bnxt_hsi.h:9432

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Definition: bnxt_hsi.h:8334

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__le64 resp_addr
Definition: bnxt_hsi.h:8522

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Definition: bnxt_hsi.h:10538

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Definition: bnxt_hsi.h:4117

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Definition: bnxt_hsi.h:10333

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__le16 req_type
Definition: bnxt_hsi.h:8371

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__le16 cmpl_ring
Definition: bnxt_hsi.h:6181

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u8 valid
Definition: bnxt_hsi.h:4098

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__le64 srq_page_dir
Definition: bnxt_hsi.h:2437

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__le16 req_type
Definition: bnxt_hsi.h:6878

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__le16 vf_a_fid
Definition: bnxt_hsi.h:8176

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__le16 error_code
Definition: bnxt_hsi.h:8816

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__le16 req_type
Definition: bnxt_hsi.h:2486

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Definition: bnxt_hsi.h:8798

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__le32 flags
Definition: bnxt_hsi.h:1875

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__le16 error_code
Definition: bnxt_hsi.h:1871

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u8 led1_id
Definition: bnxt_hsi.h:4608

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__le16 cmpl_ring
Definition: bnxt_hsi.h:8424

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__le16 target_id
Definition: bnxt_hsi.h:8342

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Definition: bnxt_hsi.h:1900

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__le64 tx_bcast_bytes
Definition: bnxt_hsi.h:8497

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__le16 unused[3]
Definition: bnxt_hsi.h:2927

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Definition: bnxt_hsi.h:9283

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__le16 type
Definition: bnxt_hsi.h:768

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Definition: bnxt_hsi.h:6420

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__le32 intf_num
Definition: bnxt_hsi.h:9009

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__le16 seq_id
Definition: bnxt_hsi.h:8648

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__le64 tx_oversz_frames
Definition: bnxt_hsi.h:3816

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__le32 enables
Definition: bnxt_hsi.h:1536

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__le16 error_code
Definition: bnxt_hsi.h:10543

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__le64 resp_addr
Definition: bnxt_hsi.h:1692

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u8 cq_pg_size_cq_lvl
Definition: bnxt_hsi.h:2212

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__le16 mrav_entry_size
Definition: bnxt_hsi.h:2479

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Definition: bnxt_hsi.h:1067

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Definition: bnxt_hsi.h:9833

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__le16 cmpl_ring
Definition: bnxt_hsi.h:7943

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__le16 error_code
Definition: bnxt_hsi.h:4112

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Definition: bnxt_hsi.h:10155

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__le16 req_type
Definition: bnxt_hsi.h:4847

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Definition: bnxt_hsi.h:6818

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__le16 vnic_id
Definition: bnxt_hsi.h:5939

hwrm_nvm_validate_option_input::unused_0
u8 unused_0[2]
Definition: bnxt_hsi.h:10415

hwrm_dbg_read_direct_input::read_len32
__le32 read_len32
Definition: bnxt_hsi.h:9520

hwrm_ring_grp_free_output::resp_len
__le16 resp_len
Definition: bnxt_hsi.h:6502

hwrm_cfa_redirect_query_tunnel_type_input::resp_addr
__le64 resp_addr
Definition: bnxt_hsi.h:8363

hwrm_nvm_validate_option_input::req_type
__le16 req_type
Definition: bnxt_hsi.h:10399

pcie_ctx_hw_stats::pcie_ltssm_histogram
__le32 pcie_ltssm_histogram[4]
Definition: bnxt_hsi.h:8688

hwrm_func_qcfg_input::unused_0
u8 unused_0[6]
Definition: bnxt_hsi.h:1399

hwrm_struct_data_lldp_device::ttl
__le16 ttl
Definition: bnxt_hsi.h:9000

hwrm_cfa_pair_free_input::resp_addr
__le64 resp_addr
Definition: bnxt_hsi.h:8247

hwrm_func_buf_rgtr_input::target_id
__le16 target_id
Definition: bnxt_hsi.h:1908

hwrm_vnic_rss_qcfg_output::hash_mode_flags
u8 hash_mode_flags
Definition: bnxt_hsi.h:6081

hwrm_queue_dscp2pri_qcfg_output::seq_id
__le16 seq_id
Definition: bnxt_hsi.h:5725