bnxt__hsi_8h_source.html

/* Broadcom NetXtreme-C/E network driver.

 *

 * Copyright (c) 2014-2016 Broadcom Corporation

 * Copyright (c) 2016-2019 Broadcom Limited

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation.

 *

 * DO NOT MODIFY!!! This file is automatically generated.

 */


#ifndef _BNXT_HSI_H_

#define _BNXT_HSI_H_


/* hwrm_cmd_hdr (size:128b/16B) */


struct hwrm_cmd_hdr {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_resp_hdr (size:64b/8B) */


struct hwrm_resp_hdr {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

};


#define CMD_DISCR_TLV_ENCAP 0x8000UL

#define CMD_DISCR_LAST     CMD_DISCR_TLV_ENCAP


#define TLV_TYPE_HWRM_REQUEST                    0x1UL

#define TLV_TYPE_HWRM_RESPONSE                   0x2UL

#define TLV_TYPE_ROCE_SP_COMMAND                 0x3UL

#define TLV_TYPE_QUERY_ROCE_CC_GEN1              0x4UL

#define TLV_TYPE_MODIFY_ROCE_CC_GEN1             0x5UL

#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL

#define TLV_TYPE_ENGINE_CKV_NONCE                0x8002UL

#define TLV_TYPE_ENGINE_CKV_IV                   0x8003UL

#define TLV_TYPE_ENGINE_CKV_AUTH_TAG             0x8004UL

#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT           0x8005UL

#define TLV_TYPE_ENGINE_CKV_ALGORITHMS           0x8006UL

#define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY       0x8007UL

#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE      0x8008UL

#define TLV_TYPE_LAST                           TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE


/* tlv (size:64b/8B) */


struct tlv {

        __le16    cmd_discr;

        u8    reserved_8b;

        u8    flags;

        #define TLV_FLAGS_MORE         0x1UL

        #define TLV_FLAGS_MORE_LAST      0x0UL

        #define TLV_FLAGS_MORE_NOT_LAST  0x1UL

        #define TLV_FLAGS_REQUIRED     0x2UL

        #define TLV_FLAGS_REQUIRED_NO    (0x0UL << 1)

        #define TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)

        #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES

        __le16    tlv_type;

        __le16    length;

};


/* input (size:128b/16B) */


struct input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* output (size:64b/8B) */


struct output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

};


/* hwrm_short_input (size:128b/16B) */


struct hwrm_short_input {

        __le16    req_type;

        __le16    signature;

        #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL

        #define SHORT_REQ_SIGNATURE_LAST     SHORT_REQ_SIGNATURE_SHORT_CMD

        __le16    unused_0;

        __le16    size;

        __le64    req_addr;

};


/* cmd_nums (size:64b/8B) */


struct cmd_nums {

        __le16    req_type;

        #define HWRM_VER_GET                              0x0UL

        #define HWRM_ER_QCFG                              0xcUL

        #define HWRM_FUNC_DRV_IF_CHANGE                   0xdUL

        #define HWRM_FUNC_BUF_UNRGTR                      0xeUL

        #define HWRM_FUNC_VF_CFG                          0xfUL

        #define HWRM_RESERVED1                            0x10UL

        #define HWRM_FUNC_RESET                           0x11UL

        #define HWRM_FUNC_GETFID                          0x12UL

        #define HWRM_FUNC_VF_ALLOC                        0x13UL

        #define HWRM_FUNC_VF_FREE                         0x14UL

        #define HWRM_FUNC_QCAPS                           0x15UL

        #define HWRM_FUNC_QCFG                            0x16UL

        #define HWRM_FUNC_CFG                             0x17UL

        #define HWRM_FUNC_QSTATS                          0x18UL

        #define HWRM_FUNC_CLR_STATS                       0x19UL

        #define HWRM_FUNC_DRV_UNRGTR                      0x1aUL

        #define HWRM_FUNC_VF_RESC_FREE                    0x1bUL

        #define HWRM_FUNC_VF_VNIC_IDS_QUERY               0x1cUL

        #define HWRM_FUNC_DRV_RGTR                        0x1dUL

        #define HWRM_FUNC_DRV_QVER                        0x1eUL

        #define HWRM_FUNC_BUF_RGTR                        0x1fUL

        #define HWRM_PORT_PHY_CFG                         0x20UL

        #define HWRM_PORT_MAC_CFG                         0x21UL

        #define HWRM_PORT_TS_QUERY                        0x22UL

        #define HWRM_PORT_QSTATS                          0x23UL

        #define HWRM_PORT_LPBK_QSTATS                     0x24UL

        #define HWRM_PORT_CLR_STATS                       0x25UL

        #define HWRM_PORT_LPBK_CLR_STATS                  0x26UL

        #define HWRM_PORT_PHY_QCFG                        0x27UL

        #define HWRM_PORT_MAC_QCFG                        0x28UL

        #define HWRM_PORT_MAC_PTP_QCFG                    0x29UL

        #define HWRM_PORT_PHY_QCAPS                       0x2aUL

        #define HWRM_PORT_PHY_I2C_WRITE                   0x2bUL

        #define HWRM_PORT_PHY_I2C_READ                    0x2cUL

        #define HWRM_PORT_LED_CFG                         0x2dUL

        #define HWRM_PORT_LED_QCFG                        0x2eUL

        #define HWRM_PORT_LED_QCAPS                       0x2fUL

        #define HWRM_QUEUE_QPORTCFG                       0x30UL

        #define HWRM_QUEUE_QCFG                           0x31UL

        #define HWRM_QUEUE_CFG                            0x32UL

        #define HWRM_FUNC_VLAN_CFG                        0x33UL

        #define HWRM_FUNC_VLAN_QCFG                       0x34UL

        #define HWRM_QUEUE_PFCENABLE_QCFG                 0x35UL

        #define HWRM_QUEUE_PFCENABLE_CFG                  0x36UL

        #define HWRM_QUEUE_PRI2COS_QCFG                   0x37UL

        #define HWRM_QUEUE_PRI2COS_CFG                    0x38UL

        #define HWRM_QUEUE_COS2BW_QCFG                    0x39UL

        #define HWRM_QUEUE_COS2BW_CFG                     0x3aUL

        #define HWRM_QUEUE_DSCP_QCAPS                     0x3bUL

        #define HWRM_QUEUE_DSCP2PRI_QCFG                  0x3cUL

        #define HWRM_QUEUE_DSCP2PRI_CFG                   0x3dUL

        #define HWRM_VNIC_ALLOC                           0x40UL

        #define HWRM_VNIC_FREE                            0x41UL

        #define HWRM_VNIC_CFG                             0x42UL

        #define HWRM_VNIC_QCFG                            0x43UL

        #define HWRM_VNIC_TPA_CFG                         0x44UL

        #define HWRM_VNIC_TPA_QCFG                        0x45UL

        #define HWRM_VNIC_RSS_CFG                         0x46UL

        #define HWRM_VNIC_RSS_QCFG                        0x47UL

        #define HWRM_VNIC_PLCMODES_CFG                    0x48UL

        #define HWRM_VNIC_PLCMODES_QCFG                   0x49UL

        #define HWRM_VNIC_QCAPS                           0x4aUL

        #define HWRM_RING_ALLOC                           0x50UL

        #define HWRM_RING_FREE                            0x51UL

        #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        0x52UL

        #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS     0x53UL

        #define HWRM_RING_AGGINT_QCAPS                    0x54UL

        #define HWRM_RING_RESET                           0x5eUL

        #define HWRM_RING_GRP_ALLOC                       0x60UL

        #define HWRM_RING_GRP_FREE                        0x61UL

        #define HWRM_RESERVED5                            0x64UL

        #define HWRM_RESERVED6                            0x65UL

        #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC            0x70UL

        #define HWRM_VNIC_RSS_COS_LB_CTX_FREE             0x71UL

        #define HWRM_CFA_L2_FILTER_ALLOC                  0x90UL

        #define HWRM_CFA_L2_FILTER_FREE                   0x91UL

        #define HWRM_CFA_L2_FILTER_CFG                    0x92UL

        #define HWRM_CFA_L2_SET_RX_MASK                   0x93UL

        #define HWRM_CFA_VLAN_ANTISPOOF_CFG               0x94UL

        #define HWRM_CFA_TUNNEL_FILTER_ALLOC              0x95UL

        #define HWRM_CFA_TUNNEL_FILTER_FREE               0x96UL

        #define HWRM_CFA_ENCAP_RECORD_ALLOC               0x97UL

        #define HWRM_CFA_ENCAP_RECORD_FREE                0x98UL

        #define HWRM_CFA_NTUPLE_FILTER_ALLOC              0x99UL

        #define HWRM_CFA_NTUPLE_FILTER_FREE               0x9aUL

        #define HWRM_CFA_NTUPLE_FILTER_CFG                0x9bUL

        #define HWRM_CFA_EM_FLOW_ALLOC                    0x9cUL

        #define HWRM_CFA_EM_FLOW_FREE                     0x9dUL

        #define HWRM_CFA_EM_FLOW_CFG                      0x9eUL

        #define HWRM_TUNNEL_DST_PORT_QUERY                0xa0UL

        #define HWRM_TUNNEL_DST_PORT_ALLOC                0xa1UL

        #define HWRM_TUNNEL_DST_PORT_FREE                 0xa2UL

        #define HWRM_STAT_CTX_ENG_QUERY                   0xafUL

        #define HWRM_STAT_CTX_ALLOC                       0xb0UL

        #define HWRM_STAT_CTX_FREE                        0xb1UL

        #define HWRM_STAT_CTX_QUERY                       0xb2UL

        #define HWRM_STAT_CTX_CLR_STATS                   0xb3UL

        #define HWRM_PORT_QSTATS_EXT                      0xb4UL

        #define HWRM_FW_RESET                             0xc0UL

        #define HWRM_FW_QSTATUS                           0xc1UL

        #define HWRM_FW_HEALTH_CHECK                      0xc2UL

        #define HWRM_FW_SYNC                              0xc3UL

        #define HWRM_FW_SET_TIME                          0xc8UL

        #define HWRM_FW_GET_TIME                          0xc9UL

        #define HWRM_FW_SET_STRUCTURED_DATA               0xcaUL

        #define HWRM_FW_GET_STRUCTURED_DATA               0xcbUL

        #define HWRM_FW_IPC_MAILBOX                       0xccUL

        #define HWRM_EXEC_FWD_RESP                        0xd0UL

        #define HWRM_REJECT_FWD_RESP                      0xd1UL

        #define HWRM_FWD_RESP                             0xd2UL

        #define HWRM_FWD_ASYNC_EVENT_CMPL                 0xd3UL

        #define HWRM_OEM_CMD                              0xd4UL

        #define HWRM_TEMP_MONITOR_QUERY                   0xe0UL

        #define HWRM_WOL_FILTER_ALLOC                     0xf0UL

        #define HWRM_WOL_FILTER_FREE                      0xf1UL

        #define HWRM_WOL_FILTER_QCFG                      0xf2UL

        #define HWRM_WOL_REASON_QCFG                      0xf3UL

        #define HWRM_CFA_METER_PROFILE_ALLOC              0xf5UL

        #define HWRM_CFA_METER_PROFILE_FREE               0xf6UL

        #define HWRM_CFA_METER_PROFILE_CFG                0xf7UL

        #define HWRM_CFA_METER_INSTANCE_ALLOC             0xf8UL

        #define HWRM_CFA_METER_INSTANCE_FREE              0xf9UL

        #define HWRM_CFA_VFR_ALLOC                        0xfdUL

        #define HWRM_CFA_VFR_FREE                         0xfeUL

        #define HWRM_CFA_VF_PAIR_ALLOC                    0x100UL

        #define HWRM_CFA_VF_PAIR_FREE                     0x101UL

        #define HWRM_CFA_VF_PAIR_INFO                     0x102UL

        #define HWRM_CFA_FLOW_ALLOC                       0x103UL

        #define HWRM_CFA_FLOW_FREE                        0x104UL

        #define HWRM_CFA_FLOW_FLUSH                       0x105UL

        #define HWRM_CFA_FLOW_STATS                       0x106UL

        #define HWRM_CFA_FLOW_INFO                        0x107UL

        #define HWRM_CFA_DECAP_FILTER_ALLOC               0x108UL

        #define HWRM_CFA_DECAP_FILTER_FREE                0x109UL

        #define HWRM_CFA_VLAN_ANTISPOOF_QCFG              0x10aUL

        #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC       0x10bUL

        #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE        0x10cUL

        #define HWRM_CFA_PAIR_ALLOC                       0x10dUL

        #define HWRM_CFA_PAIR_FREE                        0x10eUL

        #define HWRM_CFA_PAIR_INFO                        0x10fUL

        #define HWRM_FW_IPC_MSG                           0x110UL

        #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        0x111UL

        #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       0x112UL

        #define HWRM_CFA_FLOW_AGING_TIMER_RESET           0x113UL

        #define HWRM_CFA_FLOW_AGING_CFG                   0x114UL

        #define HWRM_CFA_FLOW_AGING_QCFG                  0x115UL

        #define HWRM_CFA_FLOW_AGING_QCAPS                 0x116UL

        #define HWRM_ENGINE_CKV_HELLO                     0x12dUL

        #define HWRM_ENGINE_CKV_STATUS                    0x12eUL

        #define HWRM_ENGINE_CKV_CKEK_ADD                  0x12fUL

        #define HWRM_ENGINE_CKV_CKEK_DELETE               0x130UL

        #define HWRM_ENGINE_CKV_KEY_ADD                   0x131UL

        #define HWRM_ENGINE_CKV_KEY_DELETE                0x132UL

        #define HWRM_ENGINE_CKV_FLUSH                     0x133UL

        #define HWRM_ENGINE_CKV_RNG_GET                   0x134UL

        #define HWRM_ENGINE_CKV_KEY_GEN                   0x135UL

        #define HWRM_ENGINE_QG_CONFIG_QUERY               0x13cUL

        #define HWRM_ENGINE_QG_QUERY                      0x13dUL

        #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL

        #define HWRM_ENGINE_QG_METER_PROFILE_QUERY        0x13fUL

        #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC        0x140UL

        #define HWRM_ENGINE_QG_METER_PROFILE_FREE         0x141UL

        #define HWRM_ENGINE_QG_METER_QUERY                0x142UL

        #define HWRM_ENGINE_QG_METER_BIND                 0x143UL

        #define HWRM_ENGINE_QG_METER_UNBIND               0x144UL

        #define HWRM_ENGINE_QG_FUNC_BIND                  0x145UL

        #define HWRM_ENGINE_SG_CONFIG_QUERY               0x146UL

        #define HWRM_ENGINE_SG_QUERY                      0x147UL

        #define HWRM_ENGINE_SG_METER_QUERY                0x148UL

        #define HWRM_ENGINE_SG_METER_CONFIG               0x149UL

        #define HWRM_ENGINE_SG_QG_BIND                    0x14aUL

        #define HWRM_ENGINE_QG_SG_UNBIND                  0x14bUL

        #define HWRM_ENGINE_CONFIG_QUERY                  0x154UL

        #define HWRM_ENGINE_STATS_CONFIG                  0x155UL

        #define HWRM_ENGINE_STATS_CLEAR                   0x156UL

        #define HWRM_ENGINE_STATS_QUERY                   0x157UL

        #define HWRM_ENGINE_RQ_ALLOC                      0x15eUL

        #define HWRM_ENGINE_RQ_FREE                       0x15fUL

        #define HWRM_ENGINE_CQ_ALLOC                      0x160UL

        #define HWRM_ENGINE_CQ_FREE                       0x161UL

        #define HWRM_ENGINE_NQ_ALLOC                      0x162UL

        #define HWRM_ENGINE_NQ_FREE                       0x163UL

        #define HWRM_ENGINE_ON_DIE_RQE_CREDITS            0x164UL

        #define HWRM_FUNC_RESOURCE_QCAPS                  0x190UL

        #define HWRM_FUNC_VF_RESOURCE_CFG                 0x191UL

        #define HWRM_FUNC_BACKING_STORE_QCAPS             0x192UL

        #define HWRM_FUNC_BACKING_STORE_CFG               0x193UL

        #define HWRM_FUNC_BACKING_STORE_QCFG              0x194UL

        #define HWRM_FUNC_VF_BW_CFG                       0x195UL

        #define HWRM_FUNC_VF_BW_QCFG                      0x196UL

        #define HWRM_SELFTEST_QLIST                       0x200UL

        #define HWRM_SELFTEST_EXEC                        0x201UL

        #define HWRM_SELFTEST_IRQ                         0x202UL

        #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA        0x203UL

        #define HWRM_PCIE_QSTATS                          0x204UL

        #define HWRM_DBG_READ_DIRECT                      0xff10UL

        #define HWRM_DBG_READ_INDIRECT                    0xff11UL

        #define HWRM_DBG_WRITE_DIRECT                     0xff12UL

        #define HWRM_DBG_WRITE_INDIRECT                   0xff13UL

        #define HWRM_DBG_DUMP                             0xff14UL

        #define HWRM_DBG_ERASE_NVM                        0xff15UL

        #define HWRM_DBG_CFG                              0xff16UL

        #define HWRM_DBG_COREDUMP_LIST                    0xff17UL

        #define HWRM_DBG_COREDUMP_INITIATE                0xff18UL

        #define HWRM_DBG_COREDUMP_RETRIEVE                0xff19UL

        #define HWRM_DBG_FW_CLI                           0xff1aUL

        #define HWRM_DBG_I2C_CMD                          0xff1bUL

        #define HWRM_DBG_RING_INFO_GET                    0xff1cUL

        #define HWRM_NVM_FACTORY_DEFAULTS                 0xffeeUL

        #define HWRM_NVM_VALIDATE_OPTION                  0xffefUL

        #define HWRM_NVM_FLUSH                            0xfff0UL

        #define HWRM_NVM_GET_VARIABLE                     0xfff1UL

        #define HWRM_NVM_SET_VARIABLE                     0xfff2UL

        #define HWRM_NVM_INSTALL_UPDATE                   0xfff3UL

        #define HWRM_NVM_MODIFY                           0xfff4UL

        #define HWRM_NVM_VERIFY_UPDATE                    0xfff5UL

        #define HWRM_NVM_GET_DEV_INFO                     0xfff6UL

        #define HWRM_NVM_ERASE_DIR_ENTRY                  0xfff7UL

        #define HWRM_NVM_MOD_DIR_ENTRY                    0xfff8UL

        #define HWRM_NVM_FIND_DIR_ENTRY                   0xfff9UL

        #define HWRM_NVM_GET_DIR_ENTRIES                  0xfffaUL

        #define HWRM_NVM_GET_DIR_INFO                     0xfffbUL

        #define HWRM_NVM_RAW_DUMP                         0xfffcUL

        #define HWRM_NVM_READ                             0xfffdUL

        #define HWRM_NVM_WRITE                            0xfffeUL

        #define HWRM_NVM_RAW_WRITE_BLK                    0xffffUL

        #define HWRM_LAST                                HWRM_NVM_RAW_WRITE_BLK

        __le16    unused_0[3];

};


/* ret_codes (size:64b/8B) */


struct ret_codes {

        __le16    error_code;

        #define HWRM_ERR_CODE_SUCCESS                   0x0UL

        #define HWRM_ERR_CODE_FAIL                      0x1UL

        #define HWRM_ERR_CODE_INVALID_PARAMS            0x2UL

        #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED    0x3UL

        #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR      0x4UL

        #define HWRM_ERR_CODE_INVALID_FLAGS             0x5UL

        #define HWRM_ERR_CODE_INVALID_ENABLES           0x6UL

        #define HWRM_ERR_CODE_UNSUPPORTED_TLV           0x7UL

        #define HWRM_ERR_CODE_NO_BUFFER                 0x8UL

        #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR    0x9UL

        #define HWRM_ERR_CODE_HOT_RESET_PROGRESS        0xaUL

        #define HWRM_ERR_CODE_HOT_RESET_FAIL            0xbUL

        #define HWRM_ERR_CODE_HWRM_ERROR                0xfUL

        #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL

        #define HWRM_ERR_CODE_UNKNOWN_ERR               0xfffeUL

        #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED         0xffffUL

        #define HWRM_ERR_CODE_LAST                     HWRM_ERR_CODE_CMD_NOT_SUPPORTED

        __le16    unused_0[3];

};


/* hwrm_err_output (size:128b/16B) */


struct hwrm_err_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    opaque_0;

        __le16    opaque_1;

        u8    cmd_err;

        u8    valid;

};


#define HWRM_NA_SIGNATURE ((__le32)(-1))

#define HWRM_MAX_REQ_LEN 128

#define HWRM_MAX_RESP_LEN 280

#define HW_HASH_INDEX_SIZE 0x80

#define HW_HASH_KEY_SIZE 40

#define HWRM_RESP_VALID_KEY 1

#define HWRM_VERSION_MAJOR 1

#define HWRM_VERSION_MINOR 10

#define HWRM_VERSION_UPDATE 0

#define HWRM_VERSION_RSVD 18

#define HWRM_VERSION_STR "1.10.0.18"


/* hwrm_ver_get_input (size:192b/24B) */


struct hwrm_ver_get_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    hwrm_intf_maj;

        u8    hwrm_intf_min;

        u8    hwrm_intf_upd;

        u8    unused_0[5];

};


/* hwrm_ver_get_output (size:1408b/176B) */


struct hwrm_ver_get_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    hwrm_intf_maj_8b;

        u8    hwrm_intf_min_8b;

        u8    hwrm_intf_upd_8b;

        u8    hwrm_intf_rsvd_8b;

        u8    hwrm_fw_maj_8b;

        u8    hwrm_fw_min_8b;

        u8    hwrm_fw_bld_8b;

        u8    hwrm_fw_rsvd_8b;

        u8    mgmt_fw_maj_8b;

        u8    mgmt_fw_min_8b;

        u8    mgmt_fw_bld_8b;

        u8    mgmt_fw_rsvd_8b;

        u8    netctrl_fw_maj_8b;

        u8    netctrl_fw_min_8b;

        u8    netctrl_fw_bld_8b;

        u8    netctrl_fw_rsvd_8b;

        __le32    dev_caps_cfg;

        #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED                  0x1UL

        #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED                  0x2UL

        #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED                      0x4UL

        #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED                       0x8UL

        #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED                   0x10UL

        #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED              0x20UL

        #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED     0x40UL

        #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED         0x80UL

        #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED                     0x100UL

        #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED                     0x200UL

        u8    roce_fw_maj_8b;

        u8    roce_fw_min_8b;

        u8    roce_fw_bld_8b;

        u8    roce_fw_rsvd_8b;

        char    hwrm_fw_name[16];

        char    mgmt_fw_name[16];

        char    netctrl_fw_name[16];

        u8    reserved2[16];

        char    roce_fw_name[16];

        __le16    chip_num;

        u8    chip_rev;

        u8    chip_metal;

        u8    chip_bond_id;

        u8    chip_platform_type;

        #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC      0x0UL

        #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA      0x1UL

        #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL

        #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST     VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM

        __le16    max_req_win_len;

        __le16    max_resp_len;

        __le16    def_req_timeout;

        u8    flags;

        #define VER_GET_RESP_FLAGS_DEV_NOT_RDY       0x1UL

        #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL     0x2UL

        u8    unused_0[2];

        u8    always_1;

        __le16    hwrm_intf_major;

        __le16    hwrm_intf_minor;

        __le16    hwrm_intf_build;

        __le16    hwrm_intf_patch;

        __le16    hwrm_fw_major;

        __le16    hwrm_fw_minor;

        __le16    hwrm_fw_build;

        __le16    hwrm_fw_patch;

        __le16    mgmt_fw_major;

        __le16    mgmt_fw_minor;

        __le16    mgmt_fw_build;

        __le16    mgmt_fw_patch;

        __le16    netctrl_fw_major;

        __le16    netctrl_fw_minor;

        __le16    netctrl_fw_build;

        __le16    netctrl_fw_patch;

        __le16    roce_fw_major;

        __le16    roce_fw_minor;

        __le16    roce_fw_build;

        __le16    roce_fw_patch;

        __le16    max_ext_req_len;

        u8    unused_1[5];

        u8    valid;

};


/* eject_cmpl (size:128b/16B) */


struct eject_cmpl {

        __le16    type;

        #define EJECT_CMPL_TYPE_MASK       0x3fUL

        #define EJECT_CMPL_TYPE_SFT        0

        #define EJECT_CMPL_TYPE_STAT_EJECT   0x1aUL

        #define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT

        #define EJECT_CMPL_FLAGS_MASK      0xffc0UL

        #define EJECT_CMPL_FLAGS_SFT       6

        #define EJECT_CMPL_FLAGS_ERROR      0x40UL

        __le16    len;

        __le32    opaque;

        __le16    v;

        #define EJECT_CMPL_V                              0x1UL

        #define EJECT_CMPL_ERRORS_MASK                    0xfffeUL

        #define EJECT_CMPL_ERRORS_SFT                     1

        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        0xeUL

        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1

        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER     (0x0UL << 1)

        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (0x1UL << 1)

        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT    (0x3UL << 1)

        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH         (0x5UL << 1)

        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST         EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH

        __le16    reserved16;

        __le32    unused_2;

};


/* hwrm_cmpl (size:128b/16B) */


struct hwrm_cmpl {

        __le16    type;

        #define CMPL_TYPE_MASK     0x3fUL

        #define CMPL_TYPE_SFT      0

        #define CMPL_TYPE_HWRM_DONE  0x20UL

        #define CMPL_TYPE_LAST      CMPL_TYPE_HWRM_DONE

        __le16    sequence_id;

        __le32    unused_1;

        __le32    v;

        #define CMPL_V     0x1UL

        __le32    unused_3;

};


/* hwrm_fwd_req_cmpl (size:128b/16B) */


struct hwrm_fwd_req_cmpl {

        __le16    req_len_type;

        #define FWD_REQ_CMPL_TYPE_MASK        0x3fUL

        #define FWD_REQ_CMPL_TYPE_SFT         0

        #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ  0x22UL

        #define FWD_REQ_CMPL_TYPE_LAST         FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ

        #define FWD_REQ_CMPL_REQ_LEN_MASK     0xffc0UL

        #define FWD_REQ_CMPL_REQ_LEN_SFT      6

        __le16    source_id;

        __le32    unused0;

        __le32    req_buf_addr_v[2];

        #define FWD_REQ_CMPL_V                0x1UL

        #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL

        #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1

};


/* hwrm_fwd_resp_cmpl (size:128b/16B) */


struct hwrm_fwd_resp_cmpl {

        __le16    type;

        #define FWD_RESP_CMPL_TYPE_MASK         0x3fUL

        #define FWD_RESP_CMPL_TYPE_SFT          0

        #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP  0x24UL

        #define FWD_RESP_CMPL_TYPE_LAST          FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP

        __le16    source_id;

        __le16    resp_len;

        __le16    unused_1;

        __le32    resp_buf_addr_v[2];

        #define FWD_RESP_CMPL_V                 0x1UL

        #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL

        #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1

};


/* hwrm_async_event_cmpl (size:128b/16B) */


struct hwrm_async_event_cmpl {

        __le16    type;

        #define ASYNC_EVENT_CMPL_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_TYPE_LAST             ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE         0x0UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE            0x1UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE          0x2UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE          0x3UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED      0x4UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE      0x6UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE        0x7UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY               0x8UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY             0x9UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD           0x10UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD             0x11UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT        0x12UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD             0x20UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD               0x21UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR                     0x30UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE         0x31UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE   0x32UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE              0x33UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE            0x34UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE        0x35UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED               0x36UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION         0x37UL

        #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG               0xfeUL

        #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                 0xffUL

        #define ASYNC_EVENT_CMPL_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_V          0x1UL

        #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_ER_EVENT_DATA1_MASTER_FUNC          0x1UL

        #define ASYNC_EVENT_CMPL_ER_EVENT_DATA1_RECOVERY_ENABLED     0x2UL

        #define ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_FATAL       (0x2UL << 8)

        #define ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_MASK        0xff00UL

};


/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */


struct hwrm_async_event_cmpl_link_status_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE     0x1UL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN  0x0UL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP    0x1UL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK       0xeUL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT        1

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK    0xffff0UL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT     4

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK      0xff00000UL

        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT       20

};


/* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */


struct hwrm_async_event_cmpl_link_mtu_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST           ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0

};


/* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */


struct hwrm_async_event_cmpl_link_speed_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_FORCE                       0x1UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_MASK 0xfffeUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_SFT  1

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_100MB  (0x1UL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_1GB    (0xaUL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_2GB    (0x14UL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_2_5GB  (0x19UL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_10GB   (0x64UL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_20GB   (0xc8UL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_25GB   (0xfaUL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_40GB   (0x190UL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_50GB   (0x1f4UL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_100GB  (0x3e8UL << 1)

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_LAST  ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_NEW_LINK_SPEED_100MBPS_100GB

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_PORT_ID_MASK                0xffff0000UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_PORT_ID_SFT                 16

};


/* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */


struct hwrm_async_event_cmpl_dcb_config_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST             ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE

        __le32    event_data2;

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS     0x1UL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC     0x2UL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP     0x4UL

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK                0xffffUL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT                 0

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE  (0xffUL << 16)

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK  0xff000000UL

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT   24

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE    (0xffUL << 24)

        #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST   ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE

};


/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */


struct hwrm_async_event_cmpl_port_conn_not_allowed {

        __le16    type;

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V          0x1UL

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK                 0xffffUL

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT                  0

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK      0xff0000UL

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT       16

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE        (0x0UL << 16)

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (0x1UL << 16)

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG  (0x2UL << 16)

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN     (0x3UL << 16)

        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST       ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN

};


/* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */


struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {

        __le16    type;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V          0x1UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0

};


/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */


struct hwrm_async_event_cmpl_link_speed_cfg_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_PORT_ID_MASK                     0xffffUL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_PORT_ID_SFT                      0

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_SUPPORTED_LINK_SPEEDS_CHANGE     0x10000UL

        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_ILLEGAL_LINK_SPEED_CFG           0x20000UL

};


/* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */


struct hwrm_async_event_cmpl_port_phy_cfg_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST               ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_PORT_ID_MASK         0xffffUL

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_PORT_ID_SFT          0

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_FEC_CFG_CHANGE       0x10000UL

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EEE_CFG_CHANGE       0x20000UL

        #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_PAUSE_CFG_CHANGE     0x40000UL

};


/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */


struct hwrm_async_event_cmpl_reset_notify {

        __le16    type;

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST             ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST        ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V          0x1UL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK                  0xffUL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT                   0

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE    0x1UL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN           0x2UL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST                   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK                    0xff00UL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT                     8

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST  (0x1UL << 8)

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL        (0x2UL << 8)

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL    (0x3UL << 8)

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST                     ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK           0xffff0000UL

        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT            16

};


/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */


struct hwrm_async_event_cmpl_func_drvr_unload {

        __le16    type;

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST             ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST            ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V          0x1UL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0

};


/* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */


struct hwrm_async_event_cmpl_func_drvr_load {

        __le16    type;

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST             ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST          ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V          0x1UL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0

};


/* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */


struct hwrm_async_event_cmpl_func_flr_proc_cmplt {

        __le16    type;

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST             ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST               ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V          0x1UL

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0

};


/* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */


struct hwrm_async_event_cmpl_pf_drvr_unload {

        __le16    type;

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST             ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST          ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V          0x1UL

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK   0x70000UL

        #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT    16

};


/* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */


struct hwrm_async_event_cmpl_pf_drvr_load {

        __le16    type;

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST             ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST        ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V          0x1UL

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK   0x70000UL

        #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT    16

};


/* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */


struct hwrm_async_event_cmpl_vf_flr {

        __le16    type;

        #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST             ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL

        #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST  ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_VF_FLR_V          0x1UL

        #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0

        #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK 0xff0000UL

        #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16

};


/* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */


struct hwrm_async_event_cmpl_vf_mac_addr_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL

        #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0

};


/* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */


struct hwrm_async_event_cmpl_pf_vf_comm_status_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST                    ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED     0x1UL

};


/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */


struct hwrm_async_event_cmpl_vf_cfg_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST         ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE                0x1UL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE                0x2UL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE      0x4UL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE          0x8UL

        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE     0x10UL

};


/* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */


struct hwrm_async_event_cmpl_llfc_pfc_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK         0xffc0UL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT          6

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE 0x34UL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST           ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK 0x3UL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT 0

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC  0x1UL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC   0x2UL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK    0x1cUL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT     2

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK 0x1fffe0UL

        #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT  5

};


/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */


struct hwrm_async_event_cmpl_default_vnic_change {

        __le16    type;

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK         0xffc0UL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT          6

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST                   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V          0x1UL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK          0x3UL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT           0

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC  0x1UL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   0x2UL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST           ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK                   0x3fcUL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT                    2

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK                   0x3fffc00UL

        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT                    10

};


/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */


struct hwrm_async_event_cmpl_hw_flow_aged {

        __le16    type;

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST             ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST        ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED

        __le32    event_data2;

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          0x1UL

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK       0x7fffffffUL

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT        0

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION     0x80000000UL

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX    (0x0UL << 31)

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX    (0x1UL << 31)

        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX

};


/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */


struct hwrm_async_event_cmpl_hwrm_error {

        __le16    type;

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK            0x3fUL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT             0

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT  0x2eUL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST             ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT

        __le16    event_id;

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST      ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR

        __le32    event_data2;

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK    0xffUL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT     0

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING   0x0UL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL  0x1UL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL     0x2UL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST     ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL

        u8    opaque_v;

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_V          0x1UL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1

        u8    timestamp_lo;

        __le16    timestamp_hi;

        __le32    event_data1;

        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP     0x1UL

};


/* hwrm_func_reset_input (size:192b/24B) */


struct hwrm_func_reset_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID     0x1UL

        __le16    vf_id;

        u8    func_reset_level;

        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL      0x0UL

        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME       0x1UL

        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL

        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF       0x3UL

        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST         FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF

        u8    unused_0;

};


/* hwrm_func_reset_output (size:128b/16B) */


struct hwrm_func_reset_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_getfid_input (size:192b/24B) */


struct hwrm_func_getfid_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define FUNC_GETFID_REQ_ENABLES_PCI_ID     0x1UL

        __le16    pci_id;

        u8    unused_0[2];

};


/* hwrm_func_getfid_output (size:128b/16B) */


struct hwrm_func_getfid_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    fid;

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_func_vf_alloc_input (size:192b/24B) */


struct hwrm_func_vf_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID     0x1UL

        __le16    first_vf_id;

        __le16    num_vfs;

};


/* hwrm_func_vf_alloc_output (size:128b/16B) */


struct hwrm_func_vf_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    first_vf_id;

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_func_vf_free_input (size:192b/24B) */


struct hwrm_func_vf_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID     0x1UL

        __le16    first_vf_id;

        __le16    num_vfs;

};


/* hwrm_func_vf_free_output (size:128b/16B) */


struct hwrm_func_vf_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_vf_cfg_input (size:448b/56B) */


struct hwrm_func_vf_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define FUNC_VF_CFG_REQ_ENABLES_MTU                  0x1UL

        #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN           0x2UL

        #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR       0x4UL

        #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR        0x8UL

        #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS      0x10UL

        #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS       0x20UL

        #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS         0x40UL

        #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS         0x80UL

        #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS          0x100UL

        #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS            0x200UL

        #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS        0x400UL

        #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS     0x800UL

        __le16    mtu;

        __le16    guest_vlan;

        __le16    async_event_cr;

        u8    dflt_mac_addr[6];

        __le32    flags;

        #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST             0x1UL

        #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST             0x2UL

        #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST           0x4UL

        #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST     0x8UL

        #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST       0x10UL

        #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST       0x20UL

        #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST           0x40UL

        #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST         0x80UL

        __le16    num_rsscos_ctxs;

        __le16    num_cmpl_rings;

        __le16    num_tx_rings;

        __le16    num_rx_rings;

        __le16    num_l2_ctxs;

        __le16    num_vnics;

        __le16    num_stat_ctxs;

        __le16    num_hw_ring_grps;

        u8    unused_0[4];

};


/* hwrm_func_vf_cfg_output (size:128b/16B) */


struct hwrm_func_vf_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_qcaps_input (size:192b/24B) */


struct hwrm_func_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[6];

};


/* hwrm_func_qcaps_output (size:640b/80B) */


struct hwrm_func_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    fid;

        __le16    port_id;

        __le32    flags;

        #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED             0x1UL

        #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING         0x2UL

        #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED                   0x4UL

        #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED               0x8UL

        #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED               0x10UL

        #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED          0x20UL

        #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED               0x40UL

        #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED            0x80UL

        #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED             0x100UL

        #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED         0x200UL

        #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED             0x400UL

        #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED      0x800UL

        #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED      0x1000UL

        #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED       0x2000UL

        #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED         0x4000UL

        #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED        0x8000UL

        #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED            0x10000UL

        #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED            0x20000UL

        #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED              0x40000UL

        #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED     0x80000UL

        #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE                   0x100000UL

        #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC           0x200000UL

        #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE               0x400000UL

        #define FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE        0x800000UL

        u8    mac_address[6];

        __le16    max_rsscos_ctx;

        __le16    max_cmpl_rings;

        __le16    max_tx_rings;

        __le16    max_rx_rings;

        __le16    max_l2_ctxs;

        __le16    max_vnics;

        __le16    first_vf_id;

        __le16    max_vfs;

        __le16    max_stat_ctx;

        __le32    max_encap_records;

        __le32    max_decap_records;

        __le32    max_tx_em_flows;

        __le32    max_tx_wm_flows;

        __le32    max_rx_em_flows;

        __le32    max_rx_wm_flows;

        __le32    max_mcast_filters;

        __le32    max_flow_id;

        __le32    max_hw_ring_grps;

        __le16    max_sp_tx_rings;

        u8    unused_0;

        u8    valid;

};


/* hwrm_func_qcfg_input (size:192b/24B) */


struct hwrm_func_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[6];

};


/* hwrm_func_qcfg_output (size:704b/88B) */


struct hwrm_func_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    fid;

        __le16    port_id;

        __le16    vlan;

        __le16    flags;

        #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED     0x1UL

        #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED          0x2UL

        #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED        0x4UL

        #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED     0x8UL

        #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED        0x10UL

        #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST                   0x20UL

        #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF                   0x40UL

        u8    mac_address[6];

        __le16    pci_id;

        __le16    alloc_rsscos_ctx;

        __le16    alloc_cmpl_rings;

        __le16    alloc_tx_rings;

        __le16    alloc_rx_rings;

        __le16    alloc_l2_ctx;

        __le16    alloc_vnics;

        __le16    mtu;

        __le16    mru;

        __le16    stat_ctx_id;

        u8    port_partition_type;

        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF     0x0UL

        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS    0x1UL

        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL

        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL

        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL

        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL

        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST   FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN

        u8    port_pf_cnt;

        #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL

        #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST   FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL

        __le16    dflt_vnic_id;

        __le16    max_mtu_configured;

        __le32    min_bw;

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT              0

        #define FUNC_QCFG_RESP_MIN_BW_SCALE                     0x10000000UL

        #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    max_bw;

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT              0

        #define FUNC_QCFG_RESP_MAX_BW_SCALE                     0x10000000UL

        #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    evb_mode;

        #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL

        #define FUNC_QCFG_RESP_EVB_MODE_VEB    0x1UL

        #define FUNC_QCFG_RESP_EVB_MODE_VEPA   0x2UL

        #define FUNC_QCFG_RESP_EVB_MODE_LAST  FUNC_QCFG_RESP_EVB_MODE_VEPA

        u8    options;

        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK         0x3UL

        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT          0

        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL

        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL

        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST          FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128

        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL

        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT        2

        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)

        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)

        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)

        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO

        #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK                   0xf0UL

        #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT                    4

        __le16    alloc_vfs;

        __le32    alloc_mcast_filters;

        __le32    alloc_hw_ring_grps;

        __le16    alloc_sp_tx_rings;

        __le16    alloc_stat_ctx;

        __le16    alloc_msix;

        __le16    registered_vfs;

        u8    unused_1[3];

        u8    always_1;

        __le32    reset_addr_poll;

        u8    unused_2[3];

        u8    valid;

};


/* hwrm_func_cfg_input (size:704b/88B) */


struct hwrm_func_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        __le16    num_msix;

        __le32    flags;

        #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE     0x1UL

        #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE      0x2UL

        #define FUNC_CFG_REQ_FLAGS_RSVD_MASK                      0x1fcUL

        #define FUNC_CFG_REQ_FLAGS_RSVD_SFT                       2

        #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE        0x200UL

        #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE       0x400UL

        #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST               0x800UL

        #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC         0x1000UL

        #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST                 0x2000UL

        #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST                 0x4000UL

        #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST               0x8000UL

        #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST         0x10000UL

        #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST           0x20000UL

        #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST           0x40000UL

        #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST               0x80000UL

        #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST             0x100000UL

        #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE              0x200000UL

        #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC          0x400000UL

        __le32    enables;

        #define FUNC_CFG_REQ_ENABLES_MTU                     0x1UL

        #define FUNC_CFG_REQ_ENABLES_MRU                     0x2UL

        #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS         0x4UL

        #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS          0x8UL

        #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS            0x10UL

        #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS            0x20UL

        #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS             0x40UL

        #define FUNC_CFG_REQ_ENABLES_NUM_VNICS               0x80UL

        #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS           0x100UL

        #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR           0x200UL

        #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN               0x400UL

        #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR            0x800UL

        #define FUNC_CFG_REQ_ENABLES_MIN_BW                  0x1000UL

        #define FUNC_CFG_REQ_ENABLES_MAX_BW                  0x2000UL

        #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR          0x4000UL

        #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE     0x8000UL

        #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS       0x10000UL

        #define FUNC_CFG_REQ_ENABLES_EVB_MODE                0x20000UL

        #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS       0x40000UL

        #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS        0x80000UL

        #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE          0x100000UL

        #define FUNC_CFG_REQ_ENABLES_NUM_MSIX                0x200000UL

        #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE        0x400000UL

        __le16    mtu;

        __le16    mru;

        __le16    num_rsscos_ctxs;

        __le16    num_cmpl_rings;

        __le16    num_tx_rings;

        __le16    num_rx_rings;

        __le16    num_l2_ctxs;

        __le16    num_vnics;

        __le16    num_stat_ctxs;

        __le16    num_hw_ring_grps;

        u8    dflt_mac_addr[6];

        __le16    dflt_vlan;

        __be32    dflt_ip_addr[4];

        __le32    min_bw;

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT              0

        #define FUNC_CFG_REQ_MIN_BW_SCALE                     0x10000000UL

        #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_MIN_BW_SCALE_BYTES

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    max_bw;

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT              0

        #define FUNC_CFG_REQ_MAX_BW_SCALE                     0x10000000UL

        #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_MAX_BW_SCALE_BYTES

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID

        __le16    async_event_cr;

        u8    vlan_antispoof_mode;

        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK                 0x0UL

        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN           0x1UL

        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE       0x2UL

        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL

        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST                   FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN

        u8    allowed_vlan_pris;

        u8    evb_mode;

        #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL

        #define FUNC_CFG_REQ_EVB_MODE_VEB    0x1UL

        #define FUNC_CFG_REQ_EVB_MODE_VEPA   0x2UL

        #define FUNC_CFG_REQ_EVB_MODE_LAST  FUNC_CFG_REQ_EVB_MODE_VEPA

        u8    options;

        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK         0x3UL

        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT          0

        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL

        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL

        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST          FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128

        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL

        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT        2

        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)

        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)

        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)

        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO

        #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK                   0xf0UL

        #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT                    4

        __le16    num_mcast_filters;

};


/* hwrm_func_cfg_output (size:128b/16B) */


struct hwrm_func_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_qstats_input (size:192b/24B) */


struct hwrm_func_qstats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[6];

};


/* hwrm_func_qstats_output (size:1408b/176B) */


struct hwrm_func_qstats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    tx_ucast_pkts;

        __le64    tx_mcast_pkts;

        __le64    tx_bcast_pkts;

        __le64    tx_discard_pkts;

        __le64    tx_drop_pkts;

        __le64    tx_ucast_bytes;

        __le64    tx_mcast_bytes;

        __le64    tx_bcast_bytes;

        __le64    rx_ucast_pkts;

        __le64    rx_mcast_pkts;

        __le64    rx_bcast_pkts;

        __le64    rx_discard_pkts;

        __le64    rx_drop_pkts;

        __le64    rx_ucast_bytes;

        __le64    rx_mcast_bytes;

        __le64    rx_bcast_bytes;

        __le64    rx_agg_pkts;

        __le64    rx_agg_bytes;

        __le64    rx_agg_events;

        __le64    rx_agg_aborts;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_clr_stats_input (size:192b/24B) */


struct hwrm_func_clr_stats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[6];

};


/* hwrm_func_clr_stats_output (size:128b/16B) */


struct hwrm_func_clr_stats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_vf_resc_free_input (size:192b/24B) */


struct hwrm_func_vf_resc_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    vf_id;

        u8    unused_0[6];

};


/* hwrm_func_vf_resc_free_output (size:128b/16B) */


struct hwrm_func_vf_resc_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_error_recovery_input (size:192b/24B) */


struct hwrm_error_recovery_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    unused_0[8];

};


/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */


struct hwrm_error_recovery_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    flags;

        #define ER_QCFG_FLAGS_HOST       0x1UL

        #define ER_QCFG_FLAGS_CO_CPU     0x2UL

        __le32    driver_polling_freq;

        __le32    master_wait_period;

        __le32    normal_wait_period;

        __le32    master_wait_post_reset;

        __le32    max_bailout_time;

        __le32    fw_health_status_reg;

        #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK    0x3UL

        #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_SFT     0

        #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG  0x0UL

        #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC       0x1UL

        #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0      0x2UL

        #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1      0x3UL

        #define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_LAST     ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1

        #define ER_QCFG_FW_HEALTH_REG_ADDR_MASK          0xfffffffcUL

        #define ER_QCFG_FW_HEALTH_REG_ADDR_SFT           2

        __le32    fw_heartbeat_reg;

        #define ER_QCFG_FW_HB_REG_ADDR_SPACE_MASK    0x3UL

        #define ER_QCFG_FW_HB_REG_ADDR_SPACE_SFT     0

        #define ER_QCFG_FW_HB_REG_ADDR_SPACE_PCIE_CFG  0x0UL

        #define ER_QCFG_FW_HB_REG_ADDR_SPACE_GRC       0x1UL

        #define ER_QCFG_FW_HB_REG_ADDR_SPACE_BAR0      0x2UL

        #define ER_QCFG_FW_HB_REG_ADDR_SPACE_BAR1      0x3UL

        #define ER_QCFG_FW_HB_REG_ADDR_SPACE_LAST     ER_QCFG_FW_HB_REG_ADDR_SPACE_BAR1

        #define ER_QCFG_FW_HB_REG_ADDR_MASK          0xfffffffcUL

        #define ER_QCFG_FW_HB_REG_ADDR_SFT           2

        __le32    fw_reset_cnt_reg;

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_MASK    0x3UL

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_SFT     0

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_GRC       0x1UL

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_BAR0      0x2UL

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_BAR1      0x3UL

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_LAST     ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_BAR1

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_MASK          0xfffffffcUL

        #define ER_QCFG_FW_RESET_CNT_REG_ADDR_SFT           2

        __le32    reset_inprogress_reg;

        #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_MASK    0x3UL

        #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_SFT     0

        #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_PCIE_CFG  0x0UL

        #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_GRC       0x1UL

        #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_BAR0      0x2UL

        #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_BAR1      0x3UL

        #define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_LAST     ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_BAR1

        #define ER_QCFG_RESET_INPRG_REG_ADDR_MASK          0xfffffffcUL

        #define ER_QCFG_RESET_INPRG_REG_ADDR_SFT           2

        __le32    reset_inprogress_reg_mask;

        u8    unused_0[3];

        u8    reg_array_cnt;

        __le32    reset_reg[16];

        #define ER_QCFG_RESET_REG_ADDR_SPACE_MASK    0x3UL

        #define ER_QCFG_RESET_REG_ADDR_SPACE_SFT     0

        #define ER_QCFG_RESET_REG_ADDR_SPACE_PCIE_CFG  0x0UL

        #define ER_QCFG_RESET_REG_ADDR_SPACE_GRC       0x1UL

        #define ER_QCFG_RESET_REG_ADDR_SPACE_BAR0      0x2UL

        #define ER_QCFG_RESET_REG_ADDR_SPACE_BAR1      0x3UL

        #define ER_QCFG_RESET_REG_ADDR_SPACE_LAST     ER_QCFG_RESET_REG_ADDR_SPACE_BAR1

        #define ER_QCFG_RESET_REG_ADDR_MASK          0xfffffffcUL

        #define ER_QCFG_RESET_REG_ADDR_SFT           2

        __le32    reset_reg_val[16];

        u8    delay_after_reset[16];

        __le32    err_recovery_cnt_reg;

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_MASK    0x3UL

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_SFT     0

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_GRC       0x1UL

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_BAR0      0x2UL

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_BAR1      0x3UL

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_LAST     ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_BAR1

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_MASK          0xfffffffcUL

        #define ER_QCFG_RCVRY_CNT_REG_ADDR_SFT           2

        u8    unused_1[3];

        u8    valid;

};


/* hwrm_func_drv_rgtr_input (size:896b/112B) */


struct hwrm_func_drv_rgtr_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE               0x1UL

        #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE              0x2UL

        #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE             0x4UL

        #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE     0x8UL

        #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT          0x10UL

        #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT     0x20UL

        #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT             0x40UL

        __le32    enables;

        #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE             0x1UL

        #define FUNC_DRV_RGTR_REQ_ENABLES_VER                 0x2UL

        #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP           0x4UL

        #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD          0x8UL

        #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD     0x10UL

        __le16    os_type;

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN   0x0UL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER     0x1UL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS     0xeUL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS   0x12UL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS   0x1dUL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX     0x24UL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD   0x2aUL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI      0x68UL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864    0x73UL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI      0x8000UL

        #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST     FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI

        u8    ver_maj_8b;

        u8    ver_min_8b;

        u8    ver_upd_8b;

        u8    unused_0[3];

        __le32    timestamp;

        u8    unused_1[4];

        __le32    vf_req_fwd[8];

        __le32    async_event_fwd[8];

        __le16    ver_maj;

        __le16    ver_min;

        __le16    ver_upd;

        __le16    ver_patch;

};


/* hwrm_func_drv_rgtr_output (size:128b/16B) */


struct hwrm_func_drv_rgtr_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    flags;

        #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED     0x1UL

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_func_drv_unrgtr_input (size:192b/24B) */


struct hwrm_func_drv_unrgtr_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN     0x1UL

        u8    unused_0[4];

};


/* hwrm_func_drv_unrgtr_output (size:128b/16B) */


struct hwrm_func_drv_unrgtr_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_buf_rgtr_input (size:1024b/128B) */


struct hwrm_func_buf_rgtr_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID            0x1UL

        #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR     0x2UL

        __le16    vf_id;

        __le16    req_buf_num_pages;

        __le16    req_buf_page_size;

        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL

        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K  0xcUL

        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K  0xdUL

        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL

        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M  0x15UL

        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M  0x16UL

        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G  0x1eUL

        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G

        __le16    req_buf_len;

        __le16    resp_buf_len;

        u8    unused_0[2];

        __le64    req_buf_page_addr0;

        __le64    req_buf_page_addr1;

        __le64    req_buf_page_addr2;

        __le64    req_buf_page_addr3;

        __le64    req_buf_page_addr4;

        __le64    req_buf_page_addr5;

        __le64    req_buf_page_addr6;

        __le64    req_buf_page_addr7;

        __le64    req_buf_page_addr8;

        __le64    req_buf_page_addr9;

        __le64    error_buf_addr;

        __le64    resp_buf_addr;

};


/* hwrm_func_buf_rgtr_output (size:128b/16B) */


struct hwrm_func_buf_rgtr_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_buf_unrgtr_input (size:192b/24B) */


struct hwrm_func_buf_unrgtr_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define FUNC_BUF_UNRGTR_REQ_ENABLES_VF_ID     0x1UL

        __le16    vf_id;

        u8    unused_0[2];

};


/* hwrm_func_buf_unrgtr_output (size:128b/16B) */


struct hwrm_func_buf_unrgtr_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_drv_qver_input (size:192b/24B) */


struct hwrm_func_drv_qver_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    reserved;

        __le16    fid;

        u8    unused_0[2];

};


/* hwrm_func_drv_qver_output (size:256b/32B) */


struct hwrm_func_drv_qver_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    os_type;

        #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN   0x0UL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER     0x1UL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS     0xeUL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS   0x12UL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS   0x1dUL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX     0x24UL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD   0x2aUL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI      0x68UL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864    0x73UL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI      0x8000UL

        #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST     FUNC_DRV_QVER_RESP_OS_TYPE_UEFI

        u8    ver_maj_8b;

        u8    ver_min_8b;

        u8    ver_upd_8b;

        u8    unused_0[3];

        __le16    ver_maj;

        __le16    ver_min;

        __le16    ver_upd;

        __le16    ver_patch;

        u8    unused_1[7];

        u8    valid;

};


/* hwrm_func_resource_qcaps_input (size:192b/24B) */


struct hwrm_func_resource_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[6];

};


/* hwrm_func_resource_qcaps_output (size:448b/56B) */


struct hwrm_func_resource_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    max_vfs;

        __le16    max_msix;

        __le16    vf_reservation_strategy;

        #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL        0x0UL

        #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL        0x1UL

        #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL

        #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST          FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC

        __le16    min_rsscos_ctx;

        __le16    max_rsscos_ctx;

        __le16    min_cmpl_rings;

        __le16    max_cmpl_rings;

        __le16    min_tx_rings;

        __le16    max_tx_rings;

        __le16    min_rx_rings;

        __le16    max_rx_rings;

        __le16    min_l2_ctxs;

        __le16    max_l2_ctxs;

        __le16    min_vnics;

        __le16    max_vnics;

        __le16    min_stat_ctx;

        __le16    max_stat_ctx;

        __le16    min_hw_ring_grps;

        __le16    max_hw_ring_grps;

        __le16    max_tx_scheduler_inputs;

        __le16    flags;

        #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED     0x1UL

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */


struct hwrm_func_vf_resource_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    vf_id;

        __le16    max_msix;

        __le16    min_rsscos_ctx;

        __le16    max_rsscos_ctx;

        __le16    min_cmpl_rings;

        __le16    max_cmpl_rings;

        __le16    min_tx_rings;

        __le16    max_tx_rings;

        __le16    min_rx_rings;

        __le16    max_rx_rings;

        __le16    min_l2_ctxs;

        __le16    max_l2_ctxs;

        __le16    min_vnics;

        __le16    max_vnics;

        __le16    min_stat_ctx;

        __le16    max_stat_ctx;

        __le16    min_hw_ring_grps;

        __le16    max_hw_ring_grps;

        __le16    flags;

        #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED     0x1UL

        u8    unused_0[2];

};


/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */


struct hwrm_func_vf_resource_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    reserved_rsscos_ctx;

        __le16    reserved_cmpl_rings;

        __le16    reserved_tx_rings;

        __le16    reserved_rx_rings;

        __le16    reserved_l2_ctxs;

        __le16    reserved_vnics;

        __le16    reserved_stat_ctx;

        __le16    reserved_hw_ring_grps;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */


struct hwrm_func_backing_store_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */


struct hwrm_func_backing_store_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    qp_max_entries;

        __le16    qp_min_qp1_entries;

        __le16    qp_max_l2_entries;

        __le16    qp_entry_size;

        __le16    srq_max_l2_entries;

        __le32    srq_max_entries;

        __le16    srq_entry_size;

        __le16    cq_max_l2_entries;

        __le32    cq_max_entries;

        __le16    cq_entry_size;

        __le16    vnic_max_vnic_entries;

        __le16    vnic_max_ring_table_entries;

        __le16    vnic_entry_size;

        __le32    stat_max_entries;

        __le16    stat_entry_size;

        __le16    tqm_entry_size;

        __le32    tqm_min_entries_per_ring;

        __le32    tqm_max_entries_per_ring;

        __le32    mrav_max_entries;

        __le16    mrav_entry_size;

        __le16    tim_entry_size;

        __le32    tim_max_entries;

        u8    unused_0[2];

        u8    tqm_entries_multiple;

        u8    valid;

};


/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */


struct hwrm_func_backing_store_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE     0x1UL

        __le32    enables;

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP            0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ           0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ            0x4UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC          0x8UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT          0x10UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP        0x20UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0     0x40UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1     0x80UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2     0x100UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3     0x200UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4     0x400UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5     0x800UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6     0x1000UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7     0x2000UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV          0x4000UL

        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM           0x8000UL

        u8    qpc_pg_size_qpc_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G

        u8    srq_pg_size_srq_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G

        u8    cq_pg_size_cq_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G

        u8    vnic_pg_size_vnic_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G

        u8    stat_pg_size_stat_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G

        u8    tqm_sp_pg_size_tqm_sp_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G

        u8    tqm_ring0_pg_size_tqm_ring0_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G

        u8    tqm_ring1_pg_size_tqm_ring1_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G

        u8    tqm_ring2_pg_size_tqm_ring2_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G

        u8    tqm_ring3_pg_size_tqm_ring3_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G

        u8    tqm_ring4_pg_size_tqm_ring4_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G

        u8    tqm_ring5_pg_size_tqm_ring5_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G

        u8    tqm_ring6_pg_size_tqm_ring6_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G

        u8    tqm_ring7_pg_size_tqm_ring7_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G

        u8    mrav_pg_size_mrav_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G

        u8    tim_pg_size_tim_lvl;

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT       0

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G

        __le64    qpc_page_dir;

        __le64    srq_page_dir;

        __le64    cq_page_dir;

        __le64    vnic_page_dir;

        __le64    stat_page_dir;

        __le64    tqm_sp_page_dir;

        __le64    tqm_ring0_page_dir;

        __le64    tqm_ring1_page_dir;

        __le64    tqm_ring2_page_dir;

        __le64    tqm_ring3_page_dir;

        __le64    tqm_ring4_page_dir;

        __le64    tqm_ring5_page_dir;

        __le64    tqm_ring6_page_dir;

        __le64    tqm_ring7_page_dir;

        __le64    mrav_page_dir;

        __le64    tim_page_dir;

        __le32    qp_num_entries;

        __le32    srq_num_entries;

        __le32    cq_num_entries;

        __le32    stat_num_entries;

        __le32    tqm_sp_num_entries;

        __le32    tqm_ring0_num_entries;

        __le32    tqm_ring1_num_entries;

        __le32    tqm_ring2_num_entries;

        __le32    tqm_ring3_num_entries;

        __le32    tqm_ring4_num_entries;

        __le32    tqm_ring5_num_entries;

        __le32    tqm_ring6_num_entries;

        __le32    tqm_ring7_num_entries;

        __le32    mrav_num_entries;

        __le32    tim_num_entries;

        __le16    qp_num_qp1_entries;

        __le16    qp_num_l2_entries;

        __le16    qp_entry_size;

        __le16    srq_num_l2_entries;

        __le16    srq_entry_size;

        __le16    cq_num_l2_entries;

        __le16    cq_entry_size;

        __le16    vnic_num_vnic_entries;

        __le16    vnic_num_ring_table_entries;

        __le16    vnic_entry_size;

        __le16    stat_entry_size;

        __le16    tqm_entry_size;

        __le16    mrav_entry_size;

        __le16    tim_entry_size;

};


/* hwrm_func_backing_store_cfg_output (size:128b/16B) */


struct hwrm_func_backing_store_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_backing_store_qcfg_input (size:128b/16B) */


struct hwrm_func_backing_store_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */


struct hwrm_func_backing_store_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    flags;

        #define FUNC_BACKING_STORE_QCFG_RESP_FLAGS_PREBOOT_MODE     0x1UL

        u8    unused_0[4];

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_QP            0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_SRQ           0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_CQ            0x4UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_VNIC          0x8UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_STAT          0x10UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_SP        0x20UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING0     0x40UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING1     0x80UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING2     0x100UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING3     0x200UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING4     0x400UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING5     0x800UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING6     0x1000UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING7     0x2000UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_MRAV          0x4000UL

        #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TIM           0x8000UL

        u8    qpc_pg_size_qpc_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G

        u8    srq_pg_size_srq_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G

        u8    cq_pg_size_cq_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G

        u8    vnic_pg_size_vnic_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G

        u8    stat_pg_size_stat_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G

        u8    tqm_sp_pg_size_tqm_sp_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G

        u8    tqm_ring0_pg_size_tqm_ring0_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G

        u8    tqm_ring1_pg_size_tqm_ring1_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G

        u8    tqm_ring2_pg_size_tqm_ring2_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G

        u8    tqm_ring3_pg_size_tqm_ring3_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G

        u8    tqm_ring4_pg_size_tqm_ring4_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G

        u8    tqm_ring5_pg_size_tqm_ring5_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G

        u8    tqm_ring6_pg_size_tqm_ring6_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G

        u8    tqm_ring7_pg_size_tqm_ring7_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G

        u8    mrav_pg_size_mrav_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G

        u8    tim_pg_size_tim_lvl;

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_MASK      0xfUL

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_SFT       0

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_0       0x0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_1       0x1UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2       0x2UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LAST       FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_MASK  0xf0UL

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_SFT   4

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_4K   (0x0UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8K   (0x1UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_64K  (0x2UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_2M   (0x3UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8M   (0x4UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G   (0x5UL << 4)

        #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G

        __le64    qpc_page_dir;

        __le64    srq_page_dir;

        __le64    cq_page_dir;

        __le64    vnic_page_dir;

        __le64    stat_page_dir;

        __le64    tqm_sp_page_dir;

        __le64    tqm_ring0_page_dir;

        __le64    tqm_ring1_page_dir;

        __le64    tqm_ring2_page_dir;

        __le64    tqm_ring3_page_dir;

        __le64    tqm_ring4_page_dir;

        __le64    tqm_ring5_page_dir;

        __le64    tqm_ring6_page_dir;

        __le64    tqm_ring7_page_dir;

        __le64    mrav_page_dir;

        __le64    tim_page_dir;

        __le16    qp_num_qp1_entries;

        __le16    qp_num_l2_entries;

        __le32    qp_num_entries;

        __le32    srq_num_entries;

        __le16    srq_num_l2_entries;

        __le16    cq_num_l2_entries;

        __le32    cq_num_entries;

        __le16    vnic_num_vnic_entries;

        __le16    vnic_num_ring_table_entries;

        __le32    stat_num_entries;

        __le32    tqm_sp_num_entries;

        __le32    tqm_ring0_num_entries;

        __le32    tqm_ring1_num_entries;

        __le32    tqm_ring2_num_entries;

        __le32    tqm_ring3_num_entries;

        __le32    tqm_ring4_num_entries;

        __le32    tqm_ring5_num_entries;

        __le32    tqm_ring6_num_entries;

        __le32    tqm_ring7_num_entries;

        __le32    mrav_num_entries;

        __le32    tim_num_entries;

        u8    unused_1[7];

        u8    valid;

};


/* hwrm_func_vlan_qcfg_input (size:192b/24B) */


struct hwrm_func_vlan_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[6];

};


/* hwrm_func_vlan_qcfg_output (size:320b/40B) */


struct hwrm_func_vlan_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    unused_0;

        __le16    stag_vid;

        u8    stag_pcp;

        u8    unused_1;

        __be16    stag_tpid;

        __le16    ctag_vid;

        u8    ctag_pcp;

        u8    unused_2;

        __be16    ctag_tpid;

        __le32    rsvd2;

        __le32    rsvd3;

        u8    unused_3[3];

        u8    valid;

};


/* hwrm_func_vlan_cfg_input (size:384b/48B) */


struct hwrm_func_vlan_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[2];

        __le32    enables;

        #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID      0x1UL

        #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID      0x2UL

        #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP      0x4UL

        #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP      0x8UL

        #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID     0x10UL

        #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID     0x20UL

        __le16    stag_vid;

        u8    stag_pcp;

        u8    unused_1;

        __be16    stag_tpid;

        __le16    ctag_vid;

        u8    ctag_pcp;

        u8    unused_2;

        __be16    ctag_tpid;

        __le32    rsvd1;

        __le32    rsvd2;

        u8    unused_3[4];

};


/* hwrm_func_vlan_cfg_output (size:128b/16B) */


struct hwrm_func_vlan_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */


struct hwrm_func_vf_vnic_ids_query_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    vf_id;

        u8    unused_0[2];

        __le32    max_vnic_id_cnt;

        __le64    vnic_id_tbl_addr;

};


/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */


struct hwrm_func_vf_vnic_ids_query_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    vnic_id_cnt;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */


struct hwrm_func_vf_bw_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    num_vfs;

        __le16    unused[3];

        __le16    vfn[48];

        #define FUNC_VF_BW_CFG_REQ_VFN_VFID_MASK     0xfffUL

        #define FUNC_VF_BW_CFG_REQ_VFN_VFID_SFT      0

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_MASK     0xf000UL

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_SFT      12

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_0      (0x0UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_6_66   (0x1UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_13_33  (0x2UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_20     (0x3UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_26_66  (0x4UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_33_33  (0x5UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_40     (0x6UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_46_66  (0x7UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_53_33  (0x8UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_60     (0x9UL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_66_66  (0xaUL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_73_33  (0xbUL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_80     (0xcUL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_86_66  (0xdUL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_93_33  (0xeUL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100    (0xfUL << 12)

        #define FUNC_VF_BW_CFG_REQ_VFN_RATE_LAST      FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100

};


/* hwrm_func_vf_bw_cfg_output (size:128b/16B) */


struct hwrm_func_vf_bw_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */


struct hwrm_func_vf_bw_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    num_vfs;

        __le16    unused[3];

        __le16    vfn[48];

        #define FUNC_VF_BW_QCFG_REQ_VFN_VFID_MASK 0xfffUL

        #define FUNC_VF_BW_QCFG_REQ_VFN_VFID_SFT 0

};


/* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */


struct hwrm_func_vf_bw_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    num_vfs;

        __le16    unused[3];

        __le16    vfn[48];

        #define FUNC_VF_BW_QCFG_RESP_VFN_VFID_MASK     0xfffUL

        #define FUNC_VF_BW_QCFG_RESP_VFN_VFID_SFT      0

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_MASK     0xf000UL

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_SFT      12

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_0      (0x0UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_6_66   (0x1UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_13_33  (0x2UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_20     (0x3UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_26_66  (0x4UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_33_33  (0x5UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_40     (0x6UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_46_66  (0x7UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_53_33  (0x8UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_60     (0x9UL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_66_66  (0xaUL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_73_33  (0xbUL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_80     (0xcUL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_86_66  (0xdUL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_93_33  (0xeUL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100    (0xfUL << 12)

        #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_LAST      FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_func_drv_if_change_input (size:192b/24B) */


struct hwrm_func_drv_if_change_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP     0x1UL

        __le32    unused;

};


/* hwrm_func_drv_if_change_output (size:128b/16B) */


struct hwrm_func_drv_if_change_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    flags;

        #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE     0x1UL

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_port_phy_cfg_input (size:512b/64B) */


struct hwrm_port_phy_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY                0x1UL

        #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED               0x2UL

        #define PORT_PHY_CFG_REQ_FLAGS_FORCE                    0x4UL

        #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG          0x8UL

        #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE               0x10UL

        #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE              0x20UL

        #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE        0x40UL

        #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE       0x80UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE       0x100UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE      0x200UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE      0x400UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE     0x800UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE      0x1000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE     0x2000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN           0x4000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE     0x8000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE    0x10000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE    0x20000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE   0x40000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE     0x80000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE    0x100000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE    0x200000UL

        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE   0x400000UL


        __le32    enables;

        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE                0x1UL

        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX              0x2UL

        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE               0x4UL

        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED          0x8UL

        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK     0x10UL

        #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED                0x20UL

        #define PORT_PHY_CFG_REQ_ENABLES_LPBK                     0x40UL

        #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS              0x80UL

        #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE              0x100UL

        #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK      0x200UL

        #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER             0x400UL

        #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED         0x800UL

        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK     0x1000UL

        #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2            0x2000UL

        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK        0x4000UL

        __le16    port_id;

        __le16    force_link_speed;

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB   0xaUL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB   0x14UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB  0x64UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB  0xc8UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB  0xfaUL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB  0x190UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB  0x1f4UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB  0xffffUL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB

        u8    auto_mode;

        #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE         0x0UL

        #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS   0x1UL

        #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED    0x2UL

        #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL

        #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK   0x4UL

        #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST        PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK

        u8    auto_duplex;

        #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL

        #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL

        #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL

        #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH

        u8    auto_pause;

        #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX                0x1UL

        #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX                0x2UL

        #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL

        u8    unused_0;

        __le16    auto_link_speed;

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB   0xaUL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB   0x14UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB  0x64UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB  0xc8UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB  0xfaUL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB  0x190UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB  0x1f4UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB  0xffffUL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB

        __le16    auto_link_speed_mask;

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB       0x2UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB         0x8UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB         0x10UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB        0x40UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB        0x80UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB        0x100UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB        0x200UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB        0x400UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB       0x800UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB        0x2000UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB       0x4000UL

        u8    wirespeed;

        #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL

        #define PORT_PHY_CFG_REQ_WIRESPEED_ON  0x1UL

        #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON

        u8    lpbk;

        #define PORT_PHY_CFG_REQ_LPBK_NONE     0x0UL

        #define PORT_PHY_CFG_REQ_LPBK_LOCAL    0x1UL

        #define PORT_PHY_CFG_REQ_LPBK_REMOTE   0x2UL

        #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL

        #define PORT_PHY_CFG_REQ_LPBK_LAST    PORT_PHY_CFG_REQ_LPBK_EXTERNAL

        u8    force_pause;

        #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX     0x1UL

        #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX     0x2UL

        u8    unused_1;

        __le32    preemphasis;

        __le16    eee_link_speed_mask;

        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1     0x1UL

        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB     0x2UL

        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2     0x4UL

        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB       0x8UL

        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3     0x10UL

        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4     0x20UL

        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB      0x40UL

        __le16    force_pam4_link_speed;

        #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL

        #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL

        #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL

        #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB

        __le32    tx_lpi_timer;

        #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL

        #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0

        __le16    auto_link_pam4_speed_mask;

        #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G      0x1UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G     0x2UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G     0x4UL

        __le16    force_link_speeds2;

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB            0xaUL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB           0x64UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB           0xfaUL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB           0x190UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB           0x1f4UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB          0x3e8UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56   0x1f5UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56  0x3e9UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56  0x7d1UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56  0xfa1UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL

        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112

        __le16    auto_link_speeds2_mask;

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB                0x1UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB               0x2UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB               0x4UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB               0x8UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB               0x10UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB              0x20UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56       0x40UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56      0x80UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56      0x100UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56      0x200UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112     0x400UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112     0x800UL

        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112     0x1000UL

        u8    unused_2[6];

};


/* hwrm_port_phy_cfg_output (size:128b/16B) */


struct hwrm_port_phy_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */


struct hwrm_port_phy_cfg_cmd_err {

        u8    code;

        #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN       0x0UL

        #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL

        #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY         0x2UL

        #define PORT_PHY_CFG_CMD_ERR_CODE_LAST         PORT_PHY_CFG_CMD_ERR_CODE_RETRY

        u8    unused_0[7];

};


/* hwrm_port_phy_qcfg_input (size:192b/24B) */


struct hwrm_port_phy_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

};


/* hwrm_port_phy_qcfg_output (size:832b/104B) */


struct hwrm_port_phy_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    link;

        #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL

        #define PORT_PHY_QCFG_RESP_LINK_SIGNAL  0x1UL

        #define PORT_PHY_QCFG_RESP_LINK_LINK    0x2UL

        #define PORT_PHY_QCFG_RESP_LINK_LAST   PORT_PHY_QCFG_RESP_LINK_LINK

        u8    active_fec_signal_mode;

        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK     0xfUL

        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT      0

        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ      0x0UL

        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4     0x1UL

        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL

        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST     HWRM_PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK                   0xf0UL

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT                    4

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE        (0x0UL << 4)

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE    (0x1UL << 4)

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE    (0x2UL << 4)

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE   (0x3UL << 4)

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE  (0x4UL << 4)

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE   (0x5UL << 4)

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE  (0x6UL << 4)

        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST                   PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE

        __le16    link_speed;

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB   0xaUL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB   0x14UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB  0x64UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB  0xc8UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB  0xfaUL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB  0x190UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB  0x1f4UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB  0xffffUL

        #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB

        u8    duplex_cfg;

        #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL

        #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL

        #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL

        u8    pause;

        #define PORT_PHY_QCFG_RESP_PAUSE_TX     0x1UL

        #define PORT_PHY_QCFG_RESP_PAUSE_RX     0x2UL

        __le16    support_speeds;

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD     0x1UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB       0x2UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD       0x4UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB         0x8UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB         0x10UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB       0x20UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB        0x40UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB        0x80UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB        0x100UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB        0x200UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB        0x400UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB       0x800UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD      0x1000UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB        0x2000UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB       0x4000UL

        __le16    force_link_speed;

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB   0xaUL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB   0x14UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB  0x64UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB  0xc8UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB  0xfaUL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB  0x190UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB  0x1f4UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB  0xffffUL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB

        u8    auto_mode;

        #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE         0x0UL

        #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS   0x1UL

        #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED    0x2UL

        #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL

        #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK   0x4UL

        #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK

        u8    auto_pause;

        #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX                0x1UL

        #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX                0x2UL

        #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL

        __le16    auto_link_speed;

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB   0xaUL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB   0x14UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB  0x64UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB  0xc8UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB  0xfaUL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB  0x190UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB  0x1f4UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB  0xffffUL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB

        __le16    auto_link_speed_mask;

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB       0x2UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB         0x8UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB         0x10UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB        0x40UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB        0x80UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB        0x100UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB        0x200UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB        0x400UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB       0x800UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB        0x2000UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB       0x4000UL

        u8    wirespeed;

        #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL

        #define PORT_PHY_QCFG_RESP_WIRESPEED_ON  0x1UL

        #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON

        u8    lpbk;

        #define PORT_PHY_QCFG_RESP_LPBK_NONE     0x0UL

        #define PORT_PHY_QCFG_RESP_LPBK_LOCAL    0x1UL

        #define PORT_PHY_QCFG_RESP_LPBK_REMOTE   0x2UL

        #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL

        #define PORT_PHY_QCFG_RESP_LPBK_LAST    PORT_PHY_QCFG_RESP_LPBK_EXTERNAL

        u8    force_pause;

        #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX     0x1UL

        #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX     0x2UL

        u8    module_status;

        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE          0x0UL

        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX     0x1UL

        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG    0x2UL

        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN       0x3UL

        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED   0x4UL

        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL

        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST         PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE

        __le32    preemphasis;

        u8    phy_maj;

        u8    phy_min;

        u8    phy_bld;

        u8    phy_type;

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN          0x0UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR           0x1UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4          0x2UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR           0x3UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR           0x4UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2          0x5UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX           0x6UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR           0x7UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET            0x8UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE           0x9UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY      0xaUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L  0xbUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S  0xcUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N  0xdUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR       0xeUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4     0xfUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4     0x10UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4     0x11UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4     0x12UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10    0x13UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4      0x14UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4      0x15UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4      0x16UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4      0x17UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET         0x19UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX        0x1aUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX        0x1bUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4     0x1cUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4     0x1dUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4     0x1eUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4     0x1fUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR       0x20UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR       0x21UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR       0x22UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER       0x23UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2     0x24UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2     0x25UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2     0x26UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2     0x27UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR      0x28UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR      0x29UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR      0x2aUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER      0x2bUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2     0x2cUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2     0x2dUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2     0x2eUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2     0x2fUL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8     0x30UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8     0x31UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8     0x32UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8     0x33UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4     0x34UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4     0x35UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4     0x36UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4     0x37UL

        #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4

        u8    media_type;

        #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL

        #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP      0x1UL

        #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC     0x2UL

        #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE   0x3UL

        #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST   PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE

        u8    xcvr_pkg_type;

        #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL

        #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL

        #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST         PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL

        u8    eee_config_phy_addr;

        #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK              0x1fUL

        #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT               0

        #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK            0xe0UL

        #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT             5

        #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED      0x20UL

        #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE       0x40UL

        #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI       0x80UL

        u8    parallel_detect;

        #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT     0x1UL

        __le16    link_partner_adv_speeds;

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD     0x1UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB       0x2UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD       0x4UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB         0x8UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB         0x10UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB       0x20UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB        0x40UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB        0x80UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB        0x100UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB        0x200UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB        0x400UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB       0x800UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD      0x1000UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB        0x2000UL

        u8    link_partner_adv_auto_mode;

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE         0x0UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS   0x1UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED    0x2UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK   0x4UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK

        u8    link_partner_adv_pause;

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX     0x1UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX     0x2UL

        __le16    adv_eee_link_speed_mask;

        #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL

        #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL

        #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL

        #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL

        #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL

        #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL

        #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL

        __le16    link_partner_adv_eee_link_speed_mask;

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL

        __le32    xcvr_identifier_type_tx_lpi_timer;

        #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK            0xffffffUL

        #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT             0

        #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK    0xff000000UL

        #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT     24

        #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN   (0x0UL << 24)

        #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP       (0x3UL << 24)

        #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP      (0xcUL << 24)

        #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS  (0xdUL << 24)

        #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28    (0x11UL << 24)

        #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST     PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28

        __le16    fec_cfg;

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED         0x1UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED      0x2UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED        0x4UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED     0x8UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED       0x10UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED     0x20UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED       0x40UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED    0x80UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED      0x100UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED   0x200UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED     0x400UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED    0x800UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED      0x1000UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED   0x2000UL

        #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED     0x4000UL

        u8    duplex_state;

        #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL

        #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL

        #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL

        u8    option_flags;

        #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT     0x1UL

        #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN     0x2UL

        #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED     0x4UL

        char    phy_vendor_name[16];

        char    phy_vendor_partnumber[16];

        __le16    support_pam4_speeds;

        #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G      0x1UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G     0x2UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G     0x4UL

        __le16    force_pam4_link_speed;

        #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL

        #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL

        #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL

        #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB

        __le16    auto_pam4_link_speed_mask;

        #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G      0x1UL

        #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G     0x2UL

        #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G     0x4UL

        u8    link_partner_pam4_adv_speeds;

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB      0x1UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB     0x2UL

        #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB     0x4UL

        u8    link_down_reason;

        #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF     0x1UL

        __le16    support_speeds2;

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB                0x1UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB               0x2UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB               0x4UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB               0x8UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB               0x10UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB              0x20UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56       0x40UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56      0x80UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56      0x100UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56      0x200UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112     0x400UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112     0x800UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112     0x1000UL

        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112     0x2000UL

        __le16    force_link_speeds2;

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB            0xaUL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB           0x64UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB           0xfaUL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB           0x190UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB           0x1f4UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB          0x3e8UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56   0x1f5UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56  0x3e9UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56  0x7d1UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56  0xfa1UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL

        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112

        __le16    auto_link_speeds2;

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB                0x1UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB               0x2UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB               0x4UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB               0x8UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB               0x10UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB              0x20UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56       0x40UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56      0x80UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56      0x100UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56      0x200UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112     0x400UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112     0x800UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112     0x1000UL

        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112     0x2000UL

        u8    active_lanes;

        u8    valid;

};


/* hwrm_port_mac_cfg_input (size:320b/40B) */


struct hwrm_port_mac_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK                    0x1UL

        #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE           0x2UL

        #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE         0x4UL

        #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE            0x8UL

        #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE      0x10UL

        #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE     0x20UL

        #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE      0x40UL

        #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE     0x80UL

        #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE                0x100UL

        #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE               0x200UL

        #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE          0x400UL

        #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE        0x800UL

        #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE           0x1000UL

        __le32    enables;

        #define PORT_MAC_CFG_REQ_ENABLES_IPG                            0x1UL

        #define PORT_MAC_CFG_REQ_ENABLES_LPBK                           0x2UL

        #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI           0x4UL

        #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI         0x10UL

        #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI               0x20UL

        #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE     0x40UL

        #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE     0x80UL

        #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG                  0x100UL

        __le16    port_id;

        u8    ipg;

        u8    lpbk;

        #define PORT_MAC_CFG_REQ_LPBK_NONE   0x0UL

        #define PORT_MAC_CFG_REQ_LPBK_LOCAL  0x1UL

        #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL

        #define PORT_MAC_CFG_REQ_LPBK_LAST  PORT_MAC_CFG_REQ_LPBK_REMOTE

        u8    vlan_pri2cos_map_pri;

        u8    reserved1;

        u8    tunnel_pri2cos_map_pri;

        u8    dscp2pri_map_pri;

        __le16    rx_ts_capture_ptp_msg_type;

        __le16    tx_ts_capture_ptp_msg_type;

        u8    cos_field_cfg;

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1                     0x1UL

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK         0x6UL

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT          1

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST      (0x0UL << 1)

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER          (0x1UL << 1)

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST      (0x2UL << 1)

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED    (0x3UL << 1)

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST          PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK       0x18UL

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT        3

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST    (0x0UL << 3)

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER        (0x1UL << 3)

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST    (0x2UL << 3)

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (0x3UL << 3)

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST        PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK          0xe0UL

        #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT           5

        u8    unused_0[3];

};


/* hwrm_port_mac_cfg_output (size:128b/16B) */


struct hwrm_port_mac_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    mru;

        __le16    mtu;

        u8    ipg;

        u8    lpbk;

        #define PORT_MAC_CFG_RESP_LPBK_NONE   0x0UL

        #define PORT_MAC_CFG_RESP_LPBK_LOCAL  0x1UL

        #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL

        #define PORT_MAC_CFG_RESP_LPBK_LAST  PORT_MAC_CFG_RESP_LPBK_REMOTE

        u8    unused_0;

        u8    valid;

};


/* hwrm_port_mac_qcfg_input (size:192b/24B) */


struct hwrm_port_mac_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

};


/* hwrm_port_mac_qcfg_output (size:192b/24B) */


struct hwrm_port_mac_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    mru;

        __le16    mtu;

        u8    ipg;

        u8    lpbk;

        #define PORT_MAC_QCFG_RESP_LPBK_NONE   0x0UL

        #define PORT_MAC_QCFG_RESP_LPBK_LOCAL  0x1UL

        #define PORT_MAC_QCFG_RESP_LPBK_REMOTE 0x2UL

        #define PORT_MAC_QCFG_RESP_LPBK_LAST  PORT_MAC_QCFG_RESP_LPBK_REMOTE

        u8    vlan_pri2cos_map_pri;

        u8    flags;

        #define PORT_MAC_QCFG_RESP_FLAGS_VLAN_PRI2COS_ENABLE          0x1UL

        #define PORT_MAC_QCFG_RESP_FLAGS_TUNNEL_PRI2COS_ENABLE        0x2UL

        #define PORT_MAC_QCFG_RESP_FLAGS_IP_DSCP2COS_ENABLE           0x4UL

        #define PORT_MAC_QCFG_RESP_FLAGS_OOB_WOL_ENABLE               0x8UL

        #define PORT_MAC_QCFG_RESP_FLAGS_PTP_RX_TS_CAPTURE_ENABLE     0x10UL

        #define PORT_MAC_QCFG_RESP_FLAGS_PTP_TX_TS_CAPTURE_ENABLE     0x20UL

        u8    tunnel_pri2cos_map_pri;

        u8    dscp2pri_map_pri;

        __le16    rx_ts_capture_ptp_msg_type;

        __le16    tx_ts_capture_ptp_msg_type;

        u8    cos_field_cfg;

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_RSVD                      0x1UL

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_MASK         0x6UL

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_SFT          1

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST      (0x0UL << 1)

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER          (0x1UL << 1)

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST      (0x2UL << 1)

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED    (0x3UL << 1)

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_LAST          PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK       0x18UL

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT        3

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST    (0x0UL << 3)

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER        (0x1UL << 3)

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST    (0x2UL << 3)

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (0x3UL << 3)

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST        PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_MASK          0xe0UL

        #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_SFT           5

        u8    valid;

};


/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */


struct hwrm_port_mac_ptp_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

};


/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */


struct hwrm_port_mac_ptp_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    flags;

        #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS     0x1UL

        #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS       0x2UL

        u8    unused_0[3];

        __le32    rx_ts_reg_off_lower;

        __le32    rx_ts_reg_off_upper;

        __le32    rx_ts_reg_off_seq_id;

        __le32    rx_ts_reg_off_src_id_0;

        __le32    rx_ts_reg_off_src_id_1;

        __le32    rx_ts_reg_off_src_id_2;

        __le32    rx_ts_reg_off_domain_id;

        __le32    rx_ts_reg_off_fifo;

        __le32    rx_ts_reg_off_fifo_adv;

        __le32    rx_ts_reg_off_granularity;

        __le32    tx_ts_reg_off_lower;

        __le32    tx_ts_reg_off_upper;

        __le32    tx_ts_reg_off_seq_id;

        __le32    tx_ts_reg_off_fifo;

        __le32    tx_ts_reg_off_granularity;

        u8    unused_1[7];

        u8    valid;

};


/* tx_port_stats (size:3264b/408B) */


struct tx_port_stats {

        __le64    tx_64b_frames;

        __le64    tx_65b_127b_frames;

        __le64    tx_128b_255b_frames;

        __le64    tx_256b_511b_frames;

        __le64    tx_512b_1023b_frames;

        __le64    tx_1024b_1518b_frames;

        __le64    tx_good_vlan_frames;

        __le64    tx_1519b_2047b_frames;

        __le64    tx_2048b_4095b_frames;

        __le64    tx_4096b_9216b_frames;

        __le64    tx_9217b_16383b_frames;

        __le64    tx_good_frames;

        __le64    tx_total_frames;

        __le64    tx_ucast_frames;

        __le64    tx_mcast_frames;

        __le64    tx_bcast_frames;

        __le64    tx_pause_frames;

        __le64    tx_pfc_frames;

        __le64    tx_jabber_frames;

        __le64    tx_fcs_err_frames;

        __le64    tx_control_frames;

        __le64    tx_oversz_frames;

        __le64    tx_single_dfrl_frames;

        __le64    tx_multi_dfrl_frames;

        __le64    tx_single_coll_frames;

        __le64    tx_multi_coll_frames;

        __le64    tx_late_coll_frames;

        __le64    tx_excessive_coll_frames;

        __le64    tx_frag_frames;

        __le64    tx_err;

        __le64    tx_tagged_frames;

        __le64    tx_dbl_tagged_frames;

        __le64    tx_runt_frames;

        __le64    tx_fifo_underruns;

        __le64    tx_pfc_ena_frames_pri0;

        __le64    tx_pfc_ena_frames_pri1;

        __le64    tx_pfc_ena_frames_pri2;

        __le64    tx_pfc_ena_frames_pri3;

        __le64    tx_pfc_ena_frames_pri4;

        __le64    tx_pfc_ena_frames_pri5;

        __le64    tx_pfc_ena_frames_pri6;

        __le64    tx_pfc_ena_frames_pri7;

        __le64    tx_eee_lpi_events;

        __le64    tx_eee_lpi_duration;

        __le64    tx_llfc_logical_msgs;

        __le64    tx_hcfc_msgs;

        __le64    tx_total_collisions;

        __le64    tx_bytes;

        __le64    tx_xthol_frames;

        __le64    tx_stat_discard;

        __le64    tx_stat_error;

};


/* rx_port_stats (size:4224b/528B) */


struct rx_port_stats {

        __le64    rx_64b_frames;

        __le64    rx_65b_127b_frames;

        __le64    rx_128b_255b_frames;

        __le64    rx_256b_511b_frames;

        __le64    rx_512b_1023b_frames;

        __le64    rx_1024b_1518b_frames;

        __le64    rx_good_vlan_frames;

        __le64    rx_1519b_2047b_frames;

        __le64    rx_2048b_4095b_frames;

        __le64    rx_4096b_9216b_frames;

        __le64    rx_9217b_16383b_frames;

        __le64    rx_total_frames;

        __le64    rx_ucast_frames;

        __le64    rx_mcast_frames;

        __le64    rx_bcast_frames;

        __le64    rx_fcs_err_frames;

        __le64    rx_ctrl_frames;

        __le64    rx_pause_frames;

        __le64    rx_pfc_frames;

        __le64    rx_unsupported_opcode_frames;

        __le64    rx_unsupported_da_pausepfc_frames;

        __le64    rx_wrong_sa_frames;

        __le64    rx_align_err_frames;

        __le64    rx_oor_len_frames;

        __le64    rx_code_err_frames;

        __le64    rx_false_carrier_frames;

        __le64    rx_ovrsz_frames;

        __le64    rx_jbr_frames;

        __le64    rx_mtu_err_frames;

        __le64    rx_match_crc_frames;

        __le64    rx_promiscuous_frames;

        __le64    rx_tagged_frames;

        __le64    rx_double_tagged_frames;

        __le64    rx_trunc_frames;

        __le64    rx_good_frames;

        __le64    rx_pfc_xon2xoff_frames_pri0;

        __le64    rx_pfc_xon2xoff_frames_pri1;

        __le64    rx_pfc_xon2xoff_frames_pri2;

        __le64    rx_pfc_xon2xoff_frames_pri3;

        __le64    rx_pfc_xon2xoff_frames_pri4;

        __le64    rx_pfc_xon2xoff_frames_pri5;

        __le64    rx_pfc_xon2xoff_frames_pri6;

        __le64    rx_pfc_xon2xoff_frames_pri7;

        __le64    rx_pfc_ena_frames_pri0;

        __le64    rx_pfc_ena_frames_pri1;

        __le64    rx_pfc_ena_frames_pri2;

        __le64    rx_pfc_ena_frames_pri3;

        __le64    rx_pfc_ena_frames_pri4;

        __le64    rx_pfc_ena_frames_pri5;

        __le64    rx_pfc_ena_frames_pri6;

        __le64    rx_pfc_ena_frames_pri7;

        __le64    rx_sch_crc_err_frames;

        __le64    rx_undrsz_frames;

        __le64    rx_frag_frames;

        __le64    rx_eee_lpi_events;

        __le64    rx_eee_lpi_duration;

        __le64    rx_llfc_physical_msgs;

        __le64    rx_llfc_logical_msgs;

        __le64    rx_llfc_msgs_with_crc_err;

        __le64    rx_hcfc_msgs;

        __le64    rx_hcfc_msgs_with_crc_err;

        __le64    rx_bytes;

        __le64    rx_runt_bytes;

        __le64    rx_runt_frames;

        __le64    rx_stat_discard;

        __le64    rx_stat_err;

};


/* hwrm_port_qstats_input (size:320b/40B) */


struct hwrm_port_qstats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

        __le64    tx_stat_host_addr;

        __le64    rx_stat_host_addr;

};


/* hwrm_port_qstats_output (size:128b/16B) */


struct hwrm_port_qstats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    tx_stat_size;

        __le16    rx_stat_size;

        u8    unused_0[3];

        u8    valid;

};


/* tx_port_stats_ext (size:2048b/256B) */


struct tx_port_stats_ext {

        __le64    tx_bytes_cos0;

        __le64    tx_bytes_cos1;

        __le64    tx_bytes_cos2;

        __le64    tx_bytes_cos3;

        __le64    tx_bytes_cos4;

        __le64    tx_bytes_cos5;

        __le64    tx_bytes_cos6;

        __le64    tx_bytes_cos7;

        __le64    tx_packets_cos0;

        __le64    tx_packets_cos1;

        __le64    tx_packets_cos2;

        __le64    tx_packets_cos3;

        __le64    tx_packets_cos4;

        __le64    tx_packets_cos5;

        __le64    tx_packets_cos6;

        __le64    tx_packets_cos7;

        __le64    pfc_pri0_tx_duration_us;

        __le64    pfc_pri0_tx_transitions;

        __le64    pfc_pri1_tx_duration_us;

        __le64    pfc_pri1_tx_transitions;

        __le64    pfc_pri2_tx_duration_us;

        __le64    pfc_pri2_tx_transitions;

        __le64    pfc_pri3_tx_duration_us;

        __le64    pfc_pri3_tx_transitions;

        __le64    pfc_pri4_tx_duration_us;

        __le64    pfc_pri4_tx_transitions;

        __le64    pfc_pri5_tx_duration_us;

        __le64    pfc_pri5_tx_transitions;

        __le64    pfc_pri6_tx_duration_us;

        __le64    pfc_pri6_tx_transitions;

        __le64    pfc_pri7_tx_duration_us;

        __le64    pfc_pri7_tx_transitions;

};


/* rx_port_stats_ext (size:2368b/296B) */


struct rx_port_stats_ext {

        __le64    link_down_events;

        __le64    continuous_pause_events;

        __le64    resume_pause_events;

        __le64    continuous_roce_pause_events;

        __le64    resume_roce_pause_events;

        __le64    rx_bytes_cos0;

        __le64    rx_bytes_cos1;

        __le64    rx_bytes_cos2;

        __le64    rx_bytes_cos3;

        __le64    rx_bytes_cos4;

        __le64    rx_bytes_cos5;

        __le64    rx_bytes_cos6;

        __le64    rx_bytes_cos7;

        __le64    rx_packets_cos0;

        __le64    rx_packets_cos1;

        __le64    rx_packets_cos2;

        __le64    rx_packets_cos3;

        __le64    rx_packets_cos4;

        __le64    rx_packets_cos5;

        __le64    rx_packets_cos6;

        __le64    rx_packets_cos7;

        __le64    pfc_pri0_rx_duration_us;

        __le64    pfc_pri0_rx_transitions;

        __le64    pfc_pri1_rx_duration_us;

        __le64    pfc_pri1_rx_transitions;

        __le64    pfc_pri2_rx_duration_us;

        __le64    pfc_pri2_rx_transitions;

        __le64    pfc_pri3_rx_duration_us;

        __le64    pfc_pri3_rx_transitions;

        __le64    pfc_pri4_rx_duration_us;

        __le64    pfc_pri4_rx_transitions;

        __le64    pfc_pri5_rx_duration_us;

        __le64    pfc_pri5_rx_transitions;

        __le64    pfc_pri6_rx_duration_us;

        __le64    pfc_pri6_rx_transitions;

        __le64    pfc_pri7_rx_duration_us;

        __le64    pfc_pri7_rx_transitions;

};


/* hwrm_port_qstats_ext_input (size:320b/40B) */


struct hwrm_port_qstats_ext_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        __le16    tx_stat_size;

        __le16    rx_stat_size;

        u8    unused_0[2];

        __le64    tx_stat_host_addr;

        __le64    rx_stat_host_addr;

};


/* hwrm_port_qstats_ext_output (size:128b/16B) */


struct hwrm_port_qstats_ext_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    tx_stat_size;

        __le16    rx_stat_size;

        __le16    total_active_cos_queues;

        u8    flags;

        #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED     0x1UL

        u8    valid;

};


/* hwrm_port_lpbk_qstats_input (size:128b/16B) */


struct hwrm_port_lpbk_qstats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_port_lpbk_qstats_output (size:768b/96B) */


struct hwrm_port_lpbk_qstats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    lpbk_ucast_frames;

        __le64    lpbk_mcast_frames;

        __le64    lpbk_bcast_frames;

        __le64    lpbk_ucast_bytes;

        __le64    lpbk_mcast_bytes;

        __le64    lpbk_bcast_bytes;

        __le64    tx_stat_discard;

        __le64    tx_stat_error;

        __le64    rx_stat_discard;

        __le64    rx_stat_error;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_port_clr_stats_input (size:192b/24B) */


struct hwrm_port_clr_stats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    flags;

        #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS     0x1UL

        u8    unused_0[5];

};


/* hwrm_port_clr_stats_output (size:128b/16B) */


struct hwrm_port_clr_stats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */


struct hwrm_port_lpbk_clr_stats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */


struct hwrm_port_lpbk_clr_stats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_port_ts_query_input (size:192b/24B) */


struct hwrm_port_ts_query_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define PORT_TS_QUERY_REQ_FLAGS_PATH     0x1UL

        #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX    0x0UL

        #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX    0x1UL

        #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX

        __le16    port_id;

        u8    unused_0[2];

};


/* hwrm_port_ts_query_output (size:192b/24B) */


struct hwrm_port_ts_query_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    ptp_msg_ts;

        __le16    ptp_msg_seqid;

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_port_phy_qcaps_input (size:192b/24B) */


struct hwrm_port_phy_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

};


/* hwrm_port_phy_qcaps_output (size:320b/40B) */


struct hwrm_port_phy_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    flags;

        #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED               0x1UL

        #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED     0x2UL

        #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK                  0xfcUL

        #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT                   2

        u8    port_cnt;

        #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL

        #define PORT_PHY_QCAPS_RESP_PORT_CNT_1       0x1UL

        #define PORT_PHY_QCAPS_RESP_PORT_CNT_2       0x2UL

        #define PORT_PHY_QCAPS_RESP_PORT_CNT_3       0x3UL

        #define PORT_PHY_QCAPS_RESP_PORT_CNT_4       0x4UL

        #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST   PORT_PHY_QCAPS_RESP_PORT_CNT_4

        __le16    supported_speeds_force_mode;

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD     0x1UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB       0x2UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD       0x4UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB         0x8UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB         0x10UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB       0x20UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB        0x40UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB        0x80UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB        0x100UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB        0x200UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB        0x400UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB       0x800UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD      0x1000UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB        0x2000UL

        __le16    supported_speeds_auto_mode;

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD     0x1UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB       0x2UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD       0x4UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB         0x8UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB         0x10UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB       0x20UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB        0x40UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB        0x80UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB        0x100UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB        0x200UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB        0x400UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB       0x800UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD      0x1000UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB        0x2000UL

        __le16    supported_speeds_eee_mode;

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1     0x1UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB     0x2UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2     0x4UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB       0x8UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3     0x10UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4     0x20UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB      0x40UL

        __le32    tx_lpi_timer_low;

        #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL

        #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0

        #define PORT_PHY_QCAPS_RESP_RSVD2_MASK           0xff000000UL

        #define PORT_PHY_QCAPS_RESP_RSVD2_SFT            24

        __le32    valid_tx_lpi_timer_high;

        #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL

        #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0

        #define PORT_PHY_QCAPS_RESP_VALID_MASK            0xff000000UL

        #define PORT_PHY_QCAPS_RESP_VALID_SFT             24

        __le16    supported_pam4_speeds_auto_mode;

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G      0x1UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G     0x2UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G     0x4UL

        __le16    supported_pam4_speeds_force_mode;

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G      0x1UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G     0x2UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G     0x4UL

        __le16    flags2;

        #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED       0x1UL

        #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED         0x2UL

        #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED     0x4UL

        #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED       0x8UL

        u8    internal_port_cnt;

        u8    unused_0;

        __le16    supported_speeds2_force_mode;

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB                0x1UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB               0x2UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB               0x4UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB               0x8UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB               0x10UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB              0x20UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56       0x40UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56      0x80UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56      0x100UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56      0x200UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112     0x400UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112     0x800UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112     0x1000UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112     0x2000UL

        __le16    supported_speeds2_auto_mode;

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB                0x1UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB               0x2UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB               0x4UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB               0x8UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB               0x10UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB              0x20UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56       0x40UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56      0x80UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56      0x100UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56      0x200UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112     0x400UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112     0x800UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112     0x1000UL

        #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112     0x2000UL

        u8    unused_1[3];

        u8    valid;

};


/* hwrm_port_phy_i2c_write_input (size:832b/104B) */


struct hwrm_port_phy_i2c_write_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        __le32    enables;

        #define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET     0x1UL

        __le16    port_id;

        u8    i2c_slave_addr;

        u8    unused_0;

        __le16    page_number;

        __le16    page_offset;

        u8    data_length;

        u8    unused_1[7];

        __le32    data[16];

};


/* hwrm_port_phy_i2c_write_output (size:128b/16B) */


struct hwrm_port_phy_i2c_write_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_port_phy_i2c_read_input (size:320b/40B) */


struct hwrm_port_phy_i2c_read_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        __le32    enables;

        #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET     0x1UL

        __le16    port_id;

        u8    i2c_slave_addr;

        u8    unused_0;

        __le16    page_number;

        __le16    page_offset;

        u8    data_length;

        u8    unused_1[7];

};


/* hwrm_port_phy_i2c_read_output (size:640b/80B) */


struct hwrm_port_phy_i2c_read_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    data[16];

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_port_led_cfg_input (size:512b/64B) */


struct hwrm_port_led_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define PORT_LED_CFG_REQ_ENABLES_LED0_ID            0x1UL

        #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE         0x2UL

        #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR         0x4UL

        #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON      0x8UL

        #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF     0x10UL

        #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID      0x20UL

        #define PORT_LED_CFG_REQ_ENABLES_LED1_ID            0x40UL

        #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE         0x80UL

        #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR         0x100UL

        #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON      0x200UL

        #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF     0x400UL

        #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID      0x800UL

        #define PORT_LED_CFG_REQ_ENABLES_LED2_ID            0x1000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE         0x2000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR         0x4000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON      0x8000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF     0x10000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID      0x20000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED3_ID            0x40000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE         0x80000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR         0x100000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON      0x200000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF     0x400000UL

        #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID      0x800000UL

        __le16    port_id;

        u8    num_leds;

        u8    rsvd;

        u8    led0_id;

        u8    led0_state;

        #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT  0x0UL

        #define PORT_LED_CFG_REQ_LED0_STATE_OFF      0x1UL

        #define PORT_LED_CFG_REQ_LED0_STATE_ON       0x2UL

        #define PORT_LED_CFG_REQ_LED0_STATE_BLINK    0x3UL

        #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL

        #define PORT_LED_CFG_REQ_LED0_STATE_LAST    PORT_LED_CFG_REQ_LED0_STATE_BLINKALT

        u8    led0_color;

        #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT    0x0UL

        #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER      0x1UL

        #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN      0x2UL

        #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL

        #define PORT_LED_CFG_REQ_LED0_COLOR_LAST      PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER

        u8    unused_0;

        __le16    led0_blink_on;

        __le16    led0_blink_off;

        u8    led0_group_id;

        u8    rsvd0;

        u8    led1_id;

        u8    led1_state;

        #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT  0x0UL

        #define PORT_LED_CFG_REQ_LED1_STATE_OFF      0x1UL

        #define PORT_LED_CFG_REQ_LED1_STATE_ON       0x2UL

        #define PORT_LED_CFG_REQ_LED1_STATE_BLINK    0x3UL

        #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL

        #define PORT_LED_CFG_REQ_LED1_STATE_LAST    PORT_LED_CFG_REQ_LED1_STATE_BLINKALT

        u8    led1_color;

        #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT    0x0UL

        #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER      0x1UL

        #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN      0x2UL

        #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL

        #define PORT_LED_CFG_REQ_LED1_COLOR_LAST      PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER

        u8    unused_1;

        __le16    led1_blink_on;

        __le16    led1_blink_off;

        u8    led1_group_id;

        u8    rsvd1;

        u8    led2_id;

        u8    led2_state;

        #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT  0x0UL

        #define PORT_LED_CFG_REQ_LED2_STATE_OFF      0x1UL

        #define PORT_LED_CFG_REQ_LED2_STATE_ON       0x2UL

        #define PORT_LED_CFG_REQ_LED2_STATE_BLINK    0x3UL

        #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL

        #define PORT_LED_CFG_REQ_LED2_STATE_LAST    PORT_LED_CFG_REQ_LED2_STATE_BLINKALT

        u8    led2_color;

        #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT    0x0UL

        #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER      0x1UL

        #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN      0x2UL

        #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL

        #define PORT_LED_CFG_REQ_LED2_COLOR_LAST      PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER

        u8    unused_2;

        __le16    led2_blink_on;

        __le16    led2_blink_off;

        u8    led2_group_id;

        u8    rsvd2;

        u8    led3_id;

        u8    led3_state;

        #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT  0x0UL

        #define PORT_LED_CFG_REQ_LED3_STATE_OFF      0x1UL

        #define PORT_LED_CFG_REQ_LED3_STATE_ON       0x2UL

        #define PORT_LED_CFG_REQ_LED3_STATE_BLINK    0x3UL

        #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL

        #define PORT_LED_CFG_REQ_LED3_STATE_LAST    PORT_LED_CFG_REQ_LED3_STATE_BLINKALT

        u8    led3_color;

        #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT    0x0UL

        #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER      0x1UL

        #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN      0x2UL

        #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL

        #define PORT_LED_CFG_REQ_LED3_COLOR_LAST      PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER

        u8    unused_3;

        __le16    led3_blink_on;

        __le16    led3_blink_off;

        u8    led3_group_id;

        u8    rsvd3;

};


/* hwrm_port_led_cfg_output (size:128b/16B) */


struct hwrm_port_led_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_port_led_qcfg_input (size:192b/24B) */


struct hwrm_port_led_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

};


/* hwrm_port_led_qcfg_output (size:448b/56B) */


struct hwrm_port_led_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    num_leds;

        u8    led0_id;

        u8    led0_type;

        #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED    0x0UL

        #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL

        #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID  0xffUL

        #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST    PORT_LED_QCFG_RESP_LED0_TYPE_INVALID

        u8    led0_state;

        #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT  0x0UL

        #define PORT_LED_QCFG_RESP_LED0_STATE_OFF      0x1UL

        #define PORT_LED_QCFG_RESP_LED0_STATE_ON       0x2UL

        #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK    0x3UL

        #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL

        #define PORT_LED_QCFG_RESP_LED0_STATE_LAST    PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT

        u8    led0_color;

        #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT    0x0UL

        #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER      0x1UL

        #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN      0x2UL

        #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL

        #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST      PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER

        u8    unused_0;

        __le16    led0_blink_on;

        __le16    led0_blink_off;

        u8    led0_group_id;

        u8    led1_id;

        u8    led1_type;

        #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED    0x0UL

        #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL

        #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID  0xffUL

        #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST    PORT_LED_QCFG_RESP_LED1_TYPE_INVALID

        u8    led1_state;

        #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT  0x0UL

        #define PORT_LED_QCFG_RESP_LED1_STATE_OFF      0x1UL

        #define PORT_LED_QCFG_RESP_LED1_STATE_ON       0x2UL

        #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK    0x3UL

        #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL

        #define PORT_LED_QCFG_RESP_LED1_STATE_LAST    PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT

        u8    led1_color;

        #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT    0x0UL

        #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER      0x1UL

        #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN      0x2UL

        #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL

        #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST      PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER

        u8    unused_1;

        __le16    led1_blink_on;

        __le16    led1_blink_off;

        u8    led1_group_id;

        u8    led2_id;

        u8    led2_type;

        #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED    0x0UL

        #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL

        #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID  0xffUL

        #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST    PORT_LED_QCFG_RESP_LED2_TYPE_INVALID

        u8    led2_state;

        #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT  0x0UL

        #define PORT_LED_QCFG_RESP_LED2_STATE_OFF      0x1UL

        #define PORT_LED_QCFG_RESP_LED2_STATE_ON       0x2UL

        #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK    0x3UL

        #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL

        #define PORT_LED_QCFG_RESP_LED2_STATE_LAST    PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT

        u8    led2_color;

        #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT    0x0UL

        #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER      0x1UL

        #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN      0x2UL

        #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL

        #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST      PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER

        u8    unused_2;

        __le16    led2_blink_on;

        __le16    led2_blink_off;

        u8    led2_group_id;

        u8    led3_id;

        u8    led3_type;

        #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED    0x0UL

        #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL

        #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID  0xffUL

        #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST    PORT_LED_QCFG_RESP_LED3_TYPE_INVALID

        u8    led3_state;

        #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT  0x0UL

        #define PORT_LED_QCFG_RESP_LED3_STATE_OFF      0x1UL

        #define PORT_LED_QCFG_RESP_LED3_STATE_ON       0x2UL

        #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK    0x3UL

        #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL

        #define PORT_LED_QCFG_RESP_LED3_STATE_LAST    PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT

        u8    led3_color;

        #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT    0x0UL

        #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER      0x1UL

        #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN      0x2UL

        #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL

        #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST      PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER

        u8    unused_3;

        __le16    led3_blink_on;

        __le16    led3_blink_off;

        u8    led3_group_id;

        u8    unused_4[6];

        u8    valid;

};


/* hwrm_port_led_qcaps_input (size:192b/24B) */


struct hwrm_port_led_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

};


/* hwrm_port_led_qcaps_output (size:384b/48B) */


struct hwrm_port_led_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    num_leds;

        u8    unused[3];

        u8    led0_id;

        u8    led0_type;

        #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED    0x0UL

        #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL

        #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID  0xffUL

        #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST    PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID

        u8    led0_group_id;

        u8    unused_0;

        __le16    led0_state_caps;

        #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED                 0x1UL

        #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED           0x2UL

        #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED            0x4UL

        #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED         0x8UL

        #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL

        __le16    led0_color_caps;

        #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD                0x1UL

        #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED     0x2UL

        #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED     0x4UL

        u8    led1_id;

        u8    led1_type;

        #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED    0x0UL

        #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL

        #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID  0xffUL

        #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST    PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID

        u8    led1_group_id;

        u8    unused_1;

        __le16    led1_state_caps;

        #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED                 0x1UL

        #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED           0x2UL

        #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED            0x4UL

        #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED         0x8UL

        #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL

        __le16    led1_color_caps;

        #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD                0x1UL

        #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED     0x2UL

        #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED     0x4UL

        u8    led2_id;

        u8    led2_type;

        #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED    0x0UL

        #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL

        #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID  0xffUL

        #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST    PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID

        u8    led2_group_id;

        u8    unused_2;

        __le16    led2_state_caps;

        #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED                 0x1UL

        #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED           0x2UL

        #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED            0x4UL

        #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED         0x8UL

        #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL

        __le16    led2_color_caps;

        #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD                0x1UL

        #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED     0x2UL

        #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED     0x4UL

        u8    led3_id;

        u8    led3_type;

        #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED    0x0UL

        #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL

        #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID  0xffUL

        #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST    PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID

        u8    led3_group_id;

        u8    unused_3;

        __le16    led3_state_caps;

        #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED                 0x1UL

        #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED           0x2UL

        #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED            0x4UL

        #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED         0x8UL

        #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL

        __le16    led3_color_caps;

        #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD                0x1UL

        #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED     0x2UL

        #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED     0x4UL

        u8    unused_4[3];

        u8    valid;

};


/* hwrm_queue_qportcfg_input (size:192b/24B) */


struct hwrm_queue_qportcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define QUEUE_QPORTCFG_REQ_FLAGS_PATH     0x1UL

        #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX    0x0UL

        #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX    0x1UL

        #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX

        __le16    port_id;

        u8    drv_qmap_cap;

        #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL

        #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED  0x1UL

        #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST    QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED

        u8    unused_0;

};


/* hwrm_queue_qportcfg_output (size:256b/32B) */


struct hwrm_queue_qportcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    max_configurable_queues;

        u8    max_configurable_lossless_queues;

        u8    queue_cfg_allowed;

        u8    queue_cfg_info;

        #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL

        u8    queue_pfcenable_cfg_allowed;

        u8    queue_pri2cos_cfg_allowed;

        u8    queue_cos2bw_cfg_allowed;

        u8    queue_id0;

        u8    queue_id0_service_profile;

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY          0x0UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS       0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN        0xffUL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN

        u8    queue_id1;

        u8    queue_id1_service_profile;

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY          0x0UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS       0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN        0xffUL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN

        u8    queue_id2;

        u8    queue_id2_service_profile;

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY          0x0UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS       0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN        0xffUL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN

        u8    queue_id3;

        u8    queue_id3_service_profile;

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY          0x0UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS       0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN        0xffUL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN

        u8    queue_id4;

        u8    queue_id4_service_profile;

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY          0x0UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS       0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN        0xffUL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN

        u8    queue_id5;

        u8    queue_id5_service_profile;

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY          0x0UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS       0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN        0xffUL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN

        u8    queue_id6;

        u8    queue_id6_service_profile;

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY          0x0UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS       0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN        0xffUL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN

        u8    queue_id7;

        u8    queue_id7_service_profile;

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY          0x0UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS       0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN        0xffUL

        #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN

        u8    valid;

};


/* hwrm_queue_qcfg_input (size:192b/24B) */


struct hwrm_queue_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define QUEUE_QCFG_REQ_FLAGS_PATH     0x1UL

        #define QUEUE_QCFG_REQ_FLAGS_PATH_TX    0x0UL

        #define QUEUE_QCFG_REQ_FLAGS_PATH_RX    0x1UL

        #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX

        __le32    queue_id;

};


/* hwrm_queue_qcfg_output (size:128b/16B) */


struct hwrm_queue_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    queue_len;

        u8    service_profile;

        #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY    0x0UL

        #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL

        #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN  0xffUL

        #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST    QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN

        u8    queue_cfg_info;

        #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL

        u8    unused_0;

        u8    valid;

};


/* hwrm_queue_cfg_input (size:320b/40B) */


struct hwrm_queue_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL

        #define QUEUE_CFG_REQ_FLAGS_PATH_SFT  0

        #define QUEUE_CFG_REQ_FLAGS_PATH_TX     0x0UL

        #define QUEUE_CFG_REQ_FLAGS_PATH_RX     0x1UL

        #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL

        #define QUEUE_CFG_REQ_FLAGS_PATH_LAST  QUEUE_CFG_REQ_FLAGS_PATH_BIDIR

        __le32    enables;

        #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN            0x1UL

        #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE     0x2UL

        __le32    queue_id;

        __le32    dflt_len;

        u8    service_profile;

        #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY    0x0UL

        #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL

        #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN  0xffUL

        #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST    QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN

        u8    unused_0[7];

};


/* hwrm_queue_cfg_output (size:128b/16B) */


struct hwrm_queue_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */


struct hwrm_queue_pfcenable_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

};


/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */


struct hwrm_queue_pfcenable_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    flags;

        #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED     0x1UL

        #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED     0x2UL

        #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED     0x4UL

        #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED     0x8UL

        #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED     0x10UL

        #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED     0x20UL

        #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED     0x40UL

        #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED     0x80UL

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */


struct hwrm_queue_pfcenable_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED     0x1UL

        #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED     0x2UL

        #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED     0x4UL

        #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED     0x8UL

        #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED     0x10UL

        #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED     0x20UL

        #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED     0x40UL

        #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED     0x80UL

        __le16    port_id;

        u8    unused_0[2];

};


/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */


struct hwrm_queue_pfcenable_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */


struct hwrm_queue_pri2cos_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH      0x1UL

        #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX     0x0UL

        #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX     0x1UL

        #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX

        #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN     0x2UL

        u8    port_id;

        u8    unused_0[3];

};


/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */


struct hwrm_queue_pri2cos_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    pri0_cos_queue_id;

        u8    pri1_cos_queue_id;

        u8    pri2_cos_queue_id;

        u8    pri3_cos_queue_id;

        u8    pri4_cos_queue_id;

        u8    pri5_cos_queue_id;

        u8    pri6_cos_queue_id;

        u8    pri7_cos_queue_id;

        u8    queue_cfg_info;

        #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL

        u8    unused_0[6];

        u8    valid;

};


/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */


struct hwrm_queue_pri2cos_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL

        #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT  0

        #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX     0x0UL

        #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX     0x1UL

        #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL

        #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR

        #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN     0x4UL

        __le32    enables;

        #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID     0x1UL

        #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID     0x2UL

        #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID     0x4UL

        #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID     0x8UL

        #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID     0x10UL

        #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID     0x20UL

        #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID     0x40UL

        #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID     0x80UL

        u8    port_id;

        u8    pri0_cos_queue_id;

        u8    pri1_cos_queue_id;

        u8    pri2_cos_queue_id;

        u8    pri3_cos_queue_id;

        u8    pri4_cos_queue_id;

        u8    pri5_cos_queue_id;

        u8    pri6_cos_queue_id;

        u8    pri7_cos_queue_id;

        u8    unused_0[7];

};


/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */


struct hwrm_queue_pri2cos_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */


struct hwrm_queue_cos2bw_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

};


/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */


struct hwrm_queue_cos2bw_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    queue_id0;

        u8    unused_0;

        __le16    unused_1;

        __le32    queue_id0_min_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id0_max_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id0_tsa_assign;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id0_pri_lvl;

        u8    queue_id0_bw_weight;

        u8    queue_id1;

        __le32    queue_id1_min_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id1_max_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id1_tsa_assign;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id1_pri_lvl;

        u8    queue_id1_bw_weight;

        u8    queue_id2;

        __le32    queue_id2_min_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id2_max_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id2_tsa_assign;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id2_pri_lvl;

        u8    queue_id2_bw_weight;

        u8    queue_id3;

        __le32    queue_id3_min_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id3_max_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id3_tsa_assign;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id3_pri_lvl;

        u8    queue_id3_bw_weight;

        u8    queue_id4;

        __le32    queue_id4_min_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id4_max_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id4_tsa_assign;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id4_pri_lvl;

        u8    queue_id4_bw_weight;

        u8    queue_id5;

        __le32    queue_id5_min_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id5_max_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id5_tsa_assign;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id5_pri_lvl;

        u8    queue_id5_bw_weight;

        u8    queue_id6;

        __le32    queue_id6_min_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id6_max_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id6_tsa_assign;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id6_pri_lvl;

        u8    queue_id6_bw_weight;

        u8    queue_id7;

        __le32    queue_id7_min_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id7_max_bw;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id7_tsa_assign;

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id7_pri_lvl;

        u8    queue_id7_bw_weight;

        u8    unused_2[4];

        u8    valid;

};


/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */


struct hwrm_queue_cos2bw_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        __le32    enables;

        #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID     0x1UL

        #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID     0x2UL

        #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID     0x4UL

        #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID     0x8UL

        #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID     0x10UL

        #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID     0x20UL

        #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID     0x40UL

        #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID     0x80UL

        __le16    port_id;

        u8    queue_id0;

        u8    unused_0;

        __le32    queue_id0_min_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id0_max_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id0_tsa_assign;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id0_pri_lvl;

        u8    queue_id0_bw_weight;

        u8    queue_id1;

        __le32    queue_id1_min_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id1_max_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id1_tsa_assign;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id1_pri_lvl;

        u8    queue_id1_bw_weight;

        u8    queue_id2;

        __le32    queue_id2_min_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id2_max_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id2_tsa_assign;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id2_pri_lvl;

        u8    queue_id2_bw_weight;

        u8    queue_id3;

        __le32    queue_id3_min_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id3_max_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id3_tsa_assign;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id3_pri_lvl;

        u8    queue_id3_bw_weight;

        u8    queue_id4;

        __le32    queue_id4_min_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id4_max_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id4_tsa_assign;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id4_pri_lvl;

        u8    queue_id4_bw_weight;

        u8    queue_id5;

        __le32    queue_id5_min_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id5_max_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id5_tsa_assign;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id5_pri_lvl;

        u8    queue_id5_bw_weight;

        u8    queue_id6;

        __le32    queue_id6_min_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id6_max_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id6_tsa_assign;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id6_pri_lvl;

        u8    queue_id6_bw_weight;

        u8    queue_id7;

        __le32    queue_id7_min_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID

        __le32    queue_id7_max_bw;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT              0

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE                     0x10000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    queue_id7_tsa_assign;

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP             0x0UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS            0x1UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL

        #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST  0xffUL

        u8    queue_id7_pri_lvl;

        u8    queue_id7_bw_weight;

        u8    unused_1[5];

};


/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */


struct hwrm_queue_cos2bw_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */


struct hwrm_queue_dscp_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    port_id;

        u8    unused_0[7];

};


/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */


struct hwrm_queue_dscp_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    num_dscp_bits;

        u8    unused_0;

        __le16    max_entries;

        u8    unused_1[3];

        u8    valid;

};


/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */


struct hwrm_queue_dscp2pri_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    dest_data_addr;

        u8    port_id;

        u8    unused_0;

        __le16    dest_data_buffer_size;

        u8    unused_1[4];

};


/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */


struct hwrm_queue_dscp2pri_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    entry_cnt;

        u8    default_pri;

        u8    unused_0[4];

        u8    valid;

};


/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */


struct hwrm_queue_dscp2pri_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    src_data_addr;

        __le32    flags;

        #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI     0x1UL

        __le32    enables;

        #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI     0x1UL

        u8    port_id;

        u8    default_pri;

        __le16    entry_cnt;

        u8    unused_0[4];

};


/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */


struct hwrm_queue_dscp2pri_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_vnic_alloc_input (size:192b/24B) */


struct hwrm_vnic_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define VNIC_ALLOC_REQ_FLAGS_DEFAULT     0x1UL

        u8    unused_0[4];

};


/* hwrm_vnic_alloc_output (size:128b/16B) */


struct hwrm_vnic_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    vnic_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_vnic_free_input (size:192b/24B) */


struct hwrm_vnic_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    vnic_id;

        u8    unused_0[4];

};


/* hwrm_vnic_free_output (size:128b/16B) */


struct hwrm_vnic_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_vnic_cfg_input (size:320b/40B) */


struct hwrm_vnic_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define VNIC_CFG_REQ_FLAGS_DEFAULT                              0x1UL

        #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE                      0x2UL

        #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE                        0x4UL

        #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE                  0x8UL

        #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE                  0x10UL

        #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE                     0x20UL

        #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE     0x40UL

        __le32    enables;

        #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP            0x1UL

        #define VNIC_CFG_REQ_ENABLES_RSS_RULE                 0x2UL

        #define VNIC_CFG_REQ_ENABLES_COS_RULE                 0x4UL

        #define VNIC_CFG_REQ_ENABLES_LB_RULE                  0x8UL

        #define VNIC_CFG_REQ_ENABLES_MRU                      0x10UL

        #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID       0x20UL

        #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID     0x40UL

        __le16    vnic_id;

        __le16    dflt_ring_grp;

        __le16    rss_rule;

        __le16    cos_rule;

        __le16    lb_rule;

        __le16    mru;

        __le16    default_rx_ring_id;

        __le16    default_cmpl_ring_id;

};


/* hwrm_vnic_cfg_output (size:128b/16B) */


struct hwrm_vnic_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_vnic_qcfg_input (size:256b/32B) */


struct hwrm_vnic_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define VNIC_QCFG_REQ_ENABLES_VF_ID_VALID     0x1UL

        __le32    vnic_id;

        __le16    vf_id;

        u8    unused_0[6];

};


/* hwrm_vnic_qcfg_output (size:256b/32B) */


struct hwrm_vnic_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    dflt_ring_grp;

        __le16    rss_rule;

        __le16    cos_rule;

        __le16    lb_rule;

        __le16    mru;

        u8    unused_0[2];

        __le32    flags;

        #define VNIC_QCFG_RESP_FLAGS_DEFAULT                              0x1UL

        #define VNIC_QCFG_RESP_FLAGS_VLAN_STRIP_MODE                      0x2UL

        #define VNIC_QCFG_RESP_FLAGS_BD_STALL_MODE                        0x4UL

        #define VNIC_QCFG_RESP_FLAGS_ROCE_DUAL_VNIC_MODE                  0x8UL

        #define VNIC_QCFG_RESP_FLAGS_ROCE_ONLY_VNIC_MODE                  0x10UL

        #define VNIC_QCFG_RESP_FLAGS_RSS_DFLT_CR_MODE                     0x20UL

        #define VNIC_QCFG_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE     0x40UL

        u8    unused_1[7];

        u8    valid;

};


/* hwrm_vnic_qcaps_input (size:192b/24B) */


struct hwrm_vnic_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        u8    unused_0[4];

};


/* hwrm_vnic_qcaps_output (size:192b/24B) */


struct hwrm_vnic_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    mru;

        u8    unused_0[2];

        __le32    flags;

        #define VNIC_QCAPS_RESP_FLAGS_UNUSED                              0x1UL

        #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP                      0x2UL

        #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP                        0x4UL

        #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP                  0x8UL

        #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP                  0x10UL

        #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP                     0x20UL

        #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP     0x40UL

        #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP                   0x80UL

        u8    unused_1[7];

        u8    valid;

};


/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */


struct hwrm_vnic_tpa_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define VNIC_TPA_CFG_REQ_FLAGS_TPA                       0x1UL

        #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA                 0x2UL

        #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE            0x4UL

        #define VNIC_TPA_CFG_REQ_FLAGS_GRO                       0x8UL

        #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN              0x10UL

        #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL

        #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK            0x40UL

        #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK             0x80UL

        __le32    enables;

        #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS      0x1UL

        #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS          0x2UL

        #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER     0x4UL

        #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN       0x8UL

        __le16    vnic_id;

        __le16    max_agg_segs;

        #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1   0x0UL

        #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2   0x1UL

        #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4   0x2UL

        #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8   0x3UL

        #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL

        #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX

        __le16    max_aggs;

        #define VNIC_TPA_CFG_REQ_MAX_AGGS_1   0x0UL

        #define VNIC_TPA_CFG_REQ_MAX_AGGS_2   0x1UL

        #define VNIC_TPA_CFG_REQ_MAX_AGGS_4   0x2UL

        #define VNIC_TPA_CFG_REQ_MAX_AGGS_8   0x3UL

        #define VNIC_TPA_CFG_REQ_MAX_AGGS_16  0x4UL

        #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL

        #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX

        u8    unused_0[2];

        __le32    max_agg_timer;

        __le32    min_agg_len;

};


/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */


struct hwrm_vnic_tpa_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */


struct hwrm_vnic_tpa_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    vnic_id;

        u8    unused_0[6];

};


/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */


struct hwrm_vnic_tpa_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    flags;

        #define VNIC_TPA_QCFG_RESP_FLAGS_TPA                       0x1UL

        #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA                 0x2UL

        #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE            0x4UL

        #define VNIC_TPA_QCFG_RESP_FLAGS_GRO                       0x8UL

        #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN              0x10UL

        #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL

        #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK            0x40UL

        #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK             0x80UL

        __le16    max_agg_segs;

        #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1   0x0UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2   0x1UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4   0x2UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8   0x3UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL

        #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX

        __le16    max_aggs;

        #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1   0x0UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2   0x1UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4   0x2UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8   0x3UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16  0x4UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL

        #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX

        __le32    max_agg_timer;

        __le32    min_agg_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_vnic_rss_cfg_input (size:384b/48B) */


struct hwrm_vnic_rss_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    hash_type;

        #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4         0x1UL

        #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4     0x2UL

        #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4     0x4UL

        #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6         0x8UL

        #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6     0x10UL

        #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6     0x20UL

        __le16    vnic_id;

        u8    ring_table_pair_index;

        u8    hash_mode_flags;

        #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT         0x1UL

        #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4     0x2UL

        #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2     0x4UL

        #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL

        #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL

        __le64    ring_grp_tbl_addr;

        __le64    hash_key_tbl_addr;

        __le16    rss_ctx_idx;

        u8    unused_1[6];

};


/* hwrm_vnic_rss_cfg_output (size:128b/16B) */


struct hwrm_vnic_rss_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */


struct hwrm_vnic_rss_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    rss_ctx_idx;

        u8    unused_0[6];

};


/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */


struct hwrm_vnic_rss_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    hash_type;

        #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4         0x1UL

        #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4     0x2UL

        #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4     0x4UL

        #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6         0x8UL

        #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6     0x10UL

        #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6     0x20UL

        u8    unused_0[4];

        __le32    hash_key[10];

        u8    hash_mode_flags;

        #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT         0x1UL

        #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4     0x2UL

        #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2     0x4UL

        #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL

        #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL

        u8    unused_1[6];

        u8    valid;

};


/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */


struct hwrm_vnic_plcmodes_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT     0x1UL

        #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT       0x2UL

        #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4              0x4UL

        #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6              0x8UL

        #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE              0x10UL

        #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE              0x20UL

        __le32    enables;

        #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID      0x1UL

        #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID        0x2UL

        #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID     0x4UL

        __le32    vnic_id;

        __le16    jumbo_thresh;

        __le16    hds_offset;

        __le16    hds_threshold;

        u8    unused_0[6];

};


/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */


struct hwrm_vnic_plcmodes_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */


struct hwrm_vnic_plcmodes_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    vnic_id;

        u8    unused_0[4];

};


/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */


struct hwrm_vnic_plcmodes_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    flags;

        #define VNIC_PLCMODES_QCFG_RESP_FLAGS_REGULAR_PLACEMENT     0x1UL

        #define VNIC_PLCMODES_QCFG_RESP_FLAGS_JUMBO_PLACEMENT       0x2UL

        #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_IPV4              0x4UL

        #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_IPV6              0x8UL

        #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_FCOE              0x10UL

        #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_ROCE              0x20UL

        #define VNIC_PLCMODES_QCFG_RESP_FLAGS_DFLT_VNIC             0x40UL

        __le16    jumbo_thresh;

        __le16    hds_offset;

        __le16    hds_threshold;

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */


struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */


struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    rss_cos_lb_ctx_id;

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */


struct hwrm_vnic_rss_cos_lb_ctx_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    rss_cos_lb_ctx_id;

        u8    unused_0[6];

};


/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */


struct hwrm_vnic_rss_cos_lb_ctx_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_ring_alloc_input (size:704b/88B) */


struct hwrm_ring_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG          0x2UL

        #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID     0x8UL

        #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID          0x20UL

        #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID      0x40UL

        #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID      0x80UL

        #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID     0x100UL

        u8    ring_type;

        #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL   0x0UL

        #define RING_ALLOC_REQ_RING_TYPE_TX        0x1UL

        #define RING_ALLOC_REQ_RING_TYPE_RX        0x2UL

        #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL

        #define RING_ALLOC_REQ_RING_TYPE_RX_AGG    0x4UL

        #define RING_ALLOC_REQ_RING_TYPE_NQ        0x5UL

        #define RING_ALLOC_REQ_RING_TYPE_LAST     RING_ALLOC_REQ_RING_TYPE_NQ

        u8    unused_0;

        __le16    flags;

        #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD     0x1UL

        __le64    page_tbl_addr;

        __le32    fbo;

        u8    page_size;

        u8    page_tbl_depth;

        u8    unused_1[2];

        __le32    length;

        __le16    logical_id;

        __le16    cmpl_ring_id;

        __le16    queue_id;

        __le16    rx_buf_size;

        __le16    rx_ring_id;

        __le16    nq_ring_id;

        __le16    ring_arb_cfg;

        #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK      0xfUL

        #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT       0

        #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP          0x1UL

        #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ         0x2UL

        #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST       RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ

        #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK            0xf0UL

        #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT             4

        #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL

        #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8

        __le16    unused_3;

        __le32    reserved3;

        __le32    stat_ctx_id;

        __le32    reserved4;

        __le32    max_bw;

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT              0

        #define RING_ALLOC_REQ_MAX_BW_SCALE                     0x10000000UL

        #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)

        #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)

        #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST                 RING_ALLOC_REQ_MAX_BW_SCALE_BYTES

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST         RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID

        u8    int_mode;

        #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL

        #define RING_ALLOC_REQ_INT_MODE_RSVD   0x1UL

        #define RING_ALLOC_REQ_INT_MODE_MSIX   0x2UL

        #define RING_ALLOC_REQ_INT_MODE_POLL   0x3UL

        #define RING_ALLOC_REQ_INT_MODE_LAST  RING_ALLOC_REQ_INT_MODE_POLL

        u8    unused_4[3];

        __le64    cq_handle;

};


/* hwrm_ring_alloc_output (size:128b/16B) */


struct hwrm_ring_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    ring_id;

        __le16    logical_ring_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_ring_free_input (size:192b/24B) */


struct hwrm_ring_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    ring_type;

        #define RING_FREE_REQ_RING_TYPE_L2_CMPL   0x0UL

        #define RING_FREE_REQ_RING_TYPE_TX        0x1UL

        #define RING_FREE_REQ_RING_TYPE_RX        0x2UL

        #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL

        #define RING_FREE_REQ_RING_TYPE_RX_AGG    0x4UL

        #define RING_FREE_REQ_RING_TYPE_NQ        0x5UL

        #define RING_FREE_REQ_RING_TYPE_LAST     RING_FREE_REQ_RING_TYPE_NQ

        u8    unused_0;

        __le16    ring_id;

        u8    unused_1[4];

};


/* hwrm_ring_free_output (size:128b/16B) */


struct hwrm_ring_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_ring_reset_input (size:192b/24B) */


struct hwrm_ring_reset_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    ring_type;

        #define RING_RESET_REQ_RING_TYPE_L2_CMPL   0x0UL

        #define RING_RESET_REQ_RING_TYPE_TX        0x1UL

        #define RING_RESET_REQ_RING_TYPE_RX        0x2UL

        #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL

        #define RING_RESET_REQ_RING_TYPE_LAST     RING_RESET_REQ_RING_TYPE_ROCE_CMPL

        u8    unused_0;

        __le16    ring_id;

        u8    unused_1[4];

};


/* hwrm_ring_reset_output (size:128b/16B) */


struct hwrm_ring_reset_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */


struct hwrm_ring_aggint_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */


struct hwrm_ring_aggint_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    cmpl_params;

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN                  0x1UL

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX                  0x2UL

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET                      0x4UL

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE                        0x8UL

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR                0x10UL

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT     0x20UL

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR                0x40UL

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT     0x80UL

        #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT                0x100UL

        __le32    nq_params;

        #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN     0x1UL

        __le16    num_cmpl_dma_aggr_min;

        __le16    num_cmpl_dma_aggr_max;

        __le16    num_cmpl_dma_aggr_during_int_min;

        __le16    num_cmpl_dma_aggr_during_int_max;

        __le16    cmpl_aggr_dma_tmr_min;

        __le16    cmpl_aggr_dma_tmr_max;

        __le16    cmpl_aggr_dma_tmr_during_int_min;

        __le16    cmpl_aggr_dma_tmr_during_int_max;

        __le16    int_lat_tmr_min_min;

        __le16    int_lat_tmr_min_max;

        __le16    int_lat_tmr_max_min;

        __le16    int_lat_tmr_max_max;

        __le16    num_cmpl_aggr_int_min;

        __le16    num_cmpl_aggr_int_max;

        __le16    timer_units;

        u8    unused_0[1];

        u8    valid;

};


/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */


struct hwrm_ring_cmpl_ring_qaggint_params_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    ring_id;

        u8    unused_0[6];

};


/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */


struct hwrm_ring_cmpl_ring_qaggint_params_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    flags;

        #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET     0x1UL

        #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE       0x2UL

        __le16    num_cmpl_dma_aggr;

        __le16    num_cmpl_dma_aggr_during_int;

        __le16    cmpl_aggr_dma_tmr;

        __le16    cmpl_aggr_dma_tmr_during_int;

        __le16    int_lat_tmr_min;

        __le16    int_lat_tmr_max;

        __le16    num_cmpl_aggr_int;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */


struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    ring_id;

        __le16    flags;

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET     0x1UL

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE       0x2UL

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ           0x4UL

        __le16    num_cmpl_dma_aggr;

        __le16    num_cmpl_dma_aggr_during_int;

        __le16    cmpl_aggr_dma_tmr;

        __le16    cmpl_aggr_dma_tmr_during_int;

        __le16    int_lat_tmr_min;

        __le16    int_lat_tmr_max;

        __le16    num_cmpl_aggr_int;

        __le16    enables;

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR                0x1UL

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT     0x2UL

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR                0x4UL

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN                  0x8UL

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX                  0x10UL

        #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT                0x20UL

        u8    unused_0[4];

};


/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */


struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_ring_grp_alloc_input (size:192b/24B) */


struct hwrm_ring_grp_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    cr;

        __le16    rr;

        __le16    ar;

        __le16    sc;

};


/* hwrm_ring_grp_alloc_output (size:128b/16B) */


struct hwrm_ring_grp_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    ring_group_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_ring_grp_free_input (size:192b/24B) */


struct hwrm_ring_grp_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    ring_group_id;

        u8    unused_0[4];

};


/* hwrm_ring_grp_free_output (size:128b/16B) */


struct hwrm_ring_grp_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */


struct hwrm_cfa_l2_filter_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH              0x1UL

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX             0x0UL

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX             0x1UL

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK          0x2UL

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP              0x4UL

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST         0x8UL

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK      0x30UL

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT       4

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 4)

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 4)

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 4)

        #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE

        __le32    enables;

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR             0x1UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK        0x2UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN            0x4UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK       0x8UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN            0x10UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK       0x20UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR           0x40UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK      0x80UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN          0x100UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK     0x200UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN          0x400UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK     0x800UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE            0x1000UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID              0x2000UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE         0x4000UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID              0x8000UL

        #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID      0x10000UL

        u8    l2_addr[6];

        u8    unused_0[2];

        u8    l2_addr_mask[6];

        __le16    l2_ovlan;

        __le16    l2_ovlan_mask;

        __le16    l2_ivlan;

        __le16    l2_ivlan_mask;

        u8    unused_1[2];

        u8    t_l2_addr[6];

        u8    unused_2[2];

        u8    t_l2_addr_mask[6];

        __le16    t_l2_ovlan;

        __le16    t_l2_ovlan_mask;

        __le16    t_l2_ivlan;

        __le16    t_l2_ivlan_mask;

        u8    src_type;

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF    0x1UL

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF    0x2UL

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC  0x3UL

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG  0x4UL

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE   0x5UL

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO  0x6UL

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG  0x7UL

        #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG

        u8    unused_3;

        __le32    src_id;

        u8    tunnel_type;

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL

        u8    unused_4;

        __le16    dst_id;

        __le16    mirror_vnic_id;

        u8    pri_hint;

        #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER    0x0UL

        #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL

        #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL

        #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX          0x3UL

        #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN          0x4UL

        #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST        CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN

        u8    unused_5;

        __le32    unused_6;

        __le64    l2_filter_id_hint;

};


/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */


struct hwrm_cfa_l2_filter_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    l2_filter_id;

        __le32    flow_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */


struct hwrm_cfa_l2_filter_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    l2_filter_id;

};


/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */


struct hwrm_cfa_l2_filter_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */


struct hwrm_cfa_l2_filter_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH              0x1UL

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX             0x0UL

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX             0x1UL

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP              0x2UL

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK      0xcUL

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT       2

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 2)

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 2)

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 2)

        #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE

        __le32    enables;

        #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID                 0x1UL

        #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID     0x2UL

        __le64    l2_filter_id;

        __le32    dst_id;

        __le32    new_mirror_vnic_id;

};


/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */


struct hwrm_cfa_l2_filter_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */


struct hwrm_cfa_l2_set_rx_mask_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    vnic_id;

        __le32    mask;

        #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST               0x2UL

        #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST           0x4UL

        #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST               0x8UL

        #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS         0x10UL

        #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST           0x20UL

        #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY            0x40UL

        #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN        0x80UL

        #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN     0x100UL

        __le64    mc_tbl_addr;

        __le32    num_mc_entries;

        u8    unused_0[4];

        __le64    vlan_tag_tbl_addr;

        __le32    num_vlan_tags;

        u8    unused_1[4];

};


/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */


struct hwrm_cfa_l2_set_rx_mask_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */


struct hwrm_cfa_l2_set_rx_mask_cmd_err {

        u8    code;

        #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN                    0x0UL

        #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL

        #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST                      CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR

        u8    unused_0[7];

};


/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */


struct hwrm_cfa_vlan_antispoof_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[2];

        __le32    num_vlan_entries;

        __le64    vlan_tag_mask_tbl_addr;

};


/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */


struct hwrm_cfa_vlan_antispoof_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */


struct hwrm_cfa_vlan_antispoof_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    fid;

        u8    unused_0[2];

        __le32    max_vlan_entries;

        __le64    vlan_tag_mask_tbl_addr;

};


/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */


struct hwrm_cfa_vlan_antispoof_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    num_vlan_entries;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */


struct hwrm_cfa_tunnel_filter_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL

        __le32    enables;

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID       0x1UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR            0x2UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN           0x4UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR            0x8UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE       0x10UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE     0x20UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR          0x40UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x80UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI                0x100UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID        0x200UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x400UL

        __le64    l2_filter_id;

        u8    l2_addr[6];

        __le16    l2_ivlan;

        __le32    l3_addr[4];

        __le32    t_l3_addr[4];

        u8    l3_addr_type;

        u8    t_l3_addr_type;

        u8    tunnel_type;

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL

        u8    tunnel_flags;

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR     0x1UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1          0x2UL

        #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0         0x4UL

        __le32    vni;

        __le32    dst_vnic_id;

        __le32    mirror_vnic_id;

};


/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */


struct hwrm_cfa_tunnel_filter_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    tunnel_filter_id;

        __le32    flow_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */


struct hwrm_cfa_tunnel_filter_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    tunnel_filter_id;

};


/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */


struct hwrm_cfa_tunnel_filter_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */


struct hwrm_cfa_redirect_tunnel_type_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    dest_fid;

        u8    tunnel_type;

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL

        u8    flags;

        #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_FLAGS_MODIFY_DST     0x1UL

        u8    unused_0[4];

};


/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */


struct hwrm_cfa_redirect_tunnel_type_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */


struct hwrm_cfa_redirect_tunnel_type_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    dest_fid;

        u8    tunnel_type;

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_LAST     CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL

        u8    unused_0[5];

};


/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */


struct hwrm_cfa_redirect_tunnel_type_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */


struct hwrm_cfa_redirect_tunnel_type_info_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    src_fid;

        u8    tunnel_type;

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_LAST     CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_ANYTUNNEL

        u8    unused_0[5];

};


/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */


struct hwrm_cfa_redirect_tunnel_type_info_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    dest_fid;

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */


struct hwrm_vxlan_ipv4_hdr {

        u8    ver_hlen;

        #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL

        #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0

        #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK      0xf0UL

        #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT       4

        u8    tos;

        __be16    ip_id;

        __be16    flags_frag_offset;

        u8    ttl;

        u8    protocol;

        __be32    src_ip_addr;

        __be32    dest_ip_addr;

};


/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */


struct hwrm_vxlan_ipv6_hdr {

        __be32    ver_tc_flow_label;

        #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT         0x1cUL

        #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK        0xf0000000UL

        #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT          0x14UL

        #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK         0xff00000UL

        #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT  0x0UL

        #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL

        #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST           VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK

        __be16    payload_len;

        u8    next_hdr;

        u8    ttl;

        __be32    src_ip_addr[4];

        __be32    dest_ip_addr[4];

};


/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */


struct hwrm_cfa_encap_data_vxlan {

        u8    src_mac_addr[6];

        __le16    unused_0;

        u8    dst_mac_addr[6];

        u8    num_vlan_tags;

        u8    unused_1;

        __be16    ovlan_tpid;

        __be16    ovlan_tci;

        __be16    ivlan_tpid;

        __be16    ivlan_tci;

        __le32    l3[10];

        #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL

        #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL

        #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL

        #define CFA_ENCAP_DATA_VXLAN_L3_LAST    CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6

        __be16    src_port;

        __be16    dst_port;

        __be32    vni;

        u8    hdr_rsvd0[3];

        u8    hdr_rsvd1;

        u8    hdr_flags;

        u8    unused[3];

};


/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */


struct hwrm_cfa_encap_record_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL

        u8    encap_type;

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN    0x1UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE    0x2UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE    0x3UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP     0x4UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE   0x5UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS     0x6UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN     0x7UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE    0x8UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL

        #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST    CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE

        u8    unused_0[3];

        __le32    encap_data[20];

};


/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */


struct hwrm_cfa_encap_record_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    encap_record_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_encap_record_free_input (size:192b/24B) */


struct hwrm_cfa_encap_record_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    encap_record_id;

        u8    unused_0[4];

};


/* hwrm_cfa_encap_record_free_output (size:128b/16B) */


struct hwrm_cfa_encap_record_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */


struct hwrm_cfa_ntuple_filter_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP         0x2UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER        0x4UL

        __le32    enables;

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID         0x1UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE            0x2UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE          0x4UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR          0x8UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE          0x10UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR           0x20UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK      0x40UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR           0x80UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK      0x100UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL          0x200UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT             0x400UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK        0x800UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT             0x1000UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK        0x2000UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT             0x4000UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID     0x8000UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID               0x10000UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID       0x20000UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR          0x40000UL

        __le64    l2_filter_id;

        u8    src_macaddr[6];

        __be16    ethertype;

        u8    ip_addr_type;

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6

        u8    ip_protocol;

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP

        __le16    dst_id;

        __le16    mirror_vnic_id;

        u8    tunnel_type;

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL

        u8    pri_hint;

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE     0x1UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW     0x2UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST   0x3UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST    0x4UL

        #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST     CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST

        __be32    src_ipaddr[4];

        __be32    src_ipaddr_mask[4];

        __be32    dst_ipaddr[4];

        __be32    dst_ipaddr_mask[4];

        __be16    src_port;

        __be16    src_port_mask;

        __be16    dst_port;

        __be16    dst_port_mask;

        __le64    ntuple_filter_id_hint;

};


/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */


struct hwrm_cfa_ntuple_filter_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    ntuple_filter_id;

        __le32    flow_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */


struct hwrm_cfa_ntuple_filter_alloc_cmd_err {

        u8    code;

        #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN                   0x0UL

        #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL

        #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST                     CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR

        u8    unused_0[7];

};


/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */


struct hwrm_cfa_ntuple_filter_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    ntuple_filter_id;

};


/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */


struct hwrm_cfa_ntuple_filter_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */


struct hwrm_cfa_ntuple_filter_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID                0x1UL

        #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID        0x2UL

        #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID     0x4UL

        u8    unused_0[4];

        __le64    ntuple_filter_id;

        __le32    new_dst_id;

        __le32    new_mirror_vnic_id;

        __le16    new_meter_instance_id;

        #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL

        #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST   CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID

        u8    unused_1[6];

};


/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */


struct hwrm_cfa_ntuple_filter_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */


struct hwrm_cfa_em_flow_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH         0x1UL

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_TX        0x0UL

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_RX        0x1UL

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_LAST     CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_RX

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_BYTE_CTR     0x2UL

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PKT_CTR      0x4UL

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_DECAP        0x8UL

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_ENCAP        0x10UL

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_DROP         0x20UL

        #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_METER        0x40UL

        __le32    enables;

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_L2_FILTER_ID          0x1UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_TUNNEL_TYPE           0x2UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_TUNNEL_ID             0x4UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_MACADDR           0x8UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_MACADDR           0x10UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_OVLAN_VID             0x20UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IVLAN_VID             0x40UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_ETHERTYPE             0x80UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_IPADDR            0x100UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_IPADDR            0x200UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IPADDR_TYPE           0x400UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IP_PROTOCOL           0x800UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_PORT              0x1000UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_PORT              0x2000UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_ID                0x4000UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID        0x8000UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_ENCAP_RECORD_ID       0x10000UL

        #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_METER_INSTANCE_ID     0x20000UL

        __le64    l2_filter_id;

        u8    tunnel_type;

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL

        u8    unused_0[3];

        __le32    tunnel_id;

        u8    src_macaddr[6];

        __le16    meter_instance_id;

        #define CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_INVALID 0xffffUL

        #define CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_LAST   CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_INVALID

        u8    dst_macaddr[6];

        __le16    ovlan_vid;

        __le16    ivlan_vid;

        __be16    ethertype;

        u8    ip_addr_type;

        #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL

        #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL

        #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL

        #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV6

        u8    ip_protocol;

        #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL

        #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL

        #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL

        #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UDP

        u8    unused_1[2];

        __be32    src_ipaddr[4];

        __be32    dst_ipaddr[4];

        __be16    src_port;

        __be16    dst_port;

        __le16    dst_id;

        __le16    mirror_vnic_id;

        __le32    encap_record_id;

        u8    unused_2[4];

};


/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */


struct hwrm_cfa_em_flow_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    em_filter_id;

        __le32    flow_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_em_flow_free_input (size:192b/24B) */


struct hwrm_cfa_em_flow_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    em_filter_id;

};


/* hwrm_cfa_em_flow_free_output (size:128b/16B) */


struct hwrm_cfa_em_flow_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */


struct hwrm_cfa_em_flow_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_DST_ID                0x1UL

        #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID        0x2UL

        #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID     0x4UL

        u8    unused_0[4];

        __le64    em_filter_id;

        __le32    new_dst_id;

        __le32    new_mirror_vnic_id;

        __le16    new_meter_instance_id;

        #define CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL

        #define CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_LAST   CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID

        u8    unused_1[6];

};


/* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */


struct hwrm_cfa_em_flow_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */


struct hwrm_cfa_meter_profile_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH     0x1UL

        #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_TX    0x0UL

        #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_RX    0x1UL

        #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_RX

        u8    meter_type;

        #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC2697 0x0UL

        #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC2698 0x1UL

        #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC4115 0x2UL

        #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_LAST   CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC4115

        __le16    reserved1;

        __le32    reserved2;

        __le32    commit_rate;

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_MASK             0xfffffffUL

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_SFT              0

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE                     0x10000000UL

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BITS                  (0x0UL << 28)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BYTES                 (0x1UL << 28)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_LAST                 CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BYTES

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_SFT         29

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID

        __le32    commit_burst;

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_MASK             0xfffffffUL

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_SFT              0

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE                     0x10000000UL

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BITS                  (0x0UL << 28)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BYTES                 (0x1UL << 28)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_LAST                 CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BYTES

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_SFT         29

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID

        __le32    excess_peak_rate;

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_MASK             0xfffffffUL

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_SFT              0

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE                     0x10000000UL

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BITS                  (0x0UL << 28)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BYTES                 (0x1UL << 28)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_LAST                 CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BYTES

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT         29

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID

        __le32    excess_peak_burst;

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_MASK             0xfffffffUL

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_SFT              0

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE                     0x10000000UL

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BITS                  (0x0UL << 28)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BYTES                 (0x1UL << 28)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_LAST                 CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BYTES

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT         29

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID

};


/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */


struct hwrm_cfa_meter_profile_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    meter_profile_id;

        #define CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_INVALID 0xffffUL

        #define CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_LAST   CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_INVALID

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */


struct hwrm_cfa_meter_profile_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH     0x1UL

        #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_TX    0x0UL

        #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_RX    0x1UL

        #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_RX

        u8    unused_0;

        __le16    meter_profile_id;

        #define CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_INVALID 0xffffUL

        #define CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_LAST   CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_INVALID

        u8    unused_1[4];

};


/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */


struct hwrm_cfa_meter_profile_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */


struct hwrm_cfa_meter_profile_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH     0x1UL

        #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_TX    0x0UL

        #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_RX    0x1UL

        #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_RX

        u8    meter_type;

        #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC2697 0x0UL

        #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC2698 0x1UL

        #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC4115 0x2UL

        #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_LAST   CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC4115

        __le16    meter_profile_id;

        #define CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_INVALID 0xffffUL

        #define CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_LAST   CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_INVALID

        __le32    reserved;

        __le32    commit_rate;

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_MASK             0xfffffffUL

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_SFT              0

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE                     0x10000000UL

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BITS                  (0x0UL << 28)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BYTES                 (0x1UL << 28)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_LAST                 CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BYTES

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_SFT         29

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID

        __le32    commit_burst;

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_MASK             0xfffffffUL

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_SFT              0

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE                     0x10000000UL

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BITS                  (0x0UL << 28)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BYTES                 (0x1UL << 28)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_LAST                 CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BYTES

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_SFT         29

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID

        __le32    excess_peak_rate;

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_MASK             0xfffffffUL

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_SFT              0

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE                     0x10000000UL

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BITS                  (0x0UL << 28)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BYTES                 (0x1UL << 28)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_LAST                 CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BYTES

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT         29

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID

        __le32    excess_peak_burst;

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_MASK             0xfffffffUL

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_SFT              0

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE                     0x10000000UL

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BITS                  (0x0UL << 28)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BYTES                 (0x1UL << 28)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_LAST                 CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BYTES

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK        0xe0000000UL

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT         29

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA          (0x0UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO          (0x2UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE          (0x4UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA          (0x6UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID       (0x7UL << 29)

        #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST         CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID

};


/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */


struct hwrm_cfa_meter_profile_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */


struct hwrm_cfa_meter_instance_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH     0x1UL

        #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_TX    0x0UL

        #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_RX    0x1UL

        #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_LAST CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_RX

        u8    unused_0;

        __le16    meter_profile_id;

        #define CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_INVALID 0xffffUL

        #define CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_LAST   CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_INVALID

        u8    unused_1[4];

};


/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */


struct hwrm_cfa_meter_instance_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    meter_instance_id;

        #define CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_INVALID 0xffffUL

        #define CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_LAST   CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_INVALID

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */


struct hwrm_cfa_meter_instance_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH     0x1UL

        #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_TX    0x0UL

        #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_RX    0x1UL

        #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_LAST CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_RX

        u8    unused_0;

        __le16    meter_instance_id;

        #define CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_INVALID 0xffffUL

        #define CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_LAST   CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_INVALID

        u8    unused_1[4];

};


/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */


struct hwrm_cfa_meter_instance_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */


struct hwrm_cfa_decap_filter_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL     0x1UL

        __le32    enables;

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x1UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID          0x2UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR        0x4UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR        0x8UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID          0x10UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID          0x20UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID        0x40UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID        0x80UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE          0x100UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR         0x200UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR         0x400UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE        0x800UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL        0x1000UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT           0x2000UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT           0x4000UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID             0x8000UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x10000UL

        __be32    tunnel_id;

        u8    tunnel_type;

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL

        u8    unused_0;

        __le16    unused_1;

        u8    src_macaddr[6];

        u8    unused_2[2];

        u8    dst_macaddr[6];

        __be16    ovlan_vid;

        __be16    ivlan_vid;

        __be16    t_ovlan_vid;

        __be16    t_ivlan_vid;

        __be16    ethertype;

        u8    ip_addr_type;

        #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6

        u8    ip_protocol;

        #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL

        #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP

        __le16    unused_3;

        __le32    unused_4;

        __be32    src_ipaddr[4];

        __be32    dst_ipaddr[4];

        __be16    src_port;

        __be16    dst_port;

        __le16    dst_id;

        __le16    l2_ctxt_ref_id;

};


/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */


struct hwrm_cfa_decap_filter_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    decap_filter_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */


struct hwrm_cfa_decap_filter_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    decap_filter_id;

        u8    unused_0[4];

};


/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */


struct hwrm_cfa_decap_filter_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */


struct hwrm_cfa_flow_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    flags;

        #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL                 0x1UL

        #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK          0x6UL

        #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT           1

        #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE            (0x0UL << 1)

        #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE             (0x1UL << 1)

        #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO             (0x2UL << 1)

        #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO

        #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK          0x38UL

        #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT           3

        #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2              (0x0UL << 3)

        #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4            (0x1UL << 3)

        #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6            (0x2UL << 3)

        #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6

        #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX                0x40UL

        #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX                0x80UL

        #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI     0x100UL

        __le16    src_fid;

        __le32    tunnel_handle;

        __le16    action_flags;

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD                    0x1UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE                0x2UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP                   0x4UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER                  0x8UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL                 0x10UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC                0x20UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST               0x40UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS       0x80UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE      0x100UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT          0x200UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP              0x400UL

        #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED     0x800UL

        __le16    dst_fid;

        __be16    l2_rewrite_vlan_tpid;

        __be16    l2_rewrite_vlan_tci;

        __le16    act_meter_id;

        __le16    ref_flow_handle;

        __be16    ethertype;

        __be16    outer_vlan_tci;

        __be16    dmac[3];

        __be16    inner_vlan_tci;

        __be16    smac[3];

        u8    ip_dst_mask_len;

        u8    ip_src_mask_len;

        __be32    ip_dst[4];

        __be32    ip_src[4];

        __be16    l4_src_port;

        __be16    l4_src_port_mask;

        __be16    l4_dst_port;

        __be16    l4_dst_port_mask;

        __be32    nat_ip_address[4];

        __be16    l2_rewrite_dmac[3];

        __be16    nat_port;

        __be16    l2_rewrite_smac[3];

        u8    ip_proto;

        u8    tunnel_type;

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4  0x9UL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1  0xaUL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE  0xbUL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL

        #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST     CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL

};


/* hwrm_cfa_flow_alloc_output (size:256b/32B) */


struct hwrm_cfa_flow_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    flow_handle;

        u8    unused_0[2];

        __le32    flow_id;

        __le64    ext_flow_handle;

        u8    unused_1[7];

        u8    valid;

};


/* hwrm_cfa_flow_free_input (size:256b/32B) */


struct hwrm_cfa_flow_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    flow_handle;

        u8    unused_0[6];

        __le64    ext_flow_handle;

};


/* hwrm_cfa_flow_free_output (size:256b/32B) */


struct hwrm_cfa_flow_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    packet;

        __le64    byte;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_flow_info_input (size:256b/32B) */


struct hwrm_cfa_flow_info_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    flow_handle;

        #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK       0xfffUL

        #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT        0

        #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT        0x1000UL

        #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT     0x2000UL

        #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT     0x4000UL

        #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX         0x8000UL

        u8    unused_0[6];

        __le64    ext_flow_handle;

};


/* hwrm_cfa_flow_info_output (size:448b/56B) */


struct hwrm_cfa_flow_info_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    flags;

        u8    profile;

        __le16    src_fid;

        __le16    dst_fid;

        __le16    l2_ctxt_id;

        __le64    em_info;

        __le64    tcam_info;

        __le64    vfp_tcam_info;

        __le16    ar_id;

        __le16    flow_handle;

        __le32    tunnel_handle;

        __le16    flow_timer;

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_cfa_flow_flush_input (size:192b/24B) */


struct hwrm_cfa_flow_flush_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        u8    unused_0[4];

};


/* hwrm_cfa_flow_flush_output (size:128b/16B) */


struct hwrm_cfa_flow_flush_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_flow_stats_input (size:640b/80B) */


struct hwrm_cfa_flow_stats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    num_flows;

        __le16    flow_handle_0;

        __le16    flow_handle_1;

        __le16    flow_handle_2;

        __le16    flow_handle_3;

        __le16    flow_handle_4;

        __le16    flow_handle_5;

        __le16    flow_handle_6;

        __le16    flow_handle_7;

        __le16    flow_handle_8;

        __le16    flow_handle_9;

        u8    unused_0[2];

        __le32    flow_id_0;

        __le32    flow_id_1;

        __le32    flow_id_2;

        __le32    flow_id_3;

        __le32    flow_id_4;

        __le32    flow_id_5;

        __le32    flow_id_6;

        __le32    flow_id_7;

        __le32    flow_id_8;

        __le32    flow_id_9;

};


/* hwrm_cfa_flow_stats_output (size:1408b/176B) */


struct hwrm_cfa_flow_stats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    packet_0;

        __le64    packet_1;

        __le64    packet_2;

        __le64    packet_3;

        __le64    packet_4;

        __le64    packet_5;

        __le64    packet_6;

        __le64    packet_7;

        __le64    packet_8;

        __le64    packet_9;

        __le64    byte_0;

        __le64    byte_1;

        __le64    byte_2;

        __le64    byte_3;

        __le64    byte_4;

        __le64    byte_5;

        __le64    byte_6;

        __le64    byte_7;

        __le64    byte_8;

        __le64    byte_9;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */


struct hwrm_cfa_flow_aging_timer_reset_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    flow_handle;

        u8    unused_0[6];

        __le64    ext_flow_handle;

};


/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */


struct hwrm_cfa_flow_aging_timer_reset_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */


struct hwrm_cfa_flow_aging_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    enables;

        #define CFA_FLOW_AGING_CFG_REQ_ENABLES_TCP_FLOW_TIMER     0x1UL

        #define CFA_FLOW_AGING_CFG_REQ_ENABLES_TCP_FIN_TIMER      0x2UL

        #define CFA_FLOW_AGING_CFG_REQ_ENABLES_UDP_FLOW_TIMER     0x4UL

        u8    flags;

        #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH     0x1UL

        #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_TX    0x0UL

        #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_RX    0x1UL

        #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_RX

        u8    unused_0;

        __le32    tcp_flow_timer;

        __le32    tcp_fin_timer;

        __le32    udp_flow_timer;

};


/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */


struct hwrm_cfa_flow_aging_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */


struct hwrm_cfa_flow_aging_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH     0x1UL

        #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_TX    0x0UL

        #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_RX    0x1UL

        #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_RX

        u8    unused_0[7];

};


/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */


struct hwrm_cfa_flow_aging_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    tcp_flow_timer;

        __le32    tcp_fin_timer;

        __le32    udp_flow_timer;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */


struct hwrm_cfa_flow_aging_qcaps_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH     0x1UL

        #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_TX    0x0UL

        #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_RX    0x1UL

        #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_RX

        u8    unused_0[7];

};


/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */


struct hwrm_cfa_flow_aging_qcaps_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    max_tcp_flow_timer;

        __le32    max_tcp_fin_timer;

        __le32    max_udp_flow_timer;

        __le32    max_aging_flows;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */


struct hwrm_cfa_vf_pair_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    vf_a_id;

        __le16    vf_b_id;

        u8    unused_0[4];

        char    pair_name[32];

};


/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */


struct hwrm_cfa_vf_pair_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */


struct hwrm_cfa_vf_pair_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        char    pair_name[32];

};


/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */


struct hwrm_cfa_vf_pair_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */


struct hwrm_cfa_vf_pair_info_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_VF_PAIR_INFO_REQ_FLAGS_LOOKUP_TYPE     0x1UL

        __le16    vf_pair_index;

        u8    unused_0[2];

        char    vf_pair_name[32];

};


/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */


struct hwrm_cfa_vf_pair_info_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    next_vf_pair_index;

        __le16    vf_a_fid;

        __le16    vf_a_index;

        __le16    vf_b_fid;

        __le16    vf_b_index;

        u8    pair_state;

        #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ALLOCATED 0x1UL

        #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ACTIVE    0x2UL

        #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_LAST     CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ACTIVE

        u8    unused_0[5];

        char    pair_name[32];

        u8    unused_1[7];

        u8    valid;

};


/* hwrm_cfa_pair_alloc_input (size:576b/72B) */


struct hwrm_cfa_pair_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    pair_mode;

        #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_VF2FN         0x0UL

        #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN        0x1UL

        #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2REP       0x2UL

        #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_PROXY         0x3UL

        #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_PFPAIR        0x4UL

        #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MOD    0x5UL

        #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MODALL 0x6UL

        #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_LAST         CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MODALL

        u8    unused_0;

        __le16    vf_a_id;

        u8    host_b_id;

        u8    pf_b_id;

        __le16    vf_b_id;

        u8    port_id;

        u8    pri;

        __le16    new_pf_fid;

        __le32    enables;

        #define CFA_PAIR_ALLOC_REQ_ENABLES_Q_AB_VALID      0x1UL

        #define CFA_PAIR_ALLOC_REQ_ENABLES_Q_BA_VALID      0x2UL

        #define CFA_PAIR_ALLOC_REQ_ENABLES_FC_AB_VALID     0x4UL

        #define CFA_PAIR_ALLOC_REQ_ENABLES_FC_BA_VALID     0x8UL

        char    pair_name[32];

        u8    q_ab;

        u8    q_ba;

        u8    fc_ab;

        u8    fc_ba;

        u8    unused_1[4];

};


/* hwrm_cfa_pair_alloc_output (size:192b/24B) */


struct hwrm_cfa_pair_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    rx_cfa_code_a;

        __le16    tx_cfa_action_a;

        __le16    rx_cfa_code_b;

        __le16    tx_cfa_action_b;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_pair_free_input (size:384b/48B) */


struct hwrm_cfa_pair_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        char    pair_name[32];

};


/* hwrm_cfa_pair_free_output (size:128b/16B) */


struct hwrm_cfa_pair_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_pair_info_input (size:448b/56B) */


struct hwrm_cfa_pair_info_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define CFA_PAIR_INFO_REQ_FLAGS_LOOKUP_TYPE      0x1UL

        #define CFA_PAIR_INFO_REQ_FLAGS_LOOKUP_REPRE     0x2UL

        __le16    pair_index;

        u8    pair_pfid;

        u8    pair_vfid;

        char    pair_name[32];

};


/* hwrm_cfa_pair_info_output (size:576b/72B) */


struct hwrm_cfa_pair_info_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    next_pair_index;

        __le16    a_fid;

        u8    host_a_index;

        u8    pf_a_index;

        __le16    vf_a_index;

        __le16    rx_cfa_code_a;

        __le16    tx_cfa_action_a;

        __le16    b_fid;

        u8    host_b_index;

        u8    pf_b_index;

        __le16    vf_b_index;

        __le16    rx_cfa_code_b;

        __le16    tx_cfa_action_b;

        u8    pair_mode;

        #define CFA_PAIR_INFO_RESP_PAIR_MODE_VF2FN   0x0UL

        #define CFA_PAIR_INFO_RESP_PAIR_MODE_REP2FN  0x1UL

        #define CFA_PAIR_INFO_RESP_PAIR_MODE_REP2REP 0x2UL

        #define CFA_PAIR_INFO_RESP_PAIR_MODE_PROXY   0x3UL

        #define CFA_PAIR_INFO_RESP_PAIR_MODE_PFPAIR  0x4UL

        #define CFA_PAIR_INFO_RESP_PAIR_MODE_LAST   CFA_PAIR_INFO_RESP_PAIR_MODE_PFPAIR

        u8    pair_state;

        #define CFA_PAIR_INFO_RESP_PAIR_STATE_ALLOCATED 0x1UL

        #define CFA_PAIR_INFO_RESP_PAIR_STATE_ACTIVE    0x2UL

        #define CFA_PAIR_INFO_RESP_PAIR_STATE_LAST     CFA_PAIR_INFO_RESP_PAIR_STATE_ACTIVE

        char    pair_name[32];

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */


struct hwrm_cfa_vfr_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    vf_id;

        __le16    reserved;

        u8    unused_0[4];

        char    vfr_name[32];

};


/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */


struct hwrm_cfa_vfr_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    rx_cfa_code;

        __le16    tx_cfa_action;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_cfa_vfr_free_input (size:384b/48B) */


struct hwrm_cfa_vfr_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        char    vfr_name[32];

};


/* hwrm_cfa_vfr_free_output (size:128b/16B) */


struct hwrm_cfa_vfr_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */


struct hwrm_cfa_redirect_query_tunnel_type_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    src_fid;

        u8    unused_0[6];

};


/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */


struct hwrm_cfa_redirect_query_tunnel_type_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    tunnel_mask;

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_NONTUNNEL     0x1UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_VXLAN         0x2UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_NVGRE         0x4UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_L2GRE         0x8UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPIP          0x10UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_GENEVE        0x20UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_MPLS          0x40UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_STT           0x80UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPGRE         0x100UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_VXLAN_V4      0x200UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPGRE_V1      0x400UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_ANYTUNNEL     0x800UL

        #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_L2_ETYPE      0x1000UL

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */


struct hwrm_tunnel_dst_port_query_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    tunnel_type;

        #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN    0x1UL

        #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE   0x5UL

        #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL

        #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL

        #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL

        #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST    TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE

        u8    unused_0[7];

};


/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */


struct hwrm_tunnel_dst_port_query_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    tunnel_dst_port_id;

        __be16    tunnel_dst_port_val;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */


struct hwrm_tunnel_dst_port_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    tunnel_type;

        #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN    0x1UL

        #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE   0x5UL

        #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL

        #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL

        #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL

        #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST    TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE

        u8    unused_0;

        __be16    tunnel_dst_port_val;

        u8    unused_1[4];

};


/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */


struct hwrm_tunnel_dst_port_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    tunnel_dst_port_id;

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */


struct hwrm_tunnel_dst_port_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    tunnel_type;

        #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN    0x1UL

        #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE   0x5UL

        #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL

        #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL

        #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL

        #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST    TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE

        u8    unused_0;

        __le16    tunnel_dst_port_id;

        u8    unused_1[4];

};


/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */


struct hwrm_tunnel_dst_port_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_1[7];

        u8    valid;

};


/* ctx_hw_stats (size:1280b/160B) */


struct ctx_hw_stats {

        __le64    rx_ucast_pkts;

        __le64    rx_mcast_pkts;

        __le64    rx_bcast_pkts;

        __le64    rx_discard_pkts;

        __le64    rx_drop_pkts;

        __le64    rx_ucast_bytes;

        __le64    rx_mcast_bytes;

        __le64    rx_bcast_bytes;

        __le64    tx_ucast_pkts;

        __le64    tx_mcast_pkts;

        __le64    tx_bcast_pkts;

        __le64    tx_discard_pkts;

        __le64    tx_drop_pkts;

        __le64    tx_ucast_bytes;

        __le64    tx_mcast_bytes;

        __le64    tx_bcast_bytes;

        __le64    tpa_pkts;

        __le64    tpa_bytes;

        __le64    tpa_events;

        __le64    tpa_aborts;

};


/* ctx_eng_stats (size:512b/64B) */


struct ctx_eng_stats {

        __le64    eng_bytes_in;

        __le64    eng_bytes_out;

        __le64    aux_bytes_in;

        __le64    aux_bytes_out;

        __le64    commands;

        __le64    error_commands;

        __le64    cce_engine_usage;

        __le64    cdd_engine_usage;

};


/* hwrm_stat_ctx_alloc_input (size:256b/32B) */


struct hwrm_stat_ctx_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    stats_dma_addr;

        __le32    update_period_ms;

        u8    stat_ctx_flags;

        #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE     0x1UL

        u8    unused_0[3];

};


/* hwrm_stat_ctx_alloc_output (size:128b/16B) */


struct hwrm_stat_ctx_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    stat_ctx_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_stat_ctx_free_input (size:192b/24B) */


struct hwrm_stat_ctx_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    stat_ctx_id;

        u8    unused_0[4];

};


/* hwrm_stat_ctx_free_output (size:128b/16B) */


struct hwrm_stat_ctx_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    stat_ctx_id;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_stat_ctx_query_input (size:192b/24B) */


struct hwrm_stat_ctx_query_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    stat_ctx_id;

        u8    unused_0[4];

};


/* hwrm_stat_ctx_query_output (size:1408b/176B) */


struct hwrm_stat_ctx_query_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    tx_ucast_pkts;

        __le64    tx_mcast_pkts;

        __le64    tx_bcast_pkts;

        __le64    tx_err_pkts;

        __le64    tx_drop_pkts;

        __le64    tx_ucast_bytes;

        __le64    tx_mcast_bytes;

        __le64    tx_bcast_bytes;

        __le64    rx_ucast_pkts;

        __le64    rx_mcast_pkts;

        __le64    rx_bcast_pkts;

        __le64    rx_err_pkts;

        __le64    rx_drop_pkts;

        __le64    rx_ucast_bytes;

        __le64    rx_mcast_bytes;

        __le64    rx_bcast_bytes;

        __le64    rx_agg_pkts;

        __le64    rx_agg_bytes;

        __le64    rx_agg_events;

        __le64    rx_agg_aborts;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */


struct hwrm_stat_ctx_eng_query_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    stat_ctx_id;

        u8    unused_0[4];

};


/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */


struct hwrm_stat_ctx_eng_query_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    eng_bytes_in;

        __le64    eng_bytes_out;

        __le64    aux_bytes_in;

        __le64    aux_bytes_out;

        __le64    commands;

        __le64    error_commands;

        __le64    cce_engine_usage;

        __le64    cdd_engine_usage;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */


struct hwrm_stat_ctx_clr_stats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    stat_ctx_id;

        u8    unused_0[4];

};


/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */


struct hwrm_stat_ctx_clr_stats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_pcie_qstats_input (size:256b/32B) */


struct hwrm_pcie_qstats_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    pcie_stat_size;

        u8    unused_0[6];

        __le64    pcie_stat_host_addr;

};


/* hwrm_pcie_qstats_output (size:128b/16B) */


struct hwrm_pcie_qstats_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    pcie_stat_size;

        u8    unused_0[5];

        u8    valid;

};


/* pcie_ctx_hw_stats (size:768b/96B) */


struct pcie_ctx_hw_stats {

        __le64    pcie_pl_signal_integrity;

        __le64    pcie_dl_signal_integrity;

        __le64    pcie_tl_signal_integrity;

        __le64    pcie_link_integrity;

        __le64    pcie_tx_traffic_rate;

        __le64    pcie_rx_traffic_rate;

        __le64    pcie_tx_dllp_statistics;

        __le64    pcie_rx_dllp_statistics;

        __le64    pcie_equalization_time;

        __le32    pcie_ltssm_histogram[4];

        __le64    pcie_recovery_histogram;

};


/* hwrm_fw_reset_input (size:192b/24B) */


struct hwrm_fw_reset_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    embedded_proc_type;

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT                 0x0UL

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT                 0x1UL

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL              0x2UL

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE                 0x3UL

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST                 0x4UL

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP                   0x5UL

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP                 0x6UL

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL

        #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST                FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT

        u8    selfrst_status;

        #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE      0x0UL

        #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP      0x1UL

        #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST   0x2UL

        #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL

        #define FW_RESET_REQ_SELFRST_STATUS_LAST            FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE

        u8    host_idx;

        u8    flags;

        #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL     0x1UL

        u8    unused_0[4];

};


/* hwrm_fw_reset_output (size:128b/16B) */


struct hwrm_fw_reset_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    selfrst_status;

        #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE      0x0UL

        #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP      0x1UL

        #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST   0x2UL

        #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL

        #define FW_RESET_RESP_SELFRST_STATUS_LAST            FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE

        u8    unused_0[6];

        u8    valid;

};


/* hwrm_fw_qstatus_input (size:192b/24B) */


struct hwrm_fw_qstatus_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    embedded_proc_type;

        #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT    0x0UL

        #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT    0x1UL

        #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL

        #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE    0x3UL

        #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST    0x4UL

        #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP      0x5UL

        #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP    0x6UL

        #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST   FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP

        u8    unused_0[7];

};


/* hwrm_fw_qstatus_output (size:128b/16B) */


struct hwrm_fw_qstatus_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    selfrst_status;

        #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE    0x0UL

        #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP    0x1UL

        #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL

        #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST          FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST

        u8    unused_0[6];

        u8    valid;

};


/* hwrm_fw_set_time_input (size:256b/32B) */


struct hwrm_fw_set_time_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    year;

        #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL

        #define FW_SET_TIME_REQ_YEAR_LAST   FW_SET_TIME_REQ_YEAR_UNKNOWN

        u8    month;

        u8    day;

        u8    hour;

        u8    minute;

        u8    second;

        u8    unused_0;

        __le16    millisecond;

        __le16    zone;

        #define FW_SET_TIME_REQ_ZONE_UTC     0x0UL

        #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL

        #define FW_SET_TIME_REQ_ZONE_LAST   FW_SET_TIME_REQ_ZONE_UNKNOWN

        u8    unused_1[4];

};


/* hwrm_fw_set_time_output (size:128b/16B) */


struct hwrm_fw_set_time_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_fw_get_time_input (size:128b/16B) */


struct hwrm_fw_get_time_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_fw_get_time_output (size:192b/24B) */


struct hwrm_fw_get_time_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    year;

        #define FW_GET_TIME_RESP_YEAR_UNKNOWN 0x0UL

        #define FW_GET_TIME_RESP_YEAR_LAST   FW_GET_TIME_RESP_YEAR_UNKNOWN

        u8    month;

        u8    day;

        u8    hour;

        u8    minute;

        u8    second;

        u8    unused_0;

        __le16    millisecond;

        __le16    zone;

        #define FW_GET_TIME_RESP_ZONE_UTC     0x0UL

        #define FW_GET_TIME_RESP_ZONE_UNKNOWN 0xffffUL

        #define FW_GET_TIME_RESP_ZONE_LAST   FW_GET_TIME_RESP_ZONE_UNKNOWN

        u8    unused_1[3];

        u8    valid;

};


/* hwrm_struct_hdr (size:128b/16B) */


struct hwrm_struct_hdr {

        __le16    struct_id;

        #define STRUCT_HDR_STRUCT_ID_LLDP_CFG           0x41bUL

        #define STRUCT_HDR_STRUCT_ID_DCBX_ETS           0x41dUL

        #define STRUCT_HDR_STRUCT_ID_DCBX_PFC           0x41fUL

        #define STRUCT_HDR_STRUCT_ID_DCBX_APP           0x421UL

        #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL

        #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC       0x424UL

        #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE        0x426UL

        #define STRUCT_HDR_STRUCT_ID_POWER_BKUP         0x427UL

        #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE         0x1UL

        #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION   0xaUL

        #define STRUCT_HDR_STRUCT_ID_RSS_V2             0x64UL

        #define STRUCT_HDR_STRUCT_ID_LAST              STRUCT_HDR_STRUCT_ID_RSS_V2

        __le16    len;

        u8    version;

        u8    count;

        __le16    subtype;

        __le16    next_offset;

        #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL

        u8    unused_0[6];

};


/* hwrm_struct_data_dcbx_ets (size:256b/32B) */


struct hwrm_struct_data_dcbx_ets {

        u8    destination;

        #define STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION   0x1UL

        #define STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION 0x2UL

        #define STRUCT_DATA_DCBX_ETS_DESTINATION_LAST           STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION

        u8    max_tcs;

        __le16    unused1;

        u8    pri0_to_tc_map;

        u8    pri1_to_tc_map;

        u8    pri2_to_tc_map;

        u8    pri3_to_tc_map;

        u8    pri4_to_tc_map;

        u8    pri5_to_tc_map;

        u8    pri6_to_tc_map;

        u8    pri7_to_tc_map;

        u8    tc0_to_bw_map;

        u8    tc1_to_bw_map;

        u8    tc2_to_bw_map;

        u8    tc3_to_bw_map;

        u8    tc4_to_bw_map;

        u8    tc5_to_bw_map;

        u8    tc6_to_bw_map;

        u8    tc7_to_bw_map;

        u8    tc0_to_tsa_map;

        #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP              0x0UL

        #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS             0x1UL

        #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS             0x2UL

        #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC 0xffUL

        #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_LAST                    STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC

        u8    tc1_to_tsa_map;

        u8    tc2_to_tsa_map;

        u8    tc3_to_tsa_map;

        u8    tc4_to_tsa_map;

        u8    tc5_to_tsa_map;

        u8    tc6_to_tsa_map;

        u8    tc7_to_tsa_map;

        u8    unused_0[4];

};


/* hwrm_struct_data_dcbx_pfc (size:64b/8B) */


struct hwrm_struct_data_dcbx_pfc {

        u8    pfc_priority_bitmap;

        u8    max_pfc_tcs;

        u8    mbc;

        u8    unused_0[5];

};


/* hwrm_struct_data_dcbx_app (size:64b/8B) */


struct hwrm_struct_data_dcbx_app {

        __be16    protocol_id;

        u8    protocol_selector;

        #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE   0x1UL

        #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT     0x2UL

        #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT     0x3UL

        #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL

        #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST        STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT

        u8    priority;

        u8    valid;

        u8    unused_0[3];

};


/* hwrm_struct_data_dcbx_feature_state (size:64b/8B) */


struct hwrm_struct_data_dcbx_feature_state {

        u8    dcbx_mode;

        #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED 0x0UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE     0x1UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE      0x2UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_LAST         STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE

        u8    ets_state;

        u8    pfc_state;

        u8    app_state;

        #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS    0x7UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS   0x6UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS 0x5UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_LAST             STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS

        u8    unused[3];

        u8    resets;

        #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS   0x1UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC   0x2UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP   0x4UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE 0x8UL

        #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_LAST       STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE

};


/* hwrm_struct_data_lldp (size:64b/8B) */


struct hwrm_struct_data_lldp {

        u8    admin_state;

        #define STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE 0x0UL

        #define STRUCT_DATA_LLDP_ADMIN_STATE_TX      0x1UL

        #define STRUCT_DATA_LLDP_ADMIN_STATE_RX      0x2UL

        #define STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE  0x3UL

        #define STRUCT_DATA_LLDP_ADMIN_STATE_LAST   STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE

        u8    port_description_state;

        #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE 0x0UL

        #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE  0x1UL

        #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_LAST   STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE

        u8    system_name_state;

        #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE 0x0UL

        #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE  0x1UL

        #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_LAST   STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE

        u8    system_desc_state;

        #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE 0x0UL

        #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE  0x1UL

        #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_LAST   STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE

        u8    system_cap_state;

        #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE 0x0UL

        #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE  0x1UL

        #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_LAST   STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE

        u8    mgmt_addr_state;

        #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE 0x0UL

        #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE  0x1UL

        #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_LAST   STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE

        u8    async_event_notification_state;

        #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE 0x0UL

        #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE  0x1UL

        #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_LAST   STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE

        u8    unused_0;

};


/* hwrm_struct_data_lldp_generic (size:2112b/264B) */


struct hwrm_struct_data_lldp_generic {

        u8    tlv_type;

        #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS            0x1UL

        #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT               0x2UL

        #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME        0x3UL

        #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION 0x4UL

        #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME          0x5UL

        #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION   0x6UL

        #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_LAST              STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION

        u8    subtype;

        u8    length;

        u8    unused1[5];

        __le32    tlv_value[64];

};


/* hwrm_struct_data_lldp_device (size:1472b/184B) */


struct hwrm_struct_data_lldp_device {

        __le16    ttl;

        u8    mgmt_addr_len;

        u8    mgmt_addr_type;

        u8    unused_3[4];

        __le32    mgmt_addr[8];

        __le32    system_caps;

        u8    intf_num_type;

        u8    mgmt_addr_oid_length;

        u8    unused_4[2];

        __le32    intf_num;

        u8    unused_5[4];

        __le32    mgmt_addr_oid[32];

};


/* hwrm_struct_data_port_description (size:64b/8B) */


struct hwrm_struct_data_port_description {

        u8    port_id;

        u8    unused_0[7];

};


/* hwrm_struct_data_rss_v2 (size:128b/16B) */


struct hwrm_struct_data_rss_v2 {

        __le16    flags;

        #define STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID     0x1UL

        __le16    rss_ctx_id;

        __le16    num_ring_groups;

        __le16    hash_type;

        #define STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4         0x1UL

        #define STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4     0x2UL

        #define STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4     0x4UL

        #define STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6         0x8UL

        #define STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6     0x10UL

        #define STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6     0x20UL

        __le64    hash_key_ring_group_ids;

};


/* hwrm_struct_data_power_information (size:192b/24B) */


struct hwrm_struct_data_power_information {

        __le32    bkup_power_info_ver;

        __le32    platform_bkup_power_count;

        __le32    load_milli_watt;

        __le32    bkup_time_milli_seconds;

        __le32    bkup_power_status;

        __le32    bkup_power_charge_time;

};


/* hwrm_fw_set_structured_data_input (size:256b/32B) */


struct hwrm_fw_set_structured_data_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    src_data_addr;

        __le16    data_len;

        u8    hdr_cnt;

        u8    unused_0[5];

};


/* hwrm_fw_set_structured_data_output (size:128b/16B) */


struct hwrm_fw_set_structured_data_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */


struct hwrm_fw_set_structured_data_cmd_err {

        u8    code;

        #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN     0x0UL

        #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL

        #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT     0x2UL

        #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID      0x3UL

        #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST       FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID

        u8    unused_0[7];

};


/* hwrm_fw_get_structured_data_input (size:256b/32B) */


struct hwrm_fw_get_structured_data_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    dest_data_addr;

        __le16    data_len;

        __le16    structure_id;

        __le16    subtype;

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED                  0x0UL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL                     0xffffUL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN       0x100UL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER        0x101UL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN          0x200UL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER           0x201UL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL    0x202UL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL        0x300UL

        #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST                   FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL

        u8    count;

        u8    unused_0;

};


/* hwrm_fw_get_structured_data_output (size:128b/16B) */


struct hwrm_fw_get_structured_data_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    hdr_cnt;

        u8    unused_0[6];

        u8    valid;

};


/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */


struct hwrm_fw_get_structured_data_cmd_err {

        u8    code;

        #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL

        #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID  0x3UL

        #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST   FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID

        u8    unused_0[7];

};


/* hwrm_fw_ipc_msg_input (size:320b/40B) */


struct hwrm_fw_ipc_msg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define FW_IPC_MSG_REQ_ENABLES_COMMAND_ID        0x1UL

        #define FW_IPC_MSG_REQ_ENABLES_SRC_PROCESSOR     0x2UL

        #define FW_IPC_MSG_REQ_ENABLES_DATA_OFFSET       0x4UL

        #define FW_IPC_MSG_REQ_ENABLES_LENGTH            0x8UL

        __le16    command_id;

        #define FW_IPC_MSG_REQ_COMMAND_ID_ROCE_LAG 0x1UL

        #define FW_IPC_MSG_REQ_COMMAND_ID_LAST    FW_IPC_MSG_REQ_COMMAND_ID_ROCE_LAG

        u8    src_processor;

        #define FW_IPC_MSG_REQ_SRC_PROCESSOR_CFW  0x1UL

        #define FW_IPC_MSG_REQ_SRC_PROCESSOR_BONO 0x2UL

        #define FW_IPC_MSG_REQ_SRC_PROCESSOR_APE  0x3UL

        #define FW_IPC_MSG_REQ_SRC_PROCESSOR_KONG 0x4UL

        #define FW_IPC_MSG_REQ_SRC_PROCESSOR_LAST FW_IPC_MSG_REQ_SRC_PROCESSOR_KONG

        u8    unused_0;

        __le32    data_offset;

        __le16    length;

        u8    unused_1[2];

        __le64    opaque;

};


/* hwrm_fw_ipc_msg_output (size:128b/16B) */


struct hwrm_fw_ipc_msg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_fw_ipc_mailbox_input (size:256b/32B) */


struct hwrm_fw_ipc_mailbox_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        u8    unused;

        u8    event_id;

        u8    port_id;

        __le32    event_data1;

        __le32    event_data2;

        u8    unused_0[4];

};


/* hwrm_fw_ipc_mailbox_output (size:128b/16B) */


struct hwrm_fw_ipc_mailbox_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_fw_ipc_mailbox_cmd_err (size:64b/8B) */


struct hwrm_fw_ipc_mailbox_cmd_err {

        u8    code;

        #define FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN 0x0UL

        #define FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID  0x3UL

        #define FW_IPC_MAILBOX_CMD_ERR_CODE_LAST   FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID

        u8    unused_0[7];

};


/* hwrm_fw_health_check_input (size:128b/16B) */


struct hwrm_fw_health_check_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_fw_health_check_output (size:128b/16B) */


struct hwrm_fw_health_check_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    fw_status;

        #define FW_HEALTH_CHECK_RESP_FW_STATUS_SBI_BOOTED       0x1UL

        #define FW_HEALTH_CHECK_RESP_FW_STATUS_SBI_MISMATCH     0x2UL

        #define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT_BOOTED       0x4UL

        #define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT_MISMATCH     0x8UL

        #define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT_BOOTED       0x10UL

        #define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT_MISMATCH     0x20UL

        #define FW_HEALTH_CHECK_RESP_FW_STATUS_SECOND_RT        0x40UL

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_fw_sync_input (size:192b/24B) */


struct hwrm_fw_sync_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    sync_action;

        #define FW_SYNC_REQ_SYNC_ACTION_SYNC_SBI     0x1UL

        #define FW_SYNC_REQ_SYNC_ACTION_SYNC_SRT     0x2UL

        #define FW_SYNC_REQ_SYNC_ACTION_SYNC_CRT     0x4UL

        #define FW_SYNC_REQ_SYNC_ACTION_ACTION       0x80000000UL

        u8    unused_0[4];

};


/* hwrm_fw_sync_output (size:128b/16B) */


struct hwrm_fw_sync_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    sync_status;

        #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_MASK       0xffUL

        #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_SFT        0

        #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_SUCCESS      0x0UL

        #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_IN_PROGRESS  0x1UL

        #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_TIMEOUT      0x2UL

        #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_GENERAL      0x3UL

        #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_LAST        FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_GENERAL

        #define FW_SYNC_RESP_SYNC_STATUS_SYNC_ERR            0x40000000UL

        #define FW_SYNC_RESP_SYNC_STATUS_SYNC_COMPLETE       0x80000000UL

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_exec_fwd_resp_input (size:1024b/128B) */


struct hwrm_exec_fwd_resp_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    encap_request[26];

        __le16    encap_resp_target_id;

        u8    unused_0[6];

};


/* hwrm_exec_fwd_resp_output (size:128b/16B) */


struct hwrm_exec_fwd_resp_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_reject_fwd_resp_input (size:1024b/128B) */


struct hwrm_reject_fwd_resp_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    encap_request[26];

        __le16    encap_resp_target_id;

        u8    unused_0[6];

};


/* hwrm_reject_fwd_resp_output (size:128b/16B) */


struct hwrm_reject_fwd_resp_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_fwd_resp_input (size:1024b/128B) */


struct hwrm_fwd_resp_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    encap_resp_target_id;

        __le16    encap_resp_cmpl_ring;

        __le16    encap_resp_len;

        u8    unused_0;

        u8    unused_1;

        __le64    encap_resp_addr;

        __le32    encap_resp[24];

};


/* hwrm_fwd_resp_output (size:128b/16B) */


struct hwrm_fwd_resp_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */


struct hwrm_fwd_async_event_cmpl_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    encap_async_event_target_id;

        u8    unused_0[6];

        __le32    encap_async_event_cmpl[4];

};


/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */


struct hwrm_fwd_async_event_cmpl_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_temp_monitor_query_input (size:128b/16B) */


struct hwrm_temp_monitor_query_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_temp_monitor_query_output (size:128b/16B) */


struct hwrm_temp_monitor_query_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    temp;

        u8    unused_0[6];

        u8    valid;

};


/* hwrm_wol_filter_alloc_input (size:512b/64B) */


struct hwrm_wol_filter_alloc_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        __le32    enables;

        #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS           0x1UL

        #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET        0x2UL

        #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE      0x4UL

        #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR      0x8UL

        #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR     0x10UL

        #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE     0x20UL

        __le16    port_id;

        u8    wol_type;

        #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL

        #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP      0x1UL

        #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID  0xffUL

        #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST    WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID

        u8    unused_0[5];

        u8    mac_address[6];

        __le16    pattern_offset;

        __le16    pattern_buf_size;

        __le16    pattern_mask_size;

        u8    unused_1[4];

        __le64    pattern_buf_addr;

        __le64    pattern_mask_addr;

};


/* hwrm_wol_filter_alloc_output (size:128b/16B) */


struct hwrm_wol_filter_alloc_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    wol_filter_id;

        u8    unused_0[6];

        u8    valid;

};


/* hwrm_wol_filter_free_input (size:256b/32B) */


struct hwrm_wol_filter_free_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS     0x1UL

        __le32    enables;

        #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID     0x1UL

        __le16    port_id;

        u8    wol_filter_id;

        u8    unused_0[5];

};


/* hwrm_wol_filter_free_output (size:128b/16B) */


struct hwrm_wol_filter_free_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_wol_filter_qcfg_input (size:448b/56B) */


struct hwrm_wol_filter_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        __le16    handle;

        u8    unused_0[4];

        __le64    pattern_buf_addr;

        __le16    pattern_buf_size;

        u8    unused_1[6];

        __le64    pattern_mask_addr;

        __le16    pattern_mask_size;

        u8    unused_2[6];

};


/* hwrm_wol_filter_qcfg_output (size:256b/32B) */


struct hwrm_wol_filter_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    next_handle;

        u8    wol_filter_id;

        u8    wol_type;

        #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL

        #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP      0x1UL

        #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID  0xffUL

        #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST    WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID

        __le32    unused_0;

        u8    mac_address[6];

        __le16    pattern_offset;

        __le16    pattern_size;

        __le16    pattern_mask_size;

        u8    unused_1[3];

        u8    valid;

};


/* hwrm_wol_reason_qcfg_input (size:320b/40B) */


struct hwrm_wol_reason_qcfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    port_id;

        u8    unused_0[6];

        __le64    wol_pkt_buf_addr;

        __le16    wol_pkt_buf_size;

        u8    unused_1[6];

};


/* hwrm_wol_reason_qcfg_output (size:128b/16B) */


struct hwrm_wol_reason_qcfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    wol_filter_id;

        u8    wol_reason;

        #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL

        #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP      0x1UL

        #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID  0xffUL

        #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST    WOL_REASON_QCFG_RESP_WOL_REASON_INVALID

        u8    wol_pkt_len;

        u8    unused_0[4];

        u8    valid;

};


/* hwrm_dbg_read_direct_input (size:256b/32B) */


struct hwrm_dbg_read_direct_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

        __le32    read_addr;

        __le32    read_len32;

};


/* hwrm_dbg_read_direct_output (size:128b/16B) */


struct hwrm_dbg_read_direct_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_dbg_write_direct_input (size:448b/56B) */


struct hwrm_dbg_write_direct_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    write_addr;

        __le32    write_len32;

        __le32    write_data[8];

};


/* hwrm_dbg_write_direct_output (size:128b/16B) */


struct hwrm_dbg_write_direct_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_dbg_read_indirect_input (size:320b/40B) */


struct hwrm_dbg_read_indirect_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

        __le32    host_dest_addr_len;

        u8    indirect_access_type;

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2         0x0UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4       0x1UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2         0x2UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4       0x3UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_STAT_CTXS                  0x4UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM             0x5UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM             0x6UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM    0x7UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM    0x8UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM 0x9UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM 0xaUL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM        0xbUL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM 0xcUL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM 0xdUL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM         0xeUL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM         0xfUL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MHB                        0x10UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_PCIE_GBL                   0x11UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC             0x12UL

        #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_LAST                      DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC

        u8    unused_0[3];

        __le32    start_index;

        __le32    num_of_entries;

};


/* hwrm_dbg_read_indirect_output (size:128b/16B) */


struct hwrm_dbg_read_indirect_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_dbg_write_indirect_input (size:512b/64B) */


struct hwrm_dbg_write_indirect_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    indirect_access_type;

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2         0x0UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4       0x1UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2         0x2UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4       0x3UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_STAT_CTXS                  0x4UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM             0x5UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM             0x6UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM    0x7UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM    0x8UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM 0x9UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM 0xaUL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM        0xbUL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM 0xcUL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM 0xdUL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM         0xeUL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM         0xfUL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MHB                        0x10UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_PCIE_GBL                   0x11UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC             0x12UL

        #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_LAST                      DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC

        u8    unused_0[3];

        __le32    start_index;

        __le32    num_of_entries;

        u8    unused_1[4];

        __le32    write_data[8];

};


/* hwrm_dbg_write_indirect_output (size:128b/16B) */


struct hwrm_dbg_write_indirect_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_dbg_dump_input (size:320b/40B) */


struct hwrm_dbg_dump_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    handle;

        u8    unused_0[4];

        __le64    host_dbg_dump_addr;

        __le64    host_dbg_dump_addr_len;

};


/* hwrm_dbg_dump_output (size:192b/24B) */


struct hwrm_dbg_dump_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    nexthandle;

        __le32    dbg_data_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_dbg_erase_nvm_input (size:192b/24B) */


struct hwrm_dbg_erase_nvm_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    flags;

        #define DBG_ERASE_NVM_REQ_FLAGS_ERASE_ALL     0x1UL

        u8    unused_0[6];

};


/* hwrm_dbg_erase_nvm_output (size:128b/16B) */


struct hwrm_dbg_erase_nvm_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_dbg_cfg_input (size:192b/24B) */


struct hwrm_dbg_cfg_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    flags;

        #define DBG_CFG_REQ_FLAGS_UART_LOG               0x1UL

        #define DBG_CFG_REQ_FLAGS_UART_LOG_SECONDARY     0x2UL

        u8    unused_0[4];

};


/* hwrm_dbg_cfg_output (size:128b/16B) */


struct hwrm_dbg_cfg_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* coredump_segment_record (size:128b/16B) */


struct coredump_segment_record {

        __le16    component_id;

        __le16    segment_id;

        __le16    max_instances;

        u8    version_hi;

        u8    version_low;

        u8    seg_flags;

        u8    unused_0[7];

};


/* hwrm_dbg_coredump_list_input (size:256b/32B) */


struct hwrm_dbg_coredump_list_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

        __le32    host_buf_len;

        __le16    seq_no;

        u8    unused_0[2];

};


/* hwrm_dbg_coredump_list_output (size:128b/16B) */


struct hwrm_dbg_coredump_list_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    flags;

        #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE     0x1UL

        u8    unused_0;

        __le16    total_segments;

        __le16    data_len;

        u8    unused_1;

        u8    valid;

};


/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */


struct hwrm_dbg_coredump_initiate_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    component_id;

        __le16    segment_id;

        __le16    instance;

        __le16    unused_0;

        u8    seg_flags;

        u8    unused_1[7];

};


/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */


struct hwrm_dbg_coredump_initiate_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* coredump_data_hdr (size:128b/16B) */


struct coredump_data_hdr {

        __le32    address;

        __le32    flags_length;

        __le32    instance;

        __le32    next_offset;

};


/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */


struct hwrm_dbg_coredump_retrieve_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

        __le32    host_buf_len;

        __le32    unused_0;

        __le16    component_id;

        __le16    segment_id;

        __le16    instance;

        __le16    unused_1;

        u8    seg_flags;

        u8    unused_2;

        __le16    unused_3;

        __le32    unused_4;

        __le32    seq_no;

        __le32    unused_5;

};


/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */


struct hwrm_dbg_coredump_retrieve_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    flags;

        #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE     0x1UL

        u8    unused_0;

        __le16    data_len;

        u8    unused_1[3];

        u8    valid;

};


/* hwrm_dbg_i2c_cmd_input (size:320b/40B) */


struct hwrm_dbg_i2c_cmd_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

        __le16    read_size;

        __le16    write_size;

        u8    chnl_id;

        u8    options;

        #define DBG_I2C_CMD_REQ_OPTIONS_10_BIT_ADDRESSING     0x1UL

        #define DBG_I2C_CMD_REQ_OPTIONS_FAST_MODE             0x2UL

        __le16    slave_addr;

        u8    xfer_mode;

        #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_READ       0x0UL

        #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE      0x1UL

        #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE_READ 0x2UL

        #define DBG_I2C_CMD_REQ_XFER_MODE_LAST             DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE_READ

        u8    unused_1[7];

};


/* hwrm_dbg_i2c_cmd_output (size:128b/16B) */


struct hwrm_dbg_i2c_cmd_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_dbg_fw_cli_input (size:1024b/128B) */


struct hwrm_dbg_fw_cli_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

        __le32    host_buf_len;

        __le16    cli_cmd_len;

        u8    unused_0[2];

        u8    cli_cmd[96];

};


/* hwrm_dbg_fw_cli_output (size:128b/16B) */


struct hwrm_dbg_fw_cli_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    cli_data_len;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_dbg_ring_info_get_input (size:192b/24B) */


struct hwrm_dbg_ring_info_get_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    ring_type;

        #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL

        #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX      0x1UL

        #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX      0x2UL

        #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST   DBG_RING_INFO_GET_REQ_RING_TYPE_RX

        u8    unused_0[3];

        __le32    fw_ring_id;

};


/* hwrm_dbg_ring_info_get_output (size:192b/24B) */


struct hwrm_dbg_ring_info_get_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    producer_index;

        __le32    consumer_index;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */


struct hwrm_nvm_raw_write_blk_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_src_addr;

        __le32    dest_addr;

        __le32    len;

};


/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */


struct hwrm_nvm_raw_write_blk_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_read_input (size:320b/40B) */


struct hwrm_nvm_read_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

        __le16    dir_idx;

        u8    unused_0[2];

        __le32    offset;

        __le32    len;

        u8    unused_1[4];

};


/* hwrm_nvm_read_output (size:128b/16B) */


struct hwrm_nvm_read_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_raw_dump_input (size:256b/32B) */


struct hwrm_nvm_raw_dump_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

        __le32    offset;

        __le32    len;

};


/* hwrm_nvm_raw_dump_output (size:128b/16B) */


struct hwrm_nvm_raw_dump_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */


struct hwrm_nvm_get_dir_entries_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_dest_addr;

};


/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */


struct hwrm_nvm_get_dir_entries_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_get_dir_info_input (size:128b/16B) */


struct hwrm_nvm_get_dir_info_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_nvm_get_dir_info_output (size:192b/24B) */


struct hwrm_nvm_get_dir_info_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    entries;

        __le32    entry_length;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_write_input (size:384b/48B) */


struct hwrm_nvm_write_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_src_addr;

        __le16    dir_type;

        __le16    dir_ordinal;

        __le16    dir_ext;

        __le16    dir_attr;

        __le32    dir_data_length;

        __le16    option;

        __le16    flags;

        #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG     0x1UL

        __le32    dir_item_length;

        __le32    unused_0;

};


/* hwrm_nvm_write_output (size:128b/16B) */


struct hwrm_nvm_write_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    dir_item_length;

        __le16    dir_idx;

        u8    unused_0;

        u8    valid;

};


/* hwrm_nvm_write_cmd_err (size:64b/8B) */


struct hwrm_nvm_write_cmd_err {

        u8    code;

        #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN  0x0UL

        #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL

        #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL

        #define NVM_WRITE_CMD_ERR_CODE_LAST    NVM_WRITE_CMD_ERR_CODE_NO_SPACE

        u8    unused_0[7];

};


/* hwrm_nvm_modify_input (size:320b/40B) */


struct hwrm_nvm_modify_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    host_src_addr;

        __le16    dir_idx;

        u8    unused_0[2];

        __le32    offset;

        __le32    len;

        u8    unused_1[4];

};


/* hwrm_nvm_modify_output (size:128b/16B) */


struct hwrm_nvm_modify_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */


struct hwrm_nvm_find_dir_entry_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID     0x1UL

        __le16    dir_idx;

        __le16    dir_type;

        __le16    dir_ordinal;

        __le16    dir_ext;

        u8    opt_ordinal;

        #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL

        #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0

        #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ    0x0UL

        #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE    0x1UL

        #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT    0x2UL

        #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT

        u8    unused_0[3];

};


/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */


struct hwrm_nvm_find_dir_entry_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    dir_item_length;

        __le32    dir_data_length;

        __le32    fw_ver;

        __le16    dir_ordinal;

        __le16    dir_idx;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */


struct hwrm_nvm_erase_dir_entry_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    dir_idx;

        u8    unused_0[6];

};


/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */


struct hwrm_nvm_erase_dir_entry_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_get_dev_info_input (size:128b/16B) */


struct hwrm_nvm_get_dev_info_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_nvm_get_dev_info_output (size:256b/32B) */


struct hwrm_nvm_get_dev_info_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    manufacturer_id;

        __le16    device_id;

        __le32    sector_size;

        __le32    nvram_size;

        __le32    reserved_size;

        __le32    available_size;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */


struct hwrm_nvm_mod_dir_entry_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    enables;

        #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM     0x1UL

        __le16    dir_idx;

        __le16    dir_ordinal;

        __le16    dir_ext;

        __le16    dir_attr;

        __le32    checksum;

};


/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */


struct hwrm_nvm_mod_dir_entry_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_verify_update_input (size:192b/24B) */


struct hwrm_nvm_verify_update_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le16    dir_type;

        __le16    dir_ordinal;

        __le16    dir_ext;

        u8    unused_0[2];

};


/* hwrm_nvm_verify_update_output (size:128b/16B) */


struct hwrm_nvm_verify_update_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_install_update_input (size:192b/24B) */


struct hwrm_nvm_install_update_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    install_type;

        #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL

        #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL    0xffffffffUL

        #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST  NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL

        __le16    flags;

        #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE     0x1UL

        #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG      0x2UL

        #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG      0x4UL

        u8    unused_0[2];

};


/* hwrm_nvm_install_update_output (size:192b/24B) */


struct hwrm_nvm_install_update_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le64    installed_items;

        u8    result;

        #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL

        #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST   NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS

        u8    problem_item;

        #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE    0x0UL

        #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL

        #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST   NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE

        u8    reset_required;

        #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE  0x0UL

        #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI   0x1UL

        #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL

        #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER

        u8    unused_0[4];

        u8    valid;

};


/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */


struct hwrm_nvm_install_update_cmd_err {

        u8    code;

        #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN  0x0UL

        #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL

        #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL

        #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST    NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE

        u8    unused_0[7];

};


/* hwrm_nvm_flush_input (size:128b/16B) */


struct hwrm_nvm_flush_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_nvm_flush_output (size:128b/16B) */


struct hwrm_nvm_flush_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_flush_cmd_err (size:64b/8B) */


struct hwrm_nvm_flush_cmd_err {

        u8    code;

        #define NVM_FLUSH_CMD_ERR_CODE_UNKNOWN 0x0UL

        #define NVM_FLUSH_CMD_ERR_CODE_FAIL    0x1UL

        #define NVM_FLUSH_CMD_ERR_CODE_LAST   NVM_FLUSH_CMD_ERR_CODE_FAIL

        u8    unused_0[7];

};


/* hwrm_nvm_get_variable_input (size:320b/40B) */


struct hwrm_nvm_get_variable_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    dest_data_addr;

        __le16    data_len;

        __le16    option_num;

        #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL

        #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL

        #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF

        __le16    dimensions;

        __le16    index_0;

        __le16    index_1;

        __le16    index_2;

        __le16    index_3;

        u8    flags;

        #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT     0x1UL

        u8    unused_0;

};


/* hwrm_nvm_get_variable_output (size:128b/16B) */


struct hwrm_nvm_get_variable_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    data_len;

        __le16    option_num;

        #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0    0x0UL

        #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL

        #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST     NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */


struct hwrm_nvm_get_variable_cmd_err {

        u8    code;

        #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL

        #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL

        #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL

        #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL

        #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST         NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT

        u8    unused_0[7];

};


/* hwrm_nvm_set_variable_input (size:320b/40B) */


struct hwrm_nvm_set_variable_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    src_data_addr;

        __le16    data_len;

        __le16    option_num;

        #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL

        #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL

        #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF

        __le16    dimensions;

        __le16    index_0;

        __le16    index_1;

        __le16    index_2;

        __le16    index_3;

        u8    flags;

        #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH                0x1UL

        #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK          0xeUL

        #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT           1

        #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE            (0x0UL << 1)

        #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1       (0x1UL << 1)

        #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256          (0x2UL << 1)

        #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH  (0x3UL << 1)

        #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST           NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH

        u8    unused_0;

};


/* hwrm_nvm_set_variable_output (size:128b/16B) */


struct hwrm_nvm_set_variable_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */


struct hwrm_nvm_set_variable_cmd_err {

        u8    code;

        #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL

        #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL

        #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL

        #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST         NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR

        u8    unused_0[7];

};


/* hwrm_nvm_validate_option_input (size:320b/40B) */


struct hwrm_nvm_validate_option_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    src_data_addr;

        __le16    data_len;

        __le16    option_num;

        #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_0    0x0UL

        #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL

        #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_LAST     NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_FFFF

        __le16    dimensions;

        __le16    index_0;

        __le16    index_1;

        __le16    index_2;

        __le16    index_3;

        u8    unused_0[2];

};


/* hwrm_nvm_validate_option_output (size:128b/16B) */


struct hwrm_nvm_validate_option_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    result;

        #define NVM_VALIDATE_OPTION_RESP_RESULT_NOT_MATCH 0x0UL

        #define NVM_VALIDATE_OPTION_RESP_RESULT_MATCH     0x1UL

        #define NVM_VALIDATE_OPTION_RESP_RESULT_LAST     NVM_VALIDATE_OPTION_RESP_RESULT_MATCH

        u8    unused_0[6];

        u8    valid;

};


/* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */


struct hwrm_nvm_validate_option_cmd_err {

        u8    code;

        #define NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN 0x0UL

        #define NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST   NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN

        u8    unused_0[7];

};


/* hwrm_nvm_factory_defaults_input (size:192b/24B) */


struct hwrm_nvm_factory_defaults_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    mode;

        #define NVM_FACTORY_DEFAULTS_REQ_MODE_RESTORE 0x0UL

        #define NVM_FACTORY_DEFAULTS_REQ_MODE_CREATE  0x1UL

        #define NVM_FACTORY_DEFAULTS_REQ_MODE_LAST   NVM_FACTORY_DEFAULTS_REQ_MODE_CREATE

        u8    unused_0[7];

};


/* hwrm_nvm_factory_defaults_output (size:128b/16B) */


struct hwrm_nvm_factory_defaults_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    result;

        #define NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_OK      0x0UL

        #define NVM_FACTORY_DEFAULTS_RESP_RESULT_RESTORE_OK     0x1UL

        #define NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_ALREADY 0x2UL

        #define NVM_FACTORY_DEFAULTS_RESP_RESULT_LAST          NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_ALREADY

        u8    unused_0[6];

        u8    valid;

};


/* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */


struct hwrm_nvm_factory_defaults_cmd_err {

        u8    code;

        #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN      0x0UL

        #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG 0x1UL

        #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG 0x2UL

        #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST        NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG

        u8    unused_0[7];

};


/* hwrm_selftest_qlist_input (size:128b/16B) */


struct hwrm_selftest_qlist_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_selftest_qlist_output (size:2240b/280B) */


struct hwrm_selftest_qlist_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    num_tests;

        u8    available_tests;

        #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST                 0x1UL

        #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST                0x2UL

        #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST            0x4UL

        #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST              0x8UL

        #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST         0x10UL

        #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST     0x20UL

        u8    offline_tests;

        #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST                 0x1UL

        #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST                0x2UL

        #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST            0x4UL

        #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST              0x8UL

        #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST         0x10UL

        #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST     0x20UL

        u8    unused_0;

        __le16    test_timeout;

        u8    unused_1[2];

        char    test0_name[32];

        char    test1_name[32];

        char    test2_name[32];

        char    test3_name[32];

        char    test4_name[32];

        char    test5_name[32];

        char    test6_name[32];

        char    test7_name[32];

        u8    unused_2[7];

        u8    valid;

};


/* hwrm_selftest_exec_input (size:192b/24B) */


struct hwrm_selftest_exec_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        u8    flags;

        #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST                 0x1UL

        #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST                0x2UL

        #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST            0x4UL

        #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST              0x8UL

        #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST         0x10UL

        #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST     0x20UL

        u8    unused_0[7];

};


/* hwrm_selftest_exec_output (size:128b/16B) */


struct hwrm_selftest_exec_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    requested_tests;

        #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST                 0x1UL

        #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST                0x2UL

        #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST            0x4UL

        #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST              0x8UL

        #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST         0x10UL

        #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST     0x20UL

        u8    test_success;

        #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST                 0x1UL

        #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST                0x2UL

        #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST            0x4UL

        #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST              0x8UL

        #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST         0x10UL

        #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST     0x20UL

        u8    unused_0[5];

        u8    valid;

};


/* hwrm_selftest_irq_input (size:128b/16B) */


struct hwrm_selftest_irq_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

};


/* hwrm_selftest_irq_output (size:128b/16B) */


struct hwrm_selftest_irq_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        u8    unused_0[7];

        u8    valid;

};


/* hwrm_selftest_retrieve_serdes_data_input (size:256b/32B) */


struct hwrm_selftest_retrieve_serdes_data_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le64    resp_data_addr;

        __le32    resp_data_offset;

        __le16    data_len;

        u8    flags;

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_MASK         0x7UL

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_SFT          0

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_EYE_PROJECTION           0x8UL

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_PCIE_SERDES_TEST         0x10UL

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_ETHERNET_SERDES_TEST     0x20UL

        u8    options;

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PCIE_LANE_NO_MASK     0xfUL

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PCIE_LANE_NO_SFT      0

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION             0x10UL

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_HORIZONTAL    (0x0UL << 4)

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_VERTICAL      (0x1UL << 4)

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_LAST         SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_VERTICAL

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE             0x20UL

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_LEFT_TOP      (0x0UL << 5)

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM  (0x1UL << 5)

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_LAST         SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_RSVD_MASK             0xc0UL

        #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_RSVD_SFT              6

};


/* hwrm_selftest_retrieve_serdes_data_output (size:128b/16B) */


struct hwrm_selftest_retrieve_serdes_data_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le16    total_data_len;

        __le16    copied_data_len;

        u8    unused_0[3];

        u8    valid;

};


/* hwrm_oem_cmd_input (size:1024b/128B) */


struct hwrm_oem_cmd_input {

        __le16    req_type;

        __le16    cmpl_ring;

        __le16    seq_id;

        __le16    target_id;

        __le64    resp_addr;

        __le32    IANA;

        __le32    unused_0;

        __le32    oem_data[26];

};


/* hwrm_oem_cmd_output (size:1344b/168B) */


struct hwrm_oem_cmd_output {

        __le16    error_code;

        __le16    req_type;

        __le16    seq_id;

        __le16    resp_len;

        __le32    IANA;

        __le32    unused_0;

        __le32    oem_data[36];

        u8    unused_1[7];

        u8    valid;

};


#endif /* _BNXT_HSI_H_ */

__le64
#define __le64
Definition bnxt.h:23

__le16
#define __le16
Definition bnxt.h:21

__be32
#define __be32
Definition bnxt.h:25

__le32
#define __le32
Definition bnxt.h:22

__be16
#define __be16
Definition bnxt.h:24

u8
#define u8
Definition igbvf_osdep.h:40

cmd_nums
Definition bnxt_hsi.h:96

cmd_nums::unused_0
__le16 unused_0[3]
Definition bnxt_hsi.h:325

cmd_nums::req_type
__le16 req_type
Definition bnxt_hsi.h:97

coredump_data_hdr
Definition bnxt_hsi.h:9780

coredump_data_hdr::address
__le32 address
Definition bnxt_hsi.h:9781

coredump_data_hdr::next_offset
__le32 next_offset
Definition bnxt_hsi.h:9784

coredump_data_hdr::instance
__le32 instance
Definition bnxt_hsi.h:9783

coredump_data_hdr::flags_length
__le32 flags_length
Definition bnxt_hsi.h:9782

coredump_segment_record
Definition bnxt_hsi.h:9716

coredump_segment_record::version_low
u8 version_low
Definition bnxt_hsi.h:9721

coredump_segment_record::seg_flags
u8 seg_flags
Definition bnxt_hsi.h:9722

coredump_segment_record::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9723

coredump_segment_record::version_hi
u8 version_hi
Definition bnxt_hsi.h:9720

coredump_segment_record::segment_id
__le16 segment_id
Definition bnxt_hsi.h:9718

coredump_segment_record::max_instances
__le16 max_instances
Definition bnxt_hsi.h:9719

coredump_segment_record::component_id
__le16 component_id
Definition bnxt_hsi.h:9717

ctx_eng_stats
Definition bnxt_hsi.h:8505

ctx_eng_stats::cce_engine_usage
__le64 cce_engine_usage
Definition bnxt_hsi.h:8512

ctx_eng_stats::eng_bytes_in
__le64 eng_bytes_in
Definition bnxt_hsi.h:8506

ctx_eng_stats::cdd_engine_usage
__le64 cdd_engine_usage
Definition bnxt_hsi.h:8513

ctx_eng_stats::error_commands
__le64 error_commands
Definition bnxt_hsi.h:8511

ctx_eng_stats::commands
__le64 commands
Definition bnxt_hsi.h:8510

ctx_eng_stats::aux_bytes_in
__le64 aux_bytes_in
Definition bnxt_hsi.h:8508

ctx_eng_stats::aux_bytes_out
__le64 aux_bytes_out
Definition bnxt_hsi.h:8509

ctx_eng_stats::eng_bytes_out
__le64 eng_bytes_out
Definition bnxt_hsi.h:8507

ctx_hw_stats
Definition bnxt_hsi.h:8481

ctx_hw_stats::rx_mcast_bytes
__le64 rx_mcast_bytes
Definition bnxt_hsi.h:8488

ctx_hw_stats::tx_bcast_pkts
__le64 tx_bcast_pkts
Definition bnxt_hsi.h:8492

ctx_hw_stats::rx_mcast_pkts
__le64 rx_mcast_pkts
Definition bnxt_hsi.h:8483

ctx_hw_stats::tx_mcast_pkts
__le64 tx_mcast_pkts
Definition bnxt_hsi.h:8491

ctx_hw_stats::tpa_events
__le64 tpa_events
Definition bnxt_hsi.h:8500

ctx_hw_stats::tx_mcast_bytes
__le64 tx_mcast_bytes
Definition bnxt_hsi.h:8496

ctx_hw_stats::rx_ucast_pkts
__le64 rx_ucast_pkts
Definition bnxt_hsi.h:8482

ctx_hw_stats::rx_drop_pkts
__le64 rx_drop_pkts
Definition bnxt_hsi.h:8486

ctx_hw_stats::rx_bcast_pkts
__le64 rx_bcast_pkts
Definition bnxt_hsi.h:8484

ctx_hw_stats::tx_ucast_bytes
__le64 tx_ucast_bytes
Definition bnxt_hsi.h:8495

ctx_hw_stats::tpa_bytes
__le64 tpa_bytes
Definition bnxt_hsi.h:8499

ctx_hw_stats::tpa_aborts
__le64 tpa_aborts
Definition bnxt_hsi.h:8501

ctx_hw_stats::rx_bcast_bytes
__le64 rx_bcast_bytes
Definition bnxt_hsi.h:8489

ctx_hw_stats::tpa_pkts
__le64 tpa_pkts
Definition bnxt_hsi.h:8498

ctx_hw_stats::rx_discard_pkts
__le64 rx_discard_pkts
Definition bnxt_hsi.h:8485

ctx_hw_stats::rx_ucast_bytes
__le64 rx_ucast_bytes
Definition bnxt_hsi.h:8487

ctx_hw_stats::tx_discard_pkts
__le64 tx_discard_pkts
Definition bnxt_hsi.h:8493

ctx_hw_stats::tx_ucast_pkts
__le64 tx_ucast_pkts
Definition bnxt_hsi.h:8490

ctx_hw_stats::tx_bcast_bytes
__le64 tx_bcast_bytes
Definition bnxt_hsi.h:8497

ctx_hw_stats::tx_drop_pkts
__le64 tx_drop_pkts
Definition bnxt_hsi.h:8494

eject_cmpl
Definition bnxt_hsi.h:473

eject_cmpl::unused_2
__le32 unused_2
Definition bnxt_hsi.h:496

eject_cmpl::reserved16
__le16 reserved16
Definition bnxt_hsi.h:495

eject_cmpl::v
__le16 v
Definition bnxt_hsi.h:484

eject_cmpl::opaque
__le32 opaque
Definition bnxt_hsi.h:483

eject_cmpl::len
__le16 len
Definition bnxt_hsi.h:482

eject_cmpl::type
__le16 type
Definition bnxt_hsi.h:474

hwrm_async_event_cmpl_dcb_config_change
Definition bnxt_hsi.h:683

hwrm_async_event_cmpl_dcb_config_change::event_id
__le16 event_id
Definition bnxt_hsi.h:689

hwrm_async_event_cmpl_dcb_config_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:692

hwrm_async_event_cmpl_dcb_config_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:701

hwrm_async_event_cmpl_dcb_config_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:702

hwrm_async_event_cmpl_dcb_config_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:700

hwrm_async_event_cmpl_dcb_config_change::type
__le16 type
Definition bnxt_hsi.h:684

hwrm_async_event_cmpl_dcb_config_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:696

hwrm_async_event_cmpl_default_vnic_change
Definition bnxt_hsi.h:1086

hwrm_async_event_cmpl_default_vnic_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:1097

hwrm_async_event_cmpl_default_vnic_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:1104

hwrm_async_event_cmpl_default_vnic_change::type
__le16 type
Definition bnxt_hsi.h:1087

hwrm_async_event_cmpl_default_vnic_change::event_id
__le16 event_id
Definition bnxt_hsi.h:1094

hwrm_async_event_cmpl_default_vnic_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:1102

hwrm_async_event_cmpl_default_vnic_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:1103

hwrm_async_event_cmpl_default_vnic_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:1098

hwrm_async_event_cmpl_func_drvr_load
Definition bnxt_hsi.h:871

hwrm_async_event_cmpl_func_drvr_load::event_data2
__le32 event_data2
Definition bnxt_hsi.h:880

hwrm_async_event_cmpl_func_drvr_load::event_id
__le16 event_id
Definition bnxt_hsi.h:877

hwrm_async_event_cmpl_func_drvr_load::type
__le16 type
Definition bnxt_hsi.h:872

hwrm_async_event_cmpl_func_drvr_load::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:881

hwrm_async_event_cmpl_func_drvr_load::event_data1
__le32 event_data1
Definition bnxt_hsi.h:887

hwrm_async_event_cmpl_func_drvr_load::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:886

hwrm_async_event_cmpl_func_drvr_load::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:885

hwrm_async_event_cmpl_func_drvr_unload
Definition bnxt_hsi.h:849

hwrm_async_event_cmpl_func_drvr_unload::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:859

hwrm_async_event_cmpl_func_drvr_unload::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:864

hwrm_async_event_cmpl_func_drvr_unload::event_data2
__le32 event_data2
Definition bnxt_hsi.h:858

hwrm_async_event_cmpl_func_drvr_unload::event_id
__le16 event_id
Definition bnxt_hsi.h:855

hwrm_async_event_cmpl_func_drvr_unload::event_data1
__le32 event_data1
Definition bnxt_hsi.h:865

hwrm_async_event_cmpl_func_drvr_unload::type
__le16 type
Definition bnxt_hsi.h:850

hwrm_async_event_cmpl_func_drvr_unload::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:863

hwrm_async_event_cmpl_func_flr_proc_cmplt
Definition bnxt_hsi.h:893

hwrm_async_event_cmpl_func_flr_proc_cmplt::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:908

hwrm_async_event_cmpl_func_flr_proc_cmplt::type
__le16 type
Definition bnxt_hsi.h:894

hwrm_async_event_cmpl_func_flr_proc_cmplt::event_id
__le16 event_id
Definition bnxt_hsi.h:899

hwrm_async_event_cmpl_func_flr_proc_cmplt::event_data2
__le32 event_data2
Definition bnxt_hsi.h:902

hwrm_async_event_cmpl_func_flr_proc_cmplt::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:903

hwrm_async_event_cmpl_func_flr_proc_cmplt::event_data1
__le32 event_data1
Definition bnxt_hsi.h:909

hwrm_async_event_cmpl_func_flr_proc_cmplt::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:907

hwrm_async_event_cmpl_hw_flow_aged
Definition bnxt_hsi.h:1117

hwrm_async_event_cmpl_hw_flow_aged::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:1127

hwrm_async_event_cmpl_hw_flow_aged::event_data2
__le32 event_data2
Definition bnxt_hsi.h:1126

hwrm_async_event_cmpl_hw_flow_aged::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:1131

hwrm_async_event_cmpl_hw_flow_aged::event_id
__le16 event_id
Definition bnxt_hsi.h:1123

hwrm_async_event_cmpl_hw_flow_aged::event_data1
__le32 event_data1
Definition bnxt_hsi.h:1133

hwrm_async_event_cmpl_hw_flow_aged::type
__le16 type
Definition bnxt_hsi.h:1118

hwrm_async_event_cmpl_hw_flow_aged::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:1132

hwrm_async_event_cmpl_hwrm_error
Definition bnxt_hsi.h:1143

hwrm_async_event_cmpl_hwrm_error::event_data2
__le32 event_data2
Definition bnxt_hsi.h:1152

hwrm_async_event_cmpl_hwrm_error::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:1163

hwrm_async_event_cmpl_hwrm_error::event_data1
__le32 event_data1
Definition bnxt_hsi.h:1165

hwrm_async_event_cmpl_hwrm_error::event_id
__le16 event_id
Definition bnxt_hsi.h:1149

hwrm_async_event_cmpl_hwrm_error::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:1164

hwrm_async_event_cmpl_hwrm_error::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:1159

hwrm_async_event_cmpl_hwrm_error::type
__le16 type
Definition bnxt_hsi.h:1144

hwrm_async_event_cmpl_link_mtu_change
Definition bnxt_hsi.h:625

hwrm_async_event_cmpl_link_mtu_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:640

hwrm_async_event_cmpl_link_mtu_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:635

hwrm_async_event_cmpl_link_mtu_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:634

hwrm_async_event_cmpl_link_mtu_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:641

hwrm_async_event_cmpl_link_mtu_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:639

hwrm_async_event_cmpl_link_mtu_change::event_id
__le16 event_id
Definition bnxt_hsi.h:631

hwrm_async_event_cmpl_link_mtu_change::type
__le16 type
Definition bnxt_hsi.h:626

hwrm_async_event_cmpl_link_speed_cfg_change
Definition bnxt_hsi.h:767

hwrm_async_event_cmpl_link_speed_cfg_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:777

hwrm_async_event_cmpl_link_speed_cfg_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:776

hwrm_async_event_cmpl_link_speed_cfg_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:783

hwrm_async_event_cmpl_link_speed_cfg_change::event_id
__le16 event_id
Definition bnxt_hsi.h:773

hwrm_async_event_cmpl_link_speed_cfg_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:781

hwrm_async_event_cmpl_link_speed_cfg_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:782

hwrm_async_event_cmpl_link_speed_cfg_change::type
__le16 type
Definition bnxt_hsi.h:768

hwrm_async_event_cmpl_link_speed_cfg_not_allowed
Definition bnxt_hsi.h:745

hwrm_async_event_cmpl_link_speed_cfg_not_allowed::event_data2
__le32 event_data2
Definition bnxt_hsi.h:754

hwrm_async_event_cmpl_link_speed_cfg_not_allowed::event_data1
__le32 event_data1
Definition bnxt_hsi.h:761

hwrm_async_event_cmpl_link_speed_cfg_not_allowed::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:755

hwrm_async_event_cmpl_link_speed_cfg_not_allowed::event_id
__le16 event_id
Definition bnxt_hsi.h:751

hwrm_async_event_cmpl_link_speed_cfg_not_allowed::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:759

hwrm_async_event_cmpl_link_speed_cfg_not_allowed::type
__le16 type
Definition bnxt_hsi.h:746

hwrm_async_event_cmpl_link_speed_cfg_not_allowed::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:760

hwrm_async_event_cmpl_link_speed_change
Definition bnxt_hsi.h:647

hwrm_async_event_cmpl_link_speed_change::type
__le16 type
Definition bnxt_hsi.h:648

hwrm_async_event_cmpl_link_speed_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:661

hwrm_async_event_cmpl_link_speed_change::event_id
__le16 event_id
Definition bnxt_hsi.h:653

hwrm_async_event_cmpl_link_speed_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:662

hwrm_async_event_cmpl_link_speed_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:657

hwrm_async_event_cmpl_link_speed_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:663

hwrm_async_event_cmpl_link_speed_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:656

hwrm_async_event_cmpl_link_status_change
Definition bnxt_hsi.h:595

hwrm_async_event_cmpl_link_status_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:609

hwrm_async_event_cmpl_link_status_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:611

hwrm_async_event_cmpl_link_status_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:604

hwrm_async_event_cmpl_link_status_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:610

hwrm_async_event_cmpl_link_status_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:605

hwrm_async_event_cmpl_link_status_change::type
__le16 type
Definition bnxt_hsi.h:596

hwrm_async_event_cmpl_link_status_change::event_id
__le16 event_id
Definition bnxt_hsi.h:601

hwrm_async_event_cmpl_llfc_pfc_change
Definition bnxt_hsi.h:1055

hwrm_async_event_cmpl_llfc_pfc_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:1066

hwrm_async_event_cmpl_llfc_pfc_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:1073

hwrm_async_event_cmpl_llfc_pfc_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:1072

hwrm_async_event_cmpl_llfc_pfc_change::event_id
__le16 event_id
Definition bnxt_hsi.h:1063

hwrm_async_event_cmpl_llfc_pfc_change::type
__le16 type
Definition bnxt_hsi.h:1056

hwrm_async_event_cmpl_llfc_pfc_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:1071

hwrm_async_event_cmpl_llfc_pfc_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:1067

hwrm_async_event_cmpl_pf_drvr_load
Definition bnxt_hsi.h:939

hwrm_async_event_cmpl_pf_drvr_load::type
__le16 type
Definition bnxt_hsi.h:940

hwrm_async_event_cmpl_pf_drvr_load::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:953

hwrm_async_event_cmpl_pf_drvr_load::event_data2
__le32 event_data2
Definition bnxt_hsi.h:948

hwrm_async_event_cmpl_pf_drvr_load::event_id
__le16 event_id
Definition bnxt_hsi.h:945

hwrm_async_event_cmpl_pf_drvr_load::event_data1
__le32 event_data1
Definition bnxt_hsi.h:955

hwrm_async_event_cmpl_pf_drvr_load::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:949

hwrm_async_event_cmpl_pf_drvr_load::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:954

hwrm_async_event_cmpl_pf_drvr_unload
Definition bnxt_hsi.h:915

hwrm_async_event_cmpl_pf_drvr_unload::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:929

hwrm_async_event_cmpl_pf_drvr_unload::event_id
__le16 event_id
Definition bnxt_hsi.h:921

hwrm_async_event_cmpl_pf_drvr_unload::type
__le16 type
Definition bnxt_hsi.h:916

hwrm_async_event_cmpl_pf_drvr_unload::event_data2
__le32 event_data2
Definition bnxt_hsi.h:924

hwrm_async_event_cmpl_pf_drvr_unload::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:925

hwrm_async_event_cmpl_pf_drvr_unload::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:930

hwrm_async_event_cmpl_pf_drvr_unload::event_data1
__le32 event_data1
Definition bnxt_hsi.h:931

hwrm_async_event_cmpl_pf_vf_comm_status_change
Definition bnxt_hsi.h:1009

hwrm_async_event_cmpl_pf_vf_comm_status_change::type
__le16 type
Definition bnxt_hsi.h:1010

hwrm_async_event_cmpl_pf_vf_comm_status_change::event_id
__le16 event_id
Definition bnxt_hsi.h:1015

hwrm_async_event_cmpl_pf_vf_comm_status_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:1024

hwrm_async_event_cmpl_pf_vf_comm_status_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:1023

hwrm_async_event_cmpl_pf_vf_comm_status_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:1018

hwrm_async_event_cmpl_pf_vf_comm_status_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:1019

hwrm_async_event_cmpl_pf_vf_comm_status_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:1025

hwrm_async_event_cmpl_port_conn_not_allowed
Definition bnxt_hsi.h:716

hwrm_async_event_cmpl_port_conn_not_allowed::event_data1
__le32 event_data1
Definition bnxt_hsi.h:732

hwrm_async_event_cmpl_port_conn_not_allowed::type
__le16 type
Definition bnxt_hsi.h:717

hwrm_async_event_cmpl_port_conn_not_allowed::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:731

hwrm_async_event_cmpl_port_conn_not_allowed::event_id
__le16 event_id
Definition bnxt_hsi.h:722

hwrm_async_event_cmpl_port_conn_not_allowed::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:730

hwrm_async_event_cmpl_port_conn_not_allowed::event_data2
__le32 event_data2
Definition bnxt_hsi.h:725

hwrm_async_event_cmpl_port_conn_not_allowed::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:726

hwrm_async_event_cmpl_port_phy_cfg_change
Definition bnxt_hsi.h:791

hwrm_async_event_cmpl_port_phy_cfg_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:800

hwrm_async_event_cmpl_port_phy_cfg_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:801

hwrm_async_event_cmpl_port_phy_cfg_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:805

hwrm_async_event_cmpl_port_phy_cfg_change::type
__le16 type
Definition bnxt_hsi.h:792

hwrm_async_event_cmpl_port_phy_cfg_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:806

hwrm_async_event_cmpl_port_phy_cfg_change::event_id
__le16 event_id
Definition bnxt_hsi.h:797

hwrm_async_event_cmpl_port_phy_cfg_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:807

hwrm_async_event_cmpl_reset_notify
Definition bnxt_hsi.h:816

hwrm_async_event_cmpl_reset_notify::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:831

hwrm_async_event_cmpl_reset_notify::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:826

hwrm_async_event_cmpl_reset_notify::event_data1
__le32 event_data1
Definition bnxt_hsi.h:832

hwrm_async_event_cmpl_reset_notify::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:830

hwrm_async_event_cmpl_reset_notify::event_data2
__le32 event_data2
Definition bnxt_hsi.h:825

hwrm_async_event_cmpl_reset_notify::event_id
__le16 event_id
Definition bnxt_hsi.h:822

hwrm_async_event_cmpl_reset_notify::type
__le16 type
Definition bnxt_hsi.h:817

hwrm_async_event_cmpl_vf_cfg_change
Definition bnxt_hsi.h:1030

hwrm_async_event_cmpl_vf_cfg_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:1040

hwrm_async_event_cmpl_vf_cfg_change::event_id
__le16 event_id
Definition bnxt_hsi.h:1036

hwrm_async_event_cmpl_vf_cfg_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:1044

hwrm_async_event_cmpl_vf_cfg_change::type
__le16 type
Definition bnxt_hsi.h:1031

hwrm_async_event_cmpl_vf_cfg_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:1045

hwrm_async_event_cmpl_vf_cfg_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:1039

hwrm_async_event_cmpl_vf_cfg_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:1046

hwrm_async_event_cmpl_vf_flr
Definition bnxt_hsi.h:963

hwrm_async_event_cmpl_vf_flr::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:978

hwrm_async_event_cmpl_vf_flr::event_data2
__le32 event_data2
Definition bnxt_hsi.h:972

hwrm_async_event_cmpl_vf_flr::type
__le16 type
Definition bnxt_hsi.h:964

hwrm_async_event_cmpl_vf_flr::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:977

hwrm_async_event_cmpl_vf_flr::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:973

hwrm_async_event_cmpl_vf_flr::event_data1
__le32 event_data1
Definition bnxt_hsi.h:979

hwrm_async_event_cmpl_vf_flr::event_id
__le16 event_id
Definition bnxt_hsi.h:969

hwrm_async_event_cmpl_vf_mac_addr_change
Definition bnxt_hsi.h:987

hwrm_async_event_cmpl_vf_mac_addr_change::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:997

hwrm_async_event_cmpl_vf_mac_addr_change::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:1001

hwrm_async_event_cmpl_vf_mac_addr_change::event_id
__le16 event_id
Definition bnxt_hsi.h:993

hwrm_async_event_cmpl_vf_mac_addr_change::type
__le16 type
Definition bnxt_hsi.h:988

hwrm_async_event_cmpl_vf_mac_addr_change::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:1002

hwrm_async_event_cmpl_vf_mac_addr_change::event_data2
__le32 event_data2
Definition bnxt_hsi.h:996

hwrm_async_event_cmpl_vf_mac_addr_change::event_data1
__le32 event_data1
Definition bnxt_hsi.h:1003

hwrm_async_event_cmpl
Definition bnxt_hsi.h:547

hwrm_async_event_cmpl::type
__le16 type
Definition bnxt_hsi.h:548

hwrm_async_event_cmpl::opaque_v
u8 opaque_v
Definition bnxt_hsi.h:581

hwrm_async_event_cmpl::event_id
__le16 event_id
Definition bnxt_hsi.h:553

hwrm_async_event_cmpl::event_data2
__le32 event_data2
Definition bnxt_hsi.h:580

hwrm_async_event_cmpl::event_data1
__le32 event_data1
Definition bnxt_hsi.h:587

hwrm_async_event_cmpl::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:586

hwrm_async_event_cmpl::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:585

hwrm_cfa_decap_filter_alloc_input
Definition bnxt_hsi.h:7658

hwrm_cfa_decap_filter_alloc_input::t_ovlan_vid
__be16 t_ovlan_vid
Definition bnxt_hsi.h:7707

hwrm_cfa_decap_filter_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7662

hwrm_cfa_decap_filter_alloc_input::ethertype
__be16 ethertype
Definition bnxt_hsi.h:7709

hwrm_cfa_decap_filter_alloc_input::src_macaddr
u8 src_macaddr[6]
Definition bnxt_hsi.h:7702

hwrm_cfa_decap_filter_alloc_input::dst_ipaddr
__be32 dst_ipaddr[4]
Definition bnxt_hsi.h:7723

hwrm_cfa_decap_filter_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7660

hwrm_cfa_decap_filter_alloc_input::unused_4
__le32 unused_4
Definition bnxt_hsi.h:7721

hwrm_cfa_decap_filter_alloc_input::tunnel_id
__be32 tunnel_id
Definition bnxt_hsi.h:7684

hwrm_cfa_decap_filter_alloc_input::t_ivlan_vid
__be16 t_ivlan_vid
Definition bnxt_hsi.h:7708

hwrm_cfa_decap_filter_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7661

hwrm_cfa_decap_filter_alloc_input::src_ipaddr
__be32 src_ipaddr[4]
Definition bnxt_hsi.h:7722

hwrm_cfa_decap_filter_alloc_input::dst_port
__be16 dst_port
Definition bnxt_hsi.h:7725

hwrm_cfa_decap_filter_alloc_input::ivlan_vid
__be16 ivlan_vid
Definition bnxt_hsi.h:7706

hwrm_cfa_decap_filter_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7659

hwrm_cfa_decap_filter_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7663

hwrm_cfa_decap_filter_alloc_input::dst_id
__le16 dst_id
Definition bnxt_hsi.h:7726

hwrm_cfa_decap_filter_alloc_input::ip_protocol
u8 ip_protocol
Definition bnxt_hsi.h:7715

hwrm_cfa_decap_filter_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:7664

hwrm_cfa_decap_filter_alloc_input::src_port
__be16 src_port
Definition bnxt_hsi.h:7724

hwrm_cfa_decap_filter_alloc_input::l2_ctxt_ref_id
__le16 l2_ctxt_ref_id
Definition bnxt_hsi.h:7727

hwrm_cfa_decap_filter_alloc_input::ovlan_vid
__be16 ovlan_vid
Definition bnxt_hsi.h:7705

hwrm_cfa_decap_filter_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:7666

hwrm_cfa_decap_filter_alloc_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:7685

hwrm_cfa_decap_filter_alloc_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:7700

hwrm_cfa_decap_filter_alloc_input::unused_1
__le16 unused_1
Definition bnxt_hsi.h:7701

hwrm_cfa_decap_filter_alloc_input::ip_addr_type
u8 ip_addr_type
Definition bnxt_hsi.h:7710

hwrm_cfa_decap_filter_alloc_input::unused_3
__le16 unused_3
Definition bnxt_hsi.h:7720

hwrm_cfa_decap_filter_alloc_input::unused_2
u8 unused_2[2]
Definition bnxt_hsi.h:7703

hwrm_cfa_decap_filter_alloc_input::dst_macaddr
u8 dst_macaddr[6]
Definition bnxt_hsi.h:7704

hwrm_cfa_decap_filter_alloc_output
Definition bnxt_hsi.h:7731

hwrm_cfa_decap_filter_alloc_output::decap_filter_id
__le32 decap_filter_id
Definition bnxt_hsi.h:7736

hwrm_cfa_decap_filter_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7734

hwrm_cfa_decap_filter_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7735

hwrm_cfa_decap_filter_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7733

hwrm_cfa_decap_filter_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:7737

hwrm_cfa_decap_filter_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:7738

hwrm_cfa_decap_filter_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7732

hwrm_cfa_decap_filter_free_input
Definition bnxt_hsi.h:7742

hwrm_cfa_decap_filter_free_input::decap_filter_id
__le32 decap_filter_id
Definition bnxt_hsi.h:7748

hwrm_cfa_decap_filter_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7746

hwrm_cfa_decap_filter_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7743

hwrm_cfa_decap_filter_free_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:7749

hwrm_cfa_decap_filter_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7745

hwrm_cfa_decap_filter_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7744

hwrm_cfa_decap_filter_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7747

hwrm_cfa_decap_filter_free_output
Definition bnxt_hsi.h:7753

hwrm_cfa_decap_filter_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7754

hwrm_cfa_decap_filter_free_output::valid
u8 valid
Definition bnxt_hsi.h:7759

hwrm_cfa_decap_filter_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7757

hwrm_cfa_decap_filter_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7758

hwrm_cfa_decap_filter_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7756

hwrm_cfa_decap_filter_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7755

hwrm_cfa_em_flow_alloc_input
Definition bnxt_hsi.h:7226

hwrm_cfa_em_flow_alloc_input::src_port
__be16 src_port
Definition bnxt_hsi.h:7301

hwrm_cfa_em_flow_alloc_input::ivlan_vid
__le16 ivlan_vid
Definition bnxt_hsi.h:7286

hwrm_cfa_em_flow_alloc_input::ip_addr_type
u8 ip_addr_type
Definition bnxt_hsi.h:7288

hwrm_cfa_em_flow_alloc_input::src_ipaddr
__be32 src_ipaddr[4]
Definition bnxt_hsi.h:7299

hwrm_cfa_em_flow_alloc_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:7263

hwrm_cfa_em_flow_alloc_input::dst_id
__le16 dst_id
Definition bnxt_hsi.h:7303

hwrm_cfa_em_flow_alloc_input::encap_record_id
__le32 encap_record_id
Definition bnxt_hsi.h:7305

hwrm_cfa_em_flow_alloc_input::dst_port
__be16 dst_port
Definition bnxt_hsi.h:7302

hwrm_cfa_em_flow_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:7243

hwrm_cfa_em_flow_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7230

hwrm_cfa_em_flow_alloc_input::unused_1
u8 unused_1[2]
Definition bnxt_hsi.h:7298

hwrm_cfa_em_flow_alloc_input::tunnel_id
__le32 tunnel_id
Definition bnxt_hsi.h:7279

hwrm_cfa_em_flow_alloc_input::ovlan_vid
__le16 ovlan_vid
Definition bnxt_hsi.h:7285

hwrm_cfa_em_flow_alloc_input::src_macaddr
u8 src_macaddr[6]
Definition bnxt_hsi.h:7280

hwrm_cfa_em_flow_alloc_input::unused_2
u8 unused_2[4]
Definition bnxt_hsi.h:7306

hwrm_cfa_em_flow_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:7232

hwrm_cfa_em_flow_alloc_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:7278

hwrm_cfa_em_flow_alloc_input::ethertype
__be16 ethertype
Definition bnxt_hsi.h:7287

hwrm_cfa_em_flow_alloc_input::ip_protocol
u8 ip_protocol
Definition bnxt_hsi.h:7293

hwrm_cfa_em_flow_alloc_input::dst_ipaddr
__be32 dst_ipaddr[4]
Definition bnxt_hsi.h:7300

hwrm_cfa_em_flow_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7228

hwrm_cfa_em_flow_alloc_input::dst_macaddr
u8 dst_macaddr[6]
Definition bnxt_hsi.h:7284

hwrm_cfa_em_flow_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7227

hwrm_cfa_em_flow_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7231

hwrm_cfa_em_flow_alloc_input::meter_instance_id
__le16 meter_instance_id
Definition bnxt_hsi.h:7281

hwrm_cfa_em_flow_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7229

hwrm_cfa_em_flow_alloc_input::l2_filter_id
__le64 l2_filter_id
Definition bnxt_hsi.h:7262

hwrm_cfa_em_flow_alloc_input::mirror_vnic_id
__le16 mirror_vnic_id
Definition bnxt_hsi.h:7304

hwrm_cfa_em_flow_alloc_output
Definition bnxt_hsi.h:7310

hwrm_cfa_em_flow_alloc_output::flow_id
__le32 flow_id
Definition bnxt_hsi.h:7316

hwrm_cfa_em_flow_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7313

hwrm_cfa_em_flow_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:7317

hwrm_cfa_em_flow_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7314

hwrm_cfa_em_flow_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7312

hwrm_cfa_em_flow_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7311

hwrm_cfa_em_flow_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:7318

hwrm_cfa_em_flow_alloc_output::em_filter_id
__le64 em_filter_id
Definition bnxt_hsi.h:7315

hwrm_cfa_em_flow_cfg_input
Definition bnxt_hsi.h:7342

hwrm_cfa_em_flow_cfg_input::new_meter_instance_id
__le16 new_meter_instance_id
Definition bnxt_hsi.h:7356

hwrm_cfa_em_flow_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7346

hwrm_cfa_em_flow_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7343

hwrm_cfa_em_flow_cfg_input::unused_1
u8 unused_1[6]
Definition bnxt_hsi.h:7359

hwrm_cfa_em_flow_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7347

hwrm_cfa_em_flow_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7345

hwrm_cfa_em_flow_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:7348

hwrm_cfa_em_flow_cfg_input::em_filter_id
__le64 em_filter_id
Definition bnxt_hsi.h:7353

hwrm_cfa_em_flow_cfg_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:7352

hwrm_cfa_em_flow_cfg_input::new_mirror_vnic_id
__le32 new_mirror_vnic_id
Definition bnxt_hsi.h:7355

hwrm_cfa_em_flow_cfg_input::new_dst_id
__le32 new_dst_id
Definition bnxt_hsi.h:7354

hwrm_cfa_em_flow_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7344

hwrm_cfa_em_flow_cfg_output
Definition bnxt_hsi.h:7363

hwrm_cfa_em_flow_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7364

hwrm_cfa_em_flow_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7367

hwrm_cfa_em_flow_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7365

hwrm_cfa_em_flow_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7368

hwrm_cfa_em_flow_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:7369

hwrm_cfa_em_flow_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7366

hwrm_cfa_em_flow_free_input
Definition bnxt_hsi.h:7322

hwrm_cfa_em_flow_free_input::em_filter_id
__le64 em_filter_id
Definition bnxt_hsi.h:7328

hwrm_cfa_em_flow_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7325

hwrm_cfa_em_flow_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7327

hwrm_cfa_em_flow_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7323

hwrm_cfa_em_flow_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7324

hwrm_cfa_em_flow_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7326

hwrm_cfa_em_flow_free_output
Definition bnxt_hsi.h:7332

hwrm_cfa_em_flow_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7336

hwrm_cfa_em_flow_free_output::valid
u8 valid
Definition bnxt_hsi.h:7338

hwrm_cfa_em_flow_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7333

hwrm_cfa_em_flow_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7335

hwrm_cfa_em_flow_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7334

hwrm_cfa_em_flow_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7337

hwrm_cfa_encap_data_vxlan
Definition bnxt_hsi.h:6992

hwrm_cfa_encap_data_vxlan::unused_0
__le16 unused_0
Definition bnxt_hsi.h:6994

hwrm_cfa_encap_data_vxlan::hdr_rsvd0
u8 hdr_rsvd0[3]
Definition bnxt_hsi.h:7010

hwrm_cfa_encap_data_vxlan::ovlan_tci
__be16 ovlan_tci
Definition bnxt_hsi.h:6999

hwrm_cfa_encap_data_vxlan::l3
__le32 l3[10]
Definition bnxt_hsi.h:7002

hwrm_cfa_encap_data_vxlan::vni
__be32 vni
Definition bnxt_hsi.h:7009

hwrm_cfa_encap_data_vxlan::hdr_flags
u8 hdr_flags
Definition bnxt_hsi.h:7012

hwrm_cfa_encap_data_vxlan::ivlan_tpid
__be16 ivlan_tpid
Definition bnxt_hsi.h:7000

hwrm_cfa_encap_data_vxlan::unused
u8 unused[3]
Definition bnxt_hsi.h:7013

hwrm_cfa_encap_data_vxlan::dst_port
__be16 dst_port
Definition bnxt_hsi.h:7008

hwrm_cfa_encap_data_vxlan::dst_mac_addr
u8 dst_mac_addr[6]
Definition bnxt_hsi.h:6995

hwrm_cfa_encap_data_vxlan::num_vlan_tags
u8 num_vlan_tags
Definition bnxt_hsi.h:6996

hwrm_cfa_encap_data_vxlan::src_port
__be16 src_port
Definition bnxt_hsi.h:7007

hwrm_cfa_encap_data_vxlan::ovlan_tpid
__be16 ovlan_tpid
Definition bnxt_hsi.h:6998

hwrm_cfa_encap_data_vxlan::unused_1
u8 unused_1
Definition bnxt_hsi.h:6997

hwrm_cfa_encap_data_vxlan::src_mac_addr
u8 src_mac_addr[6]
Definition bnxt_hsi.h:6993

hwrm_cfa_encap_data_vxlan::hdr_rsvd1
u8 hdr_rsvd1
Definition bnxt_hsi.h:7011

hwrm_cfa_encap_data_vxlan::ivlan_tci
__be16 ivlan_tci
Definition bnxt_hsi.h:7001

hwrm_cfa_encap_record_alloc_input
Definition bnxt_hsi.h:7017

hwrm_cfa_encap_record_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7019

hwrm_cfa_encap_record_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:7023

hwrm_cfa_encap_record_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7021

hwrm_cfa_encap_record_alloc_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:7038

hwrm_cfa_encap_record_alloc_input::encap_data
__le32 encap_data[20]
Definition bnxt_hsi.h:7039

hwrm_cfa_encap_record_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7020

hwrm_cfa_encap_record_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7022

hwrm_cfa_encap_record_alloc_input::encap_type
u8 encap_type
Definition bnxt_hsi.h:7025

hwrm_cfa_encap_record_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7018

hwrm_cfa_encap_record_alloc_output
Definition bnxt_hsi.h:7043

hwrm_cfa_encap_record_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7044

hwrm_cfa_encap_record_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7045

hwrm_cfa_encap_record_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:7049

hwrm_cfa_encap_record_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7047

hwrm_cfa_encap_record_alloc_output::encap_record_id
__le32 encap_record_id
Definition bnxt_hsi.h:7048

hwrm_cfa_encap_record_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:7050

hwrm_cfa_encap_record_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7046

hwrm_cfa_encap_record_free_input
Definition bnxt_hsi.h:7054

hwrm_cfa_encap_record_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7059

hwrm_cfa_encap_record_free_input::encap_record_id
__le32 encap_record_id
Definition bnxt_hsi.h:7060

hwrm_cfa_encap_record_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7057

hwrm_cfa_encap_record_free_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:7061

hwrm_cfa_encap_record_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7056

hwrm_cfa_encap_record_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7058

hwrm_cfa_encap_record_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7055

hwrm_cfa_encap_record_free_output
Definition bnxt_hsi.h:7065

hwrm_cfa_encap_record_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7069

hwrm_cfa_encap_record_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7068

hwrm_cfa_encap_record_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7067

hwrm_cfa_encap_record_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7066

hwrm_cfa_encap_record_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7070

hwrm_cfa_encap_record_free_output::valid
u8 valid
Definition bnxt_hsi.h:7071

hwrm_cfa_flow_aging_cfg_input
Definition bnxt_hsi.h:8024

hwrm_cfa_flow_aging_cfg_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:8039

hwrm_cfa_flow_aging_cfg_input::tcp_fin_timer
__le32 tcp_fin_timer
Definition bnxt_hsi.h:8041

hwrm_cfa_flow_aging_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8029

hwrm_cfa_flow_aging_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8027

hwrm_cfa_flow_aging_cfg_input::flags
u8 flags
Definition bnxt_hsi.h:8034

hwrm_cfa_flow_aging_cfg_input::tcp_flow_timer
__le32 tcp_flow_timer
Definition bnxt_hsi.h:8040

hwrm_cfa_flow_aging_cfg_input::enables
__le16 enables
Definition bnxt_hsi.h:8030

hwrm_cfa_flow_aging_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8026

hwrm_cfa_flow_aging_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8028

hwrm_cfa_flow_aging_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8025

hwrm_cfa_flow_aging_cfg_input::udp_flow_timer
__le32 udp_flow_timer
Definition bnxt_hsi.h:8042

hwrm_cfa_flow_aging_cfg_output
Definition bnxt_hsi.h:8046

hwrm_cfa_flow_aging_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8051

hwrm_cfa_flow_aging_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8048

hwrm_cfa_flow_aging_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8047

hwrm_cfa_flow_aging_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:8052

hwrm_cfa_flow_aging_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8049

hwrm_cfa_flow_aging_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8050

hwrm_cfa_flow_aging_qcaps_input
Definition bnxt_hsi.h:8084

hwrm_cfa_flow_aging_qcaps_input::flags
u8 flags
Definition bnxt_hsi.h:8090

hwrm_cfa_flow_aging_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8089

hwrm_cfa_flow_aging_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8088

hwrm_cfa_flow_aging_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8087

hwrm_cfa_flow_aging_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8086

hwrm_cfa_flow_aging_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8085

hwrm_cfa_flow_aging_qcaps_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8095

hwrm_cfa_flow_aging_qcaps_output
Definition bnxt_hsi.h:8099

hwrm_cfa_flow_aging_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8103

hwrm_cfa_flow_aging_qcaps_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8108

hwrm_cfa_flow_aging_qcaps_output::max_aging_flows
__le32 max_aging_flows
Definition bnxt_hsi.h:8107

hwrm_cfa_flow_aging_qcaps_output::max_tcp_fin_timer
__le32 max_tcp_fin_timer
Definition bnxt_hsi.h:8105

hwrm_cfa_flow_aging_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:8109

hwrm_cfa_flow_aging_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8102

hwrm_cfa_flow_aging_qcaps_output::max_tcp_flow_timer
__le32 max_tcp_flow_timer
Definition bnxt_hsi.h:8104

hwrm_cfa_flow_aging_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8101

hwrm_cfa_flow_aging_qcaps_output::max_udp_flow_timer
__le32 max_udp_flow_timer
Definition bnxt_hsi.h:8106

hwrm_cfa_flow_aging_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8100

hwrm_cfa_flow_aging_qcfg_input
Definition bnxt_hsi.h:8056

hwrm_cfa_flow_aging_qcfg_input::flags
u8 flags
Definition bnxt_hsi.h:8062

hwrm_cfa_flow_aging_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8058

hwrm_cfa_flow_aging_qcfg_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8067

hwrm_cfa_flow_aging_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8060

hwrm_cfa_flow_aging_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8061

hwrm_cfa_flow_aging_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8057

hwrm_cfa_flow_aging_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8059

hwrm_cfa_flow_aging_qcfg_output
Definition bnxt_hsi.h:8071

hwrm_cfa_flow_aging_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8073

hwrm_cfa_flow_aging_qcfg_output::udp_flow_timer
__le32 udp_flow_timer
Definition bnxt_hsi.h:8078

hwrm_cfa_flow_aging_qcfg_output::tcp_flow_timer
__le32 tcp_flow_timer
Definition bnxt_hsi.h:8076

hwrm_cfa_flow_aging_qcfg_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:8079

hwrm_cfa_flow_aging_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8074

hwrm_cfa_flow_aging_qcfg_output::tcp_fin_timer
__le32 tcp_fin_timer
Definition bnxt_hsi.h:8077

hwrm_cfa_flow_aging_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8075

hwrm_cfa_flow_aging_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:8080

hwrm_cfa_flow_aging_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8072

hwrm_cfa_flow_aging_timer_reset_input
Definition bnxt_hsi.h:8002

hwrm_cfa_flow_aging_timer_reset_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8006

hwrm_cfa_flow_aging_timer_reset_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8007

hwrm_cfa_flow_aging_timer_reset_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8005

hwrm_cfa_flow_aging_timer_reset_input::ext_flow_handle
__le64 ext_flow_handle
Definition bnxt_hsi.h:8010

hwrm_cfa_flow_aging_timer_reset_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8003

hwrm_cfa_flow_aging_timer_reset_input::flow_handle
__le16 flow_handle
Definition bnxt_hsi.h:8008

hwrm_cfa_flow_aging_timer_reset_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8004

hwrm_cfa_flow_aging_timer_reset_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:8009

hwrm_cfa_flow_aging_timer_reset_output
Definition bnxt_hsi.h:8014

hwrm_cfa_flow_aging_timer_reset_output::valid
u8 valid
Definition bnxt_hsi.h:8020

hwrm_cfa_flow_aging_timer_reset_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8019

hwrm_cfa_flow_aging_timer_reset_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8015

hwrm_cfa_flow_aging_timer_reset_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8016

hwrm_cfa_flow_aging_timer_reset_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8018

hwrm_cfa_flow_aging_timer_reset_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8017

hwrm_cfa_flow_alloc_input
Definition bnxt_hsi.h:7763

hwrm_cfa_flow_alloc_input::nat_port
__be16 nat_port
Definition bnxt_hsi.h:7821

hwrm_cfa_flow_alloc_input::ip_dst_mask_len
u8 ip_dst_mask_len
Definition bnxt_hsi.h:7811

hwrm_cfa_flow_alloc_input::l2_rewrite_dmac
__be16 l2_rewrite_dmac[3]
Definition bnxt_hsi.h:7820

hwrm_cfa_flow_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7764

hwrm_cfa_flow_alloc_input::ref_flow_handle
__le16 ref_flow_handle
Definition bnxt_hsi.h:7805

hwrm_cfa_flow_alloc_input::l2_rewrite_vlan_tpid
__be16 l2_rewrite_vlan_tpid
Definition bnxt_hsi.h:7802

hwrm_cfa_flow_alloc_input::l4_src_port
__be16 l4_src_port
Definition bnxt_hsi.h:7815

hwrm_cfa_flow_alloc_input::act_meter_id
__le16 act_meter_id
Definition bnxt_hsi.h:7804

hwrm_cfa_flow_alloc_input::l2_rewrite_vlan_tci
__be16 l2_rewrite_vlan_tci
Definition bnxt_hsi.h:7803

hwrm_cfa_flow_alloc_input::inner_vlan_tci
__be16 inner_vlan_tci
Definition bnxt_hsi.h:7809

hwrm_cfa_flow_alloc_input::nat_ip_address
__be32 nat_ip_address[4]
Definition bnxt_hsi.h:7819

hwrm_cfa_flow_alloc_input::ip_src_mask_len
u8 ip_src_mask_len
Definition bnxt_hsi.h:7812

hwrm_cfa_flow_alloc_input::src_fid
__le16 src_fid
Definition bnxt_hsi.h:7786

hwrm_cfa_flow_alloc_input::dst_fid
__le16 dst_fid
Definition bnxt_hsi.h:7801

hwrm_cfa_flow_alloc_input::ip_proto
u8 ip_proto
Definition bnxt_hsi.h:7823

hwrm_cfa_flow_alloc_input::action_flags
__le16 action_flags
Definition bnxt_hsi.h:7788

hwrm_cfa_flow_alloc_input::l2_rewrite_smac
__be16 l2_rewrite_smac[3]
Definition bnxt_hsi.h:7822

hwrm_cfa_flow_alloc_input::ip_src
__be32 ip_src[4]
Definition bnxt_hsi.h:7814

hwrm_cfa_flow_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7768

hwrm_cfa_flow_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7765

hwrm_cfa_flow_alloc_input::ethertype
__be16 ethertype
Definition bnxt_hsi.h:7806

hwrm_cfa_flow_alloc_input::flags
__le16 flags
Definition bnxt_hsi.h:7769

hwrm_cfa_flow_alloc_input::l4_dst_port_mask
__be16 l4_dst_port_mask
Definition bnxt_hsi.h:7818

hwrm_cfa_flow_alloc_input::dmac
__be16 dmac[3]
Definition bnxt_hsi.h:7808

hwrm_cfa_flow_alloc_input::smac
__be16 smac[3]
Definition bnxt_hsi.h:7810

hwrm_cfa_flow_alloc_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:7824

hwrm_cfa_flow_alloc_input::ip_dst
__be32 ip_dst[4]
Definition bnxt_hsi.h:7813

hwrm_cfa_flow_alloc_input::l4_src_port_mask
__be16 l4_src_port_mask
Definition bnxt_hsi.h:7816

hwrm_cfa_flow_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7767

hwrm_cfa_flow_alloc_input::outer_vlan_tci
__be16 outer_vlan_tci
Definition bnxt_hsi.h:7807

hwrm_cfa_flow_alloc_input::tunnel_handle
__le32 tunnel_handle
Definition bnxt_hsi.h:7787

hwrm_cfa_flow_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7766

hwrm_cfa_flow_alloc_input::l4_dst_port
__be16 l4_dst_port
Definition bnxt_hsi.h:7817

hwrm_cfa_flow_alloc_output
Definition bnxt_hsi.h:7842

hwrm_cfa_flow_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7844

hwrm_cfa_flow_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7843

hwrm_cfa_flow_alloc_output::flow_id
__le32 flow_id
Definition bnxt_hsi.h:7849

hwrm_cfa_flow_alloc_output::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:7848

hwrm_cfa_flow_alloc_output::ext_flow_handle
__le64 ext_flow_handle
Definition bnxt_hsi.h:7850

hwrm_cfa_flow_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7846

hwrm_cfa_flow_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7845

hwrm_cfa_flow_alloc_output::flow_handle
__le16 flow_handle
Definition bnxt_hsi.h:7847

hwrm_cfa_flow_alloc_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:7851

hwrm_cfa_flow_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:7852

hwrm_cfa_flow_flush_input
Definition bnxt_hsi.h:7920

hwrm_cfa_flow_flush_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7923

hwrm_cfa_flow_flush_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7921

hwrm_cfa_flow_flush_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:7927

hwrm_cfa_flow_flush_input::flags
__le32 flags
Definition bnxt_hsi.h:7926

hwrm_cfa_flow_flush_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7925

hwrm_cfa_flow_flush_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7924

hwrm_cfa_flow_flush_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7922

hwrm_cfa_flow_flush_output
Definition bnxt_hsi.h:7931

hwrm_cfa_flow_flush_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7936

hwrm_cfa_flow_flush_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7933

hwrm_cfa_flow_flush_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7935

hwrm_cfa_flow_flush_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7934

hwrm_cfa_flow_flush_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7932

hwrm_cfa_flow_flush_output::valid
u8 valid
Definition bnxt_hsi.h:7937

hwrm_cfa_flow_free_input
Definition bnxt_hsi.h:7856

hwrm_cfa_flow_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7860

hwrm_cfa_flow_free_input::ext_flow_handle
__le64 ext_flow_handle
Definition bnxt_hsi.h:7864

hwrm_cfa_flow_free_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:7863

hwrm_cfa_flow_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7858

hwrm_cfa_flow_free_input::flow_handle
__le16 flow_handle
Definition bnxt_hsi.h:7862

hwrm_cfa_flow_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7859

hwrm_cfa_flow_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7861

hwrm_cfa_flow_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7857

hwrm_cfa_flow_free_output
Definition bnxt_hsi.h:7868

hwrm_cfa_flow_free_output::packet
__le64 packet
Definition bnxt_hsi.h:7873

hwrm_cfa_flow_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7871

hwrm_cfa_flow_free_output::valid
u8 valid
Definition bnxt_hsi.h:7876

hwrm_cfa_flow_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7872

hwrm_cfa_flow_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7870

hwrm_cfa_flow_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7869

hwrm_cfa_flow_free_output::byte
__le64 byte
Definition bnxt_hsi.h:7874

hwrm_cfa_flow_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7875

hwrm_cfa_flow_info_input
Definition bnxt_hsi.h:7880

hwrm_cfa_flow_info_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7884

hwrm_cfa_flow_info_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7882

hwrm_cfa_flow_info_input::flow_handle
__le16 flow_handle
Definition bnxt_hsi.h:7886

hwrm_cfa_flow_info_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7883

hwrm_cfa_flow_info_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7881

hwrm_cfa_flow_info_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:7893

hwrm_cfa_flow_info_input::ext_flow_handle
__le64 ext_flow_handle
Definition bnxt_hsi.h:7894

hwrm_cfa_flow_info_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7885

hwrm_cfa_flow_info_output
Definition bnxt_hsi.h:7898

hwrm_cfa_flow_info_output::profile
u8 profile
Definition bnxt_hsi.h:7904

hwrm_cfa_flow_info_output::flow_timer
__le16 flow_timer
Definition bnxt_hsi.h:7914

hwrm_cfa_flow_info_output::tcam_info
__le64 tcam_info
Definition bnxt_hsi.h:7909

hwrm_cfa_flow_info_output::src_fid
__le16 src_fid
Definition bnxt_hsi.h:7905

hwrm_cfa_flow_info_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7899

hwrm_cfa_flow_info_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7900

hwrm_cfa_flow_info_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7902

hwrm_cfa_flow_info_output::em_info
__le64 em_info
Definition bnxt_hsi.h:7908

hwrm_cfa_flow_info_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:7915

hwrm_cfa_flow_info_output::tunnel_handle
__le32 tunnel_handle
Definition bnxt_hsi.h:7913

hwrm_cfa_flow_info_output::flags
u8 flags
Definition bnxt_hsi.h:7903

hwrm_cfa_flow_info_output::ar_id
__le16 ar_id
Definition bnxt_hsi.h:7911

hwrm_cfa_flow_info_output::valid
u8 valid
Definition bnxt_hsi.h:7916

hwrm_cfa_flow_info_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7901

hwrm_cfa_flow_info_output::dst_fid
__le16 dst_fid
Definition bnxt_hsi.h:7906

hwrm_cfa_flow_info_output::flow_handle
__le16 flow_handle
Definition bnxt_hsi.h:7912

hwrm_cfa_flow_info_output::l2_ctxt_id
__le16 l2_ctxt_id
Definition bnxt_hsi.h:7907

hwrm_cfa_flow_info_output::vfp_tcam_info
__le64 vfp_tcam_info
Definition bnxt_hsi.h:7910

hwrm_cfa_flow_stats_input
Definition bnxt_hsi.h:7941

hwrm_cfa_flow_stats_input::flow_id_1
__le32 flow_id_1
Definition bnxt_hsi.h:7960

hwrm_cfa_flow_stats_input::flow_handle_7
__le16 flow_handle_7
Definition bnxt_hsi.h:7955

hwrm_cfa_flow_stats_input::flow_handle_0
__le16 flow_handle_0
Definition bnxt_hsi.h:7948

hwrm_cfa_flow_stats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7944

hwrm_cfa_flow_stats_input::flow_handle_3
__le16 flow_handle_3
Definition bnxt_hsi.h:7951

hwrm_cfa_flow_stats_input::num_flows
__le16 num_flows
Definition bnxt_hsi.h:7947

hwrm_cfa_flow_stats_input::flow_id_9
__le32 flow_id_9
Definition bnxt_hsi.h:7968

hwrm_cfa_flow_stats_input::flow_handle_1
__le16 flow_handle_1
Definition bnxt_hsi.h:7949

hwrm_cfa_flow_stats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7942

hwrm_cfa_flow_stats_input::flow_handle_9
__le16 flow_handle_9
Definition bnxt_hsi.h:7957

hwrm_cfa_flow_stats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7943

hwrm_cfa_flow_stats_input::flow_handle_6
__le16 flow_handle_6
Definition bnxt_hsi.h:7954

hwrm_cfa_flow_stats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7945

hwrm_cfa_flow_stats_input::flow_id_0
__le32 flow_id_0
Definition bnxt_hsi.h:7959

hwrm_cfa_flow_stats_input::flow_handle_2
__le16 flow_handle_2
Definition bnxt_hsi.h:7950

hwrm_cfa_flow_stats_input::flow_handle_5
__le16 flow_handle_5
Definition bnxt_hsi.h:7953

hwrm_cfa_flow_stats_input::flow_handle_8
__le16 flow_handle_8
Definition bnxt_hsi.h:7956

hwrm_cfa_flow_stats_input::flow_id_5
__le32 flow_id_5
Definition bnxt_hsi.h:7964

hwrm_cfa_flow_stats_input::flow_id_7
__le32 flow_id_7
Definition bnxt_hsi.h:7966

hwrm_cfa_flow_stats_input::flow_id_6
__le32 flow_id_6
Definition bnxt_hsi.h:7965

hwrm_cfa_flow_stats_input::flow_handle_4
__le16 flow_handle_4
Definition bnxt_hsi.h:7952

hwrm_cfa_flow_stats_input::flow_id_2
__le32 flow_id_2
Definition bnxt_hsi.h:7961

hwrm_cfa_flow_stats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7946

hwrm_cfa_flow_stats_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:7958

hwrm_cfa_flow_stats_input::flow_id_4
__le32 flow_id_4
Definition bnxt_hsi.h:7963

hwrm_cfa_flow_stats_input::flow_id_3
__le32 flow_id_3
Definition bnxt_hsi.h:7962

hwrm_cfa_flow_stats_input::flow_id_8
__le32 flow_id_8
Definition bnxt_hsi.h:7967

hwrm_cfa_flow_stats_output
Definition bnxt_hsi.h:7972

hwrm_cfa_flow_stats_output::packet_0
__le64 packet_0
Definition bnxt_hsi.h:7977

hwrm_cfa_flow_stats_output::byte_9
__le64 byte_9
Definition bnxt_hsi.h:7996

hwrm_cfa_flow_stats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7976

hwrm_cfa_flow_stats_output::packet_5
__le64 packet_5
Definition bnxt_hsi.h:7982

hwrm_cfa_flow_stats_output::packet_6
__le64 packet_6
Definition bnxt_hsi.h:7983

hwrm_cfa_flow_stats_output::packet_7
__le64 packet_7
Definition bnxt_hsi.h:7984

hwrm_cfa_flow_stats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7974

hwrm_cfa_flow_stats_output::packet_2
__le64 packet_2
Definition bnxt_hsi.h:7979

hwrm_cfa_flow_stats_output::packet_9
__le64 packet_9
Definition bnxt_hsi.h:7986

hwrm_cfa_flow_stats_output::packet_4
__le64 packet_4
Definition bnxt_hsi.h:7981

hwrm_cfa_flow_stats_output::valid
u8 valid
Definition bnxt_hsi.h:7998

hwrm_cfa_flow_stats_output::byte_0
__le64 byte_0
Definition bnxt_hsi.h:7987

hwrm_cfa_flow_stats_output::byte_2
__le64 byte_2
Definition bnxt_hsi.h:7989

hwrm_cfa_flow_stats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7975

hwrm_cfa_flow_stats_output::packet_3
__le64 packet_3
Definition bnxt_hsi.h:7980

hwrm_cfa_flow_stats_output::packet_8
__le64 packet_8
Definition bnxt_hsi.h:7985

hwrm_cfa_flow_stats_output::byte_7
__le64 byte_7
Definition bnxt_hsi.h:7994

hwrm_cfa_flow_stats_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7997

hwrm_cfa_flow_stats_output::byte_1
__le64 byte_1
Definition bnxt_hsi.h:7988

hwrm_cfa_flow_stats_output::byte_8
__le64 byte_8
Definition bnxt_hsi.h:7995

hwrm_cfa_flow_stats_output::byte_4
__le64 byte_4
Definition bnxt_hsi.h:7991

hwrm_cfa_flow_stats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7973

hwrm_cfa_flow_stats_output::byte_5
__le64 byte_5
Definition bnxt_hsi.h:7992

hwrm_cfa_flow_stats_output::packet_1
__le64 packet_1
Definition bnxt_hsi.h:7978

hwrm_cfa_flow_stats_output::byte_3
__le64 byte_3
Definition bnxt_hsi.h:7990

hwrm_cfa_flow_stats_output::byte_6
__le64 byte_6
Definition bnxt_hsi.h:7993

hwrm_cfa_l2_filter_alloc_input
Definition bnxt_hsi.h:6508

hwrm_cfa_l2_filter_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6509

hwrm_cfa_l2_filter_alloc_input::t_l2_addr_mask
u8 t_l2_addr_mask[6]
Definition bnxt_hsi.h:6556

hwrm_cfa_l2_filter_alloc_input::src_type
u8 src_type
Definition bnxt_hsi.h:6561

hwrm_cfa_l2_filter_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:6528

hwrm_cfa_l2_filter_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:6514

hwrm_cfa_l2_filter_alloc_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:6547

hwrm_cfa_l2_filter_alloc_input::unused_2
u8 unused_2[2]
Definition bnxt_hsi.h:6555

hwrm_cfa_l2_filter_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6513

hwrm_cfa_l2_filter_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6512

hwrm_cfa_l2_filter_alloc_input::t_l2_addr
u8 t_l2_addr[6]
Definition bnxt_hsi.h:6554

hwrm_cfa_l2_filter_alloc_input::unused_3
u8 unused_3
Definition bnxt_hsi.h:6571

hwrm_cfa_l2_filter_alloc_input::t_l2_ovlan
__le16 t_l2_ovlan
Definition bnxt_hsi.h:6557

hwrm_cfa_l2_filter_alloc_input::dst_id
__le16 dst_id
Definition bnxt_hsi.h:6589

hwrm_cfa_l2_filter_alloc_input::l2_ovlan
__le16 l2_ovlan
Definition bnxt_hsi.h:6549

hwrm_cfa_l2_filter_alloc_input::l2_ovlan_mask
__le16 l2_ovlan_mask
Definition bnxt_hsi.h:6550

hwrm_cfa_l2_filter_alloc_input::l2_addr
u8 l2_addr[6]
Definition bnxt_hsi.h:6546

hwrm_cfa_l2_filter_alloc_input::unused_5
u8 unused_5
Definition bnxt_hsi.h:6598

hwrm_cfa_l2_filter_alloc_input::t_l2_ivlan_mask
__le16 t_l2_ivlan_mask
Definition bnxt_hsi.h:6560

hwrm_cfa_l2_filter_alloc_input::t_l2_ovlan_mask
__le16 t_l2_ovlan_mask
Definition bnxt_hsi.h:6558

hwrm_cfa_l2_filter_alloc_input::pri_hint
u8 pri_hint
Definition bnxt_hsi.h:6591

hwrm_cfa_l2_filter_alloc_input::src_id
__le32 src_id
Definition bnxt_hsi.h:6572

hwrm_cfa_l2_filter_alloc_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:6573

hwrm_cfa_l2_filter_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6510

hwrm_cfa_l2_filter_alloc_input::unused_1
u8 unused_1[2]
Definition bnxt_hsi.h:6553

hwrm_cfa_l2_filter_alloc_input::l2_addr_mask
u8 l2_addr_mask[6]
Definition bnxt_hsi.h:6548

hwrm_cfa_l2_filter_alloc_input::unused_4
u8 unused_4
Definition bnxt_hsi.h:6588

hwrm_cfa_l2_filter_alloc_input::unused_6
__le32 unused_6
Definition bnxt_hsi.h:6599

hwrm_cfa_l2_filter_alloc_input::l2_ivlan
__le16 l2_ivlan
Definition bnxt_hsi.h:6551

hwrm_cfa_l2_filter_alloc_input::l2_filter_id_hint
__le64 l2_filter_id_hint
Definition bnxt_hsi.h:6600

hwrm_cfa_l2_filter_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6511

hwrm_cfa_l2_filter_alloc_input::mirror_vnic_id
__le16 mirror_vnic_id
Definition bnxt_hsi.h:6590

hwrm_cfa_l2_filter_alloc_input::t_l2_ivlan
__le16 t_l2_ivlan
Definition bnxt_hsi.h:6559

hwrm_cfa_l2_filter_alloc_input::l2_ivlan_mask
__le16 l2_ivlan_mask
Definition bnxt_hsi.h:6552

hwrm_cfa_l2_filter_alloc_output
Definition bnxt_hsi.h:6604

hwrm_cfa_l2_filter_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6606

hwrm_cfa_l2_filter_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:6612

hwrm_cfa_l2_filter_alloc_output::flow_id
__le32 flow_id
Definition bnxt_hsi.h:6610

hwrm_cfa_l2_filter_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6607

hwrm_cfa_l2_filter_alloc_output::l2_filter_id
__le64 l2_filter_id
Definition bnxt_hsi.h:6609

hwrm_cfa_l2_filter_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:6611

hwrm_cfa_l2_filter_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6605

hwrm_cfa_l2_filter_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6608

hwrm_cfa_l2_filter_cfg_input
Definition bnxt_hsi.h:6636

hwrm_cfa_l2_filter_cfg_input::new_mirror_vnic_id
__le32 new_mirror_vnic_id
Definition bnxt_hsi.h:6659

hwrm_cfa_l2_filter_cfg_input::dst_id
__le32 dst_id
Definition bnxt_hsi.h:6658

hwrm_cfa_l2_filter_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6639

hwrm_cfa_l2_filter_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6641

hwrm_cfa_l2_filter_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6637

hwrm_cfa_l2_filter_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:6642

hwrm_cfa_l2_filter_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6638

hwrm_cfa_l2_filter_cfg_input::l2_filter_id
__le64 l2_filter_id
Definition bnxt_hsi.h:6657

hwrm_cfa_l2_filter_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:6654

hwrm_cfa_l2_filter_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6640

hwrm_cfa_l2_filter_cfg_output
Definition bnxt_hsi.h:6663

hwrm_cfa_l2_filter_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6665

hwrm_cfa_l2_filter_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6666

hwrm_cfa_l2_filter_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6664

hwrm_cfa_l2_filter_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6667

hwrm_cfa_l2_filter_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:6669

hwrm_cfa_l2_filter_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6668

hwrm_cfa_l2_filter_free_input
Definition bnxt_hsi.h:6616

hwrm_cfa_l2_filter_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6620

hwrm_cfa_l2_filter_free_input::l2_filter_id
__le64 l2_filter_id
Definition bnxt_hsi.h:6622

hwrm_cfa_l2_filter_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6618

hwrm_cfa_l2_filter_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6617

hwrm_cfa_l2_filter_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6619

hwrm_cfa_l2_filter_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6621

hwrm_cfa_l2_filter_free_output
Definition bnxt_hsi.h:6626

hwrm_cfa_l2_filter_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6631

hwrm_cfa_l2_filter_free_output::valid
u8 valid
Definition bnxt_hsi.h:6632

hwrm_cfa_l2_filter_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6630

hwrm_cfa_l2_filter_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6627

hwrm_cfa_l2_filter_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6628

hwrm_cfa_l2_filter_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6629

hwrm_cfa_l2_set_rx_mask_cmd_err
Definition bnxt_hsi.h:6708

hwrm_cfa_l2_set_rx_mask_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6713

hwrm_cfa_l2_set_rx_mask_cmd_err::code
u8 code
Definition bnxt_hsi.h:6709

hwrm_cfa_l2_set_rx_mask_input
Definition bnxt_hsi.h:6673

hwrm_cfa_l2_set_rx_mask_input::num_mc_entries
__le32 num_mc_entries
Definition bnxt_hsi.h:6690

hwrm_cfa_l2_set_rx_mask_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6677

hwrm_cfa_l2_set_rx_mask_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:6694

hwrm_cfa_l2_set_rx_mask_input::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:6679

hwrm_cfa_l2_set_rx_mask_input::mask
__le32 mask
Definition bnxt_hsi.h:6680

hwrm_cfa_l2_set_rx_mask_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6678

hwrm_cfa_l2_set_rx_mask_input::mc_tbl_addr
__le64 mc_tbl_addr
Definition bnxt_hsi.h:6689

hwrm_cfa_l2_set_rx_mask_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6674

hwrm_cfa_l2_set_rx_mask_input::num_vlan_tags
__le32 num_vlan_tags
Definition bnxt_hsi.h:6693

hwrm_cfa_l2_set_rx_mask_input::vlan_tag_tbl_addr
__le64 vlan_tag_tbl_addr
Definition bnxt_hsi.h:6692

hwrm_cfa_l2_set_rx_mask_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6676

hwrm_cfa_l2_set_rx_mask_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:6691

hwrm_cfa_l2_set_rx_mask_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6675

hwrm_cfa_l2_set_rx_mask_output
Definition bnxt_hsi.h:6698

hwrm_cfa_l2_set_rx_mask_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6700

hwrm_cfa_l2_set_rx_mask_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6701

hwrm_cfa_l2_set_rx_mask_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6702

hwrm_cfa_l2_set_rx_mask_output::valid
u8 valid
Definition bnxt_hsi.h:6704

hwrm_cfa_l2_set_rx_mask_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6699

hwrm_cfa_l2_set_rx_mask_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6703

hwrm_cfa_meter_instance_alloc_input
Definition bnxt_hsi.h:7597

hwrm_cfa_meter_instance_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7599

hwrm_cfa_meter_instance_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7602

hwrm_cfa_meter_instance_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7601

hwrm_cfa_meter_instance_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7600

hwrm_cfa_meter_instance_alloc_input::flags
u8 flags
Definition bnxt_hsi.h:7603

hwrm_cfa_meter_instance_alloc_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:7612

hwrm_cfa_meter_instance_alloc_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:7608

hwrm_cfa_meter_instance_alloc_input::meter_profile_id
__le16 meter_profile_id
Definition bnxt_hsi.h:7609

hwrm_cfa_meter_instance_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7598

hwrm_cfa_meter_instance_alloc_output
Definition bnxt_hsi.h:7616

hwrm_cfa_meter_instance_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7617

hwrm_cfa_meter_instance_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7619

hwrm_cfa_meter_instance_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7618

hwrm_cfa_meter_instance_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:7625

hwrm_cfa_meter_instance_alloc_output::meter_instance_id
__le16 meter_instance_id
Definition bnxt_hsi.h:7621

hwrm_cfa_meter_instance_alloc_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:7624

hwrm_cfa_meter_instance_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7620

hwrm_cfa_meter_instance_free_input
Definition bnxt_hsi.h:7629

hwrm_cfa_meter_instance_free_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:7640

hwrm_cfa_meter_instance_free_input::meter_instance_id
__le16 meter_instance_id
Definition bnxt_hsi.h:7641

hwrm_cfa_meter_instance_free_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:7644

hwrm_cfa_meter_instance_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7633

hwrm_cfa_meter_instance_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7632

hwrm_cfa_meter_instance_free_input::flags
u8 flags
Definition bnxt_hsi.h:7635

hwrm_cfa_meter_instance_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7630

hwrm_cfa_meter_instance_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7634

hwrm_cfa_meter_instance_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7631

hwrm_cfa_meter_instance_free_output
Definition bnxt_hsi.h:7648

hwrm_cfa_meter_instance_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7652

hwrm_cfa_meter_instance_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7650

hwrm_cfa_meter_instance_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7649

hwrm_cfa_meter_instance_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7651

hwrm_cfa_meter_instance_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7653

hwrm_cfa_meter_instance_free_output::valid
u8 valid
Definition bnxt_hsi.h:7654

hwrm_cfa_meter_profile_alloc_input
Definition bnxt_hsi.h:7373

hwrm_cfa_meter_profile_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7376

hwrm_cfa_meter_profile_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7375

hwrm_cfa_meter_profile_alloc_input::commit_rate
__le32 commit_rate
Definition bnxt_hsi.h:7391

hwrm_cfa_meter_profile_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7378

hwrm_cfa_meter_profile_alloc_input::reserved1
__le16 reserved1
Definition bnxt_hsi.h:7389

hwrm_cfa_meter_profile_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7377

hwrm_cfa_meter_profile_alloc_input::excess_peak_rate
__le32 excess_peak_rate
Definition bnxt_hsi.h:7423

hwrm_cfa_meter_profile_alloc_input::flags
u8 flags
Definition bnxt_hsi.h:7379

hwrm_cfa_meter_profile_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7374

hwrm_cfa_meter_profile_alloc_input::commit_burst
__le32 commit_burst
Definition bnxt_hsi.h:7407

hwrm_cfa_meter_profile_alloc_input::meter_type
u8 meter_type
Definition bnxt_hsi.h:7384

hwrm_cfa_meter_profile_alloc_input::excess_peak_burst
__le32 excess_peak_burst
Definition bnxt_hsi.h:7439

hwrm_cfa_meter_profile_alloc_input::reserved2
__le32 reserved2
Definition bnxt_hsi.h:7390

hwrm_cfa_meter_profile_alloc_output
Definition bnxt_hsi.h:7458

hwrm_cfa_meter_profile_alloc_output::meter_profile_id
__le16 meter_profile_id
Definition bnxt_hsi.h:7463

hwrm_cfa_meter_profile_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:7467

hwrm_cfa_meter_profile_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7460

hwrm_cfa_meter_profile_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7461

hwrm_cfa_meter_profile_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7459

hwrm_cfa_meter_profile_alloc_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:7466

hwrm_cfa_meter_profile_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7462

hwrm_cfa_meter_profile_cfg_input
Definition bnxt_hsi.h:7500

hwrm_cfa_meter_profile_cfg_input::flags
u8 flags
Definition bnxt_hsi.h:7506

hwrm_cfa_meter_profile_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7504

hwrm_cfa_meter_profile_cfg_input::commit_burst
__le32 commit_burst
Definition bnxt_hsi.h:7536

hwrm_cfa_meter_profile_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7502

hwrm_cfa_meter_profile_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7501

hwrm_cfa_meter_profile_cfg_input::meter_profile_id
__le16 meter_profile_id
Definition bnxt_hsi.h:7516

hwrm_cfa_meter_profile_cfg_input::commit_rate
__le32 commit_rate
Definition bnxt_hsi.h:7520

hwrm_cfa_meter_profile_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7505

hwrm_cfa_meter_profile_cfg_input::meter_type
u8 meter_type
Definition bnxt_hsi.h:7511

hwrm_cfa_meter_profile_cfg_input::excess_peak_burst
__le32 excess_peak_burst
Definition bnxt_hsi.h:7568

hwrm_cfa_meter_profile_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7503

hwrm_cfa_meter_profile_cfg_input::excess_peak_rate
__le32 excess_peak_rate
Definition bnxt_hsi.h:7552

hwrm_cfa_meter_profile_cfg_input::reserved
__le32 reserved
Definition bnxt_hsi.h:7519

hwrm_cfa_meter_profile_cfg_output
Definition bnxt_hsi.h:7587

hwrm_cfa_meter_profile_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:7593

hwrm_cfa_meter_profile_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7590

hwrm_cfa_meter_profile_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7592

hwrm_cfa_meter_profile_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7591

hwrm_cfa_meter_profile_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7589

hwrm_cfa_meter_profile_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7588

hwrm_cfa_meter_profile_free_input
Definition bnxt_hsi.h:7471

hwrm_cfa_meter_profile_free_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:7486

hwrm_cfa_meter_profile_free_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:7482

hwrm_cfa_meter_profile_free_input::flags
u8 flags
Definition bnxt_hsi.h:7477

hwrm_cfa_meter_profile_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7473

hwrm_cfa_meter_profile_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7474

hwrm_cfa_meter_profile_free_input::meter_profile_id
__le16 meter_profile_id
Definition bnxt_hsi.h:7483

hwrm_cfa_meter_profile_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7475

hwrm_cfa_meter_profile_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7476

hwrm_cfa_meter_profile_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7472

hwrm_cfa_meter_profile_free_output
Definition bnxt_hsi.h:7490

hwrm_cfa_meter_profile_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7491

hwrm_cfa_meter_profile_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7495

hwrm_cfa_meter_profile_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7492

hwrm_cfa_meter_profile_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7493

hwrm_cfa_meter_profile_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7494

hwrm_cfa_meter_profile_free_output::valid
u8 valid
Definition bnxt_hsi.h:7496

hwrm_cfa_ntuple_filter_alloc_cmd_err
Definition bnxt_hsi.h:7166

hwrm_cfa_ntuple_filter_alloc_cmd_err::code
u8 code
Definition bnxt_hsi.h:7167

hwrm_cfa_ntuple_filter_alloc_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7171

hwrm_cfa_ntuple_filter_alloc_input
Definition bnxt_hsi.h:7075

hwrm_cfa_ntuple_filter_alloc_input::dst_id
__le16 dst_id
Definition bnxt_hsi.h:7118

hwrm_cfa_ntuple_filter_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7077

hwrm_cfa_ntuple_filter_alloc_input::pri_hint
u8 pri_hint
Definition bnxt_hsi.h:7135

hwrm_cfa_ntuple_filter_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:7085

hwrm_cfa_ntuple_filter_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7076

hwrm_cfa_ntuple_filter_alloc_input::dst_port
__be16 dst_port
Definition bnxt_hsi.h:7148

hwrm_cfa_ntuple_filter_alloc_input::src_port_mask
__be16 src_port_mask
Definition bnxt_hsi.h:7147

hwrm_cfa_ntuple_filter_alloc_input::l2_filter_id
__le64 l2_filter_id
Definition bnxt_hsi.h:7105

hwrm_cfa_ntuple_filter_alloc_input::src_ipaddr_mask
__be32 src_ipaddr_mask[4]
Definition bnxt_hsi.h:7143

hwrm_cfa_ntuple_filter_alloc_input::src_macaddr
u8 src_macaddr[6]
Definition bnxt_hsi.h:7106

hwrm_cfa_ntuple_filter_alloc_input::dst_ipaddr_mask
__be32 dst_ipaddr_mask[4]
Definition bnxt_hsi.h:7145

hwrm_cfa_ntuple_filter_alloc_input::dst_port_mask
__be16 dst_port_mask
Definition bnxt_hsi.h:7149

hwrm_cfa_ntuple_filter_alloc_input::ntuple_filter_id_hint
__le64 ntuple_filter_id_hint
Definition bnxt_hsi.h:7150

hwrm_cfa_ntuple_filter_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:7081

hwrm_cfa_ntuple_filter_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7078

hwrm_cfa_ntuple_filter_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7079

hwrm_cfa_ntuple_filter_alloc_input::ethertype
__be16 ethertype
Definition bnxt_hsi.h:7107

hwrm_cfa_ntuple_filter_alloc_input::dst_ipaddr
__be32 dst_ipaddr[4]
Definition bnxt_hsi.h:7144

hwrm_cfa_ntuple_filter_alloc_input::ip_addr_type
u8 ip_addr_type
Definition bnxt_hsi.h:7108

hwrm_cfa_ntuple_filter_alloc_input::ip_protocol
u8 ip_protocol
Definition bnxt_hsi.h:7113

hwrm_cfa_ntuple_filter_alloc_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:7120

hwrm_cfa_ntuple_filter_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7080

hwrm_cfa_ntuple_filter_alloc_input::src_port
__be16 src_port
Definition bnxt_hsi.h:7146

hwrm_cfa_ntuple_filter_alloc_input::src_ipaddr
__be32 src_ipaddr[4]
Definition bnxt_hsi.h:7142

hwrm_cfa_ntuple_filter_alloc_input::mirror_vnic_id
__le16 mirror_vnic_id
Definition bnxt_hsi.h:7119

hwrm_cfa_ntuple_filter_alloc_output
Definition bnxt_hsi.h:7154

hwrm_cfa_ntuple_filter_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7156

hwrm_cfa_ntuple_filter_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7157

hwrm_cfa_ntuple_filter_alloc_output::flow_id
__le32 flow_id
Definition bnxt_hsi.h:7160

hwrm_cfa_ntuple_filter_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:7162

hwrm_cfa_ntuple_filter_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7158

hwrm_cfa_ntuple_filter_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:7161

hwrm_cfa_ntuple_filter_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7155

hwrm_cfa_ntuple_filter_alloc_output::ntuple_filter_id
__le64 ntuple_filter_id
Definition bnxt_hsi.h:7159

hwrm_cfa_ntuple_filter_cfg_input
Definition bnxt_hsi.h:7195

hwrm_cfa_ntuple_filter_cfg_input::new_meter_instance_id
__le16 new_meter_instance_id
Definition bnxt_hsi.h:7209

hwrm_cfa_ntuple_filter_cfg_input::ntuple_filter_id
__le64 ntuple_filter_id
Definition bnxt_hsi.h:7206

hwrm_cfa_ntuple_filter_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7197

hwrm_cfa_ntuple_filter_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7199

hwrm_cfa_ntuple_filter_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7196

hwrm_cfa_ntuple_filter_cfg_input::new_dst_id
__le32 new_dst_id
Definition bnxt_hsi.h:7207

hwrm_cfa_ntuple_filter_cfg_input::new_mirror_vnic_id
__le32 new_mirror_vnic_id
Definition bnxt_hsi.h:7208

hwrm_cfa_ntuple_filter_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7198

hwrm_cfa_ntuple_filter_cfg_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:7205

hwrm_cfa_ntuple_filter_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:7201

hwrm_cfa_ntuple_filter_cfg_input::unused_1
u8 unused_1[6]
Definition bnxt_hsi.h:7212

hwrm_cfa_ntuple_filter_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7200

hwrm_cfa_ntuple_filter_cfg_output
Definition bnxt_hsi.h:7216

hwrm_cfa_ntuple_filter_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7219

hwrm_cfa_ntuple_filter_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:7222

hwrm_cfa_ntuple_filter_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7221

hwrm_cfa_ntuple_filter_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7220

hwrm_cfa_ntuple_filter_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7218

hwrm_cfa_ntuple_filter_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7217

hwrm_cfa_ntuple_filter_free_input
Definition bnxt_hsi.h:7175

hwrm_cfa_ntuple_filter_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:7179

hwrm_cfa_ntuple_filter_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:7177

hwrm_cfa_ntuple_filter_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:7176

hwrm_cfa_ntuple_filter_free_input::ntuple_filter_id
__le64 ntuple_filter_id
Definition bnxt_hsi.h:7181

hwrm_cfa_ntuple_filter_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7178

hwrm_cfa_ntuple_filter_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:7180

hwrm_cfa_ntuple_filter_free_output
Definition bnxt_hsi.h:7185

hwrm_cfa_ntuple_filter_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:7189

hwrm_cfa_ntuple_filter_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:7186

hwrm_cfa_ntuple_filter_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:7188

hwrm_cfa_ntuple_filter_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:7190

hwrm_cfa_ntuple_filter_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:7187

hwrm_cfa_ntuple_filter_free_output::valid
u8 valid
Definition bnxt_hsi.h:7191

hwrm_cfa_pair_alloc_input
Definition bnxt_hsi.h:8191

hwrm_cfa_pair_alloc_input::new_pf_fid
__le16 new_pf_fid
Definition bnxt_hsi.h:8213

hwrm_cfa_pair_alloc_input::port_id
u8 port_id
Definition bnxt_hsi.h:8211

hwrm_cfa_pair_alloc_input::pf_b_id
u8 pf_b_id
Definition bnxt_hsi.h:8209

hwrm_cfa_pair_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8194

hwrm_cfa_pair_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8196

hwrm_cfa_pair_alloc_input::fc_ba
u8 fc_ba
Definition bnxt_hsi.h:8223

hwrm_cfa_pair_alloc_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:8224

hwrm_cfa_pair_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8193

hwrm_cfa_pair_alloc_input::vf_b_id
__le16 vf_b_id
Definition bnxt_hsi.h:8210

hwrm_cfa_pair_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8195

hwrm_cfa_pair_alloc_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:8206

hwrm_cfa_pair_alloc_input::host_b_id
u8 host_b_id
Definition bnxt_hsi.h:8208

hwrm_cfa_pair_alloc_input::q_ba
u8 q_ba
Definition bnxt_hsi.h:8221

hwrm_cfa_pair_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8192

hwrm_cfa_pair_alloc_input::pair_name
char pair_name[32]
Definition bnxt_hsi.h:8219

hwrm_cfa_pair_alloc_input::vf_a_id
__le16 vf_a_id
Definition bnxt_hsi.h:8207

hwrm_cfa_pair_alloc_input::pair_mode
u8 pair_mode
Definition bnxt_hsi.h:8197

hwrm_cfa_pair_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:8214

hwrm_cfa_pair_alloc_input::fc_ab
u8 fc_ab
Definition bnxt_hsi.h:8222

hwrm_cfa_pair_alloc_input::pri
u8 pri
Definition bnxt_hsi.h:8212

hwrm_cfa_pair_alloc_input::q_ab
u8 q_ab
Definition bnxt_hsi.h:8220

hwrm_cfa_pair_alloc_output
Definition bnxt_hsi.h:8228

hwrm_cfa_pair_alloc_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8237

hwrm_cfa_pair_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8230

hwrm_cfa_pair_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8229

hwrm_cfa_pair_alloc_output::tx_cfa_action_a
__le16 tx_cfa_action_a
Definition bnxt_hsi.h:8234

hwrm_cfa_pair_alloc_output::rx_cfa_code_b
__le16 rx_cfa_code_b
Definition bnxt_hsi.h:8235

hwrm_cfa_pair_alloc_output::tx_cfa_action_b
__le16 tx_cfa_action_b
Definition bnxt_hsi.h:8236

hwrm_cfa_pair_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8231

hwrm_cfa_pair_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8232

hwrm_cfa_pair_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:8238

hwrm_cfa_pair_alloc_output::rx_cfa_code_a
__le16 rx_cfa_code_a
Definition bnxt_hsi.h:8233

hwrm_cfa_pair_free_input
Definition bnxt_hsi.h:8242

hwrm_cfa_pair_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8246

hwrm_cfa_pair_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8245

hwrm_cfa_pair_free_input::pair_name
char pair_name[32]
Definition bnxt_hsi.h:8248

hwrm_cfa_pair_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8244

hwrm_cfa_pair_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8243

hwrm_cfa_pair_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8247

hwrm_cfa_pair_free_output
Definition bnxt_hsi.h:8252

hwrm_cfa_pair_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8256

hwrm_cfa_pair_free_output::valid
u8 valid
Definition bnxt_hsi.h:8258

hwrm_cfa_pair_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8257

hwrm_cfa_pair_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8255

hwrm_cfa_pair_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8254

hwrm_cfa_pair_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8253

hwrm_cfa_pair_info_input
Definition bnxt_hsi.h:8262

hwrm_cfa_pair_info_input::pair_name
char pair_name[32]
Definition bnxt_hsi.h:8274

hwrm_cfa_pair_info_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8267

hwrm_cfa_pair_info_input::pair_index
__le16 pair_index
Definition bnxt_hsi.h:8271

hwrm_cfa_pair_info_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8264

hwrm_cfa_pair_info_input::pair_vfid
u8 pair_vfid
Definition bnxt_hsi.h:8273

hwrm_cfa_pair_info_input::flags
__le32 flags
Definition bnxt_hsi.h:8268

hwrm_cfa_pair_info_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8266

hwrm_cfa_pair_info_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8263

hwrm_cfa_pair_info_input::pair_pfid
u8 pair_pfid
Definition bnxt_hsi.h:8272

hwrm_cfa_pair_info_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8265

hwrm_cfa_pair_info_output
Definition bnxt_hsi.h:8278

hwrm_cfa_pair_info_output::pf_b_index
u8 pf_b_index
Definition bnxt_hsi.h:8292

hwrm_cfa_pair_info_output::rx_cfa_code_b
__le16 rx_cfa_code_b
Definition bnxt_hsi.h:8294

hwrm_cfa_pair_info_output::pf_a_index
u8 pf_a_index
Definition bnxt_hsi.h:8286

hwrm_cfa_pair_info_output::rx_cfa_code_a
__le16 rx_cfa_code_a
Definition bnxt_hsi.h:8288

hwrm_cfa_pair_info_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8281

hwrm_cfa_pair_info_output::b_fid
__le16 b_fid
Definition bnxt_hsi.h:8290

hwrm_cfa_pair_info_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8308

hwrm_cfa_pair_info_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8279

hwrm_cfa_pair_info_output::pair_mode
u8 pair_mode
Definition bnxt_hsi.h:8296

hwrm_cfa_pair_info_output::tx_cfa_action_a
__le16 tx_cfa_action_a
Definition bnxt_hsi.h:8289

hwrm_cfa_pair_info_output::a_fid
__le16 a_fid
Definition bnxt_hsi.h:8284

hwrm_cfa_pair_info_output::host_b_index
u8 host_b_index
Definition bnxt_hsi.h:8291

hwrm_cfa_pair_info_output::valid
u8 valid
Definition bnxt_hsi.h:8309

hwrm_cfa_pair_info_output::host_a_index
u8 host_a_index
Definition bnxt_hsi.h:8285

hwrm_cfa_pair_info_output::tx_cfa_action_b
__le16 tx_cfa_action_b
Definition bnxt_hsi.h:8295

hwrm_cfa_pair_info_output::pair_name
char pair_name[32]
Definition bnxt_hsi.h:8307

hwrm_cfa_pair_info_output::vf_a_index
__le16 vf_a_index
Definition bnxt_hsi.h:8287

hwrm_cfa_pair_info_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8280

hwrm_cfa_pair_info_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8282

hwrm_cfa_pair_info_output::pair_state
u8 pair_state
Definition bnxt_hsi.h:8303

hwrm_cfa_pair_info_output::vf_b_index
__le16 vf_b_index
Definition bnxt_hsi.h:8293

hwrm_cfa_pair_info_output::next_pair_index
__le16 next_pair_index
Definition bnxt_hsi.h:8283

hwrm_cfa_redirect_query_tunnel_type_input
Definition bnxt_hsi.h:8358

hwrm_cfa_redirect_query_tunnel_type_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:8365

hwrm_cfa_redirect_query_tunnel_type_input::src_fid
__le16 src_fid
Definition bnxt_hsi.h:8364

hwrm_cfa_redirect_query_tunnel_type_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8363

hwrm_cfa_redirect_query_tunnel_type_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8361

hwrm_cfa_redirect_query_tunnel_type_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8360

hwrm_cfa_redirect_query_tunnel_type_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8362

hwrm_cfa_redirect_query_tunnel_type_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8359

hwrm_cfa_redirect_query_tunnel_type_output
Definition bnxt_hsi.h:8369

hwrm_cfa_redirect_query_tunnel_type_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8370

hwrm_cfa_redirect_query_tunnel_type_output::valid
u8 valid
Definition bnxt_hsi.h:8389

hwrm_cfa_redirect_query_tunnel_type_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8371

hwrm_cfa_redirect_query_tunnel_type_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8373

hwrm_cfa_redirect_query_tunnel_type_output::tunnel_mask
__le32 tunnel_mask
Definition bnxt_hsi.h:8374

hwrm_cfa_redirect_query_tunnel_type_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:8388

hwrm_cfa_redirect_query_tunnel_type_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8372

hwrm_cfa_redirect_tunnel_type_alloc_input
Definition bnxt_hsi.h:6848

hwrm_cfa_redirect_tunnel_type_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6850

hwrm_cfa_redirect_tunnel_type_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6851

hwrm_cfa_redirect_tunnel_type_alloc_input::flags
u8 flags
Definition bnxt_hsi.h:6870

hwrm_cfa_redirect_tunnel_type_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6853

hwrm_cfa_redirect_tunnel_type_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6849

hwrm_cfa_redirect_tunnel_type_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6852

hwrm_cfa_redirect_tunnel_type_alloc_input::dest_fid
__le16 dest_fid
Definition bnxt_hsi.h:6854

hwrm_cfa_redirect_tunnel_type_alloc_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:6855

hwrm_cfa_redirect_tunnel_type_alloc_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:6872

hwrm_cfa_redirect_tunnel_type_alloc_output
Definition bnxt_hsi.h:6876

hwrm_cfa_redirect_tunnel_type_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:6882

hwrm_cfa_redirect_tunnel_type_alloc_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6881

hwrm_cfa_redirect_tunnel_type_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6877

hwrm_cfa_redirect_tunnel_type_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6879

hwrm_cfa_redirect_tunnel_type_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6878

hwrm_cfa_redirect_tunnel_type_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6880

hwrm_cfa_redirect_tunnel_type_free_input
Definition bnxt_hsi.h:6886

hwrm_cfa_redirect_tunnel_type_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6888

hwrm_cfa_redirect_tunnel_type_free_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:6893

hwrm_cfa_redirect_tunnel_type_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6890

hwrm_cfa_redirect_tunnel_type_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6887

hwrm_cfa_redirect_tunnel_type_free_input::dest_fid
__le16 dest_fid
Definition bnxt_hsi.h:6892

hwrm_cfa_redirect_tunnel_type_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6889

hwrm_cfa_redirect_tunnel_type_free_input::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:6908

hwrm_cfa_redirect_tunnel_type_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6891

hwrm_cfa_redirect_tunnel_type_free_output
Definition bnxt_hsi.h:6912

hwrm_cfa_redirect_tunnel_type_free_output::valid
u8 valid
Definition bnxt_hsi.h:6918

hwrm_cfa_redirect_tunnel_type_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6915

hwrm_cfa_redirect_tunnel_type_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6914

hwrm_cfa_redirect_tunnel_type_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6917

hwrm_cfa_redirect_tunnel_type_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6916

hwrm_cfa_redirect_tunnel_type_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6913

hwrm_cfa_redirect_tunnel_type_info_input
Definition bnxt_hsi.h:6922

hwrm_cfa_redirect_tunnel_type_info_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6923

hwrm_cfa_redirect_tunnel_type_info_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6926

hwrm_cfa_redirect_tunnel_type_info_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6925

hwrm_cfa_redirect_tunnel_type_info_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6924

hwrm_cfa_redirect_tunnel_type_info_input::src_fid
__le16 src_fid
Definition bnxt_hsi.h:6928

hwrm_cfa_redirect_tunnel_type_info_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6927

hwrm_cfa_redirect_tunnel_type_info_input::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:6944

hwrm_cfa_redirect_tunnel_type_info_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:6929

hwrm_cfa_redirect_tunnel_type_info_output
Definition bnxt_hsi.h:6948

hwrm_cfa_redirect_tunnel_type_info_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6952

hwrm_cfa_redirect_tunnel_type_info_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6951

hwrm_cfa_redirect_tunnel_type_info_output::dest_fid
__le16 dest_fid
Definition bnxt_hsi.h:6953

hwrm_cfa_redirect_tunnel_type_info_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6949

hwrm_cfa_redirect_tunnel_type_info_output::valid
u8 valid
Definition bnxt_hsi.h:6955

hwrm_cfa_redirect_tunnel_type_info_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:6954

hwrm_cfa_redirect_tunnel_type_info_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6950

hwrm_cfa_tunnel_filter_alloc_input
Definition bnxt_hsi.h:6764

hwrm_cfa_tunnel_filter_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:6770

hwrm_cfa_tunnel_filter_alloc_input::l3_addr_type
u8 l3_addr_type
Definition bnxt_hsi.h:6789

hwrm_cfa_tunnel_filter_alloc_input::vni
__le32 vni
Definition bnxt_hsi.h:6810

hwrm_cfa_tunnel_filter_alloc_input::t_l3_addr_type
u8 t_l3_addr_type
Definition bnxt_hsi.h:6790

hwrm_cfa_tunnel_filter_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:6772

hwrm_cfa_tunnel_filter_alloc_input::mirror_vnic_id
__le32 mirror_vnic_id
Definition bnxt_hsi.h:6812

hwrm_cfa_tunnel_filter_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6768

hwrm_cfa_tunnel_filter_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6769

hwrm_cfa_tunnel_filter_alloc_input::l2_filter_id
__le64 l2_filter_id
Definition bnxt_hsi.h:6784

hwrm_cfa_tunnel_filter_alloc_input::t_l3_addr
__le32 t_l3_addr[4]
Definition bnxt_hsi.h:6788

hwrm_cfa_tunnel_filter_alloc_input::tunnel_flags
u8 tunnel_flags
Definition bnxt_hsi.h:6806

hwrm_cfa_tunnel_filter_alloc_input::l2_ivlan
__le16 l2_ivlan
Definition bnxt_hsi.h:6786

hwrm_cfa_tunnel_filter_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6767

hwrm_cfa_tunnel_filter_alloc_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:6791

hwrm_cfa_tunnel_filter_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6766

hwrm_cfa_tunnel_filter_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6765

hwrm_cfa_tunnel_filter_alloc_input::l2_addr
u8 l2_addr[6]
Definition bnxt_hsi.h:6785

hwrm_cfa_tunnel_filter_alloc_input::dst_vnic_id
__le32 dst_vnic_id
Definition bnxt_hsi.h:6811

hwrm_cfa_tunnel_filter_alloc_input::l3_addr
__le32 l3_addr[4]
Definition bnxt_hsi.h:6787

hwrm_cfa_tunnel_filter_alloc_output
Definition bnxt_hsi.h:6816

hwrm_cfa_tunnel_filter_alloc_output::tunnel_filter_id
__le64 tunnel_filter_id
Definition bnxt_hsi.h:6821

hwrm_cfa_tunnel_filter_alloc_output::flow_id
__le32 flow_id
Definition bnxt_hsi.h:6822

hwrm_cfa_tunnel_filter_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6819

hwrm_cfa_tunnel_filter_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:6824

hwrm_cfa_tunnel_filter_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:6823

hwrm_cfa_tunnel_filter_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6817

hwrm_cfa_tunnel_filter_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6818

hwrm_cfa_tunnel_filter_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6820

hwrm_cfa_tunnel_filter_free_input
Definition bnxt_hsi.h:6828

hwrm_cfa_tunnel_filter_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6830

hwrm_cfa_tunnel_filter_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6831

hwrm_cfa_tunnel_filter_free_input::tunnel_filter_id
__le64 tunnel_filter_id
Definition bnxt_hsi.h:6834

hwrm_cfa_tunnel_filter_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6832

hwrm_cfa_tunnel_filter_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6833

hwrm_cfa_tunnel_filter_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6829

hwrm_cfa_tunnel_filter_free_output
Definition bnxt_hsi.h:6838

hwrm_cfa_tunnel_filter_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6841

hwrm_cfa_tunnel_filter_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6839

hwrm_cfa_tunnel_filter_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6840

hwrm_cfa_tunnel_filter_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6842

hwrm_cfa_tunnel_filter_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6843

hwrm_cfa_tunnel_filter_free_output::valid
u8 valid
Definition bnxt_hsi.h:6844

hwrm_cfa_vf_pair_alloc_input
Definition bnxt_hsi.h:8113

hwrm_cfa_vf_pair_alloc_input::pair_name
char pair_name[32]
Definition bnxt_hsi.h:8122

hwrm_cfa_vf_pair_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8115

hwrm_cfa_vf_pair_alloc_input::vf_a_id
__le16 vf_a_id
Definition bnxt_hsi.h:8119

hwrm_cfa_vf_pair_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8118

hwrm_cfa_vf_pair_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8117

hwrm_cfa_vf_pair_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8114

hwrm_cfa_vf_pair_alloc_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:8121

hwrm_cfa_vf_pair_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8116

hwrm_cfa_vf_pair_alloc_input::vf_b_id
__le16 vf_b_id
Definition bnxt_hsi.h:8120

hwrm_cfa_vf_pair_alloc_output
Definition bnxt_hsi.h:8126

hwrm_cfa_vf_pair_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8129

hwrm_cfa_vf_pair_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8130

hwrm_cfa_vf_pair_alloc_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8131

hwrm_cfa_vf_pair_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:8132

hwrm_cfa_vf_pair_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8127

hwrm_cfa_vf_pair_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8128

hwrm_cfa_vf_pair_free_input
Definition bnxt_hsi.h:8136

hwrm_cfa_vf_pair_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8137

hwrm_cfa_vf_pair_free_input::pair_name
char pair_name[32]
Definition bnxt_hsi.h:8142

hwrm_cfa_vf_pair_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8141

hwrm_cfa_vf_pair_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8140

hwrm_cfa_vf_pair_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8138

hwrm_cfa_vf_pair_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8139

hwrm_cfa_vf_pair_free_output
Definition bnxt_hsi.h:8146

hwrm_cfa_vf_pair_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8151

hwrm_cfa_vf_pair_free_output::valid
u8 valid
Definition bnxt_hsi.h:8152

hwrm_cfa_vf_pair_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8150

hwrm_cfa_vf_pair_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8149

hwrm_cfa_vf_pair_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8147

hwrm_cfa_vf_pair_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8148

hwrm_cfa_vf_pair_info_input
Definition bnxt_hsi.h:8156

hwrm_cfa_vf_pair_info_input::vf_pair_name
char vf_pair_name[32]
Definition bnxt_hsi.h:8166

hwrm_cfa_vf_pair_info_input::vf_pair_index
__le16 vf_pair_index
Definition bnxt_hsi.h:8164

hwrm_cfa_vf_pair_info_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8158

hwrm_cfa_vf_pair_info_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8161

hwrm_cfa_vf_pair_info_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8159

hwrm_cfa_vf_pair_info_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8160

hwrm_cfa_vf_pair_info_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8157

hwrm_cfa_vf_pair_info_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:8165

hwrm_cfa_vf_pair_info_input::flags
__le32 flags
Definition bnxt_hsi.h:8162

hwrm_cfa_vf_pair_info_output
Definition bnxt_hsi.h:8170

hwrm_cfa_vf_pair_info_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:8186

hwrm_cfa_vf_pair_info_output::vf_b_fid
__le16 vf_b_fid
Definition bnxt_hsi.h:8178

hwrm_cfa_vf_pair_info_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8173

hwrm_cfa_vf_pair_info_output::next_vf_pair_index
__le16 next_vf_pair_index
Definition bnxt_hsi.h:8175

hwrm_cfa_vf_pair_info_output::pair_name
char pair_name[32]
Definition bnxt_hsi.h:8185

hwrm_cfa_vf_pair_info_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8172

hwrm_cfa_vf_pair_info_output::vf_a_fid
__le16 vf_a_fid
Definition bnxt_hsi.h:8176

hwrm_cfa_vf_pair_info_output::vf_a_index
__le16 vf_a_index
Definition bnxt_hsi.h:8177

hwrm_cfa_vf_pair_info_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:8184

hwrm_cfa_vf_pair_info_output::valid
u8 valid
Definition bnxt_hsi.h:8187

hwrm_cfa_vf_pair_info_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8171

hwrm_cfa_vf_pair_info_output::vf_b_index
__le16 vf_b_index
Definition bnxt_hsi.h:8179

hwrm_cfa_vf_pair_info_output::pair_state
u8 pair_state
Definition bnxt_hsi.h:8180

hwrm_cfa_vf_pair_info_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8174

hwrm_cfa_vfr_alloc_input
Definition bnxt_hsi.h:8313

hwrm_cfa_vfr_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8317

hwrm_cfa_vfr_alloc_input::vfr_name
char vfr_name[32]
Definition bnxt_hsi.h:8322

hwrm_cfa_vfr_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8316

hwrm_cfa_vfr_alloc_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:8321

hwrm_cfa_vfr_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8314

hwrm_cfa_vfr_alloc_input::vf_id
__le16 vf_id
Definition bnxt_hsi.h:8319

hwrm_cfa_vfr_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8315

hwrm_cfa_vfr_alloc_input::reserved
__le16 reserved
Definition bnxt_hsi.h:8320

hwrm_cfa_vfr_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8318

hwrm_cfa_vfr_alloc_output
Definition bnxt_hsi.h:8326

hwrm_cfa_vfr_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8330

hwrm_cfa_vfr_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:8333

hwrm_cfa_vfr_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:8334

hwrm_cfa_vfr_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8328

hwrm_cfa_vfr_alloc_output::rx_cfa_code
__le16 rx_cfa_code
Definition bnxt_hsi.h:8331

hwrm_cfa_vfr_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8329

hwrm_cfa_vfr_alloc_output::tx_cfa_action
__le16 tx_cfa_action
Definition bnxt_hsi.h:8332

hwrm_cfa_vfr_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8327

hwrm_cfa_vfr_free_input
Definition bnxt_hsi.h:8338

hwrm_cfa_vfr_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8343

hwrm_cfa_vfr_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8341

hwrm_cfa_vfr_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8340

hwrm_cfa_vfr_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8339

hwrm_cfa_vfr_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8342

hwrm_cfa_vfr_free_input::vfr_name
char vfr_name[32]
Definition bnxt_hsi.h:8344

hwrm_cfa_vfr_free_output
Definition bnxt_hsi.h:8348

hwrm_cfa_vfr_free_output::valid
u8 valid
Definition bnxt_hsi.h:8354

hwrm_cfa_vfr_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8350

hwrm_cfa_vfr_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8353

hwrm_cfa_vfr_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8349

hwrm_cfa_vfr_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8351

hwrm_cfa_vfr_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8352

hwrm_cfa_vlan_antispoof_cfg_input
Definition bnxt_hsi.h:6717

hwrm_cfa_vlan_antispoof_cfg_input::fid
__le16 fid
Definition bnxt_hsi.h:6723

hwrm_cfa_vlan_antispoof_cfg_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:6724

hwrm_cfa_vlan_antispoof_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6721

hwrm_cfa_vlan_antispoof_cfg_input::vlan_tag_mask_tbl_addr
__le64 vlan_tag_mask_tbl_addr
Definition bnxt_hsi.h:6726

hwrm_cfa_vlan_antispoof_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6718

hwrm_cfa_vlan_antispoof_cfg_input::num_vlan_entries
__le32 num_vlan_entries
Definition bnxt_hsi.h:6725

hwrm_cfa_vlan_antispoof_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6722

hwrm_cfa_vlan_antispoof_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6719

hwrm_cfa_vlan_antispoof_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6720

hwrm_cfa_vlan_antispoof_cfg_output
Definition bnxt_hsi.h:6730

hwrm_cfa_vlan_antispoof_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6735

hwrm_cfa_vlan_antispoof_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6733

hwrm_cfa_vlan_antispoof_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:6736

hwrm_cfa_vlan_antispoof_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6731

hwrm_cfa_vlan_antispoof_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6732

hwrm_cfa_vlan_antispoof_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6734

hwrm_cfa_vlan_antispoof_qcfg_input
Definition bnxt_hsi.h:6740

hwrm_cfa_vlan_antispoof_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6745

hwrm_cfa_vlan_antispoof_qcfg_input::fid
__le16 fid
Definition bnxt_hsi.h:6746

hwrm_cfa_vlan_antispoof_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6743

hwrm_cfa_vlan_antispoof_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6742

hwrm_cfa_vlan_antispoof_qcfg_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:6747

hwrm_cfa_vlan_antispoof_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6744

hwrm_cfa_vlan_antispoof_qcfg_input::max_vlan_entries
__le32 max_vlan_entries
Definition bnxt_hsi.h:6748

hwrm_cfa_vlan_antispoof_qcfg_input::vlan_tag_mask_tbl_addr
__le64 vlan_tag_mask_tbl_addr
Definition bnxt_hsi.h:6749

hwrm_cfa_vlan_antispoof_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6741

hwrm_cfa_vlan_antispoof_qcfg_output
Definition bnxt_hsi.h:6753

hwrm_cfa_vlan_antispoof_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6754

hwrm_cfa_vlan_antispoof_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:6760

hwrm_cfa_vlan_antispoof_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6756

hwrm_cfa_vlan_antispoof_qcfg_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:6759

hwrm_cfa_vlan_antispoof_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6757

hwrm_cfa_vlan_antispoof_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6755

hwrm_cfa_vlan_antispoof_qcfg_output::num_vlan_entries
__le32 num_vlan_entries
Definition bnxt_hsi.h:6758

hwrm_cmd_hdr
Definition bnxt_hsi.h:17

hwrm_cmd_hdr::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:22

hwrm_cmd_hdr::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:19

hwrm_cmd_hdr::target_id
__le16 target_id
Definition bnxt_hsi.h:21

hwrm_cmd_hdr::seq_id
__le16 seq_id
Definition bnxt_hsi.h:20

hwrm_cmd_hdr::req_type
__le16 req_type
Definition bnxt_hsi.h:18

hwrm_cmpl
Definition bnxt_hsi.h:500

hwrm_cmpl::unused_3
__le32 unused_3
Definition bnxt_hsi.h:510

hwrm_cmpl::sequence_id
__le16 sequence_id
Definition bnxt_hsi.h:506

hwrm_cmpl::type
__le16 type
Definition bnxt_hsi.h:501

hwrm_cmpl::v
__le32 v
Definition bnxt_hsi.h:508

hwrm_cmpl::unused_1
__le32 unused_1
Definition bnxt_hsi.h:507

hwrm_dbg_cfg_input
Definition bnxt_hsi.h:9693

hwrm_dbg_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9694

hwrm_dbg_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9697

hwrm_dbg_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9696

hwrm_dbg_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9695

hwrm_dbg_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9698

hwrm_dbg_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:9699

hwrm_dbg_cfg_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:9702

hwrm_dbg_cfg_output
Definition bnxt_hsi.h:9706

hwrm_dbg_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9708

hwrm_dbg_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9710

hwrm_dbg_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9707

hwrm_dbg_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:9712

hwrm_dbg_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9709

hwrm_dbg_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9711

hwrm_dbg_coredump_initiate_input
Definition bnxt_hsi.h:9755

hwrm_dbg_coredump_initiate_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9758

hwrm_dbg_coredump_initiate_input::unused_0
__le16 unused_0
Definition bnxt_hsi.h:9764

hwrm_dbg_coredump_initiate_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9756

hwrm_dbg_coredump_initiate_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9757

hwrm_dbg_coredump_initiate_input::component_id
__le16 component_id
Definition bnxt_hsi.h:9761

hwrm_dbg_coredump_initiate_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9760

hwrm_dbg_coredump_initiate_input::instance
__le16 instance
Definition bnxt_hsi.h:9763

hwrm_dbg_coredump_initiate_input::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:9766

hwrm_dbg_coredump_initiate_input::seg_flags
u8 seg_flags
Definition bnxt_hsi.h:9765

hwrm_dbg_coredump_initiate_input::segment_id
__le16 segment_id
Definition bnxt_hsi.h:9762

hwrm_dbg_coredump_initiate_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9759

hwrm_dbg_coredump_initiate_output
Definition bnxt_hsi.h:9770

hwrm_dbg_coredump_initiate_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9771

hwrm_dbg_coredump_initiate_output::valid
u8 valid
Definition bnxt_hsi.h:9776

hwrm_dbg_coredump_initiate_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9775

hwrm_dbg_coredump_initiate_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9772

hwrm_dbg_coredump_initiate_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9773

hwrm_dbg_coredump_initiate_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9774

hwrm_dbg_coredump_list_input
Definition bnxt_hsi.h:9727

hwrm_dbg_coredump_list_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9728

hwrm_dbg_coredump_list_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:9736

hwrm_dbg_coredump_list_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9730

hwrm_dbg_coredump_list_input::host_buf_len
__le32 host_buf_len
Definition bnxt_hsi.h:9734

hwrm_dbg_coredump_list_input::seq_no
__le16 seq_no
Definition bnxt_hsi.h:9735

hwrm_dbg_coredump_list_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9733

hwrm_dbg_coredump_list_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9732

hwrm_dbg_coredump_list_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9729

hwrm_dbg_coredump_list_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9731

hwrm_dbg_coredump_list_output
Definition bnxt_hsi.h:9740

hwrm_dbg_coredump_list_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9743

hwrm_dbg_coredump_list_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:9747

hwrm_dbg_coredump_list_output::flags
u8 flags
Definition bnxt_hsi.h:9745

hwrm_dbg_coredump_list_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9742

hwrm_dbg_coredump_list_output::valid
u8 valid
Definition bnxt_hsi.h:9751

hwrm_dbg_coredump_list_output::unused_1
u8 unused_1
Definition bnxt_hsi.h:9750

hwrm_dbg_coredump_list_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9741

hwrm_dbg_coredump_list_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9744

hwrm_dbg_coredump_list_output::data_len
__le16 data_len
Definition bnxt_hsi.h:9749

hwrm_dbg_coredump_list_output::total_segments
__le16 total_segments
Definition bnxt_hsi.h:9748

hwrm_dbg_coredump_retrieve_input
Definition bnxt_hsi.h:9788

hwrm_dbg_coredump_retrieve_input::component_id
__le16 component_id
Definition bnxt_hsi.h:9797

hwrm_dbg_coredump_retrieve_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9793

hwrm_dbg_coredump_retrieve_input::seq_no
__le32 seq_no
Definition bnxt_hsi.h:9805

hwrm_dbg_coredump_retrieve_input::unused_5
__le32 unused_5
Definition bnxt_hsi.h:9806

hwrm_dbg_coredump_retrieve_input::host_buf_len
__le32 host_buf_len
Definition bnxt_hsi.h:9795

hwrm_dbg_coredump_retrieve_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9794

hwrm_dbg_coredump_retrieve_input::segment_id
__le16 segment_id
Definition bnxt_hsi.h:9798

hwrm_dbg_coredump_retrieve_input::unused_4
__le32 unused_4
Definition bnxt_hsi.h:9804

hwrm_dbg_coredump_retrieve_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9792

hwrm_dbg_coredump_retrieve_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9791

hwrm_dbg_coredump_retrieve_input::unused_0
__le32 unused_0
Definition bnxt_hsi.h:9796

hwrm_dbg_coredump_retrieve_input::unused_2
u8 unused_2
Definition bnxt_hsi.h:9802

hwrm_dbg_coredump_retrieve_input::instance
__le16 instance
Definition bnxt_hsi.h:9799

hwrm_dbg_coredump_retrieve_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9790

hwrm_dbg_coredump_retrieve_input::unused_3
__le16 unused_3
Definition bnxt_hsi.h:9803

hwrm_dbg_coredump_retrieve_input::unused_1
__le16 unused_1
Definition bnxt_hsi.h:9800

hwrm_dbg_coredump_retrieve_input::seg_flags
u8 seg_flags
Definition bnxt_hsi.h:9801

hwrm_dbg_coredump_retrieve_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9789

hwrm_dbg_coredump_retrieve_output
Definition bnxt_hsi.h:9810

hwrm_dbg_coredump_retrieve_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9813

hwrm_dbg_coredump_retrieve_output::valid
u8 valid
Definition bnxt_hsi.h:9820

hwrm_dbg_coredump_retrieve_output::flags
u8 flags
Definition bnxt_hsi.h:9815

hwrm_dbg_coredump_retrieve_output::unused_1
u8 unused_1[3]
Definition bnxt_hsi.h:9819

hwrm_dbg_coredump_retrieve_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9812

hwrm_dbg_coredump_retrieve_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:9817

hwrm_dbg_coredump_retrieve_output::data_len
__le16 data_len
Definition bnxt_hsi.h:9818

hwrm_dbg_coredump_retrieve_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9814

hwrm_dbg_coredump_retrieve_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9811

hwrm_dbg_dump_input
Definition bnxt_hsi.h:9646

hwrm_dbg_dump_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9650

hwrm_dbg_dump_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9649

hwrm_dbg_dump_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9647

hwrm_dbg_dump_input::handle
__le32 handle
Definition bnxt_hsi.h:9652

hwrm_dbg_dump_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9648

hwrm_dbg_dump_input::host_dbg_dump_addr
__le64 host_dbg_dump_addr
Definition bnxt_hsi.h:9654

hwrm_dbg_dump_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:9653

hwrm_dbg_dump_input::host_dbg_dump_addr_len
__le64 host_dbg_dump_addr_len
Definition bnxt_hsi.h:9655

hwrm_dbg_dump_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9651

hwrm_dbg_dump_output
Definition bnxt_hsi.h:9659

hwrm_dbg_dump_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9660

hwrm_dbg_dump_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9661

hwrm_dbg_dump_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9662

hwrm_dbg_dump_output::dbg_data_len
__le32 dbg_data_len
Definition bnxt_hsi.h:9665

hwrm_dbg_dump_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9663

hwrm_dbg_dump_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9666

hwrm_dbg_dump_output::valid
u8 valid
Definition bnxt_hsi.h:9667

hwrm_dbg_dump_output::nexthandle
__le32 nexthandle
Definition bnxt_hsi.h:9664

hwrm_dbg_erase_nvm_input
Definition bnxt_hsi.h:9671

hwrm_dbg_erase_nvm_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9675

hwrm_dbg_erase_nvm_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9673

hwrm_dbg_erase_nvm_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9672

hwrm_dbg_erase_nvm_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9676

hwrm_dbg_erase_nvm_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:9679

hwrm_dbg_erase_nvm_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9674

hwrm_dbg_erase_nvm_input::flags
__le16 flags
Definition bnxt_hsi.h:9677

hwrm_dbg_erase_nvm_output
Definition bnxt_hsi.h:9683

hwrm_dbg_erase_nvm_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9685

hwrm_dbg_erase_nvm_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9688

hwrm_dbg_erase_nvm_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9686

hwrm_dbg_erase_nvm_output::valid
u8 valid
Definition bnxt_hsi.h:9689

hwrm_dbg_erase_nvm_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9684

hwrm_dbg_erase_nvm_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9687

hwrm_dbg_fw_cli_input
Definition bnxt_hsi.h:9857

hwrm_dbg_fw_cli_input::host_buf_len
__le32 host_buf_len
Definition bnxt_hsi.h:9864

hwrm_dbg_fw_cli_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9862

hwrm_dbg_fw_cli_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:9866

hwrm_dbg_fw_cli_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9860

hwrm_dbg_fw_cli_input::cli_cmd
u8 cli_cmd[96]
Definition bnxt_hsi.h:9867

hwrm_dbg_fw_cli_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9859

hwrm_dbg_fw_cli_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9858

hwrm_dbg_fw_cli_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9861

hwrm_dbg_fw_cli_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9863

hwrm_dbg_fw_cli_input::cli_cmd_len
__le16 cli_cmd_len
Definition bnxt_hsi.h:9865

hwrm_dbg_fw_cli_output
Definition bnxt_hsi.h:9871

hwrm_dbg_fw_cli_output::cli_data_len
__le32 cli_data_len
Definition bnxt_hsi.h:9876

hwrm_dbg_fw_cli_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9873

hwrm_dbg_fw_cli_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9875

hwrm_dbg_fw_cli_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:9877

hwrm_dbg_fw_cli_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9874

hwrm_dbg_fw_cli_output::valid
u8 valid
Definition bnxt_hsi.h:9878

hwrm_dbg_fw_cli_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9872

hwrm_dbg_i2c_cmd_input
Definition bnxt_hsi.h:9824

hwrm_dbg_i2c_cmd_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9829

hwrm_dbg_i2c_cmd_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9826

hwrm_dbg_i2c_cmd_input::read_size
__le16 read_size
Definition bnxt_hsi.h:9831

hwrm_dbg_i2c_cmd_input::xfer_mode
u8 xfer_mode
Definition bnxt_hsi.h:9838

hwrm_dbg_i2c_cmd_input::write_size
__le16 write_size
Definition bnxt_hsi.h:9832

hwrm_dbg_i2c_cmd_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9827

hwrm_dbg_i2c_cmd_input::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:9843

hwrm_dbg_i2c_cmd_input::chnl_id
u8 chnl_id
Definition bnxt_hsi.h:9833

hwrm_dbg_i2c_cmd_input::options
u8 options
Definition bnxt_hsi.h:9834

hwrm_dbg_i2c_cmd_input::slave_addr
__le16 slave_addr
Definition bnxt_hsi.h:9837

hwrm_dbg_i2c_cmd_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9830

hwrm_dbg_i2c_cmd_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9828

hwrm_dbg_i2c_cmd_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9825

hwrm_dbg_i2c_cmd_output
Definition bnxt_hsi.h:9847

hwrm_dbg_i2c_cmd_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9848

hwrm_dbg_i2c_cmd_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9850

hwrm_dbg_i2c_cmd_output::valid
u8 valid
Definition bnxt_hsi.h:9853

hwrm_dbg_i2c_cmd_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9851

hwrm_dbg_i2c_cmd_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9852

hwrm_dbg_i2c_cmd_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9849

hwrm_dbg_read_direct_input
Definition bnxt_hsi.h:9512

hwrm_dbg_read_direct_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9515

hwrm_dbg_read_direct_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9517

hwrm_dbg_read_direct_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9513

hwrm_dbg_read_direct_input::read_len32
__le32 read_len32
Definition bnxt_hsi.h:9520

hwrm_dbg_read_direct_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9514

hwrm_dbg_read_direct_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9518

hwrm_dbg_read_direct_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9516

hwrm_dbg_read_direct_input::read_addr
__le32 read_addr
Definition bnxt_hsi.h:9519

hwrm_dbg_read_direct_output
Definition bnxt_hsi.h:9524

hwrm_dbg_read_direct_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9529

hwrm_dbg_read_direct_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9527

hwrm_dbg_read_direct_output::valid
u8 valid
Definition bnxt_hsi.h:9530

hwrm_dbg_read_direct_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9528

hwrm_dbg_read_direct_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9526

hwrm_dbg_read_direct_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9525

hwrm_dbg_read_indirect_input
Definition bnxt_hsi.h:9556

hwrm_dbg_read_indirect_input::start_index
__le32 start_index
Definition bnxt_hsi.h:9586

hwrm_dbg_read_indirect_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9557

hwrm_dbg_read_indirect_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:9585

hwrm_dbg_read_indirect_input::num_of_entries
__le32 num_of_entries
Definition bnxt_hsi.h:9587

hwrm_dbg_read_indirect_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9561

hwrm_dbg_read_indirect_input::indirect_access_type
u8 indirect_access_type
Definition bnxt_hsi.h:9564

hwrm_dbg_read_indirect_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9559

hwrm_dbg_read_indirect_input::host_dest_addr_len
__le32 host_dest_addr_len
Definition bnxt_hsi.h:9563

hwrm_dbg_read_indirect_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9562

hwrm_dbg_read_indirect_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9558

hwrm_dbg_read_indirect_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9560

hwrm_dbg_read_indirect_output
Definition bnxt_hsi.h:9591

hwrm_dbg_read_indirect_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9596

hwrm_dbg_read_indirect_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9592

hwrm_dbg_read_indirect_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9594

hwrm_dbg_read_indirect_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9595

hwrm_dbg_read_indirect_output::valid
u8 valid
Definition bnxt_hsi.h:9597

hwrm_dbg_read_indirect_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9593

hwrm_dbg_ring_info_get_input
Definition bnxt_hsi.h:9882

hwrm_dbg_ring_info_get_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:9893

hwrm_dbg_ring_info_get_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9886

hwrm_dbg_ring_info_get_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9887

hwrm_dbg_ring_info_get_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9883

hwrm_dbg_ring_info_get_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9884

hwrm_dbg_ring_info_get_input::ring_type
u8 ring_type
Definition bnxt_hsi.h:9888

hwrm_dbg_ring_info_get_input::fw_ring_id
__le32 fw_ring_id
Definition bnxt_hsi.h:9894

hwrm_dbg_ring_info_get_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9885

hwrm_dbg_ring_info_get_output
Definition bnxt_hsi.h:9898

hwrm_dbg_ring_info_get_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9905

hwrm_dbg_ring_info_get_output::valid
u8 valid
Definition bnxt_hsi.h:9906

hwrm_dbg_ring_info_get_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9900

hwrm_dbg_ring_info_get_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9901

hwrm_dbg_ring_info_get_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9902

hwrm_dbg_ring_info_get_output::consumer_index
__le32 consumer_index
Definition bnxt_hsi.h:9904

hwrm_dbg_ring_info_get_output::producer_index
__le32 producer_index
Definition bnxt_hsi.h:9903

hwrm_dbg_ring_info_get_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9899

hwrm_dbg_write_direct_input
Definition bnxt_hsi.h:9534

hwrm_dbg_write_direct_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9538

hwrm_dbg_write_direct_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9536

hwrm_dbg_write_direct_input::write_data
__le32 write_data[8]
Definition bnxt_hsi.h:9542

hwrm_dbg_write_direct_input::write_len32
__le32 write_len32
Definition bnxt_hsi.h:9541

hwrm_dbg_write_direct_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9539

hwrm_dbg_write_direct_input::write_addr
__le32 write_addr
Definition bnxt_hsi.h:9540

hwrm_dbg_write_direct_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9537

hwrm_dbg_write_direct_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9535

hwrm_dbg_write_direct_output
Definition bnxt_hsi.h:9546

hwrm_dbg_write_direct_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9548

hwrm_dbg_write_direct_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9547

hwrm_dbg_write_direct_output::valid
u8 valid
Definition bnxt_hsi.h:9552

hwrm_dbg_write_direct_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9550

hwrm_dbg_write_direct_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9549

hwrm_dbg_write_direct_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9551

hwrm_dbg_write_indirect_input
Definition bnxt_hsi.h:9601

hwrm_dbg_write_indirect_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9603

hwrm_dbg_write_indirect_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9606

hwrm_dbg_write_indirect_input::indirect_access_type
u8 indirect_access_type
Definition bnxt_hsi.h:9607

hwrm_dbg_write_indirect_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9604

hwrm_dbg_write_indirect_input::num_of_entries
__le32 num_of_entries
Definition bnxt_hsi.h:9630

hwrm_dbg_write_indirect_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:9628

hwrm_dbg_write_indirect_input::write_data
__le32 write_data[8]
Definition bnxt_hsi.h:9632

hwrm_dbg_write_indirect_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9605

hwrm_dbg_write_indirect_input::start_index
__le32 start_index
Definition bnxt_hsi.h:9629

hwrm_dbg_write_indirect_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:9631

hwrm_dbg_write_indirect_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9602

hwrm_dbg_write_indirect_output
Definition bnxt_hsi.h:9636

hwrm_dbg_write_indirect_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9637

hwrm_dbg_write_indirect_output::valid
u8 valid
Definition bnxt_hsi.h:9642

hwrm_dbg_write_indirect_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9640

hwrm_dbg_write_indirect_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9639

hwrm_dbg_write_indirect_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9638

hwrm_dbg_write_indirect_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9641

hwrm_err_output
Definition bnxt_hsi.h:352

hwrm_err_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:355

hwrm_err_output::req_type
__le16 req_type
Definition bnxt_hsi.h:354

hwrm_err_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:356

hwrm_err_output::opaque_1
__le16 opaque_1
Definition bnxt_hsi.h:358

hwrm_err_output::cmd_err
u8 cmd_err
Definition bnxt_hsi.h:359

hwrm_err_output::opaque_0
__le32 opaque_0
Definition bnxt_hsi.h:357

hwrm_err_output::error_code
__le16 error_code
Definition bnxt_hsi.h:353

hwrm_err_output::valid
u8 valid
Definition bnxt_hsi.h:360

hwrm_error_recovery_qcfg_input
Definition bnxt_hsi.h:1729

hwrm_error_recovery_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1734

hwrm_error_recovery_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1730

hwrm_error_recovery_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1732

hwrm_error_recovery_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1733

hwrm_error_recovery_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1731

hwrm_error_recovery_qcfg_input::unused_0
u8 unused_0[8]
Definition bnxt_hsi.h:1735

hwrm_error_recovery_qcfg_output
Definition bnxt_hsi.h:1739

hwrm_error_recovery_qcfg_output::reset_inprogress_reg_mask
__le32 reset_inprogress_reg_mask
Definition bnxt_hsi.h:1792

hwrm_error_recovery_qcfg_output::delay_after_reset
u8 delay_after_reset[16]
Definition bnxt_hsi.h:1806

hwrm_error_recovery_qcfg_output::reset_reg_val
__le32 reset_reg_val[16]
Definition bnxt_hsi.h:1805

hwrm_error_recovery_qcfg_output::normal_wait_period
__le32 normal_wait_period
Definition bnxt_hsi.h:1749

hwrm_error_recovery_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:1818

hwrm_error_recovery_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1740

hwrm_error_recovery_qcfg_output::master_wait_period
__le32 master_wait_period
Definition bnxt_hsi.h:1748

hwrm_error_recovery_qcfg_output::fw_heartbeat_reg
__le32 fw_heartbeat_reg
Definition bnxt_hsi.h:1762

hwrm_error_recovery_qcfg_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:1793

hwrm_error_recovery_qcfg_output::master_wait_post_reset
__le32 master_wait_post_reset
Definition bnxt_hsi.h:1750

hwrm_error_recovery_qcfg_output::driver_polling_freq
__le32 driver_polling_freq
Definition bnxt_hsi.h:1747

hwrm_error_recovery_qcfg_output::fw_health_status_reg
__le32 fw_health_status_reg
Definition bnxt_hsi.h:1752

hwrm_error_recovery_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1743

hwrm_error_recovery_qcfg_output::fw_reset_cnt_reg
__le32 fw_reset_cnt_reg
Definition bnxt_hsi.h:1772

hwrm_error_recovery_qcfg_output::err_recovery_cnt_reg
__le32 err_recovery_cnt_reg
Definition bnxt_hsi.h:1807

hwrm_error_recovery_qcfg_output::unused_1
u8 unused_1[3]
Definition bnxt_hsi.h:1817

hwrm_error_recovery_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1741

hwrm_error_recovery_qcfg_output::max_bailout_time
__le32 max_bailout_time
Definition bnxt_hsi.h:1751

hwrm_error_recovery_qcfg_output::flags
__le32 flags
Definition bnxt_hsi.h:1744

hwrm_error_recovery_qcfg_output::reset_reg
__le32 reset_reg[16]
Definition bnxt_hsi.h:1795

hwrm_error_recovery_qcfg_output::reg_array_cnt
u8 reg_array_cnt
Definition bnxt_hsi.h:1794

hwrm_error_recovery_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1742

hwrm_error_recovery_qcfg_output::reset_inprogress_reg
__le32 reset_inprogress_reg
Definition bnxt_hsi.h:1782

hwrm_exec_fwd_resp_input
Definition bnxt_hsi.h:9261

hwrm_exec_fwd_resp_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9263

hwrm_exec_fwd_resp_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9265

hwrm_exec_fwd_resp_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:9269

hwrm_exec_fwd_resp_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9266

hwrm_exec_fwd_resp_input::encap_request
__le32 encap_request[26]
Definition bnxt_hsi.h:9267

hwrm_exec_fwd_resp_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9262

hwrm_exec_fwd_resp_input::encap_resp_target_id
__le16 encap_resp_target_id
Definition bnxt_hsi.h:9268

hwrm_exec_fwd_resp_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9264

hwrm_exec_fwd_resp_output
Definition bnxt_hsi.h:9273

hwrm_exec_fwd_resp_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9277

hwrm_exec_fwd_resp_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9274

hwrm_exec_fwd_resp_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9276

hwrm_exec_fwd_resp_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9275

hwrm_exec_fwd_resp_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9278

hwrm_exec_fwd_resp_output::valid
u8 valid
Definition bnxt_hsi.h:9279

hwrm_func_backing_store_cfg_input
Definition bnxt_hsi.h:2155

hwrm_func_backing_store_cfg_input::tqm_ring0_page_dir
__le64 tqm_ring0_page_dir
Definition bnxt_hsi.h:2442

hwrm_func_backing_store_cfg_input::srq_num_l2_entries
__le16 srq_num_l2_entries
Definition bnxt_hsi.h:2470

hwrm_func_backing_store_cfg_input::tim_page_dir
__le64 tim_page_dir
Definition bnxt_hsi.h:2451

hwrm_func_backing_store_cfg_input::tqm_ring4_num_entries
__le32 tqm_ring4_num_entries
Definition bnxt_hsi.h:2461

hwrm_func_backing_store_cfg_input::tqm_ring0_pg_size_tqm_ring0_lvl
u8 tqm_ring0_pg_size_tqm_ring0_lvl
Definition bnxt_hsi.h:2276

hwrm_func_backing_store_cfg_input::tim_entry_size
__le16 tim_entry_size
Definition bnxt_hsi.h:2480

hwrm_func_backing_store_cfg_input::vnic_page_dir
__le64 vnic_page_dir
Definition bnxt_hsi.h:2439

hwrm_func_backing_store_cfg_input::srq_page_dir
__le64 srq_page_dir
Definition bnxt_hsi.h:2437

hwrm_func_backing_store_cfg_input::qp_num_l2_entries
__le16 qp_num_l2_entries
Definition bnxt_hsi.h:2468

hwrm_func_backing_store_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2158

hwrm_func_backing_store_cfg_input::tqm_ring4_page_dir
__le64 tqm_ring4_page_dir
Definition bnxt_hsi.h:2446

hwrm_func_backing_store_cfg_input::mrav_entry_size
__le16 mrav_entry_size
Definition bnxt_hsi.h:2479

hwrm_func_backing_store_cfg_input::tqm_ring2_page_dir
__le64 tqm_ring2_page_dir
Definition bnxt_hsi.h:2444

hwrm_func_backing_store_cfg_input::vnic_num_vnic_entries
__le16 vnic_num_vnic_entries
Definition bnxt_hsi.h:2474

hwrm_func_backing_store_cfg_input::tqm_ring6_num_entries
__le32 tqm_ring6_num_entries
Definition bnxt_hsi.h:2463

hwrm_func_backing_store_cfg_input::tqm_ring6_page_dir
__le64 tqm_ring6_page_dir
Definition bnxt_hsi.h:2448

hwrm_func_backing_store_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2160

hwrm_func_backing_store_cfg_input::tqm_ring7_pg_size_tqm_ring7_lvl
u8 tqm_ring7_pg_size_tqm_ring7_lvl
Definition bnxt_hsi.h:2388

hwrm_func_backing_store_cfg_input::tqm_ring2_pg_size_tqm_ring2_lvl
u8 tqm_ring2_pg_size_tqm_ring2_lvl
Definition bnxt_hsi.h:2308

hwrm_func_backing_store_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2157

hwrm_func_backing_store_cfg_input::tqm_ring5_pg_size_tqm_ring5_lvl
u8 tqm_ring5_pg_size_tqm_ring5_lvl
Definition bnxt_hsi.h:2356

hwrm_func_backing_store_cfg_input::tqm_ring1_num_entries
__le32 tqm_ring1_num_entries
Definition bnxt_hsi.h:2458

hwrm_func_backing_store_cfg_input::qp_entry_size
__le16 qp_entry_size
Definition bnxt_hsi.h:2469

hwrm_func_backing_store_cfg_input::qpc_pg_size_qpc_lvl
u8 qpc_pg_size_qpc_lvl
Definition bnxt_hsi.h:2180

hwrm_func_backing_store_cfg_input::stat_pg_size_stat_lvl
u8 stat_pg_size_stat_lvl
Definition bnxt_hsi.h:2244

hwrm_func_backing_store_cfg_input::tqm_sp_num_entries
__le32 tqm_sp_num_entries
Definition bnxt_hsi.h:2456

hwrm_func_backing_store_cfg_input::tqm_ring7_num_entries
__le32 tqm_ring7_num_entries
Definition bnxt_hsi.h:2464

hwrm_func_backing_store_cfg_input::tqm_ring1_page_dir
__le64 tqm_ring1_page_dir
Definition bnxt_hsi.h:2443

hwrm_func_backing_store_cfg_input::tqm_entry_size
__le16 tqm_entry_size
Definition bnxt_hsi.h:2478

hwrm_func_backing_store_cfg_input::cq_pg_size_cq_lvl
u8 cq_pg_size_cq_lvl
Definition bnxt_hsi.h:2212

hwrm_func_backing_store_cfg_input::qpc_page_dir
__le64 qpc_page_dir
Definition bnxt_hsi.h:2436

hwrm_func_backing_store_cfg_input::srq_pg_size_srq_lvl
u8 srq_pg_size_srq_lvl
Definition bnxt_hsi.h:2196

hwrm_func_backing_store_cfg_input::tim_pg_size_tim_lvl
u8 tim_pg_size_tim_lvl
Definition bnxt_hsi.h:2420

hwrm_func_backing_store_cfg_input::vnic_num_ring_table_entries
__le16 vnic_num_ring_table_entries
Definition bnxt_hsi.h:2475

hwrm_func_backing_store_cfg_input::cq_page_dir
__le64 cq_page_dir
Definition bnxt_hsi.h:2438

hwrm_func_backing_store_cfg_input::tqm_ring3_num_entries
__le32 tqm_ring3_num_entries
Definition bnxt_hsi.h:2460

hwrm_func_backing_store_cfg_input::qp_num_entries
__le32 qp_num_entries
Definition bnxt_hsi.h:2452

hwrm_func_backing_store_cfg_input::qp_num_qp1_entries
__le16 qp_num_qp1_entries
Definition bnxt_hsi.h:2467

hwrm_func_backing_store_cfg_input::stat_page_dir
__le64 stat_page_dir
Definition bnxt_hsi.h:2440

hwrm_func_backing_store_cfg_input::tqm_ring4_pg_size_tqm_ring4_lvl
u8 tqm_ring4_pg_size_tqm_ring4_lvl
Definition bnxt_hsi.h:2340

hwrm_func_backing_store_cfg_input::mrav_pg_size_mrav_lvl
u8 mrav_pg_size_mrav_lvl
Definition bnxt_hsi.h:2404

hwrm_func_backing_store_cfg_input::tqm_ring2_num_entries
__le32 tqm_ring2_num_entries
Definition bnxt_hsi.h:2459

hwrm_func_backing_store_cfg_input::vnic_pg_size_vnic_lvl
u8 vnic_pg_size_vnic_lvl
Definition bnxt_hsi.h:2228

hwrm_func_backing_store_cfg_input::tqm_sp_pg_size_tqm_sp_lvl
u8 tqm_sp_pg_size_tqm_sp_lvl
Definition bnxt_hsi.h:2260

hwrm_func_backing_store_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2156

hwrm_func_backing_store_cfg_input::tim_num_entries
__le32 tim_num_entries
Definition bnxt_hsi.h:2466

hwrm_func_backing_store_cfg_input::tqm_ring0_num_entries
__le32 tqm_ring0_num_entries
Definition bnxt_hsi.h:2457

hwrm_func_backing_store_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:2161

hwrm_func_backing_store_cfg_input::tqm_ring5_num_entries
__le32 tqm_ring5_num_entries
Definition bnxt_hsi.h:2462

hwrm_func_backing_store_cfg_input::tqm_ring5_page_dir
__le64 tqm_ring5_page_dir
Definition bnxt_hsi.h:2447

hwrm_func_backing_store_cfg_input::tqm_sp_page_dir
__le64 tqm_sp_page_dir
Definition bnxt_hsi.h:2441

hwrm_func_backing_store_cfg_input::srq_num_entries
__le32 srq_num_entries
Definition bnxt_hsi.h:2453

hwrm_func_backing_store_cfg_input::tqm_ring1_pg_size_tqm_ring1_lvl
u8 tqm_ring1_pg_size_tqm_ring1_lvl
Definition bnxt_hsi.h:2292

hwrm_func_backing_store_cfg_input::cq_num_entries
__le32 cq_num_entries
Definition bnxt_hsi.h:2454

hwrm_func_backing_store_cfg_input::tqm_ring3_pg_size_tqm_ring3_lvl
u8 tqm_ring3_pg_size_tqm_ring3_lvl
Definition bnxt_hsi.h:2324

hwrm_func_backing_store_cfg_input::cq_num_l2_entries
__le16 cq_num_l2_entries
Definition bnxt_hsi.h:2472

hwrm_func_backing_store_cfg_input::stat_num_entries
__le32 stat_num_entries
Definition bnxt_hsi.h:2455

hwrm_func_backing_store_cfg_input::mrav_page_dir
__le64 mrav_page_dir
Definition bnxt_hsi.h:2450

hwrm_func_backing_store_cfg_input::srq_entry_size
__le16 srq_entry_size
Definition bnxt_hsi.h:2471

hwrm_func_backing_store_cfg_input::stat_entry_size
__le16 stat_entry_size
Definition bnxt_hsi.h:2477

hwrm_func_backing_store_cfg_input::vnic_entry_size
__le16 vnic_entry_size
Definition bnxt_hsi.h:2476

hwrm_func_backing_store_cfg_input::tqm_ring3_page_dir
__le64 tqm_ring3_page_dir
Definition bnxt_hsi.h:2445

hwrm_func_backing_store_cfg_input::mrav_num_entries
__le32 mrav_num_entries
Definition bnxt_hsi.h:2465

hwrm_func_backing_store_cfg_input::tqm_ring6_pg_size_tqm_ring6_lvl
u8 tqm_ring6_pg_size_tqm_ring6_lvl
Definition bnxt_hsi.h:2372

hwrm_func_backing_store_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2159

hwrm_func_backing_store_cfg_input::tqm_ring7_page_dir
__le64 tqm_ring7_page_dir
Definition bnxt_hsi.h:2449

hwrm_func_backing_store_cfg_input::cq_entry_size
__le16 cq_entry_size
Definition bnxt_hsi.h:2473

hwrm_func_backing_store_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:2163

hwrm_func_backing_store_cfg_output
Definition bnxt_hsi.h:2484

hwrm_func_backing_store_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2488

hwrm_func_backing_store_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:2489

hwrm_func_backing_store_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2486

hwrm_func_backing_store_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2487

hwrm_func_backing_store_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2485

hwrm_func_backing_store_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:2490

hwrm_func_backing_store_qcaps_input
Definition bnxt_hsi.h:2113

hwrm_func_backing_store_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2118

hwrm_func_backing_store_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2115

hwrm_func_backing_store_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2116

hwrm_func_backing_store_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2117

hwrm_func_backing_store_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2114

hwrm_func_backing_store_qcaps_output
Definition bnxt_hsi.h:2122

hwrm_func_backing_store_qcaps_output::tim_max_entries
__le32 tim_max_entries
Definition bnxt_hsi.h:2148

hwrm_func_backing_store_qcaps_output::stat_max_entries
__le32 stat_max_entries
Definition bnxt_hsi.h:2140

hwrm_func_backing_store_qcaps_output::srq_entry_size
__le16 srq_entry_size
Definition bnxt_hsi.h:2133

hwrm_func_backing_store_qcaps_output::cq_entry_size
__le16 cq_entry_size
Definition bnxt_hsi.h:2136

hwrm_func_backing_store_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2126

hwrm_func_backing_store_qcaps_output::vnic_max_ring_table_entries
__le16 vnic_max_ring_table_entries
Definition bnxt_hsi.h:2138

hwrm_func_backing_store_qcaps_output::cq_max_l2_entries
__le16 cq_max_l2_entries
Definition bnxt_hsi.h:2134

hwrm_func_backing_store_qcaps_output::mrav_entry_size
__le16 mrav_entry_size
Definition bnxt_hsi.h:2146

hwrm_func_backing_store_qcaps_output::vnic_max_vnic_entries
__le16 vnic_max_vnic_entries
Definition bnxt_hsi.h:2137

hwrm_func_backing_store_qcaps_output::tqm_entry_size
__le16 tqm_entry_size
Definition bnxt_hsi.h:2142

hwrm_func_backing_store_qcaps_output::tqm_max_entries_per_ring
__le32 tqm_max_entries_per_ring
Definition bnxt_hsi.h:2144

hwrm_func_backing_store_qcaps_output::qp_max_entries
__le32 qp_max_entries
Definition bnxt_hsi.h:2127

hwrm_func_backing_store_qcaps_output::stat_entry_size
__le16 stat_entry_size
Definition bnxt_hsi.h:2141

hwrm_func_backing_store_qcaps_output::srq_max_entries
__le32 srq_max_entries
Definition bnxt_hsi.h:2132

hwrm_func_backing_store_qcaps_output::tqm_entries_multiple
u8 tqm_entries_multiple
Definition bnxt_hsi.h:2150

hwrm_func_backing_store_qcaps_output::qp_entry_size
__le16 qp_entry_size
Definition bnxt_hsi.h:2130

hwrm_func_backing_store_qcaps_output::qp_max_l2_entries
__le16 qp_max_l2_entries
Definition bnxt_hsi.h:2129

hwrm_func_backing_store_qcaps_output::qp_min_qp1_entries
__le16 qp_min_qp1_entries
Definition bnxt_hsi.h:2128

hwrm_func_backing_store_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2124

hwrm_func_backing_store_qcaps_output::vnic_entry_size
__le16 vnic_entry_size
Definition bnxt_hsi.h:2139

hwrm_func_backing_store_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2125

hwrm_func_backing_store_qcaps_output::cq_max_entries
__le32 cq_max_entries
Definition bnxt_hsi.h:2135

hwrm_func_backing_store_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2123

hwrm_func_backing_store_qcaps_output::tim_entry_size
__le16 tim_entry_size
Definition bnxt_hsi.h:2147

hwrm_func_backing_store_qcaps_output::tqm_min_entries_per_ring
__le32 tqm_min_entries_per_ring
Definition bnxt_hsi.h:2143

hwrm_func_backing_store_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:2151

hwrm_func_backing_store_qcaps_output::mrav_max_entries
__le32 mrav_max_entries
Definition bnxt_hsi.h:2145

hwrm_func_backing_store_qcaps_output::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:2149

hwrm_func_backing_store_qcaps_output::srq_max_l2_entries
__le16 srq_max_l2_entries
Definition bnxt_hsi.h:2131

hwrm_func_backing_store_qcfg_input
Definition bnxt_hsi.h:2494

hwrm_func_backing_store_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2499

hwrm_func_backing_store_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2497

hwrm_func_backing_store_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2496

hwrm_func_backing_store_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2498

hwrm_func_backing_store_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2495

hwrm_func_backing_store_qcfg_output
Definition bnxt_hsi.h:2503

hwrm_func_backing_store_qcfg_output::tqm_ring7_page_dir
__le64 tqm_ring7_page_dir
Definition bnxt_hsi.h:2796

hwrm_func_backing_store_qcfg_output::tqm_ring4_num_entries
__le32 tqm_ring4_num_entries
Definition bnxt_hsi.h:2814

hwrm_func_backing_store_qcfg_output::tqm_ring2_pg_size_tqm_ring2_lvl
u8 tqm_ring2_pg_size_tqm_ring2_lvl
Definition bnxt_hsi.h:2655

hwrm_func_backing_store_qcfg_output::cq_pg_size_cq_lvl
u8 cq_pg_size_cq_lvl
Definition bnxt_hsi.h:2559

hwrm_func_backing_store_qcfg_output::vnic_pg_size_vnic_lvl
u8 vnic_pg_size_vnic_lvl
Definition bnxt_hsi.h:2575

hwrm_func_backing_store_qcfg_output::tqm_ring3_page_dir
__le64 tqm_ring3_page_dir
Definition bnxt_hsi.h:2792

hwrm_func_backing_store_qcfg_output::tim_pg_size_tim_lvl
u8 tim_pg_size_tim_lvl
Definition bnxt_hsi.h:2767

hwrm_func_backing_store_qcfg_output::tqm_ring2_page_dir
__le64 tqm_ring2_page_dir
Definition bnxt_hsi.h:2791

hwrm_func_backing_store_qcfg_output::mrav_pg_size_mrav_lvl
u8 mrav_pg_size_mrav_lvl
Definition bnxt_hsi.h:2751

hwrm_func_backing_store_qcfg_output::srq_num_entries
__le32 srq_num_entries
Definition bnxt_hsi.h:2802

hwrm_func_backing_store_qcfg_output::tqm_ring6_page_dir
__le64 tqm_ring6_page_dir
Definition bnxt_hsi.h:2795

hwrm_func_backing_store_qcfg_output::flags
__le32 flags
Definition bnxt_hsi.h:2508

hwrm_func_backing_store_qcfg_output::qpc_pg_size_qpc_lvl
u8 qpc_pg_size_qpc_lvl
Definition bnxt_hsi.h:2527

hwrm_func_backing_store_qcfg_output::stat_pg_size_stat_lvl
u8 stat_pg_size_stat_lvl
Definition bnxt_hsi.h:2591

hwrm_func_backing_store_qcfg_output::vnic_page_dir
__le64 vnic_page_dir
Definition bnxt_hsi.h:2786

hwrm_func_backing_store_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:2821

hwrm_func_backing_store_qcfg_output::mrav_num_entries
__le32 mrav_num_entries
Definition bnxt_hsi.h:2818

hwrm_func_backing_store_qcfg_output::tqm_ring6_pg_size_tqm_ring6_lvl
u8 tqm_ring6_pg_size_tqm_ring6_lvl
Definition bnxt_hsi.h:2719

hwrm_func_backing_store_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2506

hwrm_func_backing_store_qcfg_output::tim_num_entries
__le32 tim_num_entries
Definition bnxt_hsi.h:2819

hwrm_func_backing_store_qcfg_output::tqm_ring1_pg_size_tqm_ring1_lvl
u8 tqm_ring1_pg_size_tqm_ring1_lvl
Definition bnxt_hsi.h:2639

hwrm_func_backing_store_qcfg_output::srq_num_l2_entries
__le16 srq_num_l2_entries
Definition bnxt_hsi.h:2803

hwrm_func_backing_store_qcfg_output::tqm_ring4_pg_size_tqm_ring4_lvl
u8 tqm_ring4_pg_size_tqm_ring4_lvl
Definition bnxt_hsi.h:2687

hwrm_func_backing_store_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2504

hwrm_func_backing_store_qcfg_output::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:2510

hwrm_func_backing_store_qcfg_output::tqm_ring5_num_entries
__le32 tqm_ring5_num_entries
Definition bnxt_hsi.h:2815

hwrm_func_backing_store_qcfg_output::cq_page_dir
__le64 cq_page_dir
Definition bnxt_hsi.h:2785

hwrm_func_backing_store_qcfg_output::tim_page_dir
__le64 tim_page_dir
Definition bnxt_hsi.h:2798

hwrm_func_backing_store_qcfg_output::qpc_page_dir
__le64 qpc_page_dir
Definition bnxt_hsi.h:2783

hwrm_func_backing_store_qcfg_output::tqm_ring5_pg_size_tqm_ring5_lvl
u8 tqm_ring5_pg_size_tqm_ring5_lvl
Definition bnxt_hsi.h:2703

hwrm_func_backing_store_qcfg_output::tqm_ring2_num_entries
__le32 tqm_ring2_num_entries
Definition bnxt_hsi.h:2812

hwrm_func_backing_store_qcfg_output::stat_page_dir
__le64 stat_page_dir
Definition bnxt_hsi.h:2787

hwrm_func_backing_store_qcfg_output::tqm_ring7_num_entries
__le32 tqm_ring7_num_entries
Definition bnxt_hsi.h:2817

hwrm_func_backing_store_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2505

hwrm_func_backing_store_qcfg_output::srq_pg_size_srq_lvl
u8 srq_pg_size_srq_lvl
Definition bnxt_hsi.h:2543

hwrm_func_backing_store_qcfg_output::stat_num_entries
__le32 stat_num_entries
Definition bnxt_hsi.h:2808

hwrm_func_backing_store_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2507

hwrm_func_backing_store_qcfg_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:2820

hwrm_func_backing_store_qcfg_output::tqm_ring3_num_entries
__le32 tqm_ring3_num_entries
Definition bnxt_hsi.h:2813

hwrm_func_backing_store_qcfg_output::qp_num_entries
__le32 qp_num_entries
Definition bnxt_hsi.h:2801

hwrm_func_backing_store_qcfg_output::vnic_num_vnic_entries
__le16 vnic_num_vnic_entries
Definition bnxt_hsi.h:2806

hwrm_func_backing_store_qcfg_output::cq_num_l2_entries
__le16 cq_num_l2_entries
Definition bnxt_hsi.h:2804

hwrm_func_backing_store_qcfg_output::tqm_sp_num_entries
__le32 tqm_sp_num_entries
Definition bnxt_hsi.h:2809

hwrm_func_backing_store_qcfg_output::tqm_ring1_num_entries
__le32 tqm_ring1_num_entries
Definition bnxt_hsi.h:2811

hwrm_func_backing_store_qcfg_output::mrav_page_dir
__le64 mrav_page_dir
Definition bnxt_hsi.h:2797

hwrm_func_backing_store_qcfg_output::tqm_ring3_pg_size_tqm_ring3_lvl
u8 tqm_ring3_pg_size_tqm_ring3_lvl
Definition bnxt_hsi.h:2671

hwrm_func_backing_store_qcfg_output::tqm_ring1_page_dir
__le64 tqm_ring1_page_dir
Definition bnxt_hsi.h:2790

hwrm_func_backing_store_qcfg_output::vnic_num_ring_table_entries
__le16 vnic_num_ring_table_entries
Definition bnxt_hsi.h:2807

hwrm_func_backing_store_qcfg_output::tqm_ring4_page_dir
__le64 tqm_ring4_page_dir
Definition bnxt_hsi.h:2793

hwrm_func_backing_store_qcfg_output::tqm_ring0_pg_size_tqm_ring0_lvl
u8 tqm_ring0_pg_size_tqm_ring0_lvl
Definition bnxt_hsi.h:2623

hwrm_func_backing_store_qcfg_output::tqm_sp_page_dir
__le64 tqm_sp_page_dir
Definition bnxt_hsi.h:2788

hwrm_func_backing_store_qcfg_output::tqm_ring0_num_entries
__le32 tqm_ring0_num_entries
Definition bnxt_hsi.h:2810

hwrm_func_backing_store_qcfg_output::tqm_sp_pg_size_tqm_sp_lvl
u8 tqm_sp_pg_size_tqm_sp_lvl
Definition bnxt_hsi.h:2607

hwrm_func_backing_store_qcfg_output::tqm_ring6_num_entries
__le32 tqm_ring6_num_entries
Definition bnxt_hsi.h:2816

hwrm_func_backing_store_qcfg_output::srq_page_dir
__le64 srq_page_dir
Definition bnxt_hsi.h:2784

hwrm_func_backing_store_qcfg_output::cq_num_entries
__le32 cq_num_entries
Definition bnxt_hsi.h:2805

hwrm_func_backing_store_qcfg_output::tqm_ring7_pg_size_tqm_ring7_lvl
u8 tqm_ring7_pg_size_tqm_ring7_lvl
Definition bnxt_hsi.h:2735

hwrm_func_backing_store_qcfg_output::qp_num_qp1_entries
__le16 qp_num_qp1_entries
Definition bnxt_hsi.h:2799

hwrm_func_backing_store_qcfg_output::tqm_ring0_page_dir
__le64 tqm_ring0_page_dir
Definition bnxt_hsi.h:2789

hwrm_func_backing_store_qcfg_output::tqm_ring5_page_dir
__le64 tqm_ring5_page_dir
Definition bnxt_hsi.h:2794

hwrm_func_backing_store_qcfg_output::qp_num_l2_entries
__le16 qp_num_l2_entries
Definition bnxt_hsi.h:2800

hwrm_func_buf_rgtr_input
Definition bnxt_hsi.h:1904

hwrm_func_buf_rgtr_input::req_buf_page_addr2
__le64 req_buf_page_addr2
Definition bnxt_hsi.h:1929

hwrm_func_buf_rgtr_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1905

hwrm_func_buf_rgtr_input::req_buf_page_addr6
__le64 req_buf_page_addr6
Definition bnxt_hsi.h:1933

hwrm_func_buf_rgtr_input::req_buf_page_addr3
__le64 req_buf_page_addr3
Definition bnxt_hsi.h:1930

hwrm_func_buf_rgtr_input::req_buf_len
__le16 req_buf_len
Definition bnxt_hsi.h:1924

hwrm_func_buf_rgtr_input::req_buf_page_addr7
__le64 req_buf_page_addr7
Definition bnxt_hsi.h:1934

hwrm_func_buf_rgtr_input::vf_id
__le16 vf_id
Definition bnxt_hsi.h:1913

hwrm_func_buf_rgtr_input::req_buf_page_addr1
__le64 req_buf_page_addr1
Definition bnxt_hsi.h:1928

hwrm_func_buf_rgtr_input::req_buf_num_pages
__le16 req_buf_num_pages
Definition bnxt_hsi.h:1914

hwrm_func_buf_rgtr_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1908

hwrm_func_buf_rgtr_input::req_buf_page_addr8
__le64 req_buf_page_addr8
Definition bnxt_hsi.h:1935

hwrm_func_buf_rgtr_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1907

hwrm_func_buf_rgtr_input::resp_buf_len
__le16 resp_buf_len
Definition bnxt_hsi.h:1925

hwrm_func_buf_rgtr_input::req_buf_page_addr4
__le64 req_buf_page_addr4
Definition bnxt_hsi.h:1931

hwrm_func_buf_rgtr_input::resp_buf_addr
__le64 resp_buf_addr
Definition bnxt_hsi.h:1938

hwrm_func_buf_rgtr_input::enables
__le32 enables
Definition bnxt_hsi.h:1910

hwrm_func_buf_rgtr_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1909

hwrm_func_buf_rgtr_input::error_buf_addr
__le64 error_buf_addr
Definition bnxt_hsi.h:1937

hwrm_func_buf_rgtr_input::req_buf_page_size
__le16 req_buf_page_size
Definition bnxt_hsi.h:1915

hwrm_func_buf_rgtr_input::req_buf_page_addr5
__le64 req_buf_page_addr5
Definition bnxt_hsi.h:1932

hwrm_func_buf_rgtr_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:1926

hwrm_func_buf_rgtr_input::req_buf_page_addr0
__le64 req_buf_page_addr0
Definition bnxt_hsi.h:1927

hwrm_func_buf_rgtr_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1906

hwrm_func_buf_rgtr_input::req_buf_page_addr9
__le64 req_buf_page_addr9
Definition bnxt_hsi.h:1936

hwrm_func_buf_rgtr_output
Definition bnxt_hsi.h:1942

hwrm_func_buf_rgtr_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1944

hwrm_func_buf_rgtr_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1946

hwrm_func_buf_rgtr_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1945

hwrm_func_buf_rgtr_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1943

hwrm_func_buf_rgtr_output::valid
u8 valid
Definition bnxt_hsi.h:1948

hwrm_func_buf_rgtr_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1947

hwrm_func_buf_unrgtr_input
Definition bnxt_hsi.h:1952

hwrm_func_buf_unrgtr_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1955

hwrm_func_buf_unrgtr_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1957

hwrm_func_buf_unrgtr_input::enables
__le32 enables
Definition bnxt_hsi.h:1958

hwrm_func_buf_unrgtr_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1956

hwrm_func_buf_unrgtr_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:1961

hwrm_func_buf_unrgtr_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1954

hwrm_func_buf_unrgtr_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1953

hwrm_func_buf_unrgtr_input::vf_id
__le16 vf_id
Definition bnxt_hsi.h:1960

hwrm_func_buf_unrgtr_output
Definition bnxt_hsi.h:1965

hwrm_func_buf_unrgtr_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1970

hwrm_func_buf_unrgtr_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1966

hwrm_func_buf_unrgtr_output::valid
u8 valid
Definition bnxt_hsi.h:1971

hwrm_func_buf_unrgtr_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1967

hwrm_func_buf_unrgtr_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1969

hwrm_func_buf_unrgtr_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1968

hwrm_func_cfg_input
Definition bnxt_hsi.h:1509

hwrm_func_cfg_input::num_mcast_filters
__le16 num_mcast_filters
Definition bnxt_hsi.h:1632

hwrm_func_cfg_input::max_bw
__le32 max_bw
Definition bnxt_hsi.h:1589

hwrm_func_cfg_input::dflt_mac_addr
u8 dflt_mac_addr[6]
Definition bnxt_hsi.h:1570

hwrm_func_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:1536

hwrm_func_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1510

hwrm_func_cfg_input::options
u8 options
Definition bnxt_hsi.h:1618

hwrm_func_cfg_input::fid
__le16 fid
Definition bnxt_hsi.h:1515

hwrm_func_cfg_input::allowed_vlan_pris
u8 allowed_vlan_pris
Definition bnxt_hsi.h:1612

hwrm_func_cfg_input::num_tx_rings
__le16 num_tx_rings
Definition bnxt_hsi.h:1564

hwrm_func_cfg_input::dflt_vlan
__le16 dflt_vlan
Definition bnxt_hsi.h:1571

hwrm_func_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:1517

hwrm_func_cfg_input::num_cmpl_rings
__le16 num_cmpl_rings
Definition bnxt_hsi.h:1563

hwrm_func_cfg_input::num_stat_ctxs
__le16 num_stat_ctxs
Definition bnxt_hsi.h:1568

hwrm_func_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1514

hwrm_func_cfg_input::num_l2_ctxs
__le16 num_l2_ctxs
Definition bnxt_hsi.h:1566

hwrm_func_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1513

hwrm_func_cfg_input::num_msix
__le16 num_msix
Definition bnxt_hsi.h:1516

hwrm_func_cfg_input::num_rsscos_ctxs
__le16 num_rsscos_ctxs
Definition bnxt_hsi.h:1562

hwrm_func_cfg_input::vlan_antispoof_mode
u8 vlan_antispoof_mode
Definition bnxt_hsi.h:1606

hwrm_func_cfg_input::num_hw_ring_grps
__le16 num_hw_ring_grps
Definition bnxt_hsi.h:1569

hwrm_func_cfg_input::mru
__le16 mru
Definition bnxt_hsi.h:1561

hwrm_func_cfg_input::mtu
__le16 mtu
Definition bnxt_hsi.h:1560

hwrm_func_cfg_input::num_vnics
__le16 num_vnics
Definition bnxt_hsi.h:1567

hwrm_func_cfg_input::min_bw
__le32 min_bw
Definition bnxt_hsi.h:1573

hwrm_func_cfg_input::num_rx_rings
__le16 num_rx_rings
Definition bnxt_hsi.h:1565

hwrm_func_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1511

hwrm_func_cfg_input::evb_mode
u8 evb_mode
Definition bnxt_hsi.h:1613

hwrm_func_cfg_input::async_event_cr
__le16 async_event_cr
Definition bnxt_hsi.h:1605

hwrm_func_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1512

hwrm_func_cfg_input::dflt_ip_addr
__be32 dflt_ip_addr[4]
Definition bnxt_hsi.h:1572

hwrm_func_cfg_output
Definition bnxt_hsi.h:1636

hwrm_func_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1639

hwrm_func_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1640

hwrm_func_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1637

hwrm_func_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:1642

hwrm_func_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1641

hwrm_func_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1638

hwrm_func_clr_stats_input
Definition bnxt_hsi.h:1687

hwrm_func_clr_stats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1690

hwrm_func_clr_stats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1688

hwrm_func_clr_stats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1691

hwrm_func_clr_stats_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:1694

hwrm_func_clr_stats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1689

hwrm_func_clr_stats_input::fid
__le16 fid
Definition bnxt_hsi.h:1693

hwrm_func_clr_stats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1692

hwrm_func_clr_stats_output
Definition bnxt_hsi.h:1698

hwrm_func_clr_stats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1702

hwrm_func_clr_stats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1700

hwrm_func_clr_stats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1701

hwrm_func_clr_stats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1699

hwrm_func_clr_stats_output::valid
u8 valid
Definition bnxt_hsi.h:1704

hwrm_func_clr_stats_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1703

hwrm_func_drv_if_change_input
Definition bnxt_hsi.h:3011

hwrm_func_drv_if_change_input::req_type
__le16 req_type
Definition bnxt_hsi.h:3012

hwrm_func_drv_if_change_input::flags
__le32 flags
Definition bnxt_hsi.h:3017

hwrm_func_drv_if_change_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3014

hwrm_func_drv_if_change_input::unused
__le32 unused
Definition bnxt_hsi.h:3019

hwrm_func_drv_if_change_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:3013

hwrm_func_drv_if_change_input::target_id
__le16 target_id
Definition bnxt_hsi.h:3015

hwrm_func_drv_if_change_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:3016

hwrm_func_drv_if_change_output
Definition bnxt_hsi.h:3023

hwrm_func_drv_if_change_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:3027

hwrm_func_drv_if_change_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:3030

hwrm_func_drv_if_change_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3026

hwrm_func_drv_if_change_output::error_code
__le16 error_code
Definition bnxt_hsi.h:3024

hwrm_func_drv_if_change_output::req_type
__le16 req_type
Definition bnxt_hsi.h:3025

hwrm_func_drv_if_change_output::valid
u8 valid
Definition bnxt_hsi.h:3031

hwrm_func_drv_if_change_output::flags
__le32 flags
Definition bnxt_hsi.h:3028

hwrm_func_drv_qver_input
Definition bnxt_hsi.h:1975

hwrm_func_drv_qver_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1979

hwrm_func_drv_qver_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1976

hwrm_func_drv_qver_input::fid
__le16 fid
Definition bnxt_hsi.h:1982

hwrm_func_drv_qver_input::reserved
__le32 reserved
Definition bnxt_hsi.h:1981

hwrm_func_drv_qver_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1978

hwrm_func_drv_qver_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:1983

hwrm_func_drv_qver_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1977

hwrm_func_drv_qver_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1980

hwrm_func_drv_qver_output
Definition bnxt_hsi.h:1987

hwrm_func_drv_qver_output::ver_min_8b
u8 ver_min_8b
Definition bnxt_hsi.h:2006

hwrm_func_drv_qver_output::ver_patch
__le16 ver_patch
Definition bnxt_hsi.h:2012

hwrm_func_drv_qver_output::ver_upd
__le16 ver_upd
Definition bnxt_hsi.h:2011

hwrm_func_drv_qver_output::os_type
__le16 os_type
Definition bnxt_hsi.h:1992

hwrm_func_drv_qver_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1990

hwrm_func_drv_qver_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1989

hwrm_func_drv_qver_output::ver_maj
__le16 ver_maj
Definition bnxt_hsi.h:2009

hwrm_func_drv_qver_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:2008

hwrm_func_drv_qver_output::ver_upd_8b
u8 ver_upd_8b
Definition bnxt_hsi.h:2007

hwrm_func_drv_qver_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1991

hwrm_func_drv_qver_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1988

hwrm_func_drv_qver_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:2013

hwrm_func_drv_qver_output::ver_min
__le16 ver_min
Definition bnxt_hsi.h:2010

hwrm_func_drv_qver_output::valid
u8 valid
Definition bnxt_hsi.h:2014

hwrm_func_drv_qver_output::ver_maj_8b
u8 ver_maj_8b
Definition bnxt_hsi.h:2005

hwrm_func_drv_rgtr_input
Definition bnxt_hsi.h:1822

hwrm_func_drv_rgtr_input::ver_maj_8b
u8 ver_maj_8b
Definition bnxt_hsi.h:1855

hwrm_func_drv_rgtr_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:1860

hwrm_func_drv_rgtr_input::flags
__le32 flags
Definition bnxt_hsi.h:1828

hwrm_func_drv_rgtr_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1827

hwrm_func_drv_rgtr_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1826

hwrm_func_drv_rgtr_input::timestamp
__le32 timestamp
Definition bnxt_hsi.h:1859

hwrm_func_drv_rgtr_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1825

hwrm_func_drv_rgtr_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:1858

hwrm_func_drv_rgtr_input::vf_req_fwd
__le32 vf_req_fwd[8]
Definition bnxt_hsi.h:1861

hwrm_func_drv_rgtr_input::ver_maj
__le16 ver_maj
Definition bnxt_hsi.h:1863

hwrm_func_drv_rgtr_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1824

hwrm_func_drv_rgtr_input::ver_min_8b
u8 ver_min_8b
Definition bnxt_hsi.h:1856

hwrm_func_drv_rgtr_input::ver_min
__le16 ver_min
Definition bnxt_hsi.h:1864

hwrm_func_drv_rgtr_input::os_type
__le16 os_type
Definition bnxt_hsi.h:1842

hwrm_func_drv_rgtr_input::ver_upd
__le16 ver_upd
Definition bnxt_hsi.h:1865

hwrm_func_drv_rgtr_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1823

hwrm_func_drv_rgtr_input::async_event_fwd
__le32 async_event_fwd[8]
Definition bnxt_hsi.h:1862

hwrm_func_drv_rgtr_input::ver_upd_8b
u8 ver_upd_8b
Definition bnxt_hsi.h:1857

hwrm_func_drv_rgtr_input::enables
__le32 enables
Definition bnxt_hsi.h:1836

hwrm_func_drv_rgtr_input::ver_patch
__le16 ver_patch
Definition bnxt_hsi.h:1866

hwrm_func_drv_rgtr_output
Definition bnxt_hsi.h:1870

hwrm_func_drv_rgtr_output::valid
u8 valid
Definition bnxt_hsi.h:1878

hwrm_func_drv_rgtr_output::flags
__le32 flags
Definition bnxt_hsi.h:1875

hwrm_func_drv_rgtr_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:1877

hwrm_func_drv_rgtr_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1874

hwrm_func_drv_rgtr_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1871

hwrm_func_drv_rgtr_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1873

hwrm_func_drv_rgtr_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1872

hwrm_func_drv_unrgtr_input
Definition bnxt_hsi.h:1882

hwrm_func_drv_unrgtr_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1885

hwrm_func_drv_unrgtr_input::flags
__le32 flags
Definition bnxt_hsi.h:1888

hwrm_func_drv_unrgtr_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1887

hwrm_func_drv_unrgtr_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1886

hwrm_func_drv_unrgtr_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:1890

hwrm_func_drv_unrgtr_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1883

hwrm_func_drv_unrgtr_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1884

hwrm_func_drv_unrgtr_output
Definition bnxt_hsi.h:1894

hwrm_func_drv_unrgtr_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1898

hwrm_func_drv_unrgtr_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1895

hwrm_func_drv_unrgtr_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1897

hwrm_func_drv_unrgtr_output::valid
u8 valid
Definition bnxt_hsi.h:1900

hwrm_func_drv_unrgtr_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1896

hwrm_func_drv_unrgtr_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1899

hwrm_func_getfid_input
Definition bnxt_hsi.h:1199

hwrm_func_getfid_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1202

hwrm_func_getfid_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1204

hwrm_func_getfid_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1200

hwrm_func_getfid_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1201

hwrm_func_getfid_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:1208

hwrm_func_getfid_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1203

hwrm_func_getfid_input::enables
__le32 enables
Definition bnxt_hsi.h:1205

hwrm_func_getfid_input::pci_id
__le16 pci_id
Definition bnxt_hsi.h:1207

hwrm_func_getfid_output
Definition bnxt_hsi.h:1212

hwrm_func_getfid_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1213

hwrm_func_getfid_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1214

hwrm_func_getfid_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:1218

hwrm_func_getfid_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1215

hwrm_func_getfid_output::fid
__le16 fid
Definition bnxt_hsi.h:1217

hwrm_func_getfid_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1216

hwrm_func_getfid_output::valid
u8 valid
Definition bnxt_hsi.h:1219

hwrm_func_qcaps_input
Definition bnxt_hsi.h:1324

hwrm_func_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1329

hwrm_func_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1327

hwrm_func_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1328

hwrm_func_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1325

hwrm_func_qcaps_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:1331

hwrm_func_qcaps_input::fid
__le16 fid
Definition bnxt_hsi.h:1330

hwrm_func_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1326

hwrm_func_qcaps_output
Definition bnxt_hsi.h:1335

hwrm_func_qcaps_output::max_decap_records
__le32 max_decap_records
Definition bnxt_hsi.h:1378

hwrm_func_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1339

hwrm_func_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1338

hwrm_func_qcaps_output::max_stat_ctx
__le16 max_stat_ctx
Definition bnxt_hsi.h:1376

hwrm_func_qcaps_output::fid
__le16 fid
Definition bnxt_hsi.h:1340

hwrm_func_qcaps_output::max_sp_tx_rings
__le16 max_sp_tx_rings
Definition bnxt_hsi.h:1386

hwrm_func_qcaps_output::port_id
__le16 port_id
Definition bnxt_hsi.h:1341

hwrm_func_qcaps_output::mac_address
u8 mac_address[6]
Definition bnxt_hsi.h:1367

hwrm_func_qcaps_output::max_tx_wm_flows
__le32 max_tx_wm_flows
Definition bnxt_hsi.h:1380

hwrm_func_qcaps_output::max_hw_ring_grps
__le32 max_hw_ring_grps
Definition bnxt_hsi.h:1385

hwrm_func_qcaps_output::max_mcast_filters
__le32 max_mcast_filters
Definition bnxt_hsi.h:1383

hwrm_func_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1337

hwrm_func_qcaps_output::max_rsscos_ctx
__le16 max_rsscos_ctx
Definition bnxt_hsi.h:1368

hwrm_func_qcaps_output::first_vf_id
__le16 first_vf_id
Definition bnxt_hsi.h:1374

hwrm_func_qcaps_output::max_vnics
__le16 max_vnics
Definition bnxt_hsi.h:1373

hwrm_func_qcaps_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:1387

hwrm_func_qcaps_output::max_cmpl_rings
__le16 max_cmpl_rings
Definition bnxt_hsi.h:1369

hwrm_func_qcaps_output::max_rx_wm_flows
__le32 max_rx_wm_flows
Definition bnxt_hsi.h:1382

hwrm_func_qcaps_output::max_vfs
__le16 max_vfs
Definition bnxt_hsi.h:1375

hwrm_func_qcaps_output::max_rx_rings
__le16 max_rx_rings
Definition bnxt_hsi.h:1371

hwrm_func_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:1388

hwrm_func_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1336

hwrm_func_qcaps_output::max_rx_em_flows
__le32 max_rx_em_flows
Definition bnxt_hsi.h:1381

hwrm_func_qcaps_output::max_encap_records
__le32 max_encap_records
Definition bnxt_hsi.h:1377

hwrm_func_qcaps_output::max_tx_em_flows
__le32 max_tx_em_flows
Definition bnxt_hsi.h:1379

hwrm_func_qcaps_output::max_l2_ctxs
__le16 max_l2_ctxs
Definition bnxt_hsi.h:1372

hwrm_func_qcaps_output::flags
__le32 flags
Definition bnxt_hsi.h:1342

hwrm_func_qcaps_output::max_flow_id
__le32 max_flow_id
Definition bnxt_hsi.h:1384

hwrm_func_qcaps_output::max_tx_rings
__le16 max_tx_rings
Definition bnxt_hsi.h:1370

hwrm_func_qcfg_input
Definition bnxt_hsi.h:1392

hwrm_func_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1395

hwrm_func_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1393

hwrm_func_qcfg_input::fid
__le16 fid
Definition bnxt_hsi.h:1398

hwrm_func_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1397

hwrm_func_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:1399

hwrm_func_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1394

hwrm_func_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1396

hwrm_func_qcfg_output
Definition bnxt_hsi.h:1403

hwrm_func_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1404

hwrm_func_qcfg_output::alloc_rx_rings
__le16 alloc_rx_rings
Definition bnxt_hsi.h:1424

hwrm_func_qcfg_output::port_id
__le16 port_id
Definition bnxt_hsi.h:1409

hwrm_func_qcfg_output::min_bw
__le32 min_bw
Definition bnxt_hsi.h:1443

hwrm_func_qcfg_output::dflt_vnic_id
__le16 dflt_vnic_id
Definition bnxt_hsi.h:1441

hwrm_func_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1407

hwrm_func_qcfg_output::alloc_l2_ctx
__le16 alloc_l2_ctx
Definition bnxt_hsi.h:1425

hwrm_func_qcfg_output::mru
__le16 mru
Definition bnxt_hsi.h:1428

hwrm_func_qcfg_output::options
u8 options
Definition bnxt_hsi.h:1480

hwrm_func_qcfg_output::max_mtu_configured
__le16 max_mtu_configured
Definition bnxt_hsi.h:1442

hwrm_func_qcfg_output::port_partition_type
u8 port_partition_type
Definition bnxt_hsi.h:1430

hwrm_func_qcfg_output::always_1
u8 always_1
Definition bnxt_hsi.h:1502

hwrm_func_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:1505

hwrm_func_qcfg_output::fid
__le16 fid
Definition bnxt_hsi.h:1408

hwrm_func_qcfg_output::alloc_tx_rings
__le16 alloc_tx_rings
Definition bnxt_hsi.h:1423

hwrm_func_qcfg_output::mac_address
u8 mac_address[6]
Definition bnxt_hsi.h:1419

hwrm_func_qcfg_output::mtu
__le16 mtu
Definition bnxt_hsi.h:1427

hwrm_func_qcfg_output::alloc_mcast_filters
__le32 alloc_mcast_filters
Definition bnxt_hsi.h:1495

hwrm_func_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1405

hwrm_func_qcfg_output::unused_2
u8 unused_2[3]
Definition bnxt_hsi.h:1504

hwrm_func_qcfg_output::alloc_msix
__le16 alloc_msix
Definition bnxt_hsi.h:1499

hwrm_func_qcfg_output::alloc_cmpl_rings
__le16 alloc_cmpl_rings
Definition bnxt_hsi.h:1422

hwrm_func_qcfg_output::alloc_vnics
__le16 alloc_vnics
Definition bnxt_hsi.h:1426

hwrm_func_qcfg_output::unused_1
u8 unused_1[3]
Definition bnxt_hsi.h:1501

hwrm_func_qcfg_output::max_bw
__le32 max_bw
Definition bnxt_hsi.h:1459

hwrm_func_qcfg_output::registered_vfs
__le16 registered_vfs
Definition bnxt_hsi.h:1500

hwrm_func_qcfg_output::stat_ctx_id
__le16 stat_ctx_id
Definition bnxt_hsi.h:1429

hwrm_func_qcfg_output::reset_addr_poll
__le32 reset_addr_poll
Definition bnxt_hsi.h:1503

hwrm_func_qcfg_output::port_pf_cnt
u8 port_pf_cnt
Definition bnxt_hsi.h:1438

hwrm_func_qcfg_output::alloc_rsscos_ctx
__le16 alloc_rsscos_ctx
Definition bnxt_hsi.h:1421

hwrm_func_qcfg_output::alloc_stat_ctx
__le16 alloc_stat_ctx
Definition bnxt_hsi.h:1498

hwrm_func_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1406

hwrm_func_qcfg_output::pci_id
__le16 pci_id
Definition bnxt_hsi.h:1420

hwrm_func_qcfg_output::vlan
__le16 vlan
Definition bnxt_hsi.h:1410

hwrm_func_qcfg_output::alloc_vfs
__le16 alloc_vfs
Definition bnxt_hsi.h:1494

hwrm_func_qcfg_output::alloc_sp_tx_rings
__le16 alloc_sp_tx_rings
Definition bnxt_hsi.h:1497

hwrm_func_qcfg_output::alloc_hw_ring_grps
__le32 alloc_hw_ring_grps
Definition bnxt_hsi.h:1496

hwrm_func_qcfg_output::evb_mode
u8 evb_mode
Definition bnxt_hsi.h:1475

hwrm_func_qcfg_output::flags
__le16 flags
Definition bnxt_hsi.h:1411

hwrm_func_qstats_input
Definition bnxt_hsi.h:1646

hwrm_func_qstats_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:1653

hwrm_func_qstats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1650

hwrm_func_qstats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1649

hwrm_func_qstats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1647

hwrm_func_qstats_input::fid
__le16 fid
Definition bnxt_hsi.h:1652

hwrm_func_qstats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1651

hwrm_func_qstats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1648

hwrm_func_qstats_output
Definition bnxt_hsi.h:1657

hwrm_func_qstats_output::rx_agg_pkts
__le64 rx_agg_pkts
Definition bnxt_hsi.h:1678

hwrm_func_qstats_output::rx_mcast_pkts
__le64 rx_mcast_pkts
Definition bnxt_hsi.h:1671

hwrm_func_qstats_output::rx_agg_bytes
__le64 rx_agg_bytes
Definition bnxt_hsi.h:1679

hwrm_func_qstats_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1682

hwrm_func_qstats_output::rx_agg_aborts
__le64 rx_agg_aborts
Definition bnxt_hsi.h:1681

hwrm_func_qstats_output::rx_discard_pkts
__le64 rx_discard_pkts
Definition bnxt_hsi.h:1673

hwrm_func_qstats_output::rx_agg_events
__le64 rx_agg_events
Definition bnxt_hsi.h:1680

hwrm_func_qstats_output::tx_bcast_pkts
__le64 tx_bcast_pkts
Definition bnxt_hsi.h:1664

hwrm_func_qstats_output::tx_ucast_pkts
__le64 tx_ucast_pkts
Definition bnxt_hsi.h:1662

hwrm_func_qstats_output::tx_drop_pkts
__le64 tx_drop_pkts
Definition bnxt_hsi.h:1666

hwrm_func_qstats_output::tx_discard_pkts
__le64 tx_discard_pkts
Definition bnxt_hsi.h:1665

hwrm_func_qstats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1661

hwrm_func_qstats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1660

hwrm_func_qstats_output::rx_bcast_pkts
__le64 rx_bcast_pkts
Definition bnxt_hsi.h:1672

hwrm_func_qstats_output::valid
u8 valid
Definition bnxt_hsi.h:1683

hwrm_func_qstats_output::tx_bcast_bytes
__le64 tx_bcast_bytes
Definition bnxt_hsi.h:1669

hwrm_func_qstats_output::tx_ucast_bytes
__le64 tx_ucast_bytes
Definition bnxt_hsi.h:1667

hwrm_func_qstats_output::tx_mcast_pkts
__le64 tx_mcast_pkts
Definition bnxt_hsi.h:1663

hwrm_func_qstats_output::rx_ucast_pkts
__le64 rx_ucast_pkts
Definition bnxt_hsi.h:1670

hwrm_func_qstats_output::rx_drop_pkts
__le64 rx_drop_pkts
Definition bnxt_hsi.h:1674

hwrm_func_qstats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1658

hwrm_func_qstats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1659

hwrm_func_qstats_output::rx_ucast_bytes
__le64 rx_ucast_bytes
Definition bnxt_hsi.h:1675

hwrm_func_qstats_output::tx_mcast_bytes
__le64 tx_mcast_bytes
Definition bnxt_hsi.h:1668

hwrm_func_qstats_output::rx_bcast_bytes
__le64 rx_bcast_bytes
Definition bnxt_hsi.h:1677

hwrm_func_qstats_output::rx_mcast_bytes
__le64 rx_mcast_bytes
Definition bnxt_hsi.h:1676

hwrm_func_reset_input
Definition bnxt_hsi.h:1170

hwrm_func_reset_input::vf_id
__le16 vf_id
Definition bnxt_hsi.h:1178

hwrm_func_reset_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1175

hwrm_func_reset_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1174

hwrm_func_reset_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1171

hwrm_func_reset_input::enables
__le32 enables
Definition bnxt_hsi.h:1176

hwrm_func_reset_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1173

hwrm_func_reset_input::func_reset_level
u8 func_reset_level
Definition bnxt_hsi.h:1179

hwrm_func_reset_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:1185

hwrm_func_reset_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1172

hwrm_func_reset_output
Definition bnxt_hsi.h:1189

hwrm_func_reset_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1191

hwrm_func_reset_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1194

hwrm_func_reset_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1190

hwrm_func_reset_output::valid
u8 valid
Definition bnxt_hsi.h:1195

hwrm_func_reset_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1192

hwrm_func_reset_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1193

hwrm_func_resource_qcaps_input
Definition bnxt_hsi.h:2018

hwrm_func_resource_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2020

hwrm_func_resource_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2023

hwrm_func_resource_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2021

hwrm_func_resource_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2019

hwrm_func_resource_qcaps_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:2025

hwrm_func_resource_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2022

hwrm_func_resource_qcaps_input::fid
__le16 fid
Definition bnxt_hsi.h:2024

hwrm_func_resource_qcaps_output
Definition bnxt_hsi.h:2029

hwrm_func_resource_qcaps_output::min_cmpl_rings
__le16 min_cmpl_rings
Definition bnxt_hsi.h:2043

hwrm_func_resource_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2033

hwrm_func_resource_qcaps_output::min_rx_rings
__le16 min_rx_rings
Definition bnxt_hsi.h:2047

hwrm_func_resource_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2031

hwrm_func_resource_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2030

hwrm_func_resource_qcaps_output::min_tx_rings
__le16 min_tx_rings
Definition bnxt_hsi.h:2045

hwrm_func_resource_qcaps_output::max_vfs
__le16 max_vfs
Definition bnxt_hsi.h:2034

hwrm_func_resource_qcaps_output::max_vnics
__le16 max_vnics
Definition bnxt_hsi.h:2052

hwrm_func_resource_qcaps_output::min_hw_ring_grps
__le16 min_hw_ring_grps
Definition bnxt_hsi.h:2055

hwrm_func_resource_qcaps_output::max_l2_ctxs
__le16 max_l2_ctxs
Definition bnxt_hsi.h:2050

hwrm_func_resource_qcaps_output::min_rsscos_ctx
__le16 min_rsscos_ctx
Definition bnxt_hsi.h:2041

hwrm_func_resource_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:2061

hwrm_func_resource_qcaps_output::min_stat_ctx
__le16 min_stat_ctx
Definition bnxt_hsi.h:2053

hwrm_func_resource_qcaps_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:2060

hwrm_func_resource_qcaps_output::max_rx_rings
__le16 max_rx_rings
Definition bnxt_hsi.h:2048

hwrm_func_resource_qcaps_output::max_msix
__le16 max_msix
Definition bnxt_hsi.h:2035

hwrm_func_resource_qcaps_output::max_hw_ring_grps
__le16 max_hw_ring_grps
Definition bnxt_hsi.h:2056

hwrm_func_resource_qcaps_output::max_tx_scheduler_inputs
__le16 max_tx_scheduler_inputs
Definition bnxt_hsi.h:2057

hwrm_func_resource_qcaps_output::min_vnics
__le16 min_vnics
Definition bnxt_hsi.h:2051

hwrm_func_resource_qcaps_output::vf_reservation_strategy
__le16 vf_reservation_strategy
Definition bnxt_hsi.h:2036

hwrm_func_resource_qcaps_output::max_cmpl_rings
__le16 max_cmpl_rings
Definition bnxt_hsi.h:2044

hwrm_func_resource_qcaps_output::max_tx_rings
__le16 max_tx_rings
Definition bnxt_hsi.h:2046

hwrm_func_resource_qcaps_output::max_rsscos_ctx
__le16 max_rsscos_ctx
Definition bnxt_hsi.h:2042

hwrm_func_resource_qcaps_output::min_l2_ctxs
__le16 min_l2_ctxs
Definition bnxt_hsi.h:2049

hwrm_func_resource_qcaps_output::flags
__le16 flags
Definition bnxt_hsi.h:2058

hwrm_func_resource_qcaps_output::max_stat_ctx
__le16 max_stat_ctx
Definition bnxt_hsi.h:2054

hwrm_func_resource_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2032

hwrm_func_vf_alloc_input
Definition bnxt_hsi.h:1223

hwrm_func_vf_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1227

hwrm_func_vf_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:1229

hwrm_func_vf_alloc_input::first_vf_id
__le16 first_vf_id
Definition bnxt_hsi.h:1231

hwrm_func_vf_alloc_input::num_vfs
__le16 num_vfs
Definition bnxt_hsi.h:1232

hwrm_func_vf_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1224

hwrm_func_vf_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1225

hwrm_func_vf_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1226

hwrm_func_vf_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1228

hwrm_func_vf_alloc_output
Definition bnxt_hsi.h:1236

hwrm_func_vf_alloc_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:1242

hwrm_func_vf_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1240

hwrm_func_vf_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1237

hwrm_func_vf_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1239

hwrm_func_vf_alloc_output::first_vf_id
__le16 first_vf_id
Definition bnxt_hsi.h:1241

hwrm_func_vf_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1238

hwrm_func_vf_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:1243

hwrm_func_vf_bw_cfg_input
Definition bnxt_hsi.h:2920

hwrm_func_vf_bw_cfg_input::num_vfs
__le16 num_vfs
Definition bnxt_hsi.h:2926

hwrm_func_vf_bw_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2923

hwrm_func_vf_bw_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2925

hwrm_func_vf_bw_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2924

hwrm_func_vf_bw_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2922

hwrm_func_vf_bw_cfg_input::unused
__le16 unused[3]
Definition bnxt_hsi.h:2927

hwrm_func_vf_bw_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2921

hwrm_func_vf_bw_cfg_input::vfn
__le16 vfn[48]
Definition bnxt_hsi.h:2928

hwrm_func_vf_bw_cfg_output
Definition bnxt_hsi.h:2953

hwrm_func_vf_bw_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:2959

hwrm_func_vf_bw_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:2958

hwrm_func_vf_bw_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2954

hwrm_func_vf_bw_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2957

hwrm_func_vf_bw_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2955

hwrm_func_vf_bw_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2956

hwrm_func_vf_bw_qcfg_input
Definition bnxt_hsi.h:2963

hwrm_func_vf_bw_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2967

hwrm_func_vf_bw_qcfg_input::num_vfs
__le16 num_vfs
Definition bnxt_hsi.h:2969

hwrm_func_vf_bw_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2968

hwrm_func_vf_bw_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2964

hwrm_func_vf_bw_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2966

hwrm_func_vf_bw_qcfg_input::unused
__le16 unused[3]
Definition bnxt_hsi.h:2970

hwrm_func_vf_bw_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2965

hwrm_func_vf_bw_qcfg_input::vfn
__le16 vfn[48]
Definition bnxt_hsi.h:2971

hwrm_func_vf_bw_qcfg_output
Definition bnxt_hsi.h:2977

hwrm_func_vf_bw_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2981

hwrm_func_vf_bw_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2980

hwrm_func_vf_bw_qcfg_output::num_vfs
__le16 num_vfs
Definition bnxt_hsi.h:2982

hwrm_func_vf_bw_qcfg_output::unused
__le16 unused[3]
Definition bnxt_hsi.h:2983

hwrm_func_vf_bw_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2978

hwrm_func_vf_bw_qcfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:3006

hwrm_func_vf_bw_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:3007

hwrm_func_vf_bw_qcfg_output::vfn
__le16 vfn[48]
Definition bnxt_hsi.h:2984

hwrm_func_vf_bw_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2979

hwrm_func_vf_cfg_input
Definition bnxt_hsi.h:1270

hwrm_func_vf_cfg_input::num_rx_rings
__le16 num_rx_rings
Definition bnxt_hsi.h:1305

hwrm_func_vf_cfg_input::guest_vlan
__le16 guest_vlan
Definition bnxt_hsi.h:1290

hwrm_func_vf_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1271

hwrm_func_vf_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1275

hwrm_func_vf_cfg_input::num_cmpl_rings
__le16 num_cmpl_rings
Definition bnxt_hsi.h:1303

hwrm_func_vf_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1272

hwrm_func_vf_cfg_input::num_tx_rings
__le16 num_tx_rings
Definition bnxt_hsi.h:1304

hwrm_func_vf_cfg_input::mtu
__le16 mtu
Definition bnxt_hsi.h:1289

hwrm_func_vf_cfg_input::num_l2_ctxs
__le16 num_l2_ctxs
Definition bnxt_hsi.h:1306

hwrm_func_vf_cfg_input::num_hw_ring_grps
__le16 num_hw_ring_grps
Definition bnxt_hsi.h:1309

hwrm_func_vf_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1274

hwrm_func_vf_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:1293

hwrm_func_vf_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:1276

hwrm_func_vf_cfg_input::dflt_mac_addr
u8 dflt_mac_addr[6]
Definition bnxt_hsi.h:1292

hwrm_func_vf_cfg_input::num_stat_ctxs
__le16 num_stat_ctxs
Definition bnxt_hsi.h:1308

hwrm_func_vf_cfg_input::async_event_cr
__le16 async_event_cr
Definition bnxt_hsi.h:1291

hwrm_func_vf_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1273

hwrm_func_vf_cfg_input::num_vnics
__le16 num_vnics
Definition bnxt_hsi.h:1307

hwrm_func_vf_cfg_input::num_rsscos_ctxs
__le16 num_rsscos_ctxs
Definition bnxt_hsi.h:1302

hwrm_func_vf_cfg_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:1310

hwrm_func_vf_cfg_output
Definition bnxt_hsi.h:1314

hwrm_func_vf_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1318

hwrm_func_vf_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1316

hwrm_func_vf_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1319

hwrm_func_vf_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:1320

hwrm_func_vf_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1315

hwrm_func_vf_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1317

hwrm_func_vf_free_input
Definition bnxt_hsi.h:1247

hwrm_func_vf_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1249

hwrm_func_vf_free_input::first_vf_id
__le16 first_vf_id
Definition bnxt_hsi.h:1255

hwrm_func_vf_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1250

hwrm_func_vf_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1248

hwrm_func_vf_free_input::enables
__le32 enables
Definition bnxt_hsi.h:1253

hwrm_func_vf_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1251

hwrm_func_vf_free_input::num_vfs
__le16 num_vfs
Definition bnxt_hsi.h:1256

hwrm_func_vf_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1252

hwrm_func_vf_free_output
Definition bnxt_hsi.h:1260

hwrm_func_vf_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1262

hwrm_func_vf_free_output::valid
u8 valid
Definition bnxt_hsi.h:1266

hwrm_func_vf_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1263

hwrm_func_vf_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1265

hwrm_func_vf_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1261

hwrm_func_vf_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1264

hwrm_func_vf_resc_free_input
Definition bnxt_hsi.h:1708

hwrm_func_vf_resc_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:1709

hwrm_func_vf_resc_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:1710

hwrm_func_vf_resc_free_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:1715

hwrm_func_vf_resc_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1711

hwrm_func_vf_resc_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:1713

hwrm_func_vf_resc_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:1712

hwrm_func_vf_resc_free_input::vf_id
__le16 vf_id
Definition bnxt_hsi.h:1714

hwrm_func_vf_resc_free_output
Definition bnxt_hsi.h:1719

hwrm_func_vf_resc_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:1720

hwrm_func_vf_resc_free_output::valid
u8 valid
Definition bnxt_hsi.h:1725

hwrm_func_vf_resc_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:1724

hwrm_func_vf_resc_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:1722

hwrm_func_vf_resc_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:1723

hwrm_func_vf_resc_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:1721

hwrm_func_vf_resource_cfg_input
Definition bnxt_hsi.h:2065

hwrm_func_vf_resource_cfg_input::min_rsscos_ctx
__le16 min_rsscos_ctx
Definition bnxt_hsi.h:2073

hwrm_func_vf_resource_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2068

hwrm_func_vf_resource_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2069

hwrm_func_vf_resource_cfg_input::vf_id
__le16 vf_id
Definition bnxt_hsi.h:2071

hwrm_func_vf_resource_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2067

hwrm_func_vf_resource_cfg_input::max_rsscos_ctx
__le16 max_rsscos_ctx
Definition bnxt_hsi.h:2074

hwrm_func_vf_resource_cfg_input::max_l2_ctxs
__le16 max_l2_ctxs
Definition bnxt_hsi.h:2082

hwrm_func_vf_resource_cfg_input::max_vnics
__le16 max_vnics
Definition bnxt_hsi.h:2084

hwrm_func_vf_resource_cfg_input::max_hw_ring_grps
__le16 max_hw_ring_grps
Definition bnxt_hsi.h:2088

hwrm_func_vf_resource_cfg_input::min_l2_ctxs
__le16 min_l2_ctxs
Definition bnxt_hsi.h:2081

hwrm_func_vf_resource_cfg_input::max_cmpl_rings
__le16 max_cmpl_rings
Definition bnxt_hsi.h:2076

hwrm_func_vf_resource_cfg_input::min_vnics
__le16 min_vnics
Definition bnxt_hsi.h:2083

hwrm_func_vf_resource_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2070

hwrm_func_vf_resource_cfg_input::max_msix
__le16 max_msix
Definition bnxt_hsi.h:2072

hwrm_func_vf_resource_cfg_input::min_cmpl_rings
__le16 min_cmpl_rings
Definition bnxt_hsi.h:2075

hwrm_func_vf_resource_cfg_input::max_tx_rings
__le16 max_tx_rings
Definition bnxt_hsi.h:2078

hwrm_func_vf_resource_cfg_input::max_rx_rings
__le16 max_rx_rings
Definition bnxt_hsi.h:2080

hwrm_func_vf_resource_cfg_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:2091

hwrm_func_vf_resource_cfg_input::min_stat_ctx
__le16 min_stat_ctx
Definition bnxt_hsi.h:2085

hwrm_func_vf_resource_cfg_input::min_tx_rings
__le16 min_tx_rings
Definition bnxt_hsi.h:2077

hwrm_func_vf_resource_cfg_input::min_rx_rings
__le16 min_rx_rings
Definition bnxt_hsi.h:2079

hwrm_func_vf_resource_cfg_input::min_hw_ring_grps
__le16 min_hw_ring_grps
Definition bnxt_hsi.h:2087

hwrm_func_vf_resource_cfg_input::max_stat_ctx
__le16 max_stat_ctx
Definition bnxt_hsi.h:2086

hwrm_func_vf_resource_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2066

hwrm_func_vf_resource_cfg_input::flags
__le16 flags
Definition bnxt_hsi.h:2089

hwrm_func_vf_resource_cfg_output
Definition bnxt_hsi.h:2095

hwrm_func_vf_resource_cfg_output::reserved_hw_ring_grps
__le16 reserved_hw_ring_grps
Definition bnxt_hsi.h:2107

hwrm_func_vf_resource_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2099

hwrm_func_vf_resource_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2098

hwrm_func_vf_resource_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2097

hwrm_func_vf_resource_cfg_output::reserved_stat_ctx
__le16 reserved_stat_ctx
Definition bnxt_hsi.h:2106

hwrm_func_vf_resource_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:2108

hwrm_func_vf_resource_cfg_output::reserved_vnics
__le16 reserved_vnics
Definition bnxt_hsi.h:2105

hwrm_func_vf_resource_cfg_output::reserved_tx_rings
__le16 reserved_tx_rings
Definition bnxt_hsi.h:2102

hwrm_func_vf_resource_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2096

hwrm_func_vf_resource_cfg_output::reserved_cmpl_rings
__le16 reserved_cmpl_rings
Definition bnxt_hsi.h:2101

hwrm_func_vf_resource_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:2109

hwrm_func_vf_resource_cfg_output::reserved_rx_rings
__le16 reserved_rx_rings
Definition bnxt_hsi.h:2103

hwrm_func_vf_resource_cfg_output::reserved_rsscos_ctx
__le16 reserved_rsscos_ctx
Definition bnxt_hsi.h:2100

hwrm_func_vf_resource_cfg_output::reserved_l2_ctxs
__le16 reserved_l2_ctxs
Definition bnxt_hsi.h:2104

hwrm_func_vf_vnic_ids_query_input
Definition bnxt_hsi.h:2896

hwrm_func_vf_vnic_ids_query_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:2903

hwrm_func_vf_vnic_ids_query_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2898

hwrm_func_vf_vnic_ids_query_input::vnic_id_tbl_addr
__le64 vnic_id_tbl_addr
Definition bnxt_hsi.h:2905

hwrm_func_vf_vnic_ids_query_input::vf_id
__le16 vf_id
Definition bnxt_hsi.h:2902

hwrm_func_vf_vnic_ids_query_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2901

hwrm_func_vf_vnic_ids_query_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2900

hwrm_func_vf_vnic_ids_query_input::max_vnic_id_cnt
__le32 max_vnic_id_cnt
Definition bnxt_hsi.h:2904

hwrm_func_vf_vnic_ids_query_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2897

hwrm_func_vf_vnic_ids_query_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2899

hwrm_func_vf_vnic_ids_query_output
Definition bnxt_hsi.h:2909

hwrm_func_vf_vnic_ids_query_output::vnic_id_cnt
__le32 vnic_id_cnt
Definition bnxt_hsi.h:2914

hwrm_func_vf_vnic_ids_query_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2910

hwrm_func_vf_vnic_ids_query_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2911

hwrm_func_vf_vnic_ids_query_output::valid
u8 valid
Definition bnxt_hsi.h:2916

hwrm_func_vf_vnic_ids_query_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2913

hwrm_func_vf_vnic_ids_query_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2912

hwrm_func_vf_vnic_ids_query_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:2915

hwrm_func_vlan_cfg_input
Definition bnxt_hsi.h:2857

hwrm_func_vlan_cfg_input::fid
__le16 fid
Definition bnxt_hsi.h:2863

hwrm_func_vlan_cfg_input::ctag_pcp
u8 ctag_pcp
Definition bnxt_hsi.h:2877

hwrm_func_vlan_cfg_input::stag_pcp
u8 stag_pcp
Definition bnxt_hsi.h:2873

hwrm_func_vlan_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2861

hwrm_func_vlan_cfg_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:2864

hwrm_func_vlan_cfg_input::unused_2
u8 unused_2
Definition bnxt_hsi.h:2878

hwrm_func_vlan_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:2865

hwrm_func_vlan_cfg_input::stag_vid
__le16 stag_vid
Definition bnxt_hsi.h:2872

hwrm_func_vlan_cfg_input::ctag_tpid
__be16 ctag_tpid
Definition bnxt_hsi.h:2879

hwrm_func_vlan_cfg_input::unused_3
u8 unused_3[4]
Definition bnxt_hsi.h:2882

hwrm_func_vlan_cfg_input::unused_1
u8 unused_1
Definition bnxt_hsi.h:2874

hwrm_func_vlan_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2862

hwrm_func_vlan_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2858

hwrm_func_vlan_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2860

hwrm_func_vlan_cfg_input::rsvd1
__le32 rsvd1
Definition bnxt_hsi.h:2880

hwrm_func_vlan_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2859

hwrm_func_vlan_cfg_input::ctag_vid
__le16 ctag_vid
Definition bnxt_hsi.h:2876

hwrm_func_vlan_cfg_input::rsvd2
__le32 rsvd2
Definition bnxt_hsi.h:2881

hwrm_func_vlan_cfg_input::stag_tpid
__be16 stag_tpid
Definition bnxt_hsi.h:2875

hwrm_func_vlan_cfg_output
Definition bnxt_hsi.h:2886

hwrm_func_vlan_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2887

hwrm_func_vlan_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2890

hwrm_func_vlan_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2888

hwrm_func_vlan_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:2892

hwrm_func_vlan_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2889

hwrm_func_vlan_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:2891

hwrm_func_vlan_qcfg_input
Definition bnxt_hsi.h:2825

hwrm_func_vlan_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:2829

hwrm_func_vlan_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:2827

hwrm_func_vlan_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:2832

hwrm_func_vlan_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:2826

hwrm_func_vlan_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2828

hwrm_func_vlan_qcfg_input::fid
__le16 fid
Definition bnxt_hsi.h:2831

hwrm_func_vlan_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:2830

hwrm_func_vlan_qcfg_output
Definition bnxt_hsi.h:2836

hwrm_func_vlan_qcfg_output::stag_vid
__le16 stag_vid
Definition bnxt_hsi.h:2842

hwrm_func_vlan_qcfg_output::stag_tpid
__be16 stag_tpid
Definition bnxt_hsi.h:2845

hwrm_func_vlan_qcfg_output::rsvd2
__le32 rsvd2
Definition bnxt_hsi.h:2850

hwrm_func_vlan_qcfg_output::stag_pcp
u8 stag_pcp
Definition bnxt_hsi.h:2843

hwrm_func_vlan_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:2840

hwrm_func_vlan_qcfg_output::ctag_tpid
__be16 ctag_tpid
Definition bnxt_hsi.h:2849

hwrm_func_vlan_qcfg_output::unused_3
u8 unused_3[3]
Definition bnxt_hsi.h:2852

hwrm_func_vlan_qcfg_output::rsvd3
__le32 rsvd3
Definition bnxt_hsi.h:2851

hwrm_func_vlan_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:2853

hwrm_func_vlan_qcfg_output::unused_2
u8 unused_2
Definition bnxt_hsi.h:2848

hwrm_func_vlan_qcfg_output::unused_0
__le64 unused_0
Definition bnxt_hsi.h:2841

hwrm_func_vlan_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:2838

hwrm_func_vlan_qcfg_output::unused_1
u8 unused_1
Definition bnxt_hsi.h:2844

hwrm_func_vlan_qcfg_output::ctag_pcp
u8 ctag_pcp
Definition bnxt_hsi.h:2847

hwrm_func_vlan_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:2839

hwrm_func_vlan_qcfg_output::ctag_vid
__le16 ctag_vid
Definition bnxt_hsi.h:2846

hwrm_func_vlan_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:2837

hwrm_fw_get_structured_data_cmd_err
Definition bnxt_hsi.h:9117

hwrm_fw_get_structured_data_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9122

hwrm_fw_get_structured_data_cmd_err::code
u8 code
Definition bnxt_hsi.h:9118

hwrm_fw_get_structured_data_input
Definition bnxt_hsi.h:9081

hwrm_fw_get_structured_data_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9082

hwrm_fw_get_structured_data_input::data_len
__le16 data_len
Definition bnxt_hsi.h:9088

hwrm_fw_get_structured_data_input::structure_id
__le16 structure_id
Definition bnxt_hsi.h:9089

hwrm_fw_get_structured_data_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9084

hwrm_fw_get_structured_data_input::subtype
__le16 subtype
Definition bnxt_hsi.h:9090

hwrm_fw_get_structured_data_input::dest_data_addr
__le64 dest_data_addr
Definition bnxt_hsi.h:9087

hwrm_fw_get_structured_data_input::count
u8 count
Definition bnxt_hsi.h:9101

hwrm_fw_get_structured_data_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9086

hwrm_fw_get_structured_data_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9085

hwrm_fw_get_structured_data_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9083

hwrm_fw_get_structured_data_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:9102

hwrm_fw_get_structured_data_output
Definition bnxt_hsi.h:9106

hwrm_fw_get_structured_data_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9110

hwrm_fw_get_structured_data_output::valid
u8 valid
Definition bnxt_hsi.h:9113

hwrm_fw_get_structured_data_output::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:9112

hwrm_fw_get_structured_data_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9108

hwrm_fw_get_structured_data_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9107

hwrm_fw_get_structured_data_output::hdr_cnt
u8 hdr_cnt
Definition bnxt_hsi.h:9111

hwrm_fw_get_structured_data_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9109

hwrm_fw_get_time_input
Definition bnxt_hsi.h:8806

hwrm_fw_get_time_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8809

hwrm_fw_get_time_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8810

hwrm_fw_get_time_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8807

hwrm_fw_get_time_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8808

hwrm_fw_get_time_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8811

hwrm_fw_get_time_output
Definition bnxt_hsi.h:8815

hwrm_fw_get_time_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8818

hwrm_fw_get_time_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:8828

hwrm_fw_get_time_output::zone
__le16 zone
Definition bnxt_hsi.h:8830

hwrm_fw_get_time_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8819

hwrm_fw_get_time_output::day
u8 day
Definition bnxt_hsi.h:8824

hwrm_fw_get_time_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8817

hwrm_fw_get_time_output::unused_1
u8 unused_1[3]
Definition bnxt_hsi.h:8834

hwrm_fw_get_time_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8816

hwrm_fw_get_time_output::hour
u8 hour
Definition bnxt_hsi.h:8825

hwrm_fw_get_time_output::valid
u8 valid
Definition bnxt_hsi.h:8835

hwrm_fw_get_time_output::second
u8 second
Definition bnxt_hsi.h:8827

hwrm_fw_get_time_output::month
u8 month
Definition bnxt_hsi.h:8823

hwrm_fw_get_time_output::minute
u8 minute
Definition bnxt_hsi.h:8826

hwrm_fw_get_time_output::millisecond
__le16 millisecond
Definition bnxt_hsi.h:8829

hwrm_fw_get_time_output::year
__le16 year
Definition bnxt_hsi.h:8820

hwrm_fw_health_check_input
Definition bnxt_hsi.h:9199

hwrm_fw_health_check_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9201

hwrm_fw_health_check_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9200

hwrm_fw_health_check_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9203

hwrm_fw_health_check_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9204

hwrm_fw_health_check_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9202

hwrm_fw_health_check_output
Definition bnxt_hsi.h:9208

hwrm_fw_health_check_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9211

hwrm_fw_health_check_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9212

hwrm_fw_health_check_output::valid
u8 valid
Definition bnxt_hsi.h:9222

hwrm_fw_health_check_output::fw_status
__le32 fw_status
Definition bnxt_hsi.h:9213

hwrm_fw_health_check_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:9221

hwrm_fw_health_check_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9210

hwrm_fw_health_check_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9209

hwrm_fw_ipc_mailbox_cmd_err
Definition bnxt_hsi.h:9190

hwrm_fw_ipc_mailbox_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9195

hwrm_fw_ipc_mailbox_cmd_err::code
u8 code
Definition bnxt_hsi.h:9191

hwrm_fw_ipc_mailbox_input
Definition bnxt_hsi.h:9164

hwrm_fw_ipc_mailbox_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:9176

hwrm_fw_ipc_mailbox_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9166

hwrm_fw_ipc_mailbox_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9169

hwrm_fw_ipc_mailbox_input::event_data1
__le32 event_data1
Definition bnxt_hsi.h:9174

hwrm_fw_ipc_mailbox_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9165

hwrm_fw_ipc_mailbox_input::event_data2
__le32 event_data2
Definition bnxt_hsi.h:9175

hwrm_fw_ipc_mailbox_input::unused
u8 unused
Definition bnxt_hsi.h:9171

hwrm_fw_ipc_mailbox_input::port_id
u8 port_id
Definition bnxt_hsi.h:9173

hwrm_fw_ipc_mailbox_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9168

hwrm_fw_ipc_mailbox_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9167

hwrm_fw_ipc_mailbox_input::flags
u8 flags
Definition bnxt_hsi.h:9170

hwrm_fw_ipc_mailbox_input::event_id
u8 event_id
Definition bnxt_hsi.h:9172

hwrm_fw_ipc_mailbox_output
Definition bnxt_hsi.h:9180

hwrm_fw_ipc_mailbox_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9185

hwrm_fw_ipc_mailbox_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9183

hwrm_fw_ipc_mailbox_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9182

hwrm_fw_ipc_mailbox_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9184

hwrm_fw_ipc_mailbox_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9181

hwrm_fw_ipc_mailbox_output::valid
u8 valid
Definition bnxt_hsi.h:9186

hwrm_fw_ipc_msg_input
Definition bnxt_hsi.h:9126

hwrm_fw_ipc_msg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9127

hwrm_fw_ipc_msg_input::command_id
__le16 command_id
Definition bnxt_hsi.h:9137

hwrm_fw_ipc_msg_input::opaque
__le64 opaque
Definition bnxt_hsi.h:9150

hwrm_fw_ipc_msg_input::length
__le16 length
Definition bnxt_hsi.h:9148

hwrm_fw_ipc_msg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9130

hwrm_fw_ipc_msg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9129

hwrm_fw_ipc_msg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9128

hwrm_fw_ipc_msg_input::unused_1
u8 unused_1[2]
Definition bnxt_hsi.h:9149

hwrm_fw_ipc_msg_input::data_offset
__le32 data_offset
Definition bnxt_hsi.h:9147

hwrm_fw_ipc_msg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9131

hwrm_fw_ipc_msg_input::src_processor
u8 src_processor
Definition bnxt_hsi.h:9140

hwrm_fw_ipc_msg_input::enables
__le32 enables
Definition bnxt_hsi.h:9132

hwrm_fw_ipc_msg_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:9146

hwrm_fw_ipc_msg_output
Definition bnxt_hsi.h:9154

hwrm_fw_ipc_msg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9158

hwrm_fw_ipc_msg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9159

hwrm_fw_ipc_msg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9155

hwrm_fw_ipc_msg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9156

hwrm_fw_ipc_msg_output::valid
u8 valid
Definition bnxt_hsi.h:9160

hwrm_fw_ipc_msg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9157

hwrm_fw_qstatus_input
Definition bnxt_hsi.h:8738

hwrm_fw_qstatus_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8739

hwrm_fw_qstatus_input::embedded_proc_type
u8 embedded_proc_type
Definition bnxt_hsi.h:8744

hwrm_fw_qstatus_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8753

hwrm_fw_qstatus_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8743

hwrm_fw_qstatus_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8740

hwrm_fw_qstatus_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8741

hwrm_fw_qstatus_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8742

hwrm_fw_qstatus_output
Definition bnxt_hsi.h:8757

hwrm_fw_qstatus_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8761

hwrm_fw_qstatus_output::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:8767

hwrm_fw_qstatus_output::selfrst_status
u8 selfrst_status
Definition bnxt_hsi.h:8762

hwrm_fw_qstatus_output::valid
u8 valid
Definition bnxt_hsi.h:8768

hwrm_fw_qstatus_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8758

hwrm_fw_qstatus_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8759

hwrm_fw_qstatus_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8760

hwrm_fw_reset_input
Definition bnxt_hsi.h:8693

hwrm_fw_reset_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8696

hwrm_fw_reset_input::selfrst_status
u8 selfrst_status
Definition bnxt_hsi.h:8709

hwrm_fw_reset_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8695

hwrm_fw_reset_input::flags
u8 flags
Definition bnxt_hsi.h:8716

hwrm_fw_reset_input::embedded_proc_type
u8 embedded_proc_type
Definition bnxt_hsi.h:8699

hwrm_fw_reset_input::host_idx
u8 host_idx
Definition bnxt_hsi.h:8715

hwrm_fw_reset_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8698

hwrm_fw_reset_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8697

hwrm_fw_reset_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8694

hwrm_fw_reset_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:8718

hwrm_fw_reset_output
Definition bnxt_hsi.h:8722

hwrm_fw_reset_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8723

hwrm_fw_reset_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8725

hwrm_fw_reset_output::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:8733

hwrm_fw_reset_output::valid
u8 valid
Definition bnxt_hsi.h:8734

hwrm_fw_reset_output::selfrst_status
u8 selfrst_status
Definition bnxt_hsi.h:8727

hwrm_fw_reset_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8724

hwrm_fw_reset_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8726

hwrm_fw_set_structured_data_cmd_err
Definition bnxt_hsi.h:9070

hwrm_fw_set_structured_data_cmd_err::code
u8 code
Definition bnxt_hsi.h:9071

hwrm_fw_set_structured_data_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9077

hwrm_fw_set_structured_data_input
Definition bnxt_hsi.h:9047

hwrm_fw_set_structured_data_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9052

hwrm_fw_set_structured_data_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9050

hwrm_fw_set_structured_data_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9048

hwrm_fw_set_structured_data_input::data_len
__le16 data_len
Definition bnxt_hsi.h:9054

hwrm_fw_set_structured_data_input::src_data_addr
__le64 src_data_addr
Definition bnxt_hsi.h:9053

hwrm_fw_set_structured_data_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9049

hwrm_fw_set_structured_data_input::hdr_cnt
u8 hdr_cnt
Definition bnxt_hsi.h:9055

hwrm_fw_set_structured_data_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9051

hwrm_fw_set_structured_data_input::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:9056

hwrm_fw_set_structured_data_output
Definition bnxt_hsi.h:9060

hwrm_fw_set_structured_data_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9062

hwrm_fw_set_structured_data_output::valid
u8 valid
Definition bnxt_hsi.h:9066

hwrm_fw_set_structured_data_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9065

hwrm_fw_set_structured_data_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9063

hwrm_fw_set_structured_data_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9061

hwrm_fw_set_structured_data_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9064

hwrm_fw_set_time_input
Definition bnxt_hsi.h:8772

hwrm_fw_set_time_input::millisecond
__le16 millisecond
Definition bnxt_hsi.h:8787

hwrm_fw_set_time_input::year
__le16 year
Definition bnxt_hsi.h:8778

hwrm_fw_set_time_input::hour
u8 hour
Definition bnxt_hsi.h:8783

hwrm_fw_set_time_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:8792

hwrm_fw_set_time_input::minute
u8 minute
Definition bnxt_hsi.h:8784

hwrm_fw_set_time_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8777

hwrm_fw_set_time_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8774

hwrm_fw_set_time_input::month
u8 month
Definition bnxt_hsi.h:8781

hwrm_fw_set_time_input::zone
__le16 zone
Definition bnxt_hsi.h:8788

hwrm_fw_set_time_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8773

hwrm_fw_set_time_input::day
u8 day
Definition bnxt_hsi.h:8782

hwrm_fw_set_time_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:8786

hwrm_fw_set_time_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8775

hwrm_fw_set_time_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8776

hwrm_fw_set_time_input::second
u8 second
Definition bnxt_hsi.h:8785

hwrm_fw_set_time_output
Definition bnxt_hsi.h:8796

hwrm_fw_set_time_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8800

hwrm_fw_set_time_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8798

hwrm_fw_set_time_output::valid
u8 valid
Definition bnxt_hsi.h:8802

hwrm_fw_set_time_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8801

hwrm_fw_set_time_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8797

hwrm_fw_set_time_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8799

hwrm_fw_sync_input
Definition bnxt_hsi.h:9226

hwrm_fw_sync_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9229

hwrm_fw_sync_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:9237

hwrm_fw_sync_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9231

hwrm_fw_sync_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9227

hwrm_fw_sync_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9230

hwrm_fw_sync_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9228

hwrm_fw_sync_input::sync_action
__le32 sync_action
Definition bnxt_hsi.h:9232

hwrm_fw_sync_output
Definition bnxt_hsi.h:9241

hwrm_fw_sync_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:9256

hwrm_fw_sync_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9244

hwrm_fw_sync_output::sync_status
__le32 sync_status
Definition bnxt_hsi.h:9246

hwrm_fw_sync_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9242

hwrm_fw_sync_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9243

hwrm_fw_sync_output::valid
u8 valid
Definition bnxt_hsi.h:9257

hwrm_fw_sync_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9245

hwrm_fwd_async_event_cmpl_input
Definition bnxt_hsi.h:9331

hwrm_fwd_async_event_cmpl_input::encap_async_event_target_id
__le16 encap_async_event_target_id
Definition bnxt_hsi.h:9337

hwrm_fwd_async_event_cmpl_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9335

hwrm_fwd_async_event_cmpl_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9332

hwrm_fwd_async_event_cmpl_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9336

hwrm_fwd_async_event_cmpl_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9333

hwrm_fwd_async_event_cmpl_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:9338

hwrm_fwd_async_event_cmpl_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9334

hwrm_fwd_async_event_cmpl_input::encap_async_event_cmpl
__le32 encap_async_event_cmpl[4]
Definition bnxt_hsi.h:9339

hwrm_fwd_async_event_cmpl_output
Definition bnxt_hsi.h:9343

hwrm_fwd_async_event_cmpl_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9345

hwrm_fwd_async_event_cmpl_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9347

hwrm_fwd_async_event_cmpl_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9346

hwrm_fwd_async_event_cmpl_output::valid
u8 valid
Definition bnxt_hsi.h:9349

hwrm_fwd_async_event_cmpl_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9348

hwrm_fwd_async_event_cmpl_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9344

hwrm_fwd_req_cmpl
Definition bnxt_hsi.h:514

hwrm_fwd_req_cmpl::source_id
__le16 source_id
Definition bnxt_hsi.h:522

hwrm_fwd_req_cmpl::unused0
__le32 unused0
Definition bnxt_hsi.h:523

hwrm_fwd_req_cmpl::req_len_type
__le16 req_len_type
Definition bnxt_hsi.h:515

hwrm_fwd_req_cmpl::req_buf_addr_v
__le32 req_buf_addr_v[2]
Definition bnxt_hsi.h:524

hwrm_fwd_resp_cmpl
Definition bnxt_hsi.h:531

hwrm_fwd_resp_cmpl::resp_len
__le16 resp_len
Definition bnxt_hsi.h:538

hwrm_fwd_resp_cmpl::resp_buf_addr_v
__le32 resp_buf_addr_v[2]
Definition bnxt_hsi.h:540

hwrm_fwd_resp_cmpl::source_id
__le16 source_id
Definition bnxt_hsi.h:537

hwrm_fwd_resp_cmpl::type
__le16 type
Definition bnxt_hsi.h:532

hwrm_fwd_resp_cmpl::unused_1
__le16 unused_1
Definition bnxt_hsi.h:539

hwrm_fwd_resp_input
Definition bnxt_hsi.h:9305

hwrm_fwd_resp_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9308

hwrm_fwd_resp_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9306

hwrm_fwd_resp_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9307

hwrm_fwd_resp_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9309

hwrm_fwd_resp_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:9314

hwrm_fwd_resp_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9310

hwrm_fwd_resp_input::encap_resp_addr
__le64 encap_resp_addr
Definition bnxt_hsi.h:9316

hwrm_fwd_resp_input::encap_resp
__le32 encap_resp[24]
Definition bnxt_hsi.h:9317

hwrm_fwd_resp_input::encap_resp_len
__le16 encap_resp_len
Definition bnxt_hsi.h:9313

hwrm_fwd_resp_input::unused_1
u8 unused_1
Definition bnxt_hsi.h:9315

hwrm_fwd_resp_input::encap_resp_target_id
__le16 encap_resp_target_id
Definition bnxt_hsi.h:9311

hwrm_fwd_resp_input::encap_resp_cmpl_ring
__le16 encap_resp_cmpl_ring
Definition bnxt_hsi.h:9312

hwrm_fwd_resp_output
Definition bnxt_hsi.h:9321

hwrm_fwd_resp_output::valid
u8 valid
Definition bnxt_hsi.h:9327

hwrm_fwd_resp_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9325

hwrm_fwd_resp_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9324

hwrm_fwd_resp_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9322

hwrm_fwd_resp_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9326

hwrm_fwd_resp_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9323

hwrm_nvm_erase_dir_entry_input
Definition bnxt_hsi.h:10125

hwrm_nvm_erase_dir_entry_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10128

hwrm_nvm_erase_dir_entry_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10127

hwrm_nvm_erase_dir_entry_input::dir_idx
__le16 dir_idx
Definition bnxt_hsi.h:10131

hwrm_nvm_erase_dir_entry_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10130

hwrm_nvm_erase_dir_entry_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10126

hwrm_nvm_erase_dir_entry_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10129

hwrm_nvm_erase_dir_entry_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:10132

hwrm_nvm_erase_dir_entry_output
Definition bnxt_hsi.h:10136

hwrm_nvm_erase_dir_entry_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10140

hwrm_nvm_erase_dir_entry_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10138

hwrm_nvm_erase_dir_entry_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10141

hwrm_nvm_erase_dir_entry_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10137

hwrm_nvm_erase_dir_entry_output::valid
u8 valid
Definition bnxt_hsi.h:10142

hwrm_nvm_erase_dir_entry_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10139

hwrm_nvm_factory_defaults_cmd_err
Definition bnxt_hsi.h:10470

hwrm_nvm_factory_defaults_cmd_err::code
u8 code
Definition bnxt_hsi.h:10471

hwrm_nvm_factory_defaults_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10476

hwrm_nvm_factory_defaults_input
Definition bnxt_hsi.h:10441

hwrm_nvm_factory_defaults_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10451

hwrm_nvm_factory_defaults_input::mode
u8 mode
Definition bnxt_hsi.h:10447

hwrm_nvm_factory_defaults_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10445

hwrm_nvm_factory_defaults_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10443

hwrm_nvm_factory_defaults_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10446

hwrm_nvm_factory_defaults_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10442

hwrm_nvm_factory_defaults_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10444

hwrm_nvm_factory_defaults_output
Definition bnxt_hsi.h:10455

hwrm_nvm_factory_defaults_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10459

hwrm_nvm_factory_defaults_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10457

hwrm_nvm_factory_defaults_output::result
u8 result
Definition bnxt_hsi.h:10460

hwrm_nvm_factory_defaults_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10456

hwrm_nvm_factory_defaults_output::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:10465

hwrm_nvm_factory_defaults_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10458

hwrm_nvm_factory_defaults_output::valid
u8 valid
Definition bnxt_hsi.h:10466

hwrm_nvm_find_dir_entry_input
Definition bnxt_hsi.h:10087

hwrm_nvm_find_dir_entry_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10091

hwrm_nvm_find_dir_entry_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:10106

hwrm_nvm_find_dir_entry_input::enables
__le32 enables
Definition bnxt_hsi.h:10093

hwrm_nvm_find_dir_entry_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10088

hwrm_nvm_find_dir_entry_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10089

hwrm_nvm_find_dir_entry_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10090

hwrm_nvm_find_dir_entry_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10092

hwrm_nvm_find_dir_entry_input::dir_ordinal
__le16 dir_ordinal
Definition bnxt_hsi.h:10097

hwrm_nvm_find_dir_entry_input::dir_ext
__le16 dir_ext
Definition bnxt_hsi.h:10098

hwrm_nvm_find_dir_entry_input::dir_idx
__le16 dir_idx
Definition bnxt_hsi.h:10095

hwrm_nvm_find_dir_entry_input::opt_ordinal
u8 opt_ordinal
Definition bnxt_hsi.h:10099

hwrm_nvm_find_dir_entry_input::dir_type
__le16 dir_type
Definition bnxt_hsi.h:10096

hwrm_nvm_find_dir_entry_output
Definition bnxt_hsi.h:10110

hwrm_nvm_find_dir_entry_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10120

hwrm_nvm_find_dir_entry_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10113

hwrm_nvm_find_dir_entry_output::valid
u8 valid
Definition bnxt_hsi.h:10121

hwrm_nvm_find_dir_entry_output::fw_ver
__le32 fw_ver
Definition bnxt_hsi.h:10117

hwrm_nvm_find_dir_entry_output::dir_ordinal
__le16 dir_ordinal
Definition bnxt_hsi.h:10118

hwrm_nvm_find_dir_entry_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10114

hwrm_nvm_find_dir_entry_output::dir_idx
__le16 dir_idx
Definition bnxt_hsi.h:10119

hwrm_nvm_find_dir_entry_output::dir_data_length
__le32 dir_data_length
Definition bnxt_hsi.h:10116

hwrm_nvm_find_dir_entry_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10111

hwrm_nvm_find_dir_entry_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10112

hwrm_nvm_find_dir_entry_output::dir_item_length
__le32 dir_item_length
Definition bnxt_hsi.h:10115

hwrm_nvm_flush_cmd_err
Definition bnxt_hsi.h:10290

hwrm_nvm_flush_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10295

hwrm_nvm_flush_cmd_err::code
u8 code
Definition bnxt_hsi.h:10291

hwrm_nvm_flush_input
Definition bnxt_hsi.h:10271

hwrm_nvm_flush_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10272

hwrm_nvm_flush_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10274

hwrm_nvm_flush_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10276

hwrm_nvm_flush_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10275

hwrm_nvm_flush_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10273

hwrm_nvm_flush_output
Definition bnxt_hsi.h:10280

hwrm_nvm_flush_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10285

hwrm_nvm_flush_output::valid
u8 valid
Definition bnxt_hsi.h:10286

hwrm_nvm_flush_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10283

hwrm_nvm_flush_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10281

hwrm_nvm_flush_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10282

hwrm_nvm_flush_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10284

hwrm_nvm_get_dev_info_input
Definition bnxt_hsi.h:10146

hwrm_nvm_get_dev_info_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10151

hwrm_nvm_get_dev_info_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10148

hwrm_nvm_get_dev_info_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10147

hwrm_nvm_get_dev_info_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10149

hwrm_nvm_get_dev_info_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10150

hwrm_nvm_get_dev_info_output
Definition bnxt_hsi.h:10155

hwrm_nvm_get_dev_info_output::nvram_size
__le32 nvram_size
Definition bnxt_hsi.h:10163

hwrm_nvm_get_dev_info_output::reserved_size
__le32 reserved_size
Definition bnxt_hsi.h:10164

hwrm_nvm_get_dev_info_output::available_size
__le32 available_size
Definition bnxt_hsi.h:10165

hwrm_nvm_get_dev_info_output::manufacturer_id
__le16 manufacturer_id
Definition bnxt_hsi.h:10160

hwrm_nvm_get_dev_info_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10159

hwrm_nvm_get_dev_info_output::valid
u8 valid
Definition bnxt_hsi.h:10167

hwrm_nvm_get_dev_info_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:10166

hwrm_nvm_get_dev_info_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10157

hwrm_nvm_get_dev_info_output::sector_size
__le32 sector_size
Definition bnxt_hsi.h:10162

hwrm_nvm_get_dev_info_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10158

hwrm_nvm_get_dev_info_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10156

hwrm_nvm_get_dev_info_output::device_id
__le16 device_id
Definition bnxt_hsi.h:10161

hwrm_nvm_get_dir_entries_input
Definition bnxt_hsi.h:9979

hwrm_nvm_get_dir_entries_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9983

hwrm_nvm_get_dir_entries_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9985

hwrm_nvm_get_dir_entries_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9981

hwrm_nvm_get_dir_entries_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9984

hwrm_nvm_get_dir_entries_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9980

hwrm_nvm_get_dir_entries_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9982

hwrm_nvm_get_dir_entries_output
Definition bnxt_hsi.h:9989

hwrm_nvm_get_dir_entries_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9992

hwrm_nvm_get_dir_entries_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9991

hwrm_nvm_get_dir_entries_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9994

hwrm_nvm_get_dir_entries_output::valid
u8 valid
Definition bnxt_hsi.h:9995

hwrm_nvm_get_dir_entries_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9993

hwrm_nvm_get_dir_entries_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9990

hwrm_nvm_get_dir_info_input
Definition bnxt_hsi.h:9999

hwrm_nvm_get_dir_info_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10003

hwrm_nvm_get_dir_info_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10004

hwrm_nvm_get_dir_info_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10001

hwrm_nvm_get_dir_info_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10000

hwrm_nvm_get_dir_info_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10002

hwrm_nvm_get_dir_info_output
Definition bnxt_hsi.h:10008

hwrm_nvm_get_dir_info_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10015

hwrm_nvm_get_dir_info_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10009

hwrm_nvm_get_dir_info_output::entries
__le32 entries
Definition bnxt_hsi.h:10013

hwrm_nvm_get_dir_info_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10010

hwrm_nvm_get_dir_info_output::valid
u8 valid
Definition bnxt_hsi.h:10016

hwrm_nvm_get_dir_info_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10011

hwrm_nvm_get_dir_info_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10012

hwrm_nvm_get_dir_info_output::entry_length
__le32 entry_length
Definition bnxt_hsi.h:10014

hwrm_nvm_get_variable_cmd_err
Definition bnxt_hsi.h:10337

hwrm_nvm_get_variable_cmd_err::code
u8 code
Definition bnxt_hsi.h:10338

hwrm_nvm_get_variable_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10344

hwrm_nvm_get_variable_input
Definition bnxt_hsi.h:10299

hwrm_nvm_get_variable_input::data_len
__le16 data_len
Definition bnxt_hsi.h:10306

hwrm_nvm_get_variable_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10303

hwrm_nvm_get_variable_input::index_3
__le16 index_3
Definition bnxt_hsi.h:10315

hwrm_nvm_get_variable_input::index_0
__le16 index_0
Definition bnxt_hsi.h:10312

hwrm_nvm_get_variable_input::dimensions
__le16 dimensions
Definition bnxt_hsi.h:10311

hwrm_nvm_get_variable_input::flags
u8 flags
Definition bnxt_hsi.h:10316

hwrm_nvm_get_variable_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10301

hwrm_nvm_get_variable_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10300

hwrm_nvm_get_variable_input::index_1
__le16 index_1
Definition bnxt_hsi.h:10313

hwrm_nvm_get_variable_input::option_num
__le16 option_num
Definition bnxt_hsi.h:10307

hwrm_nvm_get_variable_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10302

hwrm_nvm_get_variable_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:10318

hwrm_nvm_get_variable_input::dest_data_addr
__le64 dest_data_addr
Definition bnxt_hsi.h:10305

hwrm_nvm_get_variable_input::index_2
__le16 index_2
Definition bnxt_hsi.h:10314

hwrm_nvm_get_variable_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10304

hwrm_nvm_get_variable_output
Definition bnxt_hsi.h:10322

hwrm_nvm_get_variable_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:10332

hwrm_nvm_get_variable_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10326

hwrm_nvm_get_variable_output::data_len
__le16 data_len
Definition bnxt_hsi.h:10327

hwrm_nvm_get_variable_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10323

hwrm_nvm_get_variable_output::option_num
__le16 option_num
Definition bnxt_hsi.h:10328

hwrm_nvm_get_variable_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10325

hwrm_nvm_get_variable_output::valid
u8 valid
Definition bnxt_hsi.h:10333

hwrm_nvm_get_variable_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10324

hwrm_nvm_install_update_cmd_err
Definition bnxt_hsi.h:10261

hwrm_nvm_install_update_cmd_err::code
u8 code
Definition bnxt_hsi.h:10262

hwrm_nvm_install_update_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10267

hwrm_nvm_install_update_input
Definition bnxt_hsi.h:10220

hwrm_nvm_install_update_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10223

hwrm_nvm_install_update_input::flags
__le16 flags
Definition bnxt_hsi.h:10230

hwrm_nvm_install_update_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:10234

hwrm_nvm_install_update_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10222

hwrm_nvm_install_update_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10221

hwrm_nvm_install_update_input::install_type
__le32 install_type
Definition bnxt_hsi.h:10226

hwrm_nvm_install_update_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10224

hwrm_nvm_install_update_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10225

hwrm_nvm_install_update_output
Definition bnxt_hsi.h:10238

hwrm_nvm_install_update_output::reset_required
u8 reset_required
Definition bnxt_hsi.h:10251

hwrm_nvm_install_update_output::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:10256

hwrm_nvm_install_update_output::installed_items
__le64 installed_items
Definition bnxt_hsi.h:10243

hwrm_nvm_install_update_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10241

hwrm_nvm_install_update_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10239

hwrm_nvm_install_update_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10242

hwrm_nvm_install_update_output::problem_item
u8 problem_item
Definition bnxt_hsi.h:10247

hwrm_nvm_install_update_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10240

hwrm_nvm_install_update_output::result
u8 result
Definition bnxt_hsi.h:10244

hwrm_nvm_install_update_output::valid
u8 valid
Definition bnxt_hsi.h:10257

hwrm_nvm_mod_dir_entry_input
Definition bnxt_hsi.h:10171

hwrm_nvm_mod_dir_entry_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10174

hwrm_nvm_mod_dir_entry_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10173

hwrm_nvm_mod_dir_entry_input::dir_idx
__le16 dir_idx
Definition bnxt_hsi.h:10179

hwrm_nvm_mod_dir_entry_input::dir_attr
__le16 dir_attr
Definition bnxt_hsi.h:10182

hwrm_nvm_mod_dir_entry_input::dir_ordinal
__le16 dir_ordinal
Definition bnxt_hsi.h:10180

hwrm_nvm_mod_dir_entry_input::enables
__le32 enables
Definition bnxt_hsi.h:10177

hwrm_nvm_mod_dir_entry_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10175

hwrm_nvm_mod_dir_entry_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10176

hwrm_nvm_mod_dir_entry_input::checksum
__le32 checksum
Definition bnxt_hsi.h:10183

hwrm_nvm_mod_dir_entry_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10172

hwrm_nvm_mod_dir_entry_input::dir_ext
__le16 dir_ext
Definition bnxt_hsi.h:10181

hwrm_nvm_mod_dir_entry_output
Definition bnxt_hsi.h:10187

hwrm_nvm_mod_dir_entry_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10191

hwrm_nvm_mod_dir_entry_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10188

hwrm_nvm_mod_dir_entry_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10192

hwrm_nvm_mod_dir_entry_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10189

hwrm_nvm_mod_dir_entry_output::valid
u8 valid
Definition bnxt_hsi.h:10193

hwrm_nvm_mod_dir_entry_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10190

hwrm_nvm_modify_input
Definition bnxt_hsi.h:10062

hwrm_nvm_modify_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10066

hwrm_nvm_modify_input::len
__le32 len
Definition bnxt_hsi.h:10072

hwrm_nvm_modify_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10063

hwrm_nvm_modify_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:10073

hwrm_nvm_modify_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10065

hwrm_nvm_modify_input::dir_idx
__le16 dir_idx
Definition bnxt_hsi.h:10069

hwrm_nvm_modify_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10067

hwrm_nvm_modify_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:10070

hwrm_nvm_modify_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10064

hwrm_nvm_modify_input::offset
__le32 offset
Definition bnxt_hsi.h:10071

hwrm_nvm_modify_input::host_src_addr
__le64 host_src_addr
Definition bnxt_hsi.h:10068

hwrm_nvm_modify_output
Definition bnxt_hsi.h:10077

hwrm_nvm_modify_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10079

hwrm_nvm_modify_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10080

hwrm_nvm_modify_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10081

hwrm_nvm_modify_output::valid
u8 valid
Definition bnxt_hsi.h:10083

hwrm_nvm_modify_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10078

hwrm_nvm_modify_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10082

hwrm_nvm_raw_dump_input
Definition bnxt_hsi.h:9957

hwrm_nvm_raw_dump_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9959

hwrm_nvm_raw_dump_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9960

hwrm_nvm_raw_dump_input::offset
__le32 offset
Definition bnxt_hsi.h:9964

hwrm_nvm_raw_dump_input::len
__le32 len
Definition bnxt_hsi.h:9965

hwrm_nvm_raw_dump_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9958

hwrm_nvm_raw_dump_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9961

hwrm_nvm_raw_dump_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9963

hwrm_nvm_raw_dump_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9962

hwrm_nvm_raw_dump_output
Definition bnxt_hsi.h:9969

hwrm_nvm_raw_dump_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9970

hwrm_nvm_raw_dump_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9971

hwrm_nvm_raw_dump_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9972

hwrm_nvm_raw_dump_output::valid
u8 valid
Definition bnxt_hsi.h:9975

hwrm_nvm_raw_dump_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9974

hwrm_nvm_raw_dump_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9973

hwrm_nvm_raw_write_blk_input
Definition bnxt_hsi.h:9910

hwrm_nvm_raw_write_blk_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9912

hwrm_nvm_raw_write_blk_input::host_src_addr
__le64 host_src_addr
Definition bnxt_hsi.h:9916

hwrm_nvm_raw_write_blk_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9914

hwrm_nvm_raw_write_blk_input::len
__le32 len
Definition bnxt_hsi.h:9918

hwrm_nvm_raw_write_blk_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9915

hwrm_nvm_raw_write_blk_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9913

hwrm_nvm_raw_write_blk_input::dest_addr
__le32 dest_addr
Definition bnxt_hsi.h:9917

hwrm_nvm_raw_write_blk_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9911

hwrm_nvm_raw_write_blk_output
Definition bnxt_hsi.h:9922

hwrm_nvm_raw_write_blk_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9926

hwrm_nvm_raw_write_blk_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9925

hwrm_nvm_raw_write_blk_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9927

hwrm_nvm_raw_write_blk_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9924

hwrm_nvm_raw_write_blk_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9923

hwrm_nvm_raw_write_blk_output::valid
u8 valid
Definition bnxt_hsi.h:9928

hwrm_nvm_read_input
Definition bnxt_hsi.h:9932

hwrm_nvm_read_input::dir_idx
__le16 dir_idx
Definition bnxt_hsi.h:9939

hwrm_nvm_read_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:9940

hwrm_nvm_read_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9937

hwrm_nvm_read_input::offset
__le32 offset
Definition bnxt_hsi.h:9941

hwrm_nvm_read_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9935

hwrm_nvm_read_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:9943

hwrm_nvm_read_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9934

hwrm_nvm_read_input::len
__le32 len
Definition bnxt_hsi.h:9942

hwrm_nvm_read_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9936

hwrm_nvm_read_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9933

hwrm_nvm_read_input::host_dest_addr
__le64 host_dest_addr
Definition bnxt_hsi.h:9938

hwrm_nvm_read_output
Definition bnxt_hsi.h:9947

hwrm_nvm_read_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9952

hwrm_nvm_read_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9950

hwrm_nvm_read_output::valid
u8 valid
Definition bnxt_hsi.h:9953

hwrm_nvm_read_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9949

hwrm_nvm_read_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9951

hwrm_nvm_read_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9948

hwrm_nvm_set_variable_cmd_err
Definition bnxt_hsi.h:10388

hwrm_nvm_set_variable_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10394

hwrm_nvm_set_variable_cmd_err::code
u8 code
Definition bnxt_hsi.h:10389

hwrm_nvm_set_variable_input
Definition bnxt_hsi.h:10348

hwrm_nvm_set_variable_input::option_num
__le16 option_num
Definition bnxt_hsi.h:10356

hwrm_nvm_set_variable_input::data_len
__le16 data_len
Definition bnxt_hsi.h:10355

hwrm_nvm_set_variable_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10349

hwrm_nvm_set_variable_input::src_data_addr
__le64 src_data_addr
Definition bnxt_hsi.h:10354

hwrm_nvm_set_variable_input::index_1
__le16 index_1
Definition bnxt_hsi.h:10362

hwrm_nvm_set_variable_input::dimensions
__le16 dimensions
Definition bnxt_hsi.h:10360

hwrm_nvm_set_variable_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10350

hwrm_nvm_set_variable_input::index_0
__le16 index_0
Definition bnxt_hsi.h:10361

hwrm_nvm_set_variable_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:10374

hwrm_nvm_set_variable_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10352

hwrm_nvm_set_variable_input::index_3
__le16 index_3
Definition bnxt_hsi.h:10364

hwrm_nvm_set_variable_input::flags
u8 flags
Definition bnxt_hsi.h:10365

hwrm_nvm_set_variable_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10353

hwrm_nvm_set_variable_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10351

hwrm_nvm_set_variable_input::index_2
__le16 index_2
Definition bnxt_hsi.h:10363

hwrm_nvm_set_variable_output
Definition bnxt_hsi.h:10378

hwrm_nvm_set_variable_output::valid
u8 valid
Definition bnxt_hsi.h:10384

hwrm_nvm_set_variable_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10380

hwrm_nvm_set_variable_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10382

hwrm_nvm_set_variable_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10379

hwrm_nvm_set_variable_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10381

hwrm_nvm_set_variable_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10383

hwrm_nvm_validate_option_cmd_err
Definition bnxt_hsi.h:10433

hwrm_nvm_validate_option_cmd_err::code
u8 code
Definition bnxt_hsi.h:10434

hwrm_nvm_validate_option_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10437

hwrm_nvm_validate_option_input
Definition bnxt_hsi.h:10398

hwrm_nvm_validate_option_input::dimensions
__le16 dimensions
Definition bnxt_hsi.h:10410

hwrm_nvm_validate_option_input::src_data_addr
__le64 src_data_addr
Definition bnxt_hsi.h:10404

hwrm_nvm_validate_option_input::index_3
__le16 index_3
Definition bnxt_hsi.h:10414

hwrm_nvm_validate_option_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:10415

hwrm_nvm_validate_option_input::index_1
__le16 index_1
Definition bnxt_hsi.h:10412

hwrm_nvm_validate_option_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10399

hwrm_nvm_validate_option_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10402

hwrm_nvm_validate_option_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10403

hwrm_nvm_validate_option_input::index_0
__le16 index_0
Definition bnxt_hsi.h:10411

hwrm_nvm_validate_option_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10401

hwrm_nvm_validate_option_input::index_2
__le16 index_2
Definition bnxt_hsi.h:10413

hwrm_nvm_validate_option_input::data_len
__le16 data_len
Definition bnxt_hsi.h:10405

hwrm_nvm_validate_option_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10400

hwrm_nvm_validate_option_input::option_num
__le16 option_num
Definition bnxt_hsi.h:10406

hwrm_nvm_validate_option_output
Definition bnxt_hsi.h:10419

hwrm_nvm_validate_option_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10420

hwrm_nvm_validate_option_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10421

hwrm_nvm_validate_option_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10422

hwrm_nvm_validate_option_output::result
u8 result
Definition bnxt_hsi.h:10424

hwrm_nvm_validate_option_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10423

hwrm_nvm_validate_option_output::valid
u8 valid
Definition bnxt_hsi.h:10429

hwrm_nvm_validate_option_output::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:10428

hwrm_nvm_verify_update_input
Definition bnxt_hsi.h:10197

hwrm_nvm_verify_update_input::dir_ext
__le16 dir_ext
Definition bnxt_hsi.h:10205

hwrm_nvm_verify_update_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10202

hwrm_nvm_verify_update_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10200

hwrm_nvm_verify_update_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10199

hwrm_nvm_verify_update_input::dir_ordinal
__le16 dir_ordinal
Definition bnxt_hsi.h:10204

hwrm_nvm_verify_update_input::dir_type
__le16 dir_type
Definition bnxt_hsi.h:10203

hwrm_nvm_verify_update_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10198

hwrm_nvm_verify_update_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10201

hwrm_nvm_verify_update_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:10206

hwrm_nvm_verify_update_output
Definition bnxt_hsi.h:10210

hwrm_nvm_verify_update_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10212

hwrm_nvm_verify_update_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10213

hwrm_nvm_verify_update_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10215

hwrm_nvm_verify_update_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10214

hwrm_nvm_verify_update_output::valid
u8 valid
Definition bnxt_hsi.h:10216

hwrm_nvm_verify_update_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10211

hwrm_nvm_write_cmd_err
Definition bnxt_hsi.h:10052

hwrm_nvm_write_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10058

hwrm_nvm_write_cmd_err::code
u8 code
Definition bnxt_hsi.h:10053

hwrm_nvm_write_input
Definition bnxt_hsi.h:10020

hwrm_nvm_write_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10024

hwrm_nvm_write_input::unused_0
__le32 unused_0
Definition bnxt_hsi.h:10036

hwrm_nvm_write_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10021

hwrm_nvm_write_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10025

hwrm_nvm_write_input::dir_ext
__le16 dir_ext
Definition bnxt_hsi.h:10029

hwrm_nvm_write_input::flags
__le16 flags
Definition bnxt_hsi.h:10033

hwrm_nvm_write_input::option
__le16 option
Definition bnxt_hsi.h:10032

hwrm_nvm_write_input::dir_item_length
__le32 dir_item_length
Definition bnxt_hsi.h:10035

hwrm_nvm_write_input::dir_data_length
__le32 dir_data_length
Definition bnxt_hsi.h:10031

hwrm_nvm_write_input::dir_ordinal
__le16 dir_ordinal
Definition bnxt_hsi.h:10028

hwrm_nvm_write_input::dir_attr
__le16 dir_attr
Definition bnxt_hsi.h:10030

hwrm_nvm_write_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10022

hwrm_nvm_write_input::host_src_addr
__le64 host_src_addr
Definition bnxt_hsi.h:10026

hwrm_nvm_write_input::dir_type
__le16 dir_type
Definition bnxt_hsi.h:10027

hwrm_nvm_write_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10023

hwrm_nvm_write_output
Definition bnxt_hsi.h:10040

hwrm_nvm_write_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:10047

hwrm_nvm_write_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10041

hwrm_nvm_write_output::valid
u8 valid
Definition bnxt_hsi.h:10048

hwrm_nvm_write_output::dir_idx
__le16 dir_idx
Definition bnxt_hsi.h:10046

hwrm_nvm_write_output::dir_item_length
__le32 dir_item_length
Definition bnxt_hsi.h:10045

hwrm_nvm_write_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10044

hwrm_nvm_write_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10043

hwrm_nvm_write_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10042

hwrm_oem_cmd_input
Definition bnxt_hsi.h:10628

hwrm_oem_cmd_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10633

hwrm_oem_cmd_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10632

hwrm_oem_cmd_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10629

hwrm_oem_cmd_input::IANA
__le32 IANA
Definition bnxt_hsi.h:10634

hwrm_oem_cmd_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10631

hwrm_oem_cmd_input::oem_data
__le32 oem_data[26]
Definition bnxt_hsi.h:10636

hwrm_oem_cmd_input::unused_0
__le32 unused_0
Definition bnxt_hsi.h:10635

hwrm_oem_cmd_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10630

hwrm_oem_cmd_output
Definition bnxt_hsi.h:10640

hwrm_oem_cmd_output::oem_data
__le32 oem_data[36]
Definition bnxt_hsi.h:10647

hwrm_oem_cmd_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10641

hwrm_oem_cmd_output::IANA
__le32 IANA
Definition bnxt_hsi.h:10645

hwrm_oem_cmd_output::unused_0
__le32 unused_0
Definition bnxt_hsi.h:10646

hwrm_oem_cmd_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10644

hwrm_oem_cmd_output::valid
u8 valid
Definition bnxt_hsi.h:10649

hwrm_oem_cmd_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:10648

hwrm_oem_cmd_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10642

hwrm_oem_cmd_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10643

hwrm_pcie_qstats_input
Definition bnxt_hsi.h:8655

hwrm_pcie_qstats_input::pcie_stat_host_addr
__le64 pcie_stat_host_addr
Definition bnxt_hsi.h:8663

hwrm_pcie_qstats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8658

hwrm_pcie_qstats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8660

hwrm_pcie_qstats_input::pcie_stat_size
__le16 pcie_stat_size
Definition bnxt_hsi.h:8661

hwrm_pcie_qstats_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:8662

hwrm_pcie_qstats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8656

hwrm_pcie_qstats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8659

hwrm_pcie_qstats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8657

hwrm_pcie_qstats_output
Definition bnxt_hsi.h:8667

hwrm_pcie_qstats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8670

hwrm_pcie_qstats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8671

hwrm_pcie_qstats_output::pcie_stat_size
__le16 pcie_stat_size
Definition bnxt_hsi.h:8672

hwrm_pcie_qstats_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:8673

hwrm_pcie_qstats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8668

hwrm_pcie_qstats_output::valid
u8 valid
Definition bnxt_hsi.h:8674

hwrm_pcie_qstats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8669

hwrm_port_clr_stats_input
Definition bnxt_hsi.h:4079

hwrm_port_clr_stats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4080

hwrm_port_clr_stats_input::flags
u8 flags
Definition bnxt_hsi.h:4086

hwrm_port_clr_stats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4083

hwrm_port_clr_stats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4082

hwrm_port_clr_stats_input::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:4088

hwrm_port_clr_stats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4081

hwrm_port_clr_stats_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4085

hwrm_port_clr_stats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4084

hwrm_port_clr_stats_output
Definition bnxt_hsi.h:4092

hwrm_port_clr_stats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4093

hwrm_port_clr_stats_output::valid
u8 valid
Definition bnxt_hsi.h:4098

hwrm_port_clr_stats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4095

hwrm_port_clr_stats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4096

hwrm_port_clr_stats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4094

hwrm_port_clr_stats_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4097

hwrm_port_led_cfg_input
Definition bnxt_hsi.h:4335

hwrm_port_led_cfg_input::unused_3
u8 unused_3
Definition bnxt_hsi.h:4440

hwrm_port_led_cfg_input::led3_group_id
u8 led3_group_id
Definition bnxt_hsi.h:4443

hwrm_port_led_cfg_input::rsvd3
u8 rsvd3
Definition bnxt_hsi.h:4444

hwrm_port_led_cfg_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:4383

hwrm_port_led_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:4341

hwrm_port_led_cfg_input::led0_state
u8 led0_state
Definition bnxt_hsi.h:4370

hwrm_port_led_cfg_input::led2_group_id
u8 led2_group_id
Definition bnxt_hsi.h:4424

hwrm_port_led_cfg_input::led0_color
u8 led0_color
Definition bnxt_hsi.h:4377

hwrm_port_led_cfg_input::led3_id
u8 led3_id
Definition bnxt_hsi.h:4426

hwrm_port_led_cfg_input::led2_blink_on
__le16 led2_blink_on
Definition bnxt_hsi.h:4422

hwrm_port_led_cfg_input::led3_blink_off
__le16 led3_blink_off
Definition bnxt_hsi.h:4442

hwrm_port_led_cfg_input::led0_blink_on
__le16 led0_blink_on
Definition bnxt_hsi.h:4384

hwrm_port_led_cfg_input::led2_state
u8 led2_state
Definition bnxt_hsi.h:4408

hwrm_port_led_cfg_input::led3_blink_on
__le16 led3_blink_on
Definition bnxt_hsi.h:4441

hwrm_port_led_cfg_input::led3_state
u8 led3_state
Definition bnxt_hsi.h:4427

hwrm_port_led_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4337

hwrm_port_led_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4338

hwrm_port_led_cfg_input::unused_2
u8 unused_2
Definition bnxt_hsi.h:4421

hwrm_port_led_cfg_input::rsvd0
u8 rsvd0
Definition bnxt_hsi.h:4387

hwrm_port_led_cfg_input::led3_color
u8 led3_color
Definition bnxt_hsi.h:4434

hwrm_port_led_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4340

hwrm_port_led_cfg_input::led2_id
u8 led2_id
Definition bnxt_hsi.h:4407

hwrm_port_led_cfg_input::num_leds
u8 num_leds
Definition bnxt_hsi.h:4367

hwrm_port_led_cfg_input::rsvd
u8 rsvd
Definition bnxt_hsi.h:4368

hwrm_port_led_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4339

hwrm_port_led_cfg_input::led2_color
u8 led2_color
Definition bnxt_hsi.h:4415

hwrm_port_led_cfg_input::led1_blink_on
__le16 led1_blink_on
Definition bnxt_hsi.h:4403

hwrm_port_led_cfg_input::led1_state
u8 led1_state
Definition bnxt_hsi.h:4389

hwrm_port_led_cfg_input::led0_blink_off
__le16 led0_blink_off
Definition bnxt_hsi.h:4385

hwrm_port_led_cfg_input::unused_1
u8 unused_1
Definition bnxt_hsi.h:4402

hwrm_port_led_cfg_input::led2_blink_off
__le16 led2_blink_off
Definition bnxt_hsi.h:4423

hwrm_port_led_cfg_input::led1_id
u8 led1_id
Definition bnxt_hsi.h:4388

hwrm_port_led_cfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4366

hwrm_port_led_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4336

hwrm_port_led_cfg_input::led1_group_id
u8 led1_group_id
Definition bnxt_hsi.h:4405

hwrm_port_led_cfg_input::led0_id
u8 led0_id
Definition bnxt_hsi.h:4369

hwrm_port_led_cfg_input::led1_color
u8 led1_color
Definition bnxt_hsi.h:4396

hwrm_port_led_cfg_input::led1_blink_off
__le16 led1_blink_off
Definition bnxt_hsi.h:4404

hwrm_port_led_cfg_input::rsvd1
u8 rsvd1
Definition bnxt_hsi.h:4406

hwrm_port_led_cfg_input::led0_group_id
u8 led0_group_id
Definition bnxt_hsi.h:4386

hwrm_port_led_cfg_input::rsvd2
u8 rsvd2
Definition bnxt_hsi.h:4425

hwrm_port_led_cfg_output
Definition bnxt_hsi.h:4448

hwrm_port_led_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4453

hwrm_port_led_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:4454

hwrm_port_led_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4449

hwrm_port_led_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4451

hwrm_port_led_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4450

hwrm_port_led_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4452

hwrm_port_led_qcaps_input
Definition bnxt_hsi.h:4572

hwrm_port_led_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4577

hwrm_port_led_qcaps_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4578

hwrm_port_led_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4576

hwrm_port_led_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4574

hwrm_port_led_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4575

hwrm_port_led_qcaps_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:4579

hwrm_port_led_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4573

hwrm_port_led_qcaps_output
Definition bnxt_hsi.h:4583

hwrm_port_led_qcaps_output::led0_group_id
u8 led0_group_id
Definition bnxt_hsi.h:4596

hwrm_port_led_qcaps_output::led1_group_id
u8 led1_group_id
Definition bnxt_hsi.h:4614

hwrm_port_led_qcaps_output::led0_state_caps
__le16 led0_state_caps
Definition bnxt_hsi.h:4598

hwrm_port_led_qcaps_output::unused_4
u8 unused_4[3]
Definition bnxt_hsi.h:4662

hwrm_port_led_qcaps_output::led2_type
u8 led2_type
Definition bnxt_hsi.h:4627

hwrm_port_led_qcaps_output::led1_id
u8 led1_id
Definition bnxt_hsi.h:4608

hwrm_port_led_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4587

hwrm_port_led_qcaps_output::unused_2
u8 unused_2
Definition bnxt_hsi.h:4633

hwrm_port_led_qcaps_output::unused
u8 unused[3]
Definition bnxt_hsi.h:4589

hwrm_port_led_qcaps_output::led0_type
u8 led0_type
Definition bnxt_hsi.h:4591

hwrm_port_led_qcaps_output::led0_id
u8 led0_id
Definition bnxt_hsi.h:4590

hwrm_port_led_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4586

hwrm_port_led_qcaps_output::unused_3
u8 unused_3
Definition bnxt_hsi.h:4651

hwrm_port_led_qcaps_output::led1_type
u8 led1_type
Definition bnxt_hsi.h:4609

hwrm_port_led_qcaps_output::led0_color_caps
__le16 led0_color_caps
Definition bnxt_hsi.h:4604

hwrm_port_led_qcaps_output::led3_state_caps
__le16 led3_state_caps
Definition bnxt_hsi.h:4652

hwrm_port_led_qcaps_output::led3_id
u8 led3_id
Definition bnxt_hsi.h:4644

hwrm_port_led_qcaps_output::led1_color_caps
__le16 led1_color_caps
Definition bnxt_hsi.h:4622

hwrm_port_led_qcaps_output::led2_state_caps
__le16 led2_state_caps
Definition bnxt_hsi.h:4634

hwrm_port_led_qcaps_output::led3_type
u8 led3_type
Definition bnxt_hsi.h:4645

hwrm_port_led_qcaps_output::led2_group_id
u8 led2_group_id
Definition bnxt_hsi.h:4632

hwrm_port_led_qcaps_output::led2_id
u8 led2_id
Definition bnxt_hsi.h:4626

hwrm_port_led_qcaps_output::led3_group_id
u8 led3_group_id
Definition bnxt_hsi.h:4650

hwrm_port_led_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:4663

hwrm_port_led_qcaps_output::led1_state_caps
__le16 led1_state_caps
Definition bnxt_hsi.h:4616

hwrm_port_led_qcaps_output::led2_color_caps
__le16 led2_color_caps
Definition bnxt_hsi.h:4640

hwrm_port_led_qcaps_output::unused_1
u8 unused_1
Definition bnxt_hsi.h:4615

hwrm_port_led_qcaps_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:4597

hwrm_port_led_qcaps_output::led3_color_caps
__le16 led3_color_caps
Definition bnxt_hsi.h:4658

hwrm_port_led_qcaps_output::num_leds
u8 num_leds
Definition bnxt_hsi.h:4588

hwrm_port_led_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4585

hwrm_port_led_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4584

hwrm_port_led_qcfg_input
Definition bnxt_hsi.h:4458

hwrm_port_led_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4460

hwrm_port_led_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:4465

hwrm_port_led_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4462

hwrm_port_led_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4463

hwrm_port_led_qcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4464

hwrm_port_led_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4461

hwrm_port_led_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4459

hwrm_port_led_qcfg_output
Definition bnxt_hsi.h:4469

hwrm_port_led_qcfg_output::led3_id
u8 led3_id
Definition bnxt_hsi.h:4544

hwrm_port_led_qcfg_output::led0_type
u8 led0_type
Definition bnxt_hsi.h:4476

hwrm_port_led_qcfg_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:4494

hwrm_port_led_qcfg_output::led1_blink_off
__le16 led1_blink_off
Definition bnxt_hsi.h:4519

hwrm_port_led_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4473

hwrm_port_led_qcfg_output::led1_type
u8 led1_type
Definition bnxt_hsi.h:4499

hwrm_port_led_qcfg_output::led0_group_id
u8 led0_group_id
Definition bnxt_hsi.h:4497

hwrm_port_led_qcfg_output::led0_color
u8 led0_color
Definition bnxt_hsi.h:4488

hwrm_port_led_qcfg_output::led2_blink_off
__le16 led2_blink_off
Definition bnxt_hsi.h:4542

hwrm_port_led_qcfg_output::led0_blink_off
__le16 led0_blink_off
Definition bnxt_hsi.h:4496

hwrm_port_led_qcfg_output::led3_group_id
u8 led3_group_id
Definition bnxt_hsi.h:4566

hwrm_port_led_qcfg_output::unused_4
u8 unused_4[6]
Definition bnxt_hsi.h:4567

hwrm_port_led_qcfg_output::led2_blink_on
__le16 led2_blink_on
Definition bnxt_hsi.h:4541

hwrm_port_led_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4471

hwrm_port_led_qcfg_output::unused_2
u8 unused_2
Definition bnxt_hsi.h:4540

hwrm_port_led_qcfg_output::led0_state
u8 led0_state
Definition bnxt_hsi.h:4481

hwrm_port_led_qcfg_output::led2_type
u8 led2_type
Definition bnxt_hsi.h:4522

hwrm_port_led_qcfg_output::unused_3
u8 unused_3
Definition bnxt_hsi.h:4563

hwrm_port_led_qcfg_output::led3_blink_on
__le16 led3_blink_on
Definition bnxt_hsi.h:4564

hwrm_port_led_qcfg_output::led2_color
u8 led2_color
Definition bnxt_hsi.h:4534

hwrm_port_led_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:4568

hwrm_port_led_qcfg_output::led1_group_id
u8 led1_group_id
Definition bnxt_hsi.h:4520

hwrm_port_led_qcfg_output::led1_id
u8 led1_id
Definition bnxt_hsi.h:4498

hwrm_port_led_qcfg_output::led2_state
u8 led2_state
Definition bnxt_hsi.h:4527

hwrm_port_led_qcfg_output::led3_state
u8 led3_state
Definition bnxt_hsi.h:4550

hwrm_port_led_qcfg_output::led0_blink_on
__le16 led0_blink_on
Definition bnxt_hsi.h:4495

hwrm_port_led_qcfg_output::unused_1
u8 unused_1
Definition bnxt_hsi.h:4517

hwrm_port_led_qcfg_output::num_leds
u8 num_leds
Definition bnxt_hsi.h:4474

hwrm_port_led_qcfg_output::led1_state
u8 led1_state
Definition bnxt_hsi.h:4504

hwrm_port_led_qcfg_output::led1_color
u8 led1_color
Definition bnxt_hsi.h:4511

hwrm_port_led_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4470

hwrm_port_led_qcfg_output::led3_blink_off
__le16 led3_blink_off
Definition bnxt_hsi.h:4565

hwrm_port_led_qcfg_output::led3_color
u8 led3_color
Definition bnxt_hsi.h:4557

hwrm_port_led_qcfg_output::led1_blink_on
__le16 led1_blink_on
Definition bnxt_hsi.h:4518

hwrm_port_led_qcfg_output::led3_type
u8 led3_type
Definition bnxt_hsi.h:4545

hwrm_port_led_qcfg_output::led2_group_id
u8 led2_group_id
Definition bnxt_hsi.h:4543

hwrm_port_led_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4472

hwrm_port_led_qcfg_output::led2_id
u8 led2_id
Definition bnxt_hsi.h:4521

hwrm_port_led_qcfg_output::led0_id
u8 led0_id
Definition bnxt_hsi.h:4475

hwrm_port_lpbk_clr_stats_input
Definition bnxt_hsi.h:4102

hwrm_port_lpbk_clr_stats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4103

hwrm_port_lpbk_clr_stats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4106

hwrm_port_lpbk_clr_stats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4104

hwrm_port_lpbk_clr_stats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4105

hwrm_port_lpbk_clr_stats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4107

hwrm_port_lpbk_clr_stats_output
Definition bnxt_hsi.h:4111

hwrm_port_lpbk_clr_stats_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4116

hwrm_port_lpbk_clr_stats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4114

hwrm_port_lpbk_clr_stats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4113

hwrm_port_lpbk_clr_stats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4112

hwrm_port_lpbk_clr_stats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4115

hwrm_port_lpbk_clr_stats_output::valid
u8 valid
Definition bnxt_hsi.h:4117

hwrm_port_lpbk_qstats_input
Definition bnxt_hsi.h:4050

hwrm_port_lpbk_qstats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4051

hwrm_port_lpbk_qstats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4053

hwrm_port_lpbk_qstats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4052

hwrm_port_lpbk_qstats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4054

hwrm_port_lpbk_qstats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4055

hwrm_port_lpbk_qstats_output
Definition bnxt_hsi.h:4059

hwrm_port_lpbk_qstats_output::rx_stat_discard
__le64 rx_stat_discard
Definition bnxt_hsi.h:4072

hwrm_port_lpbk_qstats_output::lpbk_ucast_frames
__le64 lpbk_ucast_frames
Definition bnxt_hsi.h:4064

hwrm_port_lpbk_qstats_output::lpbk_bcast_bytes
__le64 lpbk_bcast_bytes
Definition bnxt_hsi.h:4069

hwrm_port_lpbk_qstats_output::rx_stat_error
__le64 rx_stat_error
Definition bnxt_hsi.h:4073

hwrm_port_lpbk_qstats_output::lpbk_bcast_frames
__le64 lpbk_bcast_frames
Definition bnxt_hsi.h:4066

hwrm_port_lpbk_qstats_output::valid
u8 valid
Definition bnxt_hsi.h:4075

hwrm_port_lpbk_qstats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4063

hwrm_port_lpbk_qstats_output::lpbk_mcast_frames
__le64 lpbk_mcast_frames
Definition bnxt_hsi.h:4065

hwrm_port_lpbk_qstats_output::lpbk_ucast_bytes
__le64 lpbk_ucast_bytes
Definition bnxt_hsi.h:4067

hwrm_port_lpbk_qstats_output::tx_stat_discard
__le64 tx_stat_discard
Definition bnxt_hsi.h:4070

hwrm_port_lpbk_qstats_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4074

hwrm_port_lpbk_qstats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4062

hwrm_port_lpbk_qstats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4060

hwrm_port_lpbk_qstats_output::tx_stat_error
__le64 tx_stat_error
Definition bnxt_hsi.h:4071

hwrm_port_lpbk_qstats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4061

hwrm_port_lpbk_qstats_output::lpbk_mcast_bytes
__le64 lpbk_mcast_bytes
Definition bnxt_hsi.h:4068

hwrm_port_mac_cfg_input
Definition bnxt_hsi.h:3614

hwrm_port_mac_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:3634

hwrm_port_mac_cfg_input::ipg
u8 ipg
Definition bnxt_hsi.h:3644

hwrm_port_mac_cfg_input::tx_ts_capture_ptp_msg_type
__le16 tx_ts_capture_ptp_msg_type
Definition bnxt_hsi.h:3655

hwrm_port_mac_cfg_input::lpbk
u8 lpbk
Definition bnxt_hsi.h:3645

hwrm_port_mac_cfg_input::reserved1
u8 reserved1
Definition bnxt_hsi.h:3651

hwrm_port_mac_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:3615

hwrm_port_mac_cfg_input::cos_field_cfg
u8 cos_field_cfg
Definition bnxt_hsi.h:3656

hwrm_port_mac_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:3618

hwrm_port_mac_cfg_input::vlan_pri2cos_map_pri
u8 vlan_pri2cos_map_pri
Definition bnxt_hsi.h:3650

hwrm_port_mac_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:3619

hwrm_port_mac_cfg_input::tunnel_pri2cos_map_pri
u8 tunnel_pri2cos_map_pri
Definition bnxt_hsi.h:3652

hwrm_port_mac_cfg_input::rx_ts_capture_ptp_msg_type
__le16 rx_ts_capture_ptp_msg_type
Definition bnxt_hsi.h:3654

hwrm_port_mac_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3617

hwrm_port_mac_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:3616

hwrm_port_mac_cfg_input::dscp2pri_map_pri
u8 dscp2pri_map_pri
Definition bnxt_hsi.h:3653

hwrm_port_mac_cfg_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:3674

hwrm_port_mac_cfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:3643

hwrm_port_mac_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:3620

hwrm_port_mac_cfg_output
Definition bnxt_hsi.h:3678

hwrm_port_mac_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:3680

hwrm_port_mac_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:3692

hwrm_port_mac_cfg_output::lpbk
u8 lpbk
Definition bnxt_hsi.h:3686

hwrm_port_mac_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3681

hwrm_port_mac_cfg_output::mtu
__le16 mtu
Definition bnxt_hsi.h:3684

hwrm_port_mac_cfg_output::mru
__le16 mru
Definition bnxt_hsi.h:3683

hwrm_port_mac_cfg_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:3691

hwrm_port_mac_cfg_output::ipg
u8 ipg
Definition bnxt_hsi.h:3685

hwrm_port_mac_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:3682

hwrm_port_mac_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:3679

hwrm_port_mac_ptp_qcfg_input
Definition bnxt_hsi.h:3754

hwrm_port_mac_ptp_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:3755

hwrm_port_mac_ptp_qcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:3760

hwrm_port_mac_ptp_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:3758

hwrm_port_mac_ptp_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:3761

hwrm_port_mac_ptp_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:3759

hwrm_port_mac_ptp_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3757

hwrm_port_mac_ptp_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:3756

hwrm_port_mac_ptp_qcfg_output
Definition bnxt_hsi.h:3765

hwrm_port_mac_ptp_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:3766

hwrm_port_mac_ptp_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:3790

hwrm_port_mac_ptp_qcfg_output::tx_ts_reg_off_granularity
__le32 tx_ts_reg_off_granularity
Definition bnxt_hsi.h:3788

hwrm_port_mac_ptp_qcfg_output::tx_ts_reg_off_seq_id
__le32 tx_ts_reg_off_seq_id
Definition bnxt_hsi.h:3786

hwrm_port_mac_ptp_qcfg_output::flags
u8 flags
Definition bnxt_hsi.h:3770

hwrm_port_mac_ptp_qcfg_output::tx_ts_reg_off_upper
__le32 tx_ts_reg_off_upper
Definition bnxt_hsi.h:3785

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_seq_id
__le32 rx_ts_reg_off_seq_id
Definition bnxt_hsi.h:3776

hwrm_port_mac_ptp_qcfg_output::tx_ts_reg_off_fifo
__le32 tx_ts_reg_off_fifo
Definition bnxt_hsi.h:3787

hwrm_port_mac_ptp_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3768

hwrm_port_mac_ptp_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:3769

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_lower
__le32 rx_ts_reg_off_lower
Definition bnxt_hsi.h:3774

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_fifo
__le32 rx_ts_reg_off_fifo
Definition bnxt_hsi.h:3781

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_fifo_adv
__le32 rx_ts_reg_off_fifo_adv
Definition bnxt_hsi.h:3782

hwrm_port_mac_ptp_qcfg_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:3773

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_upper
__le32 rx_ts_reg_off_upper
Definition bnxt_hsi.h:3775

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_src_id_0
__le32 rx_ts_reg_off_src_id_0
Definition bnxt_hsi.h:3777

hwrm_port_mac_ptp_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:3767

hwrm_port_mac_ptp_qcfg_output::tx_ts_reg_off_lower
__le32 tx_ts_reg_off_lower
Definition bnxt_hsi.h:3784

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_domain_id
__le32 rx_ts_reg_off_domain_id
Definition bnxt_hsi.h:3780

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_src_id_1
__le32 rx_ts_reg_off_src_id_1
Definition bnxt_hsi.h:3778

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_granularity
__le32 rx_ts_reg_off_granularity
Definition bnxt_hsi.h:3783

hwrm_port_mac_ptp_qcfg_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:3789

hwrm_port_mac_ptp_qcfg_output::rx_ts_reg_off_src_id_2
__le32 rx_ts_reg_off_src_id_2
Definition bnxt_hsi.h:3779

hwrm_port_mac_qcfg_input
Definition bnxt_hsi.h:3696

hwrm_port_mac_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:3698

hwrm_port_mac_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:3703

hwrm_port_mac_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:3697

hwrm_port_mac_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:3700

hwrm_port_mac_qcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:3702

hwrm_port_mac_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:3701

hwrm_port_mac_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3699

hwrm_port_mac_qcfg_output
Definition bnxt_hsi.h:3707

hwrm_port_mac_qcfg_output::dscp2pri_map_pri
u8 dscp2pri_map_pri
Definition bnxt_hsi.h:3729

hwrm_port_mac_qcfg_output::mru
__le16 mru
Definition bnxt_hsi.h:3712

hwrm_port_mac_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3710

hwrm_port_mac_qcfg_output::tx_ts_capture_ptp_msg_type
__le16 tx_ts_capture_ptp_msg_type
Definition bnxt_hsi.h:3731

hwrm_port_mac_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:3708

hwrm_port_mac_qcfg_output::flags
u8 flags
Definition bnxt_hsi.h:3721

hwrm_port_mac_qcfg_output::tunnel_pri2cos_map_pri
u8 tunnel_pri2cos_map_pri
Definition bnxt_hsi.h:3728

hwrm_port_mac_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:3750

hwrm_port_mac_qcfg_output::rx_ts_capture_ptp_msg_type
__le16 rx_ts_capture_ptp_msg_type
Definition bnxt_hsi.h:3730

hwrm_port_mac_qcfg_output::cos_field_cfg
u8 cos_field_cfg
Definition bnxt_hsi.h:3732

hwrm_port_mac_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:3711

hwrm_port_mac_qcfg_output::lpbk
u8 lpbk
Definition bnxt_hsi.h:3715

hwrm_port_mac_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:3709

hwrm_port_mac_qcfg_output::mtu
__le16 mtu
Definition bnxt_hsi.h:3713

hwrm_port_mac_qcfg_output::ipg
u8 ipg
Definition bnxt_hsi.h:3714

hwrm_port_mac_qcfg_output::vlan_pri2cos_map_pri
u8 vlan_pri2cos_map_pri
Definition bnxt_hsi.h:3720

hwrm_port_phy_cfg_cmd_err
Definition bnxt_hsi.h:3222

hwrm_port_phy_cfg_cmd_err::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:3228

hwrm_port_phy_cfg_cmd_err::code
u8 code
Definition bnxt_hsi.h:3223

hwrm_port_phy_cfg_input
Definition bnxt_hsi.h:3035

hwrm_port_phy_cfg_input::lpbk
u8 lpbk
Definition bnxt_hsi.h:3148

hwrm_port_phy_cfg_input::auto_duplex
u8 auto_duplex
Definition bnxt_hsi.h:3104

hwrm_port_phy_cfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:3082

hwrm_port_phy_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:3040

hwrm_port_phy_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:3041

hwrm_port_phy_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3038

hwrm_port_phy_cfg_input::auto_link_speed_mask
__le16 auto_link_speed_mask
Definition bnxt_hsi.h:3128

hwrm_port_phy_cfg_input::auto_link_speeds2_mask
__le16 auto_link_speeds2_mask
Definition bnxt_hsi.h:3194

hwrm_port_phy_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:3036

hwrm_port_phy_cfg_input::preemphasis
__le32 preemphasis
Definition bnxt_hsi.h:3158

hwrm_port_phy_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:3039

hwrm_port_phy_cfg_input::unused_2
u8 unused_2[6]
Definition bnxt_hsi.h:3208

hwrm_port_phy_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:3037

hwrm_port_phy_cfg_input::auto_mode
u8 auto_mode
Definition bnxt_hsi.h:3097

hwrm_port_phy_cfg_input::unused_1
u8 unused_1
Definition bnxt_hsi.h:3157

hwrm_port_phy_cfg_input::force_pause
u8 force_pause
Definition bnxt_hsi.h:3154

hwrm_port_phy_cfg_input::force_link_speed
__le16 force_link_speed
Definition bnxt_hsi.h:3083

hwrm_port_phy_cfg_input::auto_pause
u8 auto_pause
Definition bnxt_hsi.h:3109

hwrm_port_phy_cfg_input::eee_link_speed_mask
__le16 eee_link_speed_mask
Definition bnxt_hsi.h:3159

hwrm_port_phy_cfg_input::force_link_speeds2
__le16 force_link_speeds2
Definition bnxt_hsi.h:3179

hwrm_port_phy_cfg_input::wirespeed
u8 wirespeed
Definition bnxt_hsi.h:3144

hwrm_port_phy_cfg_input::force_pam4_link_speed
__le16 force_pam4_link_speed
Definition bnxt_hsi.h:3167

hwrm_port_phy_cfg_input::auto_link_speed
__le16 auto_link_speed
Definition bnxt_hsi.h:3114

hwrm_port_phy_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:3066

hwrm_port_phy_cfg_input::auto_link_pam4_speed_mask
__le16 auto_link_pam4_speed_mask
Definition bnxt_hsi.h:3175

hwrm_port_phy_cfg_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:3113

hwrm_port_phy_cfg_input::tx_lpi_timer
__le32 tx_lpi_timer
Definition bnxt_hsi.h:3172

hwrm_port_phy_cfg_output
Definition bnxt_hsi.h:3212

hwrm_port_phy_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:3213

hwrm_port_phy_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3215

hwrm_port_phy_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:3216

hwrm_port_phy_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:3217

hwrm_port_phy_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:3218

hwrm_port_phy_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:3214

hwrm_port_phy_i2c_read_input
Definition bnxt_hsi.h:4305

hwrm_port_phy_i2c_read_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:4316

hwrm_port_phy_i2c_read_input::enables
__le32 enables
Definition bnxt_hsi.h:4312

hwrm_port_phy_i2c_read_input::page_number
__le16 page_number
Definition bnxt_hsi.h:4317

hwrm_port_phy_i2c_read_input::flags
__le32 flags
Definition bnxt_hsi.h:4311

hwrm_port_phy_i2c_read_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4314

hwrm_port_phy_i2c_read_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4308

hwrm_port_phy_i2c_read_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4309

hwrm_port_phy_i2c_read_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4310

hwrm_port_phy_i2c_read_input::i2c_slave_addr
u8 i2c_slave_addr
Definition bnxt_hsi.h:4315

hwrm_port_phy_i2c_read_input::data_length
u8 data_length
Definition bnxt_hsi.h:4319

hwrm_port_phy_i2c_read_input::page_offset
__le16 page_offset
Definition bnxt_hsi.h:4318

hwrm_port_phy_i2c_read_input::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:4320

hwrm_port_phy_i2c_read_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4307

hwrm_port_phy_i2c_read_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4306

hwrm_port_phy_i2c_read_output
Definition bnxt_hsi.h:4324

hwrm_port_phy_i2c_read_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4330

hwrm_port_phy_i2c_read_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4328

hwrm_port_phy_i2c_read_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4327

hwrm_port_phy_i2c_read_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4325

hwrm_port_phy_i2c_read_output::valid
u8 valid
Definition bnxt_hsi.h:4331

hwrm_port_phy_i2c_read_output::data
__le32 data[16]
Definition bnxt_hsi.h:4329

hwrm_port_phy_i2c_read_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4326

hwrm_port_phy_i2c_write_input
Definition bnxt_hsi.h:4275

hwrm_port_phy_i2c_write_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4277

hwrm_port_phy_i2c_write_input::data
__le32 data[16]
Definition bnxt_hsi.h:4291

hwrm_port_phy_i2c_write_input::data_length
u8 data_length
Definition bnxt_hsi.h:4289

hwrm_port_phy_i2c_write_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:4286

hwrm_port_phy_i2c_write_input::i2c_slave_addr
u8 i2c_slave_addr
Definition bnxt_hsi.h:4285

hwrm_port_phy_i2c_write_input::page_number
__le16 page_number
Definition bnxt_hsi.h:4287

hwrm_port_phy_i2c_write_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4279

hwrm_port_phy_i2c_write_input::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:4290

hwrm_port_phy_i2c_write_input::page_offset
__le16 page_offset
Definition bnxt_hsi.h:4288

hwrm_port_phy_i2c_write_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4280

hwrm_port_phy_i2c_write_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4284

hwrm_port_phy_i2c_write_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4276

hwrm_port_phy_i2c_write_input::enables
__le32 enables
Definition bnxt_hsi.h:4282

hwrm_port_phy_i2c_write_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4278

hwrm_port_phy_i2c_write_input::flags
__le32 flags
Definition bnxt_hsi.h:4281

hwrm_port_phy_i2c_write_output
Definition bnxt_hsi.h:4295

hwrm_port_phy_i2c_write_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4298

hwrm_port_phy_i2c_write_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4300

hwrm_port_phy_i2c_write_output::valid
u8 valid
Definition bnxt_hsi.h:4301

hwrm_port_phy_i2c_write_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4297

hwrm_port_phy_i2c_write_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4299

hwrm_port_phy_i2c_write_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4296

hwrm_port_phy_qcaps_input
Definition bnxt_hsi.h:4149

hwrm_port_phy_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4150

hwrm_port_phy_qcaps_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:4156

hwrm_port_phy_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4151

hwrm_port_phy_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4153

hwrm_port_phy_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4152

hwrm_port_phy_qcaps_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4155

hwrm_port_phy_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4154

hwrm_port_phy_qcaps_output
Definition bnxt_hsi.h:4160

hwrm_port_phy_qcaps_output::supported_pam4_speeds_force_mode
__le16 supported_pam4_speeds_force_mode
Definition bnxt_hsi.h:4229

hwrm_port_phy_qcaps_output::supported_speeds_force_mode
__le16 supported_speeds_force_mode
Definition bnxt_hsi.h:4177

hwrm_port_phy_qcaps_output::supported_speeds_eee_mode
__le16 supported_speeds_eee_mode
Definition bnxt_hsi.h:4207

hwrm_port_phy_qcaps_output::internal_port_cnt
u8 internal_port_cnt
Definition bnxt_hsi.h:4238

hwrm_port_phy_qcaps_output::valid_tx_lpi_timer_high
__le32 valid_tx_lpi_timer_high
Definition bnxt_hsi.h:4220

hwrm_port_phy_qcaps_output::supported_speeds2_auto_mode
__le16 supported_speeds2_auto_mode
Definition bnxt_hsi.h:4255

hwrm_port_phy_qcaps_output::port_cnt
u8 port_cnt
Definition bnxt_hsi.h:4170

hwrm_port_phy_qcaps_output::supported_pam4_speeds_auto_mode
__le16 supported_pam4_speeds_auto_mode
Definition bnxt_hsi.h:4225

hwrm_port_phy_qcaps_output::flags2
__le16 flags2
Definition bnxt_hsi.h:4233

hwrm_port_phy_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4163

hwrm_port_phy_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4161

hwrm_port_phy_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4162

hwrm_port_phy_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4164

hwrm_port_phy_qcaps_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:4239

hwrm_port_phy_qcaps_output::flags
u8 flags
Definition bnxt_hsi.h:4165

hwrm_port_phy_qcaps_output::supported_speeds_auto_mode
__le16 supported_speeds_auto_mode
Definition bnxt_hsi.h:4192

hwrm_port_phy_qcaps_output::unused_1
u8 unused_1[3]
Definition bnxt_hsi.h:4270

hwrm_port_phy_qcaps_output::tx_lpi_timer_low
__le32 tx_lpi_timer_low
Definition bnxt_hsi.h:4215

hwrm_port_phy_qcaps_output::supported_speeds2_force_mode
__le16 supported_speeds2_force_mode
Definition bnxt_hsi.h:4240

hwrm_port_phy_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:4271

hwrm_port_phy_qcfg_input
Definition bnxt_hsi.h:3232

hwrm_port_phy_qcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:3238

hwrm_port_phy_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:3239

hwrm_port_phy_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:3237

hwrm_port_phy_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:3234

hwrm_port_phy_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:3233

hwrm_port_phy_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3235

hwrm_port_phy_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:3236

hwrm_port_phy_qcfg_output
Definition bnxt_hsi.h:3243

hwrm_port_phy_qcfg_output::wirespeed
u8 wirespeed
Definition bnxt_hsi.h:3363

hwrm_port_phy_qcfg_output::lpbk
u8 lpbk
Definition bnxt_hsi.h:3367

hwrm_port_phy_qcfg_output::link_partner_pam4_adv_speeds
u8 link_partner_pam4_adv_speeds
Definition bnxt_hsi.h:3557

hwrm_port_phy_qcfg_output::fec_cfg
__le16 fec_cfg
Definition bnxt_hsi.h:3518

hwrm_port_phy_qcfg_output::phy_bld
u8 phy_bld
Definition bnxt_hsi.h:3387

hwrm_port_phy_qcfg_output::phy_min
u8 phy_min
Definition bnxt_hsi.h:3386

hwrm_port_phy_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:3244

hwrm_port_phy_qcfg_output::active_fec_signal_mode
u8 active_fec_signal_mode
Definition bnxt_hsi.h:3253

hwrm_port_phy_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:3247

hwrm_port_phy_qcfg_output::auto_pause
u8 auto_pause
Definition bnxt_hsi.h:3329

hwrm_port_phy_qcfg_output::link_speed
__le16 link_speed
Definition bnxt_hsi.h:3270

hwrm_port_phy_qcfg_output::eee_config_phy_addr
u8 eee_config_phy_addr
Definition bnxt_hsi.h:3456

hwrm_port_phy_qcfg_output::link_partner_adv_auto_mode
u8 link_partner_adv_auto_mode
Definition bnxt_hsi.h:3481

hwrm_port_phy_qcfg_output::auto_mode
u8 auto_mode
Definition bnxt_hsi.h:3322

hwrm_port_phy_qcfg_output::support_pam4_speeds
__le16 support_pam4_speeds
Definition bnxt_hsi.h:3544

hwrm_port_phy_qcfg_output::support_speeds2
__le16 support_speeds2
Definition bnxt_hsi.h:3563

hwrm_port_phy_qcfg_output::media_type
u8 media_type
Definition bnxt_hsi.h:3446

hwrm_port_phy_qcfg_output::option_flags
u8 option_flags
Definition bnxt_hsi.h:3538

hwrm_port_phy_qcfg_output::phy_vendor_partnumber
char phy_vendor_partnumber[16]
Definition bnxt_hsi.h:3543

hwrm_port_phy_qcfg_output::active_lanes
u8 active_lanes
Definition bnxt_hsi.h:3609

hwrm_port_phy_qcfg_output::link_partner_adv_eee_link_speed_mask
__le16 link_partner_adv_eee_link_speed_mask
Definition bnxt_hsi.h:3499

hwrm_port_phy_qcfg_output::link
u8 link
Definition bnxt_hsi.h:3248

hwrm_port_phy_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3246

hwrm_port_phy_qcfg_output::adv_eee_link_speed_mask
__le16 adv_eee_link_speed_mask
Definition bnxt_hsi.h:3491

hwrm_port_phy_qcfg_output::parallel_detect
u8 parallel_detect
Definition bnxt_hsi.h:3464

hwrm_port_phy_qcfg_output::duplex_state
u8 duplex_state
Definition bnxt_hsi.h:3534

hwrm_port_phy_qcfg_output::preemphasis
__le32 preemphasis
Definition bnxt_hsi.h:3384

hwrm_port_phy_qcfg_output::auto_link_speed
__le16 auto_link_speed
Definition bnxt_hsi.h:3333

hwrm_port_phy_qcfg_output::pause
u8 pause
Definition bnxt_hsi.h:3289

hwrm_port_phy_qcfg_output::auto_link_speeds2
__le16 auto_link_speeds2
Definition bnxt_hsi.h:3594

hwrm_port_phy_qcfg_output::force_pam4_link_speed
__le16 force_pam4_link_speed
Definition bnxt_hsi.h:3548

hwrm_port_phy_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:3610

hwrm_port_phy_qcfg_output::phy_type
u8 phy_type
Definition bnxt_hsi.h:3388

hwrm_port_phy_qcfg_output::phy_vendor_name
char phy_vendor_name[16]
Definition bnxt_hsi.h:3542

hwrm_port_phy_qcfg_output::xcvr_pkg_type
u8 xcvr_pkg_type
Definition bnxt_hsi.h:3452

hwrm_port_phy_qcfg_output::link_partner_adv_speeds
__le16 link_partner_adv_speeds
Definition bnxt_hsi.h:3466

hwrm_port_phy_qcfg_output::module_status
u8 module_status
Definition bnxt_hsi.h:3376

hwrm_port_phy_qcfg_output::duplex_cfg
u8 duplex_cfg
Definition bnxt_hsi.h:3285

hwrm_port_phy_qcfg_output::auto_pam4_link_speed_mask
__le16 auto_pam4_link_speed_mask
Definition bnxt_hsi.h:3553

hwrm_port_phy_qcfg_output::force_link_speed
__le16 force_link_speed
Definition bnxt_hsi.h:3308

hwrm_port_phy_qcfg_output::force_link_speeds2
__le16 force_link_speeds2
Definition bnxt_hsi.h:3578

hwrm_port_phy_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:3245

hwrm_port_phy_qcfg_output::link_partner_adv_pause
u8 link_partner_adv_pause
Definition bnxt_hsi.h:3488

hwrm_port_phy_qcfg_output::force_pause
u8 force_pause
Definition bnxt_hsi.h:3373

hwrm_port_phy_qcfg_output::phy_maj
u8 phy_maj
Definition bnxt_hsi.h:3385

hwrm_port_phy_qcfg_output::link_down_reason
u8 link_down_reason
Definition bnxt_hsi.h:3561

hwrm_port_phy_qcfg_output::auto_link_speed_mask
__le16 auto_link_speed_mask
Definition bnxt_hsi.h:3347

hwrm_port_phy_qcfg_output::support_speeds
__le16 support_speeds
Definition bnxt_hsi.h:3292

hwrm_port_phy_qcfg_output::xcvr_identifier_type_tx_lpi_timer
__le32 xcvr_identifier_type_tx_lpi_timer
Definition bnxt_hsi.h:3507

hwrm_port_qstats_ext_input
Definition bnxt_hsi.h:4021

hwrm_port_qstats_ext_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4026

hwrm_port_qstats_ext_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4025

hwrm_port_qstats_ext_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4022

hwrm_port_qstats_ext_input::rx_stat_host_addr
__le64 rx_stat_host_addr
Definition bnxt_hsi.h:4032

hwrm_port_qstats_ext_input::tx_stat_size
__le16 tx_stat_size
Definition bnxt_hsi.h:4028

hwrm_port_qstats_ext_input::tx_stat_host_addr
__le64 tx_stat_host_addr
Definition bnxt_hsi.h:4031

hwrm_port_qstats_ext_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4027

hwrm_port_qstats_ext_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4024

hwrm_port_qstats_ext_input::rx_stat_size
__le16 rx_stat_size
Definition bnxt_hsi.h:4029

hwrm_port_qstats_ext_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4023

hwrm_port_qstats_ext_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:4030

hwrm_port_qstats_ext_output
Definition bnxt_hsi.h:4036

hwrm_port_qstats_ext_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4040

hwrm_port_qstats_ext_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4039

hwrm_port_qstats_ext_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4037

hwrm_port_qstats_ext_output::rx_stat_size
__le16 rx_stat_size
Definition bnxt_hsi.h:4042

hwrm_port_qstats_ext_output::flags
u8 flags
Definition bnxt_hsi.h:4044

hwrm_port_qstats_ext_output::total_active_cos_queues
__le16 total_active_cos_queues
Definition bnxt_hsi.h:4043

hwrm_port_qstats_ext_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4038

hwrm_port_qstats_ext_output::tx_stat_size
__le16 tx_stat_size
Definition bnxt_hsi.h:4041

hwrm_port_qstats_ext_output::valid
u8 valid
Definition bnxt_hsi.h:4046

hwrm_port_qstats_input
Definition bnxt_hsi.h:3919

hwrm_port_qstats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:3923

hwrm_port_qstats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3922

hwrm_port_qstats_input::tx_stat_host_addr
__le64 tx_stat_host_addr
Definition bnxt_hsi.h:3927

hwrm_port_qstats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:3921

hwrm_port_qstats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:3920

hwrm_port_qstats_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:3926

hwrm_port_qstats_input::rx_stat_host_addr
__le64 rx_stat_host_addr
Definition bnxt_hsi.h:3928

hwrm_port_qstats_input::port_id
__le16 port_id
Definition bnxt_hsi.h:3925

hwrm_port_qstats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:3924

hwrm_port_qstats_output
Definition bnxt_hsi.h:3932

hwrm_port_qstats_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:3939

hwrm_port_qstats_output::rx_stat_size
__le16 rx_stat_size
Definition bnxt_hsi.h:3938

hwrm_port_qstats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:3933

hwrm_port_qstats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:3936

hwrm_port_qstats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:3935

hwrm_port_qstats_output::valid
u8 valid
Definition bnxt_hsi.h:3940

hwrm_port_qstats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:3934

hwrm_port_qstats_output::tx_stat_size
__le16 tx_stat_size
Definition bnxt_hsi.h:3937

hwrm_port_ts_query_input
Definition bnxt_hsi.h:4121

hwrm_port_ts_query_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4125

hwrm_port_ts_query_input::flags
__le32 flags
Definition bnxt_hsi.h:4127

hwrm_port_ts_query_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4124

hwrm_port_ts_query_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:4133

hwrm_port_ts_query_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4132

hwrm_port_ts_query_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4126

hwrm_port_ts_query_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4122

hwrm_port_ts_query_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4123

hwrm_port_ts_query_output
Definition bnxt_hsi.h:4137

hwrm_port_ts_query_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4138

hwrm_port_ts_query_output::valid
u8 valid
Definition bnxt_hsi.h:4145

hwrm_port_ts_query_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:4144

hwrm_port_ts_query_output::ptp_msg_ts
__le64 ptp_msg_ts
Definition bnxt_hsi.h:4142

hwrm_port_ts_query_output::ptp_msg_seqid
__le16 ptp_msg_seqid
Definition bnxt_hsi.h:4143

hwrm_port_ts_query_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4139

hwrm_port_ts_query_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4140

hwrm_port_ts_query_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4141

hwrm_queue_cfg_input
Definition bnxt_hsi.h:4809

hwrm_queue_cfg_input::service_profile
u8 service_profile
Definition bnxt_hsi.h:4827

hwrm_queue_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4814

hwrm_queue_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:4815

hwrm_queue_cfg_input::dflt_len
__le32 dflt_len
Definition bnxt_hsi.h:4826

hwrm_queue_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4812

hwrm_queue_cfg_input::queue_id
__le32 queue_id
Definition bnxt_hsi.h:4825

hwrm_queue_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4811

hwrm_queue_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4813

hwrm_queue_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:4822

hwrm_queue_cfg_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4832

hwrm_queue_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4810

hwrm_queue_cfg_output
Definition bnxt_hsi.h:4836

hwrm_queue_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:4842

hwrm_queue_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4840

hwrm_queue_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4839

hwrm_queue_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4837

hwrm_queue_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4838

hwrm_queue_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4841

hwrm_queue_cos2bw_cfg_input
Definition bnxt_hsi.h:5332

hwrm_queue_cos2bw_cfg_input::unused_1
u8 unused_1[5]
Definition bnxt_hsi.h:5670

hwrm_queue_cos2bw_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:5339

hwrm_queue_cos2bw_cfg_input::queue_id7_bw_weight
u8 queue_id7_bw_weight
Definition bnxt_hsi.h:5669

hwrm_queue_cos2bw_cfg_input::queue_id6_min_bw
__le32 queue_id6_min_bw
Definition bnxt_hsi.h:5591

hwrm_queue_cos2bw_cfg_input::queue_id4_bw_weight
u8 queue_id4_bw_weight
Definition bnxt_hsi.h:5549

hwrm_queue_cos2bw_cfg_input::queue_id1_tsa_assign
u8 queue_id1_tsa_assign
Definition bnxt_hsi.h:5423

hwrm_queue_cos2bw_cfg_input::queue_id6_pri_lvl
u8 queue_id6_pri_lvl
Definition bnxt_hsi.h:5628

hwrm_queue_cos2bw_cfg_input::queue_id3_max_bw
__le32 queue_id3_max_bw
Definition bnxt_hsi.h:5487

hwrm_queue_cos2bw_cfg_input::queue_id2_max_bw
__le32 queue_id2_max_bw
Definition bnxt_hsi.h:5447

hwrm_queue_cos2bw_cfg_input::queue_id6_tsa_assign
u8 queue_id6_tsa_assign
Definition bnxt_hsi.h:5623

hwrm_queue_cos2bw_cfg_input::queue_id7_max_bw
__le32 queue_id7_max_bw
Definition bnxt_hsi.h:5647

hwrm_queue_cos2bw_cfg_input::queue_id1_pri_lvl
u8 queue_id1_pri_lvl
Definition bnxt_hsi.h:5428

hwrm_queue_cos2bw_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5336

hwrm_queue_cos2bw_cfg_input::queue_id2
u8 queue_id2
Definition bnxt_hsi.h:5430

hwrm_queue_cos2bw_cfg_input::queue_id2_pri_lvl
u8 queue_id2_pri_lvl
Definition bnxt_hsi.h:5468

hwrm_queue_cos2bw_cfg_input::queue_id0_bw_weight
u8 queue_id0_bw_weight
Definition bnxt_hsi.h:5389

hwrm_queue_cos2bw_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5334

hwrm_queue_cos2bw_cfg_input::queue_id7_min_bw
__le32 queue_id7_min_bw
Definition bnxt_hsi.h:5631

hwrm_queue_cos2bw_cfg_input::queue_id6_bw_weight
u8 queue_id6_bw_weight
Definition bnxt_hsi.h:5629

hwrm_queue_cos2bw_cfg_input::queue_id1_bw_weight
u8 queue_id1_bw_weight
Definition bnxt_hsi.h:5429

hwrm_queue_cos2bw_cfg_input::queue_id2_tsa_assign
u8 queue_id2_tsa_assign
Definition bnxt_hsi.h:5463

hwrm_queue_cos2bw_cfg_input::queue_id0
u8 queue_id0
Definition bnxt_hsi.h:5349

hwrm_queue_cos2bw_cfg_input::queue_id6
u8 queue_id6
Definition bnxt_hsi.h:5590

hwrm_queue_cos2bw_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:5338

hwrm_queue_cos2bw_cfg_input::queue_id7
u8 queue_id7
Definition bnxt_hsi.h:5630

hwrm_queue_cos2bw_cfg_input::queue_id1_max_bw
__le32 queue_id1_max_bw
Definition bnxt_hsi.h:5407

hwrm_queue_cos2bw_cfg_input::queue_id4
u8 queue_id4
Definition bnxt_hsi.h:5510

hwrm_queue_cos2bw_cfg_input::queue_id4_tsa_assign
u8 queue_id4_tsa_assign
Definition bnxt_hsi.h:5543

hwrm_queue_cos2bw_cfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:5348

hwrm_queue_cos2bw_cfg_input::queue_id1_min_bw
__le32 queue_id1_min_bw
Definition bnxt_hsi.h:5391

hwrm_queue_cos2bw_cfg_input::queue_id0_min_bw
__le32 queue_id0_min_bw
Definition bnxt_hsi.h:5351

hwrm_queue_cos2bw_cfg_input::queue_id0_max_bw
__le32 queue_id0_max_bw
Definition bnxt_hsi.h:5367

hwrm_queue_cos2bw_cfg_input::queue_id3_bw_weight
u8 queue_id3_bw_weight
Definition bnxt_hsi.h:5509

hwrm_queue_cos2bw_cfg_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:5350

hwrm_queue_cos2bw_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5335

hwrm_queue_cos2bw_cfg_input::queue_id4_max_bw
__le32 queue_id4_max_bw
Definition bnxt_hsi.h:5527

hwrm_queue_cos2bw_cfg_input::queue_id2_min_bw
__le32 queue_id2_min_bw
Definition bnxt_hsi.h:5431

hwrm_queue_cos2bw_cfg_input::queue_id7_tsa_assign
u8 queue_id7_tsa_assign
Definition bnxt_hsi.h:5663

hwrm_queue_cos2bw_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5337

hwrm_queue_cos2bw_cfg_input::queue_id2_bw_weight
u8 queue_id2_bw_weight
Definition bnxt_hsi.h:5469

hwrm_queue_cos2bw_cfg_input::queue_id5
u8 queue_id5
Definition bnxt_hsi.h:5550

hwrm_queue_cos2bw_cfg_input::queue_id5_tsa_assign
u8 queue_id5_tsa_assign
Definition bnxt_hsi.h:5583

hwrm_queue_cos2bw_cfg_input::queue_id0_tsa_assign
u8 queue_id0_tsa_assign
Definition bnxt_hsi.h:5383

hwrm_queue_cos2bw_cfg_input::queue_id4_pri_lvl
u8 queue_id4_pri_lvl
Definition bnxt_hsi.h:5548

hwrm_queue_cos2bw_cfg_input::queue_id5_bw_weight
u8 queue_id5_bw_weight
Definition bnxt_hsi.h:5589

hwrm_queue_cos2bw_cfg_input::queue_id3
u8 queue_id3
Definition bnxt_hsi.h:5470

hwrm_queue_cos2bw_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5333

hwrm_queue_cos2bw_cfg_input::queue_id1
u8 queue_id1
Definition bnxt_hsi.h:5390

hwrm_queue_cos2bw_cfg_input::queue_id3_pri_lvl
u8 queue_id3_pri_lvl
Definition bnxt_hsi.h:5508

hwrm_queue_cos2bw_cfg_input::queue_id3_min_bw
__le32 queue_id3_min_bw
Definition bnxt_hsi.h:5471

hwrm_queue_cos2bw_cfg_input::queue_id5_max_bw
__le32 queue_id5_max_bw
Definition bnxt_hsi.h:5567

hwrm_queue_cos2bw_cfg_input::queue_id7_pri_lvl
u8 queue_id7_pri_lvl
Definition bnxt_hsi.h:5668

hwrm_queue_cos2bw_cfg_input::queue_id6_max_bw
__le32 queue_id6_max_bw
Definition bnxt_hsi.h:5607

hwrm_queue_cos2bw_cfg_input::queue_id0_pri_lvl
u8 queue_id0_pri_lvl
Definition bnxt_hsi.h:5388

hwrm_queue_cos2bw_cfg_input::queue_id5_pri_lvl
u8 queue_id5_pri_lvl
Definition bnxt_hsi.h:5588

hwrm_queue_cos2bw_cfg_input::queue_id3_tsa_assign
u8 queue_id3_tsa_assign
Definition bnxt_hsi.h:5503

hwrm_queue_cos2bw_cfg_input::queue_id5_min_bw
__le32 queue_id5_min_bw
Definition bnxt_hsi.h:5551

hwrm_queue_cos2bw_cfg_input::queue_id4_min_bw
__le32 queue_id4_min_bw
Definition bnxt_hsi.h:5511

hwrm_queue_cos2bw_cfg_output
Definition bnxt_hsi.h:5674

hwrm_queue_cos2bw_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5677

hwrm_queue_cos2bw_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:5679

hwrm_queue_cos2bw_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5678

hwrm_queue_cos2bw_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5676

hwrm_queue_cos2bw_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:5680

hwrm_queue_cos2bw_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5675

hwrm_queue_cos2bw_qcfg_input
Definition bnxt_hsi.h:4989

hwrm_queue_cos2bw_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:4996

hwrm_queue_cos2bw_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4991

hwrm_queue_cos2bw_qcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4995

hwrm_queue_cos2bw_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4994

hwrm_queue_cos2bw_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4990

hwrm_queue_cos2bw_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4993

hwrm_queue_cos2bw_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4992

hwrm_queue_cos2bw_qcfg_output
Definition bnxt_hsi.h:5000

hwrm_queue_cos2bw_qcfg_output::queue_id0_min_bw
__le32 queue_id0_min_bw
Definition bnxt_hsi.h:5008

hwrm_queue_cos2bw_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5001

hwrm_queue_cos2bw_qcfg_output::queue_id4
u8 queue_id4
Definition bnxt_hsi.h:5167

hwrm_queue_cos2bw_qcfg_output::queue_id7
u8 queue_id7
Definition bnxt_hsi.h:5287

hwrm_queue_cos2bw_qcfg_output::queue_id1_bw_weight
u8 queue_id1_bw_weight
Definition bnxt_hsi.h:5086

hwrm_queue_cos2bw_qcfg_output::queue_id4_tsa_assign
u8 queue_id4_tsa_assign
Definition bnxt_hsi.h:5200

hwrm_queue_cos2bw_qcfg_output::queue_id0_tsa_assign
u8 queue_id0_tsa_assign
Definition bnxt_hsi.h:5040

hwrm_queue_cos2bw_qcfg_output::queue_id2_min_bw
__le32 queue_id2_min_bw
Definition bnxt_hsi.h:5088

hwrm_queue_cos2bw_qcfg_output::queue_id4_max_bw
__le32 queue_id4_max_bw
Definition bnxt_hsi.h:5184

hwrm_queue_cos2bw_qcfg_output::queue_id4_min_bw
__le32 queue_id4_min_bw
Definition bnxt_hsi.h:5168

hwrm_queue_cos2bw_qcfg_output::queue_id3_tsa_assign
u8 queue_id3_tsa_assign
Definition bnxt_hsi.h:5160

hwrm_queue_cos2bw_qcfg_output::queue_id6_tsa_assign
u8 queue_id6_tsa_assign
Definition bnxt_hsi.h:5280

hwrm_queue_cos2bw_qcfg_output::queue_id0_max_bw
__le32 queue_id0_max_bw
Definition bnxt_hsi.h:5024

hwrm_queue_cos2bw_qcfg_output::queue_id5_pri_lvl
u8 queue_id5_pri_lvl
Definition bnxt_hsi.h:5245

hwrm_queue_cos2bw_qcfg_output::queue_id7_pri_lvl
u8 queue_id7_pri_lvl
Definition bnxt_hsi.h:5325

hwrm_queue_cos2bw_qcfg_output::queue_id2_bw_weight
u8 queue_id2_bw_weight
Definition bnxt_hsi.h:5126

hwrm_queue_cos2bw_qcfg_output::queue_id6_max_bw
__le32 queue_id6_max_bw
Definition bnxt_hsi.h:5264

hwrm_queue_cos2bw_qcfg_output::queue_id1_tsa_assign
u8 queue_id1_tsa_assign
Definition bnxt_hsi.h:5080

hwrm_queue_cos2bw_qcfg_output::unused_1
__le16 unused_1
Definition bnxt_hsi.h:5007

hwrm_queue_cos2bw_qcfg_output::queue_id3_max_bw
__le32 queue_id3_max_bw
Definition bnxt_hsi.h:5144

hwrm_queue_cos2bw_qcfg_output::queue_id5_bw_weight
u8 queue_id5_bw_weight
Definition bnxt_hsi.h:5246

hwrm_queue_cos2bw_qcfg_output::queue_id4_pri_lvl
u8 queue_id4_pri_lvl
Definition bnxt_hsi.h:5205

hwrm_queue_cos2bw_qcfg_output::queue_id7_max_bw
__le32 queue_id7_max_bw
Definition bnxt_hsi.h:5304

hwrm_queue_cos2bw_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5004

hwrm_queue_cos2bw_qcfg_output::queue_id3_pri_lvl
u8 queue_id3_pri_lvl
Definition bnxt_hsi.h:5165

hwrm_queue_cos2bw_qcfg_output::queue_id1_min_bw
__le32 queue_id1_min_bw
Definition bnxt_hsi.h:5048

hwrm_queue_cos2bw_qcfg_output::queue_id3_bw_weight
u8 queue_id3_bw_weight
Definition bnxt_hsi.h:5166

hwrm_queue_cos2bw_qcfg_output::queue_id4_bw_weight
u8 queue_id4_bw_weight
Definition bnxt_hsi.h:5206

hwrm_queue_cos2bw_qcfg_output::queue_id2
u8 queue_id2
Definition bnxt_hsi.h:5087

hwrm_queue_cos2bw_qcfg_output::unused_2
u8 unused_2[4]
Definition bnxt_hsi.h:5327

hwrm_queue_cos2bw_qcfg_output::queue_id1_pri_lvl
u8 queue_id1_pri_lvl
Definition bnxt_hsi.h:5085

hwrm_queue_cos2bw_qcfg_output::queue_id7_tsa_assign
u8 queue_id7_tsa_assign
Definition bnxt_hsi.h:5320

hwrm_queue_cos2bw_qcfg_output::queue_id0
u8 queue_id0
Definition bnxt_hsi.h:5005

hwrm_queue_cos2bw_qcfg_output::queue_id2_max_bw
__le32 queue_id2_max_bw
Definition bnxt_hsi.h:5104

hwrm_queue_cos2bw_qcfg_output::queue_id3
u8 queue_id3
Definition bnxt_hsi.h:5127

hwrm_queue_cos2bw_qcfg_output::queue_id6_min_bw
__le32 queue_id6_min_bw
Definition bnxt_hsi.h:5248

hwrm_queue_cos2bw_qcfg_output::queue_id5
u8 queue_id5
Definition bnxt_hsi.h:5207

hwrm_queue_cos2bw_qcfg_output::queue_id6_bw_weight
u8 queue_id6_bw_weight
Definition bnxt_hsi.h:5286

hwrm_queue_cos2bw_qcfg_output::queue_id5_min_bw
__le32 queue_id5_min_bw
Definition bnxt_hsi.h:5208

hwrm_queue_cos2bw_qcfg_output::queue_id6
u8 queue_id6
Definition bnxt_hsi.h:5247

hwrm_queue_cos2bw_qcfg_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:5006

hwrm_queue_cos2bw_qcfg_output::queue_id2_pri_lvl
u8 queue_id2_pri_lvl
Definition bnxt_hsi.h:5125

hwrm_queue_cos2bw_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5002

hwrm_queue_cos2bw_qcfg_output::queue_id5_tsa_assign
u8 queue_id5_tsa_assign
Definition bnxt_hsi.h:5240

hwrm_queue_cos2bw_qcfg_output::queue_id3_min_bw
__le32 queue_id3_min_bw
Definition bnxt_hsi.h:5128

hwrm_queue_cos2bw_qcfg_output::queue_id1_max_bw
__le32 queue_id1_max_bw
Definition bnxt_hsi.h:5064

hwrm_queue_cos2bw_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:5328

hwrm_queue_cos2bw_qcfg_output::queue_id7_bw_weight
u8 queue_id7_bw_weight
Definition bnxt_hsi.h:5326

hwrm_queue_cos2bw_qcfg_output::queue_id1
u8 queue_id1
Definition bnxt_hsi.h:5047

hwrm_queue_cos2bw_qcfg_output::queue_id0_bw_weight
u8 queue_id0_bw_weight
Definition bnxt_hsi.h:5046

hwrm_queue_cos2bw_qcfg_output::queue_id2_tsa_assign
u8 queue_id2_tsa_assign
Definition bnxt_hsi.h:5120

hwrm_queue_cos2bw_qcfg_output::queue_id6_pri_lvl
u8 queue_id6_pri_lvl
Definition bnxt_hsi.h:5285

hwrm_queue_cos2bw_qcfg_output::queue_id5_max_bw
__le32 queue_id5_max_bw
Definition bnxt_hsi.h:5224

hwrm_queue_cos2bw_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5003

hwrm_queue_cos2bw_qcfg_output::queue_id7_min_bw
__le32 queue_id7_min_bw
Definition bnxt_hsi.h:5288

hwrm_queue_cos2bw_qcfg_output::queue_id0_pri_lvl
u8 queue_id0_pri_lvl
Definition bnxt_hsi.h:5045

hwrm_queue_dscp2pri_cfg_input
Definition bnxt_hsi.h:5734

hwrm_queue_dscp2pri_cfg_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:5748

hwrm_queue_dscp2pri_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:5743

hwrm_queue_dscp2pri_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5735

hwrm_queue_dscp2pri_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:5741

hwrm_queue_dscp2pri_cfg_input::entry_cnt
__le16 entry_cnt
Definition bnxt_hsi.h:5747

hwrm_queue_dscp2pri_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5737

hwrm_queue_dscp2pri_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5739

hwrm_queue_dscp2pri_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5736

hwrm_queue_dscp2pri_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5738

hwrm_queue_dscp2pri_cfg_input::port_id
u8 port_id
Definition bnxt_hsi.h:5745

hwrm_queue_dscp2pri_cfg_input::src_data_addr
__le64 src_data_addr
Definition bnxt_hsi.h:5740

hwrm_queue_dscp2pri_cfg_input::default_pri
u8 default_pri
Definition bnxt_hsi.h:5746

hwrm_queue_dscp2pri_cfg_output
Definition bnxt_hsi.h:5752

hwrm_queue_dscp2pri_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5753

hwrm_queue_dscp2pri_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5755

hwrm_queue_dscp2pri_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5756

hwrm_queue_dscp2pri_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5754

hwrm_queue_dscp2pri_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:5757

hwrm_queue_dscp2pri_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:5758

hwrm_queue_dscp2pri_qcfg_input
Definition bnxt_hsi.h:5708

hwrm_queue_dscp2pri_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5709

hwrm_queue_dscp2pri_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5713

hwrm_queue_dscp2pri_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5711

hwrm_queue_dscp2pri_qcfg_input::dest_data_buffer_size
__le16 dest_data_buffer_size
Definition bnxt_hsi.h:5717

hwrm_queue_dscp2pri_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5712

hwrm_queue_dscp2pri_qcfg_input::port_id
u8 port_id
Definition bnxt_hsi.h:5715

hwrm_queue_dscp2pri_qcfg_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:5716

hwrm_queue_dscp2pri_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5710

hwrm_queue_dscp2pri_qcfg_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:5718

hwrm_queue_dscp2pri_qcfg_input::dest_data_addr
__le64 dest_data_addr
Definition bnxt_hsi.h:5714

hwrm_queue_dscp2pri_qcfg_output
Definition bnxt_hsi.h:5722

hwrm_queue_dscp2pri_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5724

hwrm_queue_dscp2pri_qcfg_output::entry_cnt
__le16 entry_cnt
Definition bnxt_hsi.h:5727

hwrm_queue_dscp2pri_qcfg_output::default_pri
u8 default_pri
Definition bnxt_hsi.h:5728

hwrm_queue_dscp2pri_qcfg_output::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:5729

hwrm_queue_dscp2pri_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:5730

hwrm_queue_dscp2pri_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5725

hwrm_queue_dscp2pri_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5723

hwrm_queue_dscp2pri_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5726

hwrm_queue_dscp_qcaps_input
Definition bnxt_hsi.h:5684

hwrm_queue_dscp_qcaps_input::port_id
u8 port_id
Definition bnxt_hsi.h:5690

hwrm_queue_dscp_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5689

hwrm_queue_dscp_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5687

hwrm_queue_dscp_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5686

hwrm_queue_dscp_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5688

hwrm_queue_dscp_qcaps_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:5691

hwrm_queue_dscp_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5685

hwrm_queue_dscp_qcaps_output
Definition bnxt_hsi.h:5695

hwrm_queue_dscp_qcaps_output::num_dscp_bits
u8 num_dscp_bits
Definition bnxt_hsi.h:5700

hwrm_queue_dscp_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5698

hwrm_queue_dscp_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5697

hwrm_queue_dscp_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:5704

hwrm_queue_dscp_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5699

hwrm_queue_dscp_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5696

hwrm_queue_dscp_qcaps_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:5701

hwrm_queue_dscp_qcaps_output::max_entries
__le16 max_entries
Definition bnxt_hsi.h:5702

hwrm_queue_dscp_qcaps_output::unused_1
u8 unused_1[3]
Definition bnxt_hsi.h:5703

hwrm_queue_pfcenable_cfg_input
Definition bnxt_hsi.h:4876

hwrm_queue_pfcenable_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4880

hwrm_queue_pfcenable_cfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4891

hwrm_queue_pfcenable_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4879

hwrm_queue_pfcenable_cfg_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:4892

hwrm_queue_pfcenable_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4877

hwrm_queue_pfcenable_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4878

hwrm_queue_pfcenable_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:4882

hwrm_queue_pfcenable_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4881

hwrm_queue_pfcenable_cfg_output
Definition bnxt_hsi.h:4896

hwrm_queue_pfcenable_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4897

hwrm_queue_pfcenable_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:4902

hwrm_queue_pfcenable_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4901

hwrm_queue_pfcenable_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4898

hwrm_queue_pfcenable_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4900

hwrm_queue_pfcenable_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4899

hwrm_queue_pfcenable_qcfg_input
Definition bnxt_hsi.h:4846

hwrm_queue_pfcenable_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4851

hwrm_queue_pfcenable_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4850

hwrm_queue_pfcenable_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4849

hwrm_queue_pfcenable_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4847

hwrm_queue_pfcenable_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4848

hwrm_queue_pfcenable_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:4853

hwrm_queue_pfcenable_qcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4852

hwrm_queue_pfcenable_qcfg_output
Definition bnxt_hsi.h:4857

hwrm_queue_pfcenable_qcfg_output::flags
__le32 flags
Definition bnxt_hsi.h:4862

hwrm_queue_pfcenable_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4860

hwrm_queue_pfcenable_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:4872

hwrm_queue_pfcenable_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4861

hwrm_queue_pfcenable_qcfg_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:4871

hwrm_queue_pfcenable_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4858

hwrm_queue_pfcenable_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4859

hwrm_queue_pri2cos_cfg_input
Definition bnxt_hsi.h:4943

hwrm_queue_pri2cos_cfg_input::pri0_cos_queue_id
u8 pri0_cos_queue_id
Definition bnxt_hsi.h:4967

hwrm_queue_pri2cos_cfg_input::pri4_cos_queue_id
u8 pri4_cos_queue_id
Definition bnxt_hsi.h:4971

hwrm_queue_pri2cos_cfg_input::pri5_cos_queue_id
u8 pri5_cos_queue_id
Definition bnxt_hsi.h:4972

hwrm_queue_pri2cos_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:4949

hwrm_queue_pri2cos_cfg_input::pri6_cos_queue_id
u8 pri6_cos_queue_id
Definition bnxt_hsi.h:4973

hwrm_queue_pri2cos_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4944

hwrm_queue_pri2cos_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:4957

hwrm_queue_pri2cos_cfg_input::pri7_cos_queue_id
u8 pri7_cos_queue_id
Definition bnxt_hsi.h:4974

hwrm_queue_pri2cos_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4946

hwrm_queue_pri2cos_cfg_input::port_id
u8 port_id
Definition bnxt_hsi.h:4966

hwrm_queue_pri2cos_cfg_input::pri1_cos_queue_id
u8 pri1_cos_queue_id
Definition bnxt_hsi.h:4968

hwrm_queue_pri2cos_cfg_input::pri3_cos_queue_id
u8 pri3_cos_queue_id
Definition bnxt_hsi.h:4970

hwrm_queue_pri2cos_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4947

hwrm_queue_pri2cos_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4945

hwrm_queue_pri2cos_cfg_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4975

hwrm_queue_pri2cos_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4948

hwrm_queue_pri2cos_cfg_input::pri2_cos_queue_id
u8 pri2_cos_queue_id
Definition bnxt_hsi.h:4969

hwrm_queue_pri2cos_cfg_output
Definition bnxt_hsi.h:4979

hwrm_queue_pri2cos_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4983

hwrm_queue_pri2cos_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4980

hwrm_queue_pri2cos_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4982

hwrm_queue_pri2cos_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:4985

hwrm_queue_pri2cos_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4981

hwrm_queue_pri2cos_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:4984

hwrm_queue_pri2cos_qcfg_input
Definition bnxt_hsi.h:4906

hwrm_queue_pri2cos_qcfg_input::flags
__le32 flags
Definition bnxt_hsi.h:4912

hwrm_queue_pri2cos_qcfg_input::port_id
u8 port_id
Definition bnxt_hsi.h:4918

hwrm_queue_pri2cos_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4910

hwrm_queue_pri2cos_qcfg_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:4919

hwrm_queue_pri2cos_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4908

hwrm_queue_pri2cos_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4907

hwrm_queue_pri2cos_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4909

hwrm_queue_pri2cos_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4911

hwrm_queue_pri2cos_qcfg_output
Definition bnxt_hsi.h:4923

hwrm_queue_pri2cos_qcfg_output::pri5_cos_queue_id
u8 pri5_cos_queue_id
Definition bnxt_hsi.h:4933

hwrm_queue_pri2cos_qcfg_output::pri7_cos_queue_id
u8 pri7_cos_queue_id
Definition bnxt_hsi.h:4935

hwrm_queue_pri2cos_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4927

hwrm_queue_pri2cos_qcfg_output::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:4938

hwrm_queue_pri2cos_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4924

hwrm_queue_pri2cos_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4925

hwrm_queue_pri2cos_qcfg_output::pri6_cos_queue_id
u8 pri6_cos_queue_id
Definition bnxt_hsi.h:4934

hwrm_queue_pri2cos_qcfg_output::pri2_cos_queue_id
u8 pri2_cos_queue_id
Definition bnxt_hsi.h:4930

hwrm_queue_pri2cos_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4926

hwrm_queue_pri2cos_qcfg_output::pri4_cos_queue_id
u8 pri4_cos_queue_id
Definition bnxt_hsi.h:4932

hwrm_queue_pri2cos_qcfg_output::pri1_cos_queue_id
u8 pri1_cos_queue_id
Definition bnxt_hsi.h:4929

hwrm_queue_pri2cos_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:4939

hwrm_queue_pri2cos_qcfg_output::queue_cfg_info
u8 queue_cfg_info
Definition bnxt_hsi.h:4936

hwrm_queue_pri2cos_qcfg_output::pri0_cos_queue_id
u8 pri0_cos_queue_id
Definition bnxt_hsi.h:4928

hwrm_queue_pri2cos_qcfg_output::pri3_cos_queue_id
u8 pri3_cos_queue_id
Definition bnxt_hsi.h:4931

hwrm_queue_qcfg_input
Definition bnxt_hsi.h:4776

hwrm_queue_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4781

hwrm_queue_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4779

hwrm_queue_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4780

hwrm_queue_qcfg_input::queue_id
__le32 queue_id
Definition bnxt_hsi.h:4787

hwrm_queue_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4777

hwrm_queue_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4778

hwrm_queue_qcfg_input::flags
__le32 flags
Definition bnxt_hsi.h:4782

hwrm_queue_qcfg_output
Definition bnxt_hsi.h:4791

hwrm_queue_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4795

hwrm_queue_qcfg_output::queue_cfg_info
u8 queue_cfg_info
Definition bnxt_hsi.h:4802

hwrm_queue_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4794

hwrm_queue_qcfg_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:4804

hwrm_queue_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4792

hwrm_queue_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:4805

hwrm_queue_qcfg_output::service_profile
u8 service_profile
Definition bnxt_hsi.h:4797

hwrm_queue_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4793

hwrm_queue_qcfg_output::queue_len
__le32 queue_len
Definition bnxt_hsi.h:4796

hwrm_queue_qportcfg_input
Definition bnxt_hsi.h:4667

hwrm_queue_qportcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:4671

hwrm_queue_qportcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:4668

hwrm_queue_qportcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:4669

hwrm_queue_qportcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4670

hwrm_queue_qportcfg_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:4683

hwrm_queue_qportcfg_input::drv_qmap_cap
u8 drv_qmap_cap
Definition bnxt_hsi.h:4679

hwrm_queue_qportcfg_input::flags
__le32 flags
Definition bnxt_hsi.h:4673

hwrm_queue_qportcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4678

hwrm_queue_qportcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:4672

hwrm_queue_qportcfg_output
Definition bnxt_hsi.h:4687

hwrm_queue_qportcfg_output::queue_id5
u8 queue_id5
Definition bnxt_hsi.h:4745

hwrm_queue_qportcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:4691

hwrm_queue_qportcfg_output::queue_id5_service_profile
u8 queue_id5_service_profile
Definition bnxt_hsi.h:4746

hwrm_queue_qportcfg_output::queue_id0_service_profile
u8 queue_id0_service_profile
Definition bnxt_hsi.h:4701

hwrm_queue_qportcfg_output::queue_id2
u8 queue_id2
Definition bnxt_hsi.h:4718

hwrm_queue_qportcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:4690

hwrm_queue_qportcfg_output::queue_id3
u8 queue_id3
Definition bnxt_hsi.h:4727

hwrm_queue_qportcfg_output::queue_id2_service_profile
u8 queue_id2_service_profile
Definition bnxt_hsi.h:4719

hwrm_queue_qportcfg_output::queue_id1
u8 queue_id1
Definition bnxt_hsi.h:4709

hwrm_queue_qportcfg_output::queue_id6
u8 queue_id6
Definition bnxt_hsi.h:4754

hwrm_queue_qportcfg_output::queue_id6_service_profile
u8 queue_id6_service_profile
Definition bnxt_hsi.h:4755

hwrm_queue_qportcfg_output::queue_id4
u8 queue_id4
Definition bnxt_hsi.h:4736

hwrm_queue_qportcfg_output::queue_id7
u8 queue_id7
Definition bnxt_hsi.h:4763

hwrm_queue_qportcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:4689

hwrm_queue_qportcfg_output::queue_id0
u8 queue_id0
Definition bnxt_hsi.h:4700

hwrm_queue_qportcfg_output::queue_cos2bw_cfg_allowed
u8 queue_cos2bw_cfg_allowed
Definition bnxt_hsi.h:4699

hwrm_queue_qportcfg_output::queue_cfg_allowed
u8 queue_cfg_allowed
Definition bnxt_hsi.h:4694

hwrm_queue_qportcfg_output::queue_id7_service_profile
u8 queue_id7_service_profile
Definition bnxt_hsi.h:4764

hwrm_queue_qportcfg_output::queue_id4_service_profile
u8 queue_id4_service_profile
Definition bnxt_hsi.h:4737

hwrm_queue_qportcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:4688

hwrm_queue_qportcfg_output::queue_cfg_info
u8 queue_cfg_info
Definition bnxt_hsi.h:4695

hwrm_queue_qportcfg_output::queue_pfcenable_cfg_allowed
u8 queue_pfcenable_cfg_allowed
Definition bnxt_hsi.h:4697

hwrm_queue_qportcfg_output::queue_id3_service_profile
u8 queue_id3_service_profile
Definition bnxt_hsi.h:4728

hwrm_queue_qportcfg_output::max_configurable_queues
u8 max_configurable_queues
Definition bnxt_hsi.h:4692

hwrm_queue_qportcfg_output::max_configurable_lossless_queues
u8 max_configurable_lossless_queues
Definition bnxt_hsi.h:4693

hwrm_queue_qportcfg_output::queue_pri2cos_cfg_allowed
u8 queue_pri2cos_cfg_allowed
Definition bnxt_hsi.h:4698

hwrm_queue_qportcfg_output::valid
u8 valid
Definition bnxt_hsi.h:4772

hwrm_queue_qportcfg_output::queue_id1_service_profile
u8 queue_id1_service_profile
Definition bnxt_hsi.h:4710

hwrm_reject_fwd_resp_input
Definition bnxt_hsi.h:9283

hwrm_reject_fwd_resp_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9284

hwrm_reject_fwd_resp_input::encap_resp_target_id
__le16 encap_resp_target_id
Definition bnxt_hsi.h:9290

hwrm_reject_fwd_resp_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:9291

hwrm_reject_fwd_resp_input::encap_request
__le32 encap_request[26]
Definition bnxt_hsi.h:9289

hwrm_reject_fwd_resp_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9285

hwrm_reject_fwd_resp_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9288

hwrm_reject_fwd_resp_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9287

hwrm_reject_fwd_resp_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9286

hwrm_reject_fwd_resp_output
Definition bnxt_hsi.h:9295

hwrm_reject_fwd_resp_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9298

hwrm_reject_fwd_resp_output::valid
u8 valid
Definition bnxt_hsi.h:9301

hwrm_reject_fwd_resp_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9300

hwrm_reject_fwd_resp_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9299

hwrm_reject_fwd_resp_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9297

hwrm_reject_fwd_resp_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9296

hwrm_resp_hdr
Definition bnxt_hsi.h:26

hwrm_resp_hdr::seq_id
__le16 seq_id
Definition bnxt_hsi.h:29

hwrm_resp_hdr::req_type
__le16 req_type
Definition bnxt_hsi.h:28

hwrm_resp_hdr::resp_len
__le16 resp_len
Definition bnxt_hsi.h:30

hwrm_resp_hdr::error_code
__le16 error_code
Definition bnxt_hsi.h:27

hwrm_ring_aggint_qcaps_input
Definition bnxt_hsi.h:6347

hwrm_ring_aggint_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6348

hwrm_ring_aggint_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6351

hwrm_ring_aggint_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6350

hwrm_ring_aggint_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6352

hwrm_ring_aggint_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6349

hwrm_ring_aggint_qcaps_output
Definition bnxt_hsi.h:6356

hwrm_ring_aggint_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6360

hwrm_ring_aggint_qcaps_output::int_lat_tmr_min_min
__le16 int_lat_tmr_min_min
Definition bnxt_hsi.h:6381

hwrm_ring_aggint_qcaps_output::int_lat_tmr_max_min
__le16 int_lat_tmr_max_min
Definition bnxt_hsi.h:6383

hwrm_ring_aggint_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6358

hwrm_ring_aggint_qcaps_output::num_cmpl_dma_aggr_during_int_min
__le16 num_cmpl_dma_aggr_during_int_min
Definition bnxt_hsi.h:6375

hwrm_ring_aggint_qcaps_output::cmpl_aggr_dma_tmr_during_int_max
__le16 cmpl_aggr_dma_tmr_during_int_max
Definition bnxt_hsi.h:6380

hwrm_ring_aggint_qcaps_output::int_lat_tmr_min_max
__le16 int_lat_tmr_min_max
Definition bnxt_hsi.h:6382

hwrm_ring_aggint_qcaps_output::nq_params
__le32 nq_params
Definition bnxt_hsi.h:6371

hwrm_ring_aggint_qcaps_output::int_lat_tmr_max_max
__le16 int_lat_tmr_max_max
Definition bnxt_hsi.h:6384

hwrm_ring_aggint_qcaps_output::timer_units
__le16 timer_units
Definition bnxt_hsi.h:6387

hwrm_ring_aggint_qcaps_output::cmpl_aggr_dma_tmr_max
__le16 cmpl_aggr_dma_tmr_max
Definition bnxt_hsi.h:6378

hwrm_ring_aggint_qcaps_output::num_cmpl_aggr_int_max
__le16 num_cmpl_aggr_int_max
Definition bnxt_hsi.h:6386

hwrm_ring_aggint_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6357

hwrm_ring_aggint_qcaps_output::num_cmpl_dma_aggr_max
__le16 num_cmpl_dma_aggr_max
Definition bnxt_hsi.h:6374

hwrm_ring_aggint_qcaps_output::num_cmpl_dma_aggr_min
__le16 num_cmpl_dma_aggr_min
Definition bnxt_hsi.h:6373

hwrm_ring_aggint_qcaps_output::cmpl_aggr_dma_tmr_during_int_min
__le16 cmpl_aggr_dma_tmr_during_int_min
Definition bnxt_hsi.h:6379

hwrm_ring_aggint_qcaps_output::num_cmpl_aggr_int_min
__le16 num_cmpl_aggr_int_min
Definition bnxt_hsi.h:6385

hwrm_ring_aggint_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6359

hwrm_ring_aggint_qcaps_output::cmpl_params
__le32 cmpl_params
Definition bnxt_hsi.h:6361

hwrm_ring_aggint_qcaps_output::cmpl_aggr_dma_tmr_min
__le16 cmpl_aggr_dma_tmr_min
Definition bnxt_hsi.h:6377

hwrm_ring_aggint_qcaps_output::num_cmpl_dma_aggr_during_int_max
__le16 num_cmpl_dma_aggr_during_int_max
Definition bnxt_hsi.h:6376

hwrm_ring_aggint_qcaps_output::unused_0
u8 unused_0[1]
Definition bnxt_hsi.h:6388

hwrm_ring_aggint_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:6389

hwrm_ring_alloc_input
Definition bnxt_hsi.h:6200

hwrm_ring_alloc_input::cmpl_ring_id
__le16 cmpl_ring_id
Definition bnxt_hsi.h:6231

hwrm_ring_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6205

hwrm_ring_alloc_input::reserved3
__le32 reserved3
Definition bnxt_hsi.h:6247

hwrm_ring_alloc_input::length
__le32 length
Definition bnxt_hsi.h:6229

hwrm_ring_alloc_input::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:6248

hwrm_ring_alloc_input::cq_handle
__le64 cq_handle
Definition bnxt_hsi.h:6273

hwrm_ring_alloc_input::ring_type
u8 ring_type
Definition bnxt_hsi.h:6213

hwrm_ring_alloc_input::queue_id
__le16 queue_id
Definition bnxt_hsi.h:6232

hwrm_ring_alloc_input::flags
__le16 flags
Definition bnxt_hsi.h:6222

hwrm_ring_alloc_input::unused_1
u8 unused_1[2]
Definition bnxt_hsi.h:6228

hwrm_ring_alloc_input::reserved4
__le32 reserved4
Definition bnxt_hsi.h:6249

hwrm_ring_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:6206

hwrm_ring_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6202

hwrm_ring_alloc_input::page_tbl_addr
__le64 page_tbl_addr
Definition bnxt_hsi.h:6224

hwrm_ring_alloc_input::fbo
__le32 fbo
Definition bnxt_hsi.h:6225

hwrm_ring_alloc_input::page_tbl_depth
u8 page_tbl_depth
Definition bnxt_hsi.h:6227

hwrm_ring_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6201

hwrm_ring_alloc_input::ring_arb_cfg
__le16 ring_arb_cfg
Definition bnxt_hsi.h:6236

hwrm_ring_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6204

hwrm_ring_alloc_input::rx_buf_size
__le16 rx_buf_size
Definition bnxt_hsi.h:6233

hwrm_ring_alloc_input::max_bw
__le32 max_bw
Definition bnxt_hsi.h:6250

hwrm_ring_alloc_input::rx_ring_id
__le16 rx_ring_id
Definition bnxt_hsi.h:6234

hwrm_ring_alloc_input::logical_id
__le16 logical_id
Definition bnxt_hsi.h:6230

hwrm_ring_alloc_input::int_mode
u8 int_mode
Definition bnxt_hsi.h:6266

hwrm_ring_alloc_input::page_size
u8 page_size
Definition bnxt_hsi.h:6226

hwrm_ring_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6203

hwrm_ring_alloc_input::unused_4
u8 unused_4[3]
Definition bnxt_hsi.h:6272

hwrm_ring_alloc_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:6221

hwrm_ring_alloc_input::unused_3
__le16 unused_3
Definition bnxt_hsi.h:6246

hwrm_ring_alloc_input::nq_ring_id
__le16 nq_ring_id
Definition bnxt_hsi.h:6235

hwrm_ring_alloc_output
Definition bnxt_hsi.h:6277

hwrm_ring_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6280

hwrm_ring_alloc_output::logical_ring_id
__le16 logical_ring_id
Definition bnxt_hsi.h:6283

hwrm_ring_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6281

hwrm_ring_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:6284

hwrm_ring_alloc_output::ring_id
__le16 ring_id
Definition bnxt_hsi.h:6282

hwrm_ring_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6279

hwrm_ring_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:6285

hwrm_ring_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6278

hwrm_ring_cmpl_ring_cfg_aggint_params_input
Definition bnxt_hsi.h:6424

hwrm_ring_cmpl_ring_cfg_aggint_params_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6427

hwrm_ring_cmpl_ring_cfg_aggint_params_input::num_cmpl_aggr_int
__le16 num_cmpl_aggr_int
Definition bnxt_hsi.h:6441

hwrm_ring_cmpl_ring_cfg_aggint_params_input::num_cmpl_dma_aggr
__le16 num_cmpl_dma_aggr
Definition bnxt_hsi.h:6435

hwrm_ring_cmpl_ring_cfg_aggint_params_input::ring_id
__le16 ring_id
Definition bnxt_hsi.h:6430

hwrm_ring_cmpl_ring_cfg_aggint_params_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6426

hwrm_ring_cmpl_ring_cfg_aggint_params_input::num_cmpl_dma_aggr_during_int
__le16 num_cmpl_dma_aggr_during_int
Definition bnxt_hsi.h:6436

hwrm_ring_cmpl_ring_cfg_aggint_params_input::cmpl_aggr_dma_tmr
__le16 cmpl_aggr_dma_tmr
Definition bnxt_hsi.h:6437

hwrm_ring_cmpl_ring_cfg_aggint_params_input::int_lat_tmr_max
__le16 int_lat_tmr_max
Definition bnxt_hsi.h:6440

hwrm_ring_cmpl_ring_cfg_aggint_params_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6429

hwrm_ring_cmpl_ring_cfg_aggint_params_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6425

hwrm_ring_cmpl_ring_cfg_aggint_params_input::cmpl_aggr_dma_tmr_during_int
__le16 cmpl_aggr_dma_tmr_during_int
Definition bnxt_hsi.h:6438

hwrm_ring_cmpl_ring_cfg_aggint_params_input::enables
__le16 enables
Definition bnxt_hsi.h:6442

hwrm_ring_cmpl_ring_cfg_aggint_params_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:6449

hwrm_ring_cmpl_ring_cfg_aggint_params_input::int_lat_tmr_min
__le16 int_lat_tmr_min
Definition bnxt_hsi.h:6439

hwrm_ring_cmpl_ring_cfg_aggint_params_input::flags
__le16 flags
Definition bnxt_hsi.h:6431

hwrm_ring_cmpl_ring_cfg_aggint_params_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6428

hwrm_ring_cmpl_ring_cfg_aggint_params_output
Definition bnxt_hsi.h:6453

hwrm_ring_cmpl_ring_cfg_aggint_params_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6457

hwrm_ring_cmpl_ring_cfg_aggint_params_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6458

hwrm_ring_cmpl_ring_cfg_aggint_params_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6454

hwrm_ring_cmpl_ring_cfg_aggint_params_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6455

hwrm_ring_cmpl_ring_cfg_aggint_params_output::valid
u8 valid
Definition bnxt_hsi.h:6459

hwrm_ring_cmpl_ring_cfg_aggint_params_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6456

hwrm_ring_cmpl_ring_qaggint_params_input
Definition bnxt_hsi.h:6393

hwrm_ring_cmpl_ring_qaggint_params_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6395

hwrm_ring_cmpl_ring_qaggint_params_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6394

hwrm_ring_cmpl_ring_qaggint_params_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6398

hwrm_ring_cmpl_ring_qaggint_params_input::ring_id
__le16 ring_id
Definition bnxt_hsi.h:6399

hwrm_ring_cmpl_ring_qaggint_params_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6397

hwrm_ring_cmpl_ring_qaggint_params_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:6400

hwrm_ring_cmpl_ring_qaggint_params_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6396

hwrm_ring_cmpl_ring_qaggint_params_output
Definition bnxt_hsi.h:6404

hwrm_ring_cmpl_ring_qaggint_params_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6405

hwrm_ring_cmpl_ring_qaggint_params_output::int_lat_tmr_min
__le16 int_lat_tmr_min
Definition bnxt_hsi.h:6416

hwrm_ring_cmpl_ring_qaggint_params_output::flags
__le16 flags
Definition bnxt_hsi.h:6409

hwrm_ring_cmpl_ring_qaggint_params_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6408

hwrm_ring_cmpl_ring_qaggint_params_output::num_cmpl_dma_aggr_during_int
__le16 num_cmpl_dma_aggr_during_int
Definition bnxt_hsi.h:6413

hwrm_ring_cmpl_ring_qaggint_params_output::num_cmpl_dma_aggr
__le16 num_cmpl_dma_aggr
Definition bnxt_hsi.h:6412

hwrm_ring_cmpl_ring_qaggint_params_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6406

hwrm_ring_cmpl_ring_qaggint_params_output::cmpl_aggr_dma_tmr_during_int
__le16 cmpl_aggr_dma_tmr_during_int
Definition bnxt_hsi.h:6415

hwrm_ring_cmpl_ring_qaggint_params_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6419

hwrm_ring_cmpl_ring_qaggint_params_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6407

hwrm_ring_cmpl_ring_qaggint_params_output::cmpl_aggr_dma_tmr
__le16 cmpl_aggr_dma_tmr
Definition bnxt_hsi.h:6414

hwrm_ring_cmpl_ring_qaggint_params_output::int_lat_tmr_max
__le16 int_lat_tmr_max
Definition bnxt_hsi.h:6417

hwrm_ring_cmpl_ring_qaggint_params_output::num_cmpl_aggr_int
__le16 num_cmpl_aggr_int
Definition bnxt_hsi.h:6418

hwrm_ring_cmpl_ring_qaggint_params_output::valid
u8 valid
Definition bnxt_hsi.h:6420

hwrm_ring_free_input
Definition bnxt_hsi.h:6289

hwrm_ring_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6290

hwrm_ring_free_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:6305

hwrm_ring_free_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:6303

hwrm_ring_free_input::ring_id
__le16 ring_id
Definition bnxt_hsi.h:6304

hwrm_ring_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6293

hwrm_ring_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6294

hwrm_ring_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6292

hwrm_ring_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6291

hwrm_ring_free_input::ring_type
u8 ring_type
Definition bnxt_hsi.h:6295

hwrm_ring_free_output
Definition bnxt_hsi.h:6309

hwrm_ring_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6311

hwrm_ring_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6312

hwrm_ring_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6313

hwrm_ring_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6314

hwrm_ring_free_output::valid
u8 valid
Definition bnxt_hsi.h:6315

hwrm_ring_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6310

hwrm_ring_grp_alloc_input
Definition bnxt_hsi.h:6463

hwrm_ring_grp_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6466

hwrm_ring_grp_alloc_input::sc
__le16 sc
Definition bnxt_hsi.h:6472

hwrm_ring_grp_alloc_input::ar
__le16 ar
Definition bnxt_hsi.h:6471

hwrm_ring_grp_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6464

hwrm_ring_grp_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6465

hwrm_ring_grp_alloc_input::rr
__le16 rr
Definition bnxt_hsi.h:6470

hwrm_ring_grp_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6467

hwrm_ring_grp_alloc_input::cr
__le16 cr
Definition bnxt_hsi.h:6469

hwrm_ring_grp_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6468

hwrm_ring_grp_alloc_output
Definition bnxt_hsi.h:6476

hwrm_ring_grp_alloc_output::ring_group_id
__le32 ring_group_id
Definition bnxt_hsi.h:6481

hwrm_ring_grp_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:6483

hwrm_ring_grp_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:6482

hwrm_ring_grp_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6478

hwrm_ring_grp_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6479

hwrm_ring_grp_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6477

hwrm_ring_grp_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6480

hwrm_ring_grp_free_input
Definition bnxt_hsi.h:6487

hwrm_ring_grp_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6490

hwrm_ring_grp_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6491

hwrm_ring_grp_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6492

hwrm_ring_grp_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6489

hwrm_ring_grp_free_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:6494

hwrm_ring_grp_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6488

hwrm_ring_grp_free_input::ring_group_id
__le32 ring_group_id
Definition bnxt_hsi.h:6493

hwrm_ring_grp_free_output
Definition bnxt_hsi.h:6498

hwrm_ring_grp_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6503

hwrm_ring_grp_free_output::valid
u8 valid
Definition bnxt_hsi.h:6504

hwrm_ring_grp_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6502

hwrm_ring_grp_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6500

hwrm_ring_grp_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6499

hwrm_ring_grp_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6501

hwrm_ring_reset_input
Definition bnxt_hsi.h:6319

hwrm_ring_reset_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6324

hwrm_ring_reset_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6323

hwrm_ring_reset_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6322

hwrm_ring_reset_input::ring_type
u8 ring_type
Definition bnxt_hsi.h:6325

hwrm_ring_reset_input::ring_id
__le16 ring_id
Definition bnxt_hsi.h:6332

hwrm_ring_reset_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:6333

hwrm_ring_reset_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6321

hwrm_ring_reset_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:6331

hwrm_ring_reset_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6320

hwrm_ring_reset_output
Definition bnxt_hsi.h:6337

hwrm_ring_reset_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6339

hwrm_ring_reset_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6338

hwrm_ring_reset_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6342

hwrm_ring_reset_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6341

hwrm_ring_reset_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6340

hwrm_ring_reset_output::valid
u8 valid
Definition bnxt_hsi.h:6343

hwrm_selftest_exec_input
Definition bnxt_hsi.h:10525

hwrm_selftest_exec_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10526

hwrm_selftest_exec_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10538

hwrm_selftest_exec_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10529

hwrm_selftest_exec_input::flags
u8 flags
Definition bnxt_hsi.h:10531

hwrm_selftest_exec_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10528

hwrm_selftest_exec_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10527

hwrm_selftest_exec_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10530

hwrm_selftest_exec_output
Definition bnxt_hsi.h:10542

hwrm_selftest_exec_output::requested_tests
u8 requested_tests
Definition bnxt_hsi.h:10547

hwrm_selftest_exec_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10543

hwrm_selftest_exec_output::valid
u8 valid
Definition bnxt_hsi.h:10562

hwrm_selftest_exec_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:10561

hwrm_selftest_exec_output::test_success
u8 test_success
Definition bnxt_hsi.h:10554

hwrm_selftest_exec_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10545

hwrm_selftest_exec_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10544

hwrm_selftest_exec_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10546

hwrm_selftest_irq_input
Definition bnxt_hsi.h:10566

hwrm_selftest_irq_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10570

hwrm_selftest_irq_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10568

hwrm_selftest_irq_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10571

hwrm_selftest_irq_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10567

hwrm_selftest_irq_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10569

hwrm_selftest_irq_output
Definition bnxt_hsi.h:10575

hwrm_selftest_irq_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10578

hwrm_selftest_irq_output::valid
u8 valid
Definition bnxt_hsi.h:10581

hwrm_selftest_irq_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10576

hwrm_selftest_irq_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:10580

hwrm_selftest_irq_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10579

hwrm_selftest_irq_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10577

hwrm_selftest_qlist_input
Definition bnxt_hsi.h:10480

hwrm_selftest_qlist_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10483

hwrm_selftest_qlist_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10485

hwrm_selftest_qlist_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10482

hwrm_selftest_qlist_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10481

hwrm_selftest_qlist_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10484

hwrm_selftest_qlist_output
Definition bnxt_hsi.h:10489

hwrm_selftest_qlist_output::test_timeout
__le16 test_timeout
Definition bnxt_hsi.h:10510

hwrm_selftest_qlist_output::test0_name
char test0_name[32]
Definition bnxt_hsi.h:10512

hwrm_selftest_qlist_output::unused_0
u8 unused_0
Definition bnxt_hsi.h:10509

hwrm_selftest_qlist_output::test1_name
char test1_name[32]
Definition bnxt_hsi.h:10513

hwrm_selftest_qlist_output::test7_name
char test7_name[32]
Definition bnxt_hsi.h:10519

hwrm_selftest_qlist_output::offline_tests
u8 offline_tests
Definition bnxt_hsi.h:10502

hwrm_selftest_qlist_output::num_tests
u8 num_tests
Definition bnxt_hsi.h:10494

hwrm_selftest_qlist_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10490

hwrm_selftest_qlist_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10492

hwrm_selftest_qlist_output::test3_name
char test3_name[32]
Definition bnxt_hsi.h:10515

hwrm_selftest_qlist_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10493

hwrm_selftest_qlist_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10491

hwrm_selftest_qlist_output::unused_1
u8 unused_1[2]
Definition bnxt_hsi.h:10511

hwrm_selftest_qlist_output::test4_name
char test4_name[32]
Definition bnxt_hsi.h:10516

hwrm_selftest_qlist_output::available_tests
u8 available_tests
Definition bnxt_hsi.h:10495

hwrm_selftest_qlist_output::valid
u8 valid
Definition bnxt_hsi.h:10521

hwrm_selftest_qlist_output::test2_name
char test2_name[32]
Definition bnxt_hsi.h:10514

hwrm_selftest_qlist_output::unused_2
u8 unused_2[7]
Definition bnxt_hsi.h:10520

hwrm_selftest_qlist_output::test6_name
char test6_name[32]
Definition bnxt_hsi.h:10518

hwrm_selftest_qlist_output::test5_name
char test5_name[32]
Definition bnxt_hsi.h:10517

hwrm_selftest_retrieve_serdes_data_input
Definition bnxt_hsi.h:10585

hwrm_selftest_retrieve_serdes_data_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:10587

hwrm_selftest_retrieve_serdes_data_input::resp_data_addr
__le64 resp_data_addr
Definition bnxt_hsi.h:10591

hwrm_selftest_retrieve_serdes_data_input::data_len
__le16 data_len
Definition bnxt_hsi.h:10593

hwrm_selftest_retrieve_serdes_data_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10588

hwrm_selftest_retrieve_serdes_data_input::options
u8 options
Definition bnxt_hsi.h:10600

hwrm_selftest_retrieve_serdes_data_input::req_type
__le16 req_type
Definition bnxt_hsi.h:10586

hwrm_selftest_retrieve_serdes_data_input::target_id
__le16 target_id
Definition bnxt_hsi.h:10589

hwrm_selftest_retrieve_serdes_data_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:10590

hwrm_selftest_retrieve_serdes_data_input::flags
u8 flags
Definition bnxt_hsi.h:10594

hwrm_selftest_retrieve_serdes_data_input::resp_data_offset
__le32 resp_data_offset
Definition bnxt_hsi.h:10592

hwrm_selftest_retrieve_serdes_data_output
Definition bnxt_hsi.h:10616

hwrm_selftest_retrieve_serdes_data_output::total_data_len
__le16 total_data_len
Definition bnxt_hsi.h:10621

hwrm_selftest_retrieve_serdes_data_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:10623

hwrm_selftest_retrieve_serdes_data_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:10619

hwrm_selftest_retrieve_serdes_data_output::copied_data_len
__le16 copied_data_len
Definition bnxt_hsi.h:10622

hwrm_selftest_retrieve_serdes_data_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:10620

hwrm_selftest_retrieve_serdes_data_output::valid
u8 valid
Definition bnxt_hsi.h:10624

hwrm_selftest_retrieve_serdes_data_output::error_code
__le16 error_code
Definition bnxt_hsi.h:10617

hwrm_selftest_retrieve_serdes_data_output::req_type
__le16 req_type
Definition bnxt_hsi.h:10618

hwrm_short_input
Definition bnxt_hsi.h:85

hwrm_short_input::req_type
__le16 req_type
Definition bnxt_hsi.h:86

hwrm_short_input::signature
__le16 signature
Definition bnxt_hsi.h:87

hwrm_short_input::req_addr
__le64 req_addr
Definition bnxt_hsi.h:92

hwrm_short_input::unused_0
__le16 unused_0
Definition bnxt_hsi.h:90

hwrm_short_input::size
__le16 size
Definition bnxt_hsi.h:91

hwrm_stat_ctx_alloc_input
Definition bnxt_hsi.h:8517

hwrm_stat_ctx_alloc_input::stat_ctx_flags
u8 stat_ctx_flags
Definition bnxt_hsi.h:8525

hwrm_stat_ctx_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8519

hwrm_stat_ctx_alloc_input::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:8527

hwrm_stat_ctx_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8518

hwrm_stat_ctx_alloc_input::stats_dma_addr
__le64 stats_dma_addr
Definition bnxt_hsi.h:8523

hwrm_stat_ctx_alloc_input::update_period_ms
__le32 update_period_ms
Definition bnxt_hsi.h:8524

hwrm_stat_ctx_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8522

hwrm_stat_ctx_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8521

hwrm_stat_ctx_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8520

hwrm_stat_ctx_alloc_output
Definition bnxt_hsi.h:8531

hwrm_stat_ctx_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8535

hwrm_stat_ctx_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8532

hwrm_stat_ctx_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8533

hwrm_stat_ctx_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:8538

hwrm_stat_ctx_alloc_output::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:8536

hwrm_stat_ctx_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:8537

hwrm_stat_ctx_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8534

hwrm_stat_ctx_clr_stats_input
Definition bnxt_hsi.h:8634

hwrm_stat_ctx_clr_stats_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8637

hwrm_stat_ctx_clr_stats_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8638

hwrm_stat_ctx_clr_stats_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8636

hwrm_stat_ctx_clr_stats_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8635

hwrm_stat_ctx_clr_stats_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8639

hwrm_stat_ctx_clr_stats_input::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:8640

hwrm_stat_ctx_clr_stats_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:8641

hwrm_stat_ctx_clr_stats_output
Definition bnxt_hsi.h:8645

hwrm_stat_ctx_clr_stats_output::valid
u8 valid
Definition bnxt_hsi.h:8651

hwrm_stat_ctx_clr_stats_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8648

hwrm_stat_ctx_clr_stats_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8649

hwrm_stat_ctx_clr_stats_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8647

hwrm_stat_ctx_clr_stats_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8646

hwrm_stat_ctx_clr_stats_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8650

hwrm_stat_ctx_eng_query_input
Definition bnxt_hsi.h:8605

hwrm_stat_ctx_eng_query_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8607

hwrm_stat_ctx_eng_query_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:8612

hwrm_stat_ctx_eng_query_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8610

hwrm_stat_ctx_eng_query_input::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:8611

hwrm_stat_ctx_eng_query_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8609

hwrm_stat_ctx_eng_query_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8606

hwrm_stat_ctx_eng_query_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8608

hwrm_stat_ctx_eng_query_output
Definition bnxt_hsi.h:8616

hwrm_stat_ctx_eng_query_output::eng_bytes_out
__le64 eng_bytes_out
Definition bnxt_hsi.h:8622

hwrm_stat_ctx_eng_query_output::cdd_engine_usage
__le64 cdd_engine_usage
Definition bnxt_hsi.h:8628

hwrm_stat_ctx_eng_query_output::aux_bytes_out
__le64 aux_bytes_out
Definition bnxt_hsi.h:8624

hwrm_stat_ctx_eng_query_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8618

hwrm_stat_ctx_eng_query_output::cce_engine_usage
__le64 cce_engine_usage
Definition bnxt_hsi.h:8627

hwrm_stat_ctx_eng_query_output::valid
u8 valid
Definition bnxt_hsi.h:8630

hwrm_stat_ctx_eng_query_output::commands
__le64 commands
Definition bnxt_hsi.h:8625

hwrm_stat_ctx_eng_query_output::eng_bytes_in
__le64 eng_bytes_in
Definition bnxt_hsi.h:8621

hwrm_stat_ctx_eng_query_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8620

hwrm_stat_ctx_eng_query_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8629

hwrm_stat_ctx_eng_query_output::aux_bytes_in
__le64 aux_bytes_in
Definition bnxt_hsi.h:8623

hwrm_stat_ctx_eng_query_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8619

hwrm_stat_ctx_eng_query_output::error_commands
__le64 error_commands
Definition bnxt_hsi.h:8626

hwrm_stat_ctx_eng_query_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8617

hwrm_stat_ctx_free_input
Definition bnxt_hsi.h:8542

hwrm_stat_ctx_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8544

hwrm_stat_ctx_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8543

hwrm_stat_ctx_free_input::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:8548

hwrm_stat_ctx_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8547

hwrm_stat_ctx_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8546

hwrm_stat_ctx_free_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:8549

hwrm_stat_ctx_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8545

hwrm_stat_ctx_free_output
Definition bnxt_hsi.h:8553

hwrm_stat_ctx_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8555

hwrm_stat_ctx_free_output::valid
u8 valid
Definition bnxt_hsi.h:8560

hwrm_stat_ctx_free_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:8559

hwrm_stat_ctx_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8554

hwrm_stat_ctx_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8556

hwrm_stat_ctx_free_output::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:8558

hwrm_stat_ctx_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8557

hwrm_stat_ctx_query_input
Definition bnxt_hsi.h:8564

hwrm_stat_ctx_query_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8566

hwrm_stat_ctx_query_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8568

hwrm_stat_ctx_query_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8565

hwrm_stat_ctx_query_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8569

hwrm_stat_ctx_query_input::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:8570

hwrm_stat_ctx_query_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8567

hwrm_stat_ctx_query_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:8571

hwrm_stat_ctx_query_output
Definition bnxt_hsi.h:8575

hwrm_stat_ctx_query_output::rx_bcast_bytes
__le64 rx_bcast_bytes
Definition bnxt_hsi.h:8595

hwrm_stat_ctx_query_output::tx_bcast_bytes
__le64 tx_bcast_bytes
Definition bnxt_hsi.h:8587

hwrm_stat_ctx_query_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8576

hwrm_stat_ctx_query_output::tx_ucast_pkts
__le64 tx_ucast_pkts
Definition bnxt_hsi.h:8580

hwrm_stat_ctx_query_output::tx_ucast_bytes
__le64 tx_ucast_bytes
Definition bnxt_hsi.h:8585

hwrm_stat_ctx_query_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8577

hwrm_stat_ctx_query_output::rx_mcast_pkts
__le64 rx_mcast_pkts
Definition bnxt_hsi.h:8589

hwrm_stat_ctx_query_output::rx_agg_aborts
__le64 rx_agg_aborts
Definition bnxt_hsi.h:8599

hwrm_stat_ctx_query_output::tx_mcast_bytes
__le64 tx_mcast_bytes
Definition bnxt_hsi.h:8586

hwrm_stat_ctx_query_output::tx_mcast_pkts
__le64 tx_mcast_pkts
Definition bnxt_hsi.h:8581

hwrm_stat_ctx_query_output::rx_agg_bytes
__le64 rx_agg_bytes
Definition bnxt_hsi.h:8597

hwrm_stat_ctx_query_output::rx_ucast_pkts
__le64 rx_ucast_pkts
Definition bnxt_hsi.h:8588

hwrm_stat_ctx_query_output::rx_agg_pkts
__le64 rx_agg_pkts
Definition bnxt_hsi.h:8596

hwrm_stat_ctx_query_output::tx_bcast_pkts
__le64 tx_bcast_pkts
Definition bnxt_hsi.h:8582

hwrm_stat_ctx_query_output::rx_err_pkts
__le64 rx_err_pkts
Definition bnxt_hsi.h:8591

hwrm_stat_ctx_query_output::rx_drop_pkts
__le64 rx_drop_pkts
Definition bnxt_hsi.h:8592

hwrm_stat_ctx_query_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8579

hwrm_stat_ctx_query_output::tx_err_pkts
__le64 tx_err_pkts
Definition bnxt_hsi.h:8583

hwrm_stat_ctx_query_output::rx_bcast_pkts
__le64 rx_bcast_pkts
Definition bnxt_hsi.h:8590

hwrm_stat_ctx_query_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8578

hwrm_stat_ctx_query_output::rx_agg_events
__le64 rx_agg_events
Definition bnxt_hsi.h:8598

hwrm_stat_ctx_query_output::valid
u8 valid
Definition bnxt_hsi.h:8601

hwrm_stat_ctx_query_output::rx_mcast_bytes
__le64 rx_mcast_bytes
Definition bnxt_hsi.h:8594

hwrm_stat_ctx_query_output::rx_ucast_bytes
__le64 rx_ucast_bytes
Definition bnxt_hsi.h:8593

hwrm_stat_ctx_query_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8600

hwrm_stat_ctx_query_output::tx_drop_pkts
__le64 tx_drop_pkts
Definition bnxt_hsi.h:8584

hwrm_struct_data_dcbx_app
Definition bnxt_hsi.h:8911

hwrm_struct_data_dcbx_app::valid
u8 valid
Definition bnxt_hsi.h:8920

hwrm_struct_data_dcbx_app::priority
u8 priority
Definition bnxt_hsi.h:8919

hwrm_struct_data_dcbx_app::protocol_id
__be16 protocol_id
Definition bnxt_hsi.h:8912

hwrm_struct_data_dcbx_app::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:8921

hwrm_struct_data_dcbx_app::protocol_selector
u8 protocol_selector
Definition bnxt_hsi.h:8913

hwrm_struct_data_dcbx_ets
Definition bnxt_hsi.h:8863

hwrm_struct_data_dcbx_ets::pri0_to_tc_map
u8 pri0_to_tc_map
Definition bnxt_hsi.h:8870

hwrm_struct_data_dcbx_ets::tc7_to_tsa_map
u8 tc7_to_tsa_map
Definition bnxt_hsi.h:8898

hwrm_struct_data_dcbx_ets::tc1_to_bw_map
u8 tc1_to_bw_map
Definition bnxt_hsi.h:8879

hwrm_struct_data_dcbx_ets::destination
u8 destination
Definition bnxt_hsi.h:8864

hwrm_struct_data_dcbx_ets::tc0_to_tsa_map
u8 tc0_to_tsa_map
Definition bnxt_hsi.h:8886

hwrm_struct_data_dcbx_ets::tc5_to_tsa_map
u8 tc5_to_tsa_map
Definition bnxt_hsi.h:8896

hwrm_struct_data_dcbx_ets::pri1_to_tc_map
u8 pri1_to_tc_map
Definition bnxt_hsi.h:8871

hwrm_struct_data_dcbx_ets::pri2_to_tc_map
u8 pri2_to_tc_map
Definition bnxt_hsi.h:8872

hwrm_struct_data_dcbx_ets::tc4_to_tsa_map
u8 tc4_to_tsa_map
Definition bnxt_hsi.h:8895

hwrm_struct_data_dcbx_ets::pri6_to_tc_map
u8 pri6_to_tc_map
Definition bnxt_hsi.h:8876

hwrm_struct_data_dcbx_ets::pri7_to_tc_map
u8 pri7_to_tc_map
Definition bnxt_hsi.h:8877

hwrm_struct_data_dcbx_ets::tc2_to_tsa_map
u8 tc2_to_tsa_map
Definition bnxt_hsi.h:8893

hwrm_struct_data_dcbx_ets::tc0_to_bw_map
u8 tc0_to_bw_map
Definition bnxt_hsi.h:8878

hwrm_struct_data_dcbx_ets::tc4_to_bw_map
u8 tc4_to_bw_map
Definition bnxt_hsi.h:8882

hwrm_struct_data_dcbx_ets::max_tcs
u8 max_tcs
Definition bnxt_hsi.h:8868

hwrm_struct_data_dcbx_ets::tc6_to_tsa_map
u8 tc6_to_tsa_map
Definition bnxt_hsi.h:8897

hwrm_struct_data_dcbx_ets::tc5_to_bw_map
u8 tc5_to_bw_map
Definition bnxt_hsi.h:8883

hwrm_struct_data_dcbx_ets::pri3_to_tc_map
u8 pri3_to_tc_map
Definition bnxt_hsi.h:8873

hwrm_struct_data_dcbx_ets::pri4_to_tc_map
u8 pri4_to_tc_map
Definition bnxt_hsi.h:8874

hwrm_struct_data_dcbx_ets::tc3_to_tsa_map
u8 tc3_to_tsa_map
Definition bnxt_hsi.h:8894

hwrm_struct_data_dcbx_ets::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:8899

hwrm_struct_data_dcbx_ets::unused1
__le16 unused1
Definition bnxt_hsi.h:8869

hwrm_struct_data_dcbx_ets::tc7_to_bw_map
u8 tc7_to_bw_map
Definition bnxt_hsi.h:8885

hwrm_struct_data_dcbx_ets::tc6_to_bw_map
u8 tc6_to_bw_map
Definition bnxt_hsi.h:8884

hwrm_struct_data_dcbx_ets::tc2_to_bw_map
u8 tc2_to_bw_map
Definition bnxt_hsi.h:8880

hwrm_struct_data_dcbx_ets::pri5_to_tc_map
u8 pri5_to_tc_map
Definition bnxt_hsi.h:8875

hwrm_struct_data_dcbx_ets::tc3_to_bw_map
u8 tc3_to_bw_map
Definition bnxt_hsi.h:8881

hwrm_struct_data_dcbx_ets::tc1_to_tsa_map
u8 tc1_to_tsa_map
Definition bnxt_hsi.h:8892

hwrm_struct_data_dcbx_feature_state
Definition bnxt_hsi.h:8925

hwrm_struct_data_dcbx_feature_state::pfc_state
u8 pfc_state
Definition bnxt_hsi.h:8932

hwrm_struct_data_dcbx_feature_state::dcbx_mode
u8 dcbx_mode
Definition bnxt_hsi.h:8926

hwrm_struct_data_dcbx_feature_state::app_state
u8 app_state
Definition bnxt_hsi.h:8933

hwrm_struct_data_dcbx_feature_state::ets_state
u8 ets_state
Definition bnxt_hsi.h:8931

hwrm_struct_data_dcbx_feature_state::unused
u8 unused[3]
Definition bnxt_hsi.h:8938

hwrm_struct_data_dcbx_feature_state::resets
u8 resets
Definition bnxt_hsi.h:8939

hwrm_struct_data_dcbx_pfc
Definition bnxt_hsi.h:8903

hwrm_struct_data_dcbx_pfc::mbc
u8 mbc
Definition bnxt_hsi.h:8906

hwrm_struct_data_dcbx_pfc::pfc_priority_bitmap
u8 pfc_priority_bitmap
Definition bnxt_hsi.h:8904

hwrm_struct_data_dcbx_pfc::max_pfc_tcs
u8 max_pfc_tcs
Definition bnxt_hsi.h:8905

hwrm_struct_data_dcbx_pfc::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:8907

hwrm_struct_data_lldp_device
Definition bnxt_hsi.h:8999

hwrm_struct_data_lldp_device::mgmt_addr_oid_length
u8 mgmt_addr_oid_length
Definition bnxt_hsi.h:9007

hwrm_struct_data_lldp_device::ttl
__le16 ttl
Definition bnxt_hsi.h:9000

hwrm_struct_data_lldp_device::unused_3
u8 unused_3[4]
Definition bnxt_hsi.h:9003

hwrm_struct_data_lldp_device::mgmt_addr_type
u8 mgmt_addr_type
Definition bnxt_hsi.h:9002

hwrm_struct_data_lldp_device::intf_num
__le32 intf_num
Definition bnxt_hsi.h:9009

hwrm_struct_data_lldp_device::system_caps
__le32 system_caps
Definition bnxt_hsi.h:9005

hwrm_struct_data_lldp_device::unused_4
u8 unused_4[2]
Definition bnxt_hsi.h:9008

hwrm_struct_data_lldp_device::mgmt_addr_oid
__le32 mgmt_addr_oid[32]
Definition bnxt_hsi.h:9011

hwrm_struct_data_lldp_device::mgmt_addr
__le32 mgmt_addr[8]
Definition bnxt_hsi.h:9004

hwrm_struct_data_lldp_device::intf_num_type
u8 intf_num_type
Definition bnxt_hsi.h:9006

hwrm_struct_data_lldp_device::unused_5
u8 unused_5[4]
Definition bnxt_hsi.h:9010

hwrm_struct_data_lldp_device::mgmt_addr_len
u8 mgmt_addr_len
Definition bnxt_hsi.h:9001

hwrm_struct_data_lldp_generic
Definition bnxt_hsi.h:8983

hwrm_struct_data_lldp_generic::unused1
u8 unused1[5]
Definition bnxt_hsi.h:8994

hwrm_struct_data_lldp_generic::tlv_value
__le32 tlv_value[64]
Definition bnxt_hsi.h:8995

hwrm_struct_data_lldp_generic::length
u8 length
Definition bnxt_hsi.h:8993

hwrm_struct_data_lldp_generic::tlv_type
u8 tlv_type
Definition bnxt_hsi.h:8984

hwrm_struct_data_lldp_generic::subtype
u8 subtype
Definition bnxt_hsi.h:8992

hwrm_struct_data_lldp
Definition bnxt_hsi.h:8948

hwrm_struct_data_lldp::system_name_state
u8 system_name_state
Definition bnxt_hsi.h:8959

hwrm_struct_data_lldp::admin_state
u8 admin_state
Definition bnxt_hsi.h:8949

hwrm_struct_data_lldp::async_event_notification_state
u8 async_event_notification_state
Definition bnxt_hsi.h:8975

hwrm_struct_data_lldp::mgmt_addr_state
u8 mgmt_addr_state
Definition bnxt_hsi.h:8971

hwrm_struct_data_lldp::system_cap_state
u8 system_cap_state
Definition bnxt_hsi.h:8967

hwrm_struct_data_lldp::unused_0
u8 unused_0
Definition bnxt_hsi.h:8979

hwrm_struct_data_lldp::system_desc_state
u8 system_desc_state
Definition bnxt_hsi.h:8963

hwrm_struct_data_lldp::port_description_state
u8 port_description_state
Definition bnxt_hsi.h:8955

hwrm_struct_data_port_description
Definition bnxt_hsi.h:9015

hwrm_struct_data_port_description::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9017

hwrm_struct_data_port_description::port_id
u8 port_id
Definition bnxt_hsi.h:9016

hwrm_struct_data_power_information
Definition bnxt_hsi.h:9037

hwrm_struct_data_power_information::bkup_power_info_ver
__le32 bkup_power_info_ver
Definition bnxt_hsi.h:9038

hwrm_struct_data_power_information::bkup_time_milli_seconds
__le32 bkup_time_milli_seconds
Definition bnxt_hsi.h:9041

hwrm_struct_data_power_information::platform_bkup_power_count
__le32 platform_bkup_power_count
Definition bnxt_hsi.h:9039

hwrm_struct_data_power_information::bkup_power_charge_time
__le32 bkup_power_charge_time
Definition bnxt_hsi.h:9043

hwrm_struct_data_power_information::load_milli_watt
__le32 load_milli_watt
Definition bnxt_hsi.h:9040

hwrm_struct_data_power_information::bkup_power_status
__le32 bkup_power_status
Definition bnxt_hsi.h:9042

hwrm_struct_data_rss_v2
Definition bnxt_hsi.h:9021

hwrm_struct_data_rss_v2::hash_type
__le16 hash_type
Definition bnxt_hsi.h:9026

hwrm_struct_data_rss_v2::rss_ctx_id
__le16 rss_ctx_id
Definition bnxt_hsi.h:9024

hwrm_struct_data_rss_v2::num_ring_groups
__le16 num_ring_groups
Definition bnxt_hsi.h:9025

hwrm_struct_data_rss_v2::hash_key_ring_group_ids
__le64 hash_key_ring_group_ids
Definition bnxt_hsi.h:9033

hwrm_struct_data_rss_v2::flags
__le16 flags
Definition bnxt_hsi.h:9022

hwrm_struct_hdr
Definition bnxt_hsi.h:8839

hwrm_struct_hdr::count
u8 count
Definition bnxt_hsi.h:8855

hwrm_struct_hdr::len
__le16 len
Definition bnxt_hsi.h:8853

hwrm_struct_hdr::next_offset
__le16 next_offset
Definition bnxt_hsi.h:8857

hwrm_struct_hdr::version
u8 version
Definition bnxt_hsi.h:8854

hwrm_struct_hdr::subtype
__le16 subtype
Definition bnxt_hsi.h:8856

hwrm_struct_hdr::struct_id
__le16 struct_id
Definition bnxt_hsi.h:8840

hwrm_struct_hdr::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:8859

hwrm_temp_monitor_query_input
Definition bnxt_hsi.h:9353

hwrm_temp_monitor_query_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9356

hwrm_temp_monitor_query_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9358

hwrm_temp_monitor_query_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9354

hwrm_temp_monitor_query_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9355

hwrm_temp_monitor_query_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9357

hwrm_temp_monitor_query_output
Definition bnxt_hsi.h:9362

hwrm_temp_monitor_query_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9364

hwrm_temp_monitor_query_output::temp
u8 temp
Definition bnxt_hsi.h:9367

hwrm_temp_monitor_query_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9366

hwrm_temp_monitor_query_output::valid
u8 valid
Definition bnxt_hsi.h:9369

hwrm_temp_monitor_query_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9363

hwrm_temp_monitor_query_output::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:9368

hwrm_temp_monitor_query_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9365

hwrm_tunnel_dst_port_alloc_input
Definition bnxt_hsi.h:8422

hwrm_tunnel_dst_port_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8426

hwrm_tunnel_dst_port_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8427

hwrm_tunnel_dst_port_alloc_input::tunnel_dst_port_val
__be16 tunnel_dst_port_val
Definition bnxt_hsi.h:8436

hwrm_tunnel_dst_port_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8425

hwrm_tunnel_dst_port_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8424

hwrm_tunnel_dst_port_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8423

hwrm_tunnel_dst_port_alloc_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:8437

hwrm_tunnel_dst_port_alloc_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:8435

hwrm_tunnel_dst_port_alloc_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:8428

hwrm_tunnel_dst_port_alloc_output
Definition bnxt_hsi.h:8441

hwrm_tunnel_dst_port_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8445

hwrm_tunnel_dst_port_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:8448

hwrm_tunnel_dst_port_alloc_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:8447

hwrm_tunnel_dst_port_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8443

hwrm_tunnel_dst_port_alloc_output::tunnel_dst_port_id
__le16 tunnel_dst_port_id
Definition bnxt_hsi.h:8446

hwrm_tunnel_dst_port_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8442

hwrm_tunnel_dst_port_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8444

hwrm_tunnel_dst_port_free_input
Definition bnxt_hsi.h:8452

hwrm_tunnel_dst_port_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8455

hwrm_tunnel_dst_port_free_input::tunnel_dst_port_id
__le16 tunnel_dst_port_id
Definition bnxt_hsi.h:8466

hwrm_tunnel_dst_port_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8456

hwrm_tunnel_dst_port_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8457

hwrm_tunnel_dst_port_free_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:8467

hwrm_tunnel_dst_port_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8453

hwrm_tunnel_dst_port_free_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:8458

hwrm_tunnel_dst_port_free_input::unused_0
u8 unused_0
Definition bnxt_hsi.h:8465

hwrm_tunnel_dst_port_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8454

hwrm_tunnel_dst_port_free_output
Definition bnxt_hsi.h:8471

hwrm_tunnel_dst_port_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8473

hwrm_tunnel_dst_port_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8475

hwrm_tunnel_dst_port_free_output::valid
u8 valid
Definition bnxt_hsi.h:8477

hwrm_tunnel_dst_port_free_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:8476

hwrm_tunnel_dst_port_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8472

hwrm_tunnel_dst_port_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8474

hwrm_tunnel_dst_port_query_input
Definition bnxt_hsi.h:8393

hwrm_tunnel_dst_port_query_input::req_type
__le16 req_type
Definition bnxt_hsi.h:8394

hwrm_tunnel_dst_port_query_input::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:8406

hwrm_tunnel_dst_port_query_input::target_id
__le16 target_id
Definition bnxt_hsi.h:8397

hwrm_tunnel_dst_port_query_input::tunnel_type
u8 tunnel_type
Definition bnxt_hsi.h:8399

hwrm_tunnel_dst_port_query_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8396

hwrm_tunnel_dst_port_query_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:8395

hwrm_tunnel_dst_port_query_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:8398

hwrm_tunnel_dst_port_query_output
Definition bnxt_hsi.h:8410

hwrm_tunnel_dst_port_query_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:8413

hwrm_tunnel_dst_port_query_output::error_code
__le16 error_code
Definition bnxt_hsi.h:8411

hwrm_tunnel_dst_port_query_output::tunnel_dst_port_id
__le16 tunnel_dst_port_id
Definition bnxt_hsi.h:8415

hwrm_tunnel_dst_port_query_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:8417

hwrm_tunnel_dst_port_query_output::req_type
__le16 req_type
Definition bnxt_hsi.h:8412

hwrm_tunnel_dst_port_query_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:8414

hwrm_tunnel_dst_port_query_output::tunnel_dst_port_val
__be16 tunnel_dst_port_val
Definition bnxt_hsi.h:8416

hwrm_tunnel_dst_port_query_output::valid
u8 valid
Definition bnxt_hsi.h:8418

hwrm_ver_get_input
Definition bnxt_hsi.h:376

hwrm_ver_get_input::hwrm_intf_upd
u8 hwrm_intf_upd
Definition bnxt_hsi.h:384

hwrm_ver_get_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:379

hwrm_ver_get_input::req_type
__le16 req_type
Definition bnxt_hsi.h:377

hwrm_ver_get_input::hwrm_intf_min
u8 hwrm_intf_min
Definition bnxt_hsi.h:383

hwrm_ver_get_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:378

hwrm_ver_get_input::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:385

hwrm_ver_get_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:381

hwrm_ver_get_input::target_id
__le16 target_id
Definition bnxt_hsi.h:380

hwrm_ver_get_input::hwrm_intf_maj
u8 hwrm_intf_maj
Definition bnxt_hsi.h:382

hwrm_ver_get_output
Definition bnxt_hsi.h:389

hwrm_ver_get_output::netctrl_fw_major
__le16 netctrl_fw_major
Definition bnxt_hsi.h:459

hwrm_ver_get_output::roce_fw_minor
__le16 roce_fw_minor
Definition bnxt_hsi.h:464

hwrm_ver_get_output::chip_num
__le16 chip_num
Definition bnxt_hsi.h:430

hwrm_ver_get_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:392

hwrm_ver_get_output::roce_fw_name
char roce_fw_name[16]
Definition bnxt_hsi.h:429

hwrm_ver_get_output::mgmt_fw_maj_8b
u8 mgmt_fw_maj_8b
Definition bnxt_hsi.h:402

hwrm_ver_get_output::def_req_timeout
__le16 def_req_timeout
Definition bnxt_hsi.h:441

hwrm_ver_get_output::mgmt_fw_min_8b
u8 mgmt_fw_min_8b
Definition bnxt_hsi.h:403

hwrm_ver_get_output::chip_bond_id
u8 chip_bond_id
Definition bnxt_hsi.h:433

hwrm_ver_get_output::error_code
__le16 error_code
Definition bnxt_hsi.h:390

hwrm_ver_get_output::mgmt_fw_minor
__le16 mgmt_fw_minor
Definition bnxt_hsi.h:456

hwrm_ver_get_output::hwrm_fw_maj_8b
u8 hwrm_fw_maj_8b
Definition bnxt_hsi.h:398

hwrm_ver_get_output::hwrm_fw_minor
__le16 hwrm_fw_minor
Definition bnxt_hsi.h:452

hwrm_ver_get_output::req_type
__le16 req_type
Definition bnxt_hsi.h:391

hwrm_ver_get_output::netctrl_fw_name
char netctrl_fw_name[16]
Definition bnxt_hsi.h:427

hwrm_ver_get_output::netctrl_fw_minor
__le16 netctrl_fw_minor
Definition bnxt_hsi.h:460

hwrm_ver_get_output::roce_fw_rsvd_8b
u8 roce_fw_rsvd_8b
Definition bnxt_hsi.h:424

hwrm_ver_get_output::flags
u8 flags
Definition bnxt_hsi.h:442

hwrm_ver_get_output::netctrl_fw_build
__le16 netctrl_fw_build
Definition bnxt_hsi.h:461

hwrm_ver_get_output::chip_platform_type
u8 chip_platform_type
Definition bnxt_hsi.h:434

hwrm_ver_get_output::hwrm_fw_build
__le16 hwrm_fw_build
Definition bnxt_hsi.h:453

hwrm_ver_get_output::hwrm_intf_min_8b
u8 hwrm_intf_min_8b
Definition bnxt_hsi.h:395

hwrm_ver_get_output::roce_fw_bld_8b
u8 roce_fw_bld_8b
Definition bnxt_hsi.h:423

hwrm_ver_get_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:393

hwrm_ver_get_output::netctrl_fw_rsvd_8b
u8 netctrl_fw_rsvd_8b
Definition bnxt_hsi.h:409

hwrm_ver_get_output::max_ext_req_len
__le16 max_ext_req_len
Definition bnxt_hsi.h:467

hwrm_ver_get_output::valid
u8 valid
Definition bnxt_hsi.h:469

hwrm_ver_get_output::hwrm_intf_minor
__le16 hwrm_intf_minor
Definition bnxt_hsi.h:448

hwrm_ver_get_output::hwrm_intf_major
__le16 hwrm_intf_major
Definition bnxt_hsi.h:447

hwrm_ver_get_output::always_1
u8 always_1
Definition bnxt_hsi.h:446

hwrm_ver_get_output::roce_fw_build
__le16 roce_fw_build
Definition bnxt_hsi.h:465

hwrm_ver_get_output::hwrm_intf_maj_8b
u8 hwrm_intf_maj_8b
Definition bnxt_hsi.h:394

hwrm_ver_get_output::hwrm_fw_major
__le16 hwrm_fw_major
Definition bnxt_hsi.h:451

hwrm_ver_get_output::mgmt_fw_major
__le16 mgmt_fw_major
Definition bnxt_hsi.h:455

hwrm_ver_get_output::netctrl_fw_maj_8b
u8 netctrl_fw_maj_8b
Definition bnxt_hsi.h:406

hwrm_ver_get_output::max_resp_len
__le16 max_resp_len
Definition bnxt_hsi.h:440

hwrm_ver_get_output::roce_fw_patch
__le16 roce_fw_patch
Definition bnxt_hsi.h:466

hwrm_ver_get_output::hwrm_fw_patch
__le16 hwrm_fw_patch
Definition bnxt_hsi.h:454

hwrm_ver_get_output::chip_metal
u8 chip_metal
Definition bnxt_hsi.h:432

hwrm_ver_get_output::netctrl_fw_patch
__le16 netctrl_fw_patch
Definition bnxt_hsi.h:462

hwrm_ver_get_output::mgmt_fw_patch
__le16 mgmt_fw_patch
Definition bnxt_hsi.h:458

hwrm_ver_get_output::hwrm_fw_rsvd_8b
u8 hwrm_fw_rsvd_8b
Definition bnxt_hsi.h:401

hwrm_ver_get_output::hwrm_intf_build
__le16 hwrm_intf_build
Definition bnxt_hsi.h:449

hwrm_ver_get_output::unused_1
u8 unused_1[5]
Definition bnxt_hsi.h:468

hwrm_ver_get_output::hwrm_fw_min_8b
u8 hwrm_fw_min_8b
Definition bnxt_hsi.h:399

hwrm_ver_get_output::hwrm_fw_bld_8b
u8 hwrm_fw_bld_8b
Definition bnxt_hsi.h:400

hwrm_ver_get_output::hwrm_intf_upd_8b
u8 hwrm_intf_upd_8b
Definition bnxt_hsi.h:396

hwrm_ver_get_output::roce_fw_major
__le16 roce_fw_major
Definition bnxt_hsi.h:463

hwrm_ver_get_output::mgmt_fw_rsvd_8b
u8 mgmt_fw_rsvd_8b
Definition bnxt_hsi.h:405

hwrm_ver_get_output::hwrm_intf_patch
__le16 hwrm_intf_patch
Definition bnxt_hsi.h:450

hwrm_ver_get_output::reserved2
u8 reserved2[16]
Definition bnxt_hsi.h:428

hwrm_ver_get_output::roce_fw_maj_8b
u8 roce_fw_maj_8b
Definition bnxt_hsi.h:421

hwrm_ver_get_output::mgmt_fw_build
__le16 mgmt_fw_build
Definition bnxt_hsi.h:457

hwrm_ver_get_output::dev_caps_cfg
__le32 dev_caps_cfg
Definition bnxt_hsi.h:410

hwrm_ver_get_output::max_req_win_len
__le16 max_req_win_len
Definition bnxt_hsi.h:439

hwrm_ver_get_output::netctrl_fw_bld_8b
u8 netctrl_fw_bld_8b
Definition bnxt_hsi.h:408

hwrm_ver_get_output::mgmt_fw_name
char mgmt_fw_name[16]
Definition bnxt_hsi.h:426

hwrm_ver_get_output::chip_rev
u8 chip_rev
Definition bnxt_hsi.h:431

hwrm_ver_get_output::mgmt_fw_bld_8b
u8 mgmt_fw_bld_8b
Definition bnxt_hsi.h:404

hwrm_ver_get_output::hwrm_intf_rsvd_8b
u8 hwrm_intf_rsvd_8b
Definition bnxt_hsi.h:397

hwrm_ver_get_output::netctrl_fw_min_8b
u8 netctrl_fw_min_8b
Definition bnxt_hsi.h:407

hwrm_ver_get_output::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:445

hwrm_ver_get_output::roce_fw_min_8b
u8 roce_fw_min_8b
Definition bnxt_hsi.h:422

hwrm_ver_get_output::hwrm_fw_name
char hwrm_fw_name[16]
Definition bnxt_hsi.h:425

hwrm_vnic_alloc_input
Definition bnxt_hsi.h:5762

hwrm_vnic_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5767

hwrm_vnic_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5764

hwrm_vnic_alloc_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:5770

hwrm_vnic_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5765

hwrm_vnic_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5763

hwrm_vnic_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:5768

hwrm_vnic_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5766

hwrm_vnic_alloc_output
Definition bnxt_hsi.h:5774

hwrm_vnic_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5778

hwrm_vnic_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5776

hwrm_vnic_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:5781

hwrm_vnic_alloc_output::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:5779

hwrm_vnic_alloc_output::unused_0
u8 unused_0[3]
Definition bnxt_hsi.h:5780

hwrm_vnic_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5775

hwrm_vnic_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5777

hwrm_vnic_cfg_input
Definition bnxt_hsi.h:5806

hwrm_vnic_cfg_input::default_rx_ring_id
__le16 default_rx_ring_id
Definition bnxt_hsi.h:5834

hwrm_vnic_cfg_input::dflt_ring_grp
__le16 dflt_ring_grp
Definition bnxt_hsi.h:5829

hwrm_vnic_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5810

hwrm_vnic_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5808

hwrm_vnic_cfg_input::vnic_id
__le16 vnic_id
Definition bnxt_hsi.h:5828

hwrm_vnic_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5809

hwrm_vnic_cfg_input::rss_rule
__le16 rss_rule
Definition bnxt_hsi.h:5830

hwrm_vnic_cfg_input::lb_rule
__le16 lb_rule
Definition bnxt_hsi.h:5832

hwrm_vnic_cfg_input::default_cmpl_ring_id
__le16 default_cmpl_ring_id
Definition bnxt_hsi.h:5835

hwrm_vnic_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5811

hwrm_vnic_cfg_input::cos_rule
__le16 cos_rule
Definition bnxt_hsi.h:5831

hwrm_vnic_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:5812

hwrm_vnic_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:5820

hwrm_vnic_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5807

hwrm_vnic_cfg_input::mru
__le16 mru
Definition bnxt_hsi.h:5833

hwrm_vnic_cfg_output
Definition bnxt_hsi.h:5839

hwrm_vnic_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:5844

hwrm_vnic_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5842

hwrm_vnic_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:5845

hwrm_vnic_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5841

hwrm_vnic_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5840

hwrm_vnic_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5843

hwrm_vnic_free_input
Definition bnxt_hsi.h:5785

hwrm_vnic_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5789

hwrm_vnic_free_input::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:5791

hwrm_vnic_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5787

hwrm_vnic_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5788

hwrm_vnic_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5790

hwrm_vnic_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5786

hwrm_vnic_free_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:5792

hwrm_vnic_free_output
Definition bnxt_hsi.h:5796

hwrm_vnic_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5798

hwrm_vnic_free_output::valid
u8 valid
Definition bnxt_hsi.h:5802

hwrm_vnic_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5800

hwrm_vnic_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:5801

hwrm_vnic_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5799

hwrm_vnic_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5797

hwrm_vnic_plcmodes_cfg_input
Definition bnxt_hsi.h:6092

hwrm_vnic_plcmodes_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:6105

hwrm_vnic_plcmodes_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6097

hwrm_vnic_plcmodes_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:6098

hwrm_vnic_plcmodes_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6093

hwrm_vnic_plcmodes_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6094

hwrm_vnic_plcmodes_cfg_input::jumbo_thresh
__le16 jumbo_thresh
Definition bnxt_hsi.h:6110

hwrm_vnic_plcmodes_cfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:6113

hwrm_vnic_plcmodes_cfg_input::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:6109

hwrm_vnic_plcmodes_cfg_input::hds_offset
__le16 hds_offset
Definition bnxt_hsi.h:6111

hwrm_vnic_plcmodes_cfg_input::hds_threshold
__le16 hds_threshold
Definition bnxt_hsi.h:6112

hwrm_vnic_plcmodes_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6095

hwrm_vnic_plcmodes_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6096

hwrm_vnic_plcmodes_cfg_output
Definition bnxt_hsi.h:6117

hwrm_vnic_plcmodes_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6118

hwrm_vnic_plcmodes_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6121

hwrm_vnic_plcmodes_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6122

hwrm_vnic_plcmodes_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6119

hwrm_vnic_plcmodes_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:6123

hwrm_vnic_plcmodes_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6120

hwrm_vnic_plcmodes_qcfg_input
Definition bnxt_hsi.h:6127

hwrm_vnic_plcmodes_qcfg_input::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:6133

hwrm_vnic_plcmodes_qcfg_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:6134

hwrm_vnic_plcmodes_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6129

hwrm_vnic_plcmodes_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6132

hwrm_vnic_plcmodes_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6128

hwrm_vnic_plcmodes_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6131

hwrm_vnic_plcmodes_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6130

hwrm_vnic_plcmodes_qcfg_output
Definition bnxt_hsi.h:6138

hwrm_vnic_plcmodes_qcfg_output::hds_offset
__le16 hds_offset
Definition bnxt_hsi.h:6152

hwrm_vnic_plcmodes_qcfg_output::flags
__le32 flags
Definition bnxt_hsi.h:6143

hwrm_vnic_plcmodes_qcfg_output::jumbo_thresh
__le16 jumbo_thresh
Definition bnxt_hsi.h:6151

hwrm_vnic_plcmodes_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:6155

hwrm_vnic_plcmodes_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6139

hwrm_vnic_plcmodes_qcfg_output::hds_threshold
__le16 hds_threshold
Definition bnxt_hsi.h:6153

hwrm_vnic_plcmodes_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6142

hwrm_vnic_plcmodes_qcfg_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:6154

hwrm_vnic_plcmodes_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6141

hwrm_vnic_plcmodes_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6140

hwrm_vnic_qcaps_input
Definition bnxt_hsi.h:5887

hwrm_vnic_qcaps_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5890

hwrm_vnic_qcaps_input::enables
__le32 enables
Definition bnxt_hsi.h:5893

hwrm_vnic_qcaps_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5892

hwrm_vnic_qcaps_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5889

hwrm_vnic_qcaps_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5891

hwrm_vnic_qcaps_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:5894

hwrm_vnic_qcaps_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5888

hwrm_vnic_qcaps_output
Definition bnxt_hsi.h:5898

hwrm_vnic_qcaps_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5900

hwrm_vnic_qcaps_output::valid
u8 valid
Definition bnxt_hsi.h:5915

hwrm_vnic_qcaps_output::flags
__le32 flags
Definition bnxt_hsi.h:5905

hwrm_vnic_qcaps_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:5914

hwrm_vnic_qcaps_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5901

hwrm_vnic_qcaps_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5902

hwrm_vnic_qcaps_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5899

hwrm_vnic_qcaps_output::mru
__le16 mru
Definition bnxt_hsi.h:5903

hwrm_vnic_qcaps_output::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:5904

hwrm_vnic_qcfg_input
Definition bnxt_hsi.h:5849

hwrm_vnic_qcfg_input::vf_id
__le16 vf_id
Definition bnxt_hsi.h:5858

hwrm_vnic_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5851

hwrm_vnic_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5850

hwrm_vnic_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:5859

hwrm_vnic_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5852

hwrm_vnic_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5854

hwrm_vnic_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5853

hwrm_vnic_qcfg_input::enables
__le32 enables
Definition bnxt_hsi.h:5855

hwrm_vnic_qcfg_input::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:5857

hwrm_vnic_qcfg_output
Definition bnxt_hsi.h:5863

hwrm_vnic_qcfg_output::lb_rule
__le16 lb_rule
Definition bnxt_hsi.h:5871

hwrm_vnic_qcfg_output::rss_rule
__le16 rss_rule
Definition bnxt_hsi.h:5869

hwrm_vnic_qcfg_output::unused_1
u8 unused_1[7]
Definition bnxt_hsi.h:5882

hwrm_vnic_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5867

hwrm_vnic_qcfg_output::cos_rule
__le16 cos_rule
Definition bnxt_hsi.h:5870

hwrm_vnic_qcfg_output::mru
__le16 mru
Definition bnxt_hsi.h:5872

hwrm_vnic_qcfg_output::dflt_ring_grp
__le16 dflt_ring_grp
Definition bnxt_hsi.h:5868

hwrm_vnic_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5866

hwrm_vnic_qcfg_output::flags
__le32 flags
Definition bnxt_hsi.h:5874

hwrm_vnic_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5865

hwrm_vnic_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:5883

hwrm_vnic_qcfg_output::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:5873

hwrm_vnic_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5864

hwrm_vnic_rss_cfg_input
Definition bnxt_hsi.h:6018

hwrm_vnic_rss_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6022

hwrm_vnic_rss_cfg_input::vnic_id
__le16 vnic_id
Definition bnxt_hsi.h:6031

hwrm_vnic_rss_cfg_input::hash_type
__le32 hash_type
Definition bnxt_hsi.h:6024

hwrm_vnic_rss_cfg_input::hash_key_tbl_addr
__le64 hash_key_tbl_addr
Definition bnxt_hsi.h:6040

hwrm_vnic_rss_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6023

hwrm_vnic_rss_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6021

hwrm_vnic_rss_cfg_input::hash_mode_flags
u8 hash_mode_flags
Definition bnxt_hsi.h:6033

hwrm_vnic_rss_cfg_input::ring_grp_tbl_addr
__le64 ring_grp_tbl_addr
Definition bnxt_hsi.h:6039

hwrm_vnic_rss_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6019

hwrm_vnic_rss_cfg_input::unused_1
u8 unused_1[6]
Definition bnxt_hsi.h:6042

hwrm_vnic_rss_cfg_input::ring_table_pair_index
u8 ring_table_pair_index
Definition bnxt_hsi.h:6032

hwrm_vnic_rss_cfg_input::rss_ctx_idx
__le16 rss_ctx_idx
Definition bnxt_hsi.h:6041

hwrm_vnic_rss_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6020

hwrm_vnic_rss_cfg_output
Definition bnxt_hsi.h:6046

hwrm_vnic_rss_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6048

hwrm_vnic_rss_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6049

hwrm_vnic_rss_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6047

hwrm_vnic_rss_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6051

hwrm_vnic_rss_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:6052

hwrm_vnic_rss_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6050

hwrm_vnic_rss_cos_lb_ctx_alloc_input
Definition bnxt_hsi.h:6159

hwrm_vnic_rss_cos_lb_ctx_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6162

hwrm_vnic_rss_cos_lb_ctx_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6163

hwrm_vnic_rss_cos_lb_ctx_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6164

hwrm_vnic_rss_cos_lb_ctx_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6160

hwrm_vnic_rss_cos_lb_ctx_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6161

hwrm_vnic_rss_cos_lb_ctx_alloc_output
Definition bnxt_hsi.h:6168

hwrm_vnic_rss_cos_lb_ctx_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6169

hwrm_vnic_rss_cos_lb_ctx_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:6175

hwrm_vnic_rss_cos_lb_ctx_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6171

hwrm_vnic_rss_cos_lb_ctx_alloc_output::rss_cos_lb_ctx_id
__le16 rss_cos_lb_ctx_id
Definition bnxt_hsi.h:6173

hwrm_vnic_rss_cos_lb_ctx_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6170

hwrm_vnic_rss_cos_lb_ctx_alloc_output::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:6174

hwrm_vnic_rss_cos_lb_ctx_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6172

hwrm_vnic_rss_cos_lb_ctx_free_input
Definition bnxt_hsi.h:6179

hwrm_vnic_rss_cos_lb_ctx_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6183

hwrm_vnic_rss_cos_lb_ctx_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6182

hwrm_vnic_rss_cos_lb_ctx_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6184

hwrm_vnic_rss_cos_lb_ctx_free_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:6186

hwrm_vnic_rss_cos_lb_ctx_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6181

hwrm_vnic_rss_cos_lb_ctx_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6180

hwrm_vnic_rss_cos_lb_ctx_free_input::rss_cos_lb_ctx_id
__le16 rss_cos_lb_ctx_id
Definition bnxt_hsi.h:6185

hwrm_vnic_rss_cos_lb_ctx_free_output
Definition bnxt_hsi.h:6190

hwrm_vnic_rss_cos_lb_ctx_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6195

hwrm_vnic_rss_cos_lb_ctx_free_output::valid
u8 valid
Definition bnxt_hsi.h:6196

hwrm_vnic_rss_cos_lb_ctx_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6192

hwrm_vnic_rss_cos_lb_ctx_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6191

hwrm_vnic_rss_cos_lb_ctx_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6193

hwrm_vnic_rss_cos_lb_ctx_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6194

hwrm_vnic_rss_qcfg_input
Definition bnxt_hsi.h:6056

hwrm_vnic_rss_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:6061

hwrm_vnic_rss_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:6060

hwrm_vnic_rss_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:6063

hwrm_vnic_rss_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:6057

hwrm_vnic_rss_qcfg_input::rss_ctx_idx
__le16 rss_ctx_idx
Definition bnxt_hsi.h:6062

hwrm_vnic_rss_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:6058

hwrm_vnic_rss_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6059

hwrm_vnic_rss_qcfg_output
Definition bnxt_hsi.h:6067

hwrm_vnic_rss_qcfg_output::hash_type
__le32 hash_type
Definition bnxt_hsi.h:6072

hwrm_vnic_rss_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:6088

hwrm_vnic_rss_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:6069

hwrm_vnic_rss_qcfg_output::unused_1
u8 unused_1[6]
Definition bnxt_hsi.h:6087

hwrm_vnic_rss_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:6068

hwrm_vnic_rss_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:6071

hwrm_vnic_rss_qcfg_output::hash_key
__le32 hash_key[10]
Definition bnxt_hsi.h:6080

hwrm_vnic_rss_qcfg_output::hash_mode_flags
u8 hash_mode_flags
Definition bnxt_hsi.h:6081

hwrm_vnic_rss_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:6070

hwrm_vnic_rss_qcfg_output::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:6079

hwrm_vnic_tpa_cfg_input
Definition bnxt_hsi.h:5919

hwrm_vnic_tpa_cfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5921

hwrm_vnic_tpa_cfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5923

hwrm_vnic_tpa_cfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5922

hwrm_vnic_tpa_cfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5924

hwrm_vnic_tpa_cfg_input::max_agg_segs
__le16 max_agg_segs
Definition bnxt_hsi.h:5940

hwrm_vnic_tpa_cfg_input::min_agg_len
__le32 min_agg_len
Definition bnxt_hsi.h:5957

hwrm_vnic_tpa_cfg_input::vnic_id
__le16 vnic_id
Definition bnxt_hsi.h:5939

hwrm_vnic_tpa_cfg_input::max_aggs
__le16 max_aggs
Definition bnxt_hsi.h:5947

hwrm_vnic_tpa_cfg_input::max_agg_timer
__le32 max_agg_timer
Definition bnxt_hsi.h:5956

hwrm_vnic_tpa_cfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5920

hwrm_vnic_tpa_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:5934

hwrm_vnic_tpa_cfg_input::unused_0
u8 unused_0[2]
Definition bnxt_hsi.h:5955

hwrm_vnic_tpa_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:5925

hwrm_vnic_tpa_cfg_output
Definition bnxt_hsi.h:5961

hwrm_vnic_tpa_cfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5963

hwrm_vnic_tpa_cfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5962

hwrm_vnic_tpa_cfg_output::valid
u8 valid
Definition bnxt_hsi.h:5967

hwrm_vnic_tpa_cfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5964

hwrm_vnic_tpa_cfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5965

hwrm_vnic_tpa_cfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:5966

hwrm_vnic_tpa_qcfg_input
Definition bnxt_hsi.h:5971

hwrm_vnic_tpa_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:5978

hwrm_vnic_tpa_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:5972

hwrm_vnic_tpa_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5974

hwrm_vnic_tpa_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:5975

hwrm_vnic_tpa_qcfg_input::vnic_id
__le16 vnic_id
Definition bnxt_hsi.h:5977

hwrm_vnic_tpa_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:5973

hwrm_vnic_tpa_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:5976

hwrm_vnic_tpa_qcfg_output
Definition bnxt_hsi.h:5982

hwrm_vnic_tpa_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:5985

hwrm_vnic_tpa_qcfg_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:6013

hwrm_vnic_tpa_qcfg_output::max_agg_segs
__le16 max_agg_segs
Definition bnxt_hsi.h:5996

hwrm_vnic_tpa_qcfg_output::min_agg_len
__le32 min_agg_len
Definition bnxt_hsi.h:6012

hwrm_vnic_tpa_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:6014

hwrm_vnic_tpa_qcfg_output::max_agg_timer
__le32 max_agg_timer
Definition bnxt_hsi.h:6011

hwrm_vnic_tpa_qcfg_output::flags
__le32 flags
Definition bnxt_hsi.h:5987

hwrm_vnic_tpa_qcfg_output::max_aggs
__le16 max_aggs
Definition bnxt_hsi.h:6003

hwrm_vnic_tpa_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:5983

hwrm_vnic_tpa_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:5986

hwrm_vnic_tpa_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:5984

hwrm_vxlan_ipv4_hdr
Definition bnxt_hsi.h:6959

hwrm_vxlan_ipv4_hdr::protocol
u8 protocol
Definition bnxt_hsi.h:6969

hwrm_vxlan_ipv4_hdr::ttl
u8 ttl
Definition bnxt_hsi.h:6968

hwrm_vxlan_ipv4_hdr::ip_id
__be16 ip_id
Definition bnxt_hsi.h:6966

hwrm_vxlan_ipv4_hdr::dest_ip_addr
__be32 dest_ip_addr
Definition bnxt_hsi.h:6971

hwrm_vxlan_ipv4_hdr::ver_hlen
u8 ver_hlen
Definition bnxt_hsi.h:6960

hwrm_vxlan_ipv4_hdr::src_ip_addr
__be32 src_ip_addr
Definition bnxt_hsi.h:6970

hwrm_vxlan_ipv4_hdr::flags_frag_offset
__be16 flags_frag_offset
Definition bnxt_hsi.h:6967

hwrm_vxlan_ipv4_hdr::tos
u8 tos
Definition bnxt_hsi.h:6965

hwrm_vxlan_ipv6_hdr
Definition bnxt_hsi.h:6975

hwrm_vxlan_ipv6_hdr::ttl
u8 ttl
Definition bnxt_hsi.h:6986

hwrm_vxlan_ipv6_hdr::dest_ip_addr
__be32 dest_ip_addr[4]
Definition bnxt_hsi.h:6988

hwrm_vxlan_ipv6_hdr::src_ip_addr
__be32 src_ip_addr[4]
Definition bnxt_hsi.h:6987

hwrm_vxlan_ipv6_hdr::next_hdr
u8 next_hdr
Definition bnxt_hsi.h:6985

hwrm_vxlan_ipv6_hdr::ver_tc_flow_label
__be32 ver_tc_flow_label
Definition bnxt_hsi.h:6976

hwrm_vxlan_ipv6_hdr::payload_len
__be16 payload_len
Definition bnxt_hsi.h:6984

hwrm_wol_filter_alloc_input
Definition bnxt_hsi.h:9373

hwrm_wol_filter_alloc_input::pattern_mask_size
__le16 pattern_mask_size
Definition bnxt_hsi.h:9397

hwrm_wol_filter_alloc_input::pattern_mask_addr
__le64 pattern_mask_addr
Definition bnxt_hsi.h:9400

hwrm_wol_filter_alloc_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9378

hwrm_wol_filter_alloc_input::port_id
__le16 port_id
Definition bnxt_hsi.h:9387

hwrm_wol_filter_alloc_input::wol_type
u8 wol_type
Definition bnxt_hsi.h:9388

hwrm_wol_filter_alloc_input::mac_address
u8 mac_address[6]
Definition bnxt_hsi.h:9394

hwrm_wol_filter_alloc_input::pattern_buf_size
__le16 pattern_buf_size
Definition bnxt_hsi.h:9396

hwrm_wol_filter_alloc_input::unused_1
u8 unused_1[4]
Definition bnxt_hsi.h:9398

hwrm_wol_filter_alloc_input::pattern_buf_addr
__le64 pattern_buf_addr
Definition bnxt_hsi.h:9399

hwrm_wol_filter_alloc_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9374

hwrm_wol_filter_alloc_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9376

hwrm_wol_filter_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:9380

hwrm_wol_filter_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:9379

hwrm_wol_filter_alloc_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9375

hwrm_wol_filter_alloc_input::pattern_offset
__le16 pattern_offset
Definition bnxt_hsi.h:9395

hwrm_wol_filter_alloc_input::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:9393

hwrm_wol_filter_alloc_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9377

hwrm_wol_filter_alloc_output
Definition bnxt_hsi.h:9404

hwrm_wol_filter_alloc_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9408

hwrm_wol_filter_alloc_output::wol_filter_id
u8 wol_filter_id
Definition bnxt_hsi.h:9409

hwrm_wol_filter_alloc_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9406

hwrm_wol_filter_alloc_output::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:9410

hwrm_wol_filter_alloc_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9407

hwrm_wol_filter_alloc_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9405

hwrm_wol_filter_alloc_output::valid
u8 valid
Definition bnxt_hsi.h:9411

hwrm_wol_filter_free_input
Definition bnxt_hsi.h:9415

hwrm_wol_filter_free_input::port_id
__le16 port_id
Definition bnxt_hsi.h:9425

hwrm_wol_filter_free_input::wol_filter_id
u8 wol_filter_id
Definition bnxt_hsi.h:9426

hwrm_wol_filter_free_input::unused_0
u8 unused_0[5]
Definition bnxt_hsi.h:9427

hwrm_wol_filter_free_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9418

hwrm_wol_filter_free_input::enables
__le32 enables
Definition bnxt_hsi.h:9423

hwrm_wol_filter_free_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9417

hwrm_wol_filter_free_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9419

hwrm_wol_filter_free_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9420

hwrm_wol_filter_free_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9416

hwrm_wol_filter_free_input::flags
__le32 flags
Definition bnxt_hsi.h:9421

hwrm_wol_filter_free_output
Definition bnxt_hsi.h:9431

hwrm_wol_filter_free_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9434

hwrm_wol_filter_free_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9432

hwrm_wol_filter_free_output::unused_0
u8 unused_0[7]
Definition bnxt_hsi.h:9436

hwrm_wol_filter_free_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9433

hwrm_wol_filter_free_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9435

hwrm_wol_filter_free_output::valid
u8 valid
Definition bnxt_hsi.h:9437

hwrm_wol_filter_qcfg_input
Definition bnxt_hsi.h:9441

hwrm_wol_filter_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9445

hwrm_wol_filter_qcfg_input::pattern_buf_size
__le16 pattern_buf_size
Definition bnxt_hsi.h:9451

hwrm_wol_filter_qcfg_input::unused_1
u8 unused_1[6]
Definition bnxt_hsi.h:9452

hwrm_wol_filter_qcfg_input::pattern_buf_addr
__le64 pattern_buf_addr
Definition bnxt_hsi.h:9450

hwrm_wol_filter_qcfg_input::pattern_mask_addr
__le64 pattern_mask_addr
Definition bnxt_hsi.h:9453

hwrm_wol_filter_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9446

hwrm_wol_filter_qcfg_input::pattern_mask_size
__le16 pattern_mask_size
Definition bnxt_hsi.h:9454

hwrm_wol_filter_qcfg_input::unused_2
u8 unused_2[6]
Definition bnxt_hsi.h:9455

hwrm_wol_filter_qcfg_input::handle
__le16 handle
Definition bnxt_hsi.h:9448

hwrm_wol_filter_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9442

hwrm_wol_filter_qcfg_input::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:9449

hwrm_wol_filter_qcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:9447

hwrm_wol_filter_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9443

hwrm_wol_filter_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9444

hwrm_wol_filter_qcfg_output
Definition bnxt_hsi.h:9459

hwrm_wol_filter_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9461

hwrm_wol_filter_qcfg_output::unused_0
__le32 unused_0
Definition bnxt_hsi.h:9471

hwrm_wol_filter_qcfg_output::wol_filter_id
u8 wol_filter_id
Definition bnxt_hsi.h:9465

hwrm_wol_filter_qcfg_output::next_handle
__le16 next_handle
Definition bnxt_hsi.h:9464

hwrm_wol_filter_qcfg_output::unused_1
u8 unused_1[3]
Definition bnxt_hsi.h:9476

hwrm_wol_filter_qcfg_output::pattern_mask_size
__le16 pattern_mask_size
Definition bnxt_hsi.h:9475

hwrm_wol_filter_qcfg_output::wol_type
u8 wol_type
Definition bnxt_hsi.h:9466

hwrm_wol_filter_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9463

hwrm_wol_filter_qcfg_output::pattern_offset
__le16 pattern_offset
Definition bnxt_hsi.h:9473

hwrm_wol_filter_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:9477

hwrm_wol_filter_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9462

hwrm_wol_filter_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9460

hwrm_wol_filter_qcfg_output::mac_address
u8 mac_address[6]
Definition bnxt_hsi.h:9472

hwrm_wol_filter_qcfg_output::pattern_size
__le16 pattern_size
Definition bnxt_hsi.h:9474

hwrm_wol_reason_qcfg_input
Definition bnxt_hsi.h:9481

hwrm_wol_reason_qcfg_input::target_id
__le16 target_id
Definition bnxt_hsi.h:9485

hwrm_wol_reason_qcfg_input::unused_1
u8 unused_1[6]
Definition bnxt_hsi.h:9491

hwrm_wol_reason_qcfg_input::wol_pkt_buf_addr
__le64 wol_pkt_buf_addr
Definition bnxt_hsi.h:9489

hwrm_wol_reason_qcfg_input::unused_0
u8 unused_0[6]
Definition bnxt_hsi.h:9488

hwrm_wol_reason_qcfg_input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:9483

hwrm_wol_reason_qcfg_input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9484

hwrm_wol_reason_qcfg_input::req_type
__le16 req_type
Definition bnxt_hsi.h:9482

hwrm_wol_reason_qcfg_input::wol_pkt_buf_size
__le16 wol_pkt_buf_size
Definition bnxt_hsi.h:9490

hwrm_wol_reason_qcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:9487

hwrm_wol_reason_qcfg_input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:9486

hwrm_wol_reason_qcfg_output
Definition bnxt_hsi.h:9495

hwrm_wol_reason_qcfg_output::valid
u8 valid
Definition bnxt_hsi.h:9508

hwrm_wol_reason_qcfg_output::req_type
__le16 req_type
Definition bnxt_hsi.h:9497

hwrm_wol_reason_qcfg_output::error_code
__le16 error_code
Definition bnxt_hsi.h:9496

hwrm_wol_reason_qcfg_output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:9498

hwrm_wol_reason_qcfg_output::unused_0
u8 unused_0[4]
Definition bnxt_hsi.h:9507

hwrm_wol_reason_qcfg_output::wol_filter_id
u8 wol_filter_id
Definition bnxt_hsi.h:9500

hwrm_wol_reason_qcfg_output::wol_reason
u8 wol_reason
Definition bnxt_hsi.h:9501

hwrm_wol_reason_qcfg_output::wol_pkt_len
u8 wol_pkt_len
Definition bnxt_hsi.h:9506

hwrm_wol_reason_qcfg_output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:9499

input
Definition bnxt_hsi.h:68

input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:71

input::req_type
__le16 req_type
Definition bnxt_hsi.h:69

input::target_id
__le16 target_id
Definition bnxt_hsi.h:72

input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:73

input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:70

output
Definition bnxt_hsi.h:77

output::error_code
__le16 error_code
Definition bnxt_hsi.h:78

output::req_type
__le16 req_type
Definition bnxt_hsi.h:79

output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:81

output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:80

pcie_ctx_hw_stats
Definition bnxt_hsi.h:8678

pcie_ctx_hw_stats::pcie_equalization_time
__le64 pcie_equalization_time
Definition bnxt_hsi.h:8687

pcie_ctx_hw_stats::pcie_link_integrity
__le64 pcie_link_integrity
Definition bnxt_hsi.h:8682

pcie_ctx_hw_stats::pcie_ltssm_histogram
__le32 pcie_ltssm_histogram[4]
Definition bnxt_hsi.h:8688

pcie_ctx_hw_stats::pcie_rx_dllp_statistics
__le64 pcie_rx_dllp_statistics
Definition bnxt_hsi.h:8686

pcie_ctx_hw_stats::pcie_pl_signal_integrity
__le64 pcie_pl_signal_integrity
Definition bnxt_hsi.h:8679

pcie_ctx_hw_stats::pcie_tx_dllp_statistics
__le64 pcie_tx_dllp_statistics
Definition bnxt_hsi.h:8685

pcie_ctx_hw_stats::pcie_recovery_histogram
__le64 pcie_recovery_histogram
Definition bnxt_hsi.h:8689

pcie_ctx_hw_stats::pcie_tl_signal_integrity
__le64 pcie_tl_signal_integrity
Definition bnxt_hsi.h:8681

pcie_ctx_hw_stats::pcie_tx_traffic_rate
__le64 pcie_tx_traffic_rate
Definition bnxt_hsi.h:8683

pcie_ctx_hw_stats::pcie_rx_traffic_rate
__le64 pcie_rx_traffic_rate
Definition bnxt_hsi.h:8684

pcie_ctx_hw_stats::pcie_dl_signal_integrity
__le64 pcie_dl_signal_integrity
Definition bnxt_hsi.h:8680

ret_codes
Definition bnxt_hsi.h:329

ret_codes::error_code
__le16 error_code
Definition bnxt_hsi.h:330

ret_codes::unused_0
__le16 unused_0[3]
Definition bnxt_hsi.h:348

rx_port_stats_ext
Definition bnxt_hsi.h:3980

rx_port_stats_ext::rx_bytes_cos3
__le64 rx_bytes_cos3
Definition bnxt_hsi.h:3989

rx_port_stats_ext::pfc_pri7_rx_transitions
__le64 pfc_pri7_rx_transitions
Definition bnxt_hsi.h:4017

rx_port_stats_ext::pfc_pri0_rx_duration_us
__le64 pfc_pri0_rx_duration_us
Definition bnxt_hsi.h:4002

rx_port_stats_ext::continuous_pause_events
__le64 continuous_pause_events
Definition bnxt_hsi.h:3982

rx_port_stats_ext::rx_packets_cos2
__le64 rx_packets_cos2
Definition bnxt_hsi.h:3996

rx_port_stats_ext::pfc_pri2_rx_transitions
__le64 pfc_pri2_rx_transitions
Definition bnxt_hsi.h:4007

rx_port_stats_ext::pfc_pri5_rx_duration_us
__le64 pfc_pri5_rx_duration_us
Definition bnxt_hsi.h:4012

rx_port_stats_ext::pfc_pri0_rx_transitions
__le64 pfc_pri0_rx_transitions
Definition bnxt_hsi.h:4003

rx_port_stats_ext::rx_bytes_cos7
__le64 rx_bytes_cos7
Definition bnxt_hsi.h:3993

rx_port_stats_ext::pfc_pri4_rx_duration_us
__le64 pfc_pri4_rx_duration_us
Definition bnxt_hsi.h:4010

rx_port_stats_ext::continuous_roce_pause_events
__le64 continuous_roce_pause_events
Definition bnxt_hsi.h:3984

rx_port_stats_ext::rx_bytes_cos1
__le64 rx_bytes_cos1
Definition bnxt_hsi.h:3987

rx_port_stats_ext::rx_packets_cos0
__le64 rx_packets_cos0
Definition bnxt_hsi.h:3994

rx_port_stats_ext::pfc_pri2_rx_duration_us
__le64 pfc_pri2_rx_duration_us
Definition bnxt_hsi.h:4006

rx_port_stats_ext::pfc_pri7_rx_duration_us
__le64 pfc_pri7_rx_duration_us
Definition bnxt_hsi.h:4016

rx_port_stats_ext::pfc_pri6_rx_duration_us
__le64 pfc_pri6_rx_duration_us
Definition bnxt_hsi.h:4014

rx_port_stats_ext::rx_packets_cos4
__le64 rx_packets_cos4
Definition bnxt_hsi.h:3998

rx_port_stats_ext::rx_bytes_cos4
__le64 rx_bytes_cos4
Definition bnxt_hsi.h:3990

rx_port_stats_ext::pfc_pri3_rx_duration_us
__le64 pfc_pri3_rx_duration_us
Definition bnxt_hsi.h:4008

rx_port_stats_ext::rx_packets_cos1
__le64 rx_packets_cos1
Definition bnxt_hsi.h:3995

rx_port_stats_ext::rx_packets_cos3
__le64 rx_packets_cos3
Definition bnxt_hsi.h:3997

rx_port_stats_ext::pfc_pri3_rx_transitions
__le64 pfc_pri3_rx_transitions
Definition bnxt_hsi.h:4009

rx_port_stats_ext::resume_pause_events
__le64 resume_pause_events
Definition bnxt_hsi.h:3983

rx_port_stats_ext::resume_roce_pause_events
__le64 resume_roce_pause_events
Definition bnxt_hsi.h:3985

rx_port_stats_ext::rx_bytes_cos0
__le64 rx_bytes_cos0
Definition bnxt_hsi.h:3986

rx_port_stats_ext::rx_packets_cos6
__le64 rx_packets_cos6
Definition bnxt_hsi.h:4000

rx_port_stats_ext::rx_bytes_cos6
__le64 rx_bytes_cos6
Definition bnxt_hsi.h:3992

rx_port_stats_ext::rx_bytes_cos5
__le64 rx_bytes_cos5
Definition bnxt_hsi.h:3991

rx_port_stats_ext::rx_packets_cos7
__le64 rx_packets_cos7
Definition bnxt_hsi.h:4001

rx_port_stats_ext::pfc_pri1_rx_duration_us
__le64 pfc_pri1_rx_duration_us
Definition bnxt_hsi.h:4004

rx_port_stats_ext::rx_bytes_cos2
__le64 rx_bytes_cos2
Definition bnxt_hsi.h:3988

rx_port_stats_ext::link_down_events
__le64 link_down_events
Definition bnxt_hsi.h:3981

rx_port_stats_ext::rx_packets_cos5
__le64 rx_packets_cos5
Definition bnxt_hsi.h:3999

rx_port_stats_ext::pfc_pri1_rx_transitions
__le64 pfc_pri1_rx_transitions
Definition bnxt_hsi.h:4005

rx_port_stats_ext::pfc_pri4_rx_transitions
__le64 pfc_pri4_rx_transitions
Definition bnxt_hsi.h:4011

rx_port_stats_ext::pfc_pri5_rx_transitions
__le64 pfc_pri5_rx_transitions
Definition bnxt_hsi.h:4013

rx_port_stats_ext::pfc_pri6_rx_transitions
__le64 pfc_pri6_rx_transitions
Definition bnxt_hsi.h:4015

rx_port_stats
Definition bnxt_hsi.h:3849

rx_port_stats::rx_pfc_frames
__le64 rx_pfc_frames
Definition bnxt_hsi.h:3868

rx_port_stats::rx_undrsz_frames
__le64 rx_undrsz_frames
Definition bnxt_hsi.h:3902

rx_port_stats::rx_pfc_ena_frames_pri2
__le64 rx_pfc_ena_frames_pri2
Definition bnxt_hsi.h:3895

rx_port_stats::rx_pfc_ena_frames_pri6
__le64 rx_pfc_ena_frames_pri6
Definition bnxt_hsi.h:3899

rx_port_stats::rx_llfc_physical_msgs
__le64 rx_llfc_physical_msgs
Definition bnxt_hsi.h:3906

rx_port_stats::rx_pfc_xon2xoff_frames_pri2
__le64 rx_pfc_xon2xoff_frames_pri2
Definition bnxt_hsi.h:3887

rx_port_stats::rx_stat_discard
__le64 rx_stat_discard
Definition bnxt_hsi.h:3914

rx_port_stats::rx_runt_frames
__le64 rx_runt_frames
Definition bnxt_hsi.h:3913

rx_port_stats::rx_pfc_xon2xoff_frames_pri6
__le64 rx_pfc_xon2xoff_frames_pri6
Definition bnxt_hsi.h:3891

rx_port_stats::rx_frag_frames
__le64 rx_frag_frames
Definition bnxt_hsi.h:3903

rx_port_stats::rx_sch_crc_err_frames
__le64 rx_sch_crc_err_frames
Definition bnxt_hsi.h:3901

rx_port_stats::rx_pfc_ena_frames_pri0
__le64 rx_pfc_ena_frames_pri0
Definition bnxt_hsi.h:3893

rx_port_stats::rx_false_carrier_frames
__le64 rx_false_carrier_frames
Definition bnxt_hsi.h:3875

rx_port_stats::rx_bcast_frames
__le64 rx_bcast_frames
Definition bnxt_hsi.h:3864

rx_port_stats::rx_jbr_frames
__le64 rx_jbr_frames
Definition bnxt_hsi.h:3877

rx_port_stats::rx_good_frames
__le64 rx_good_frames
Definition bnxt_hsi.h:3884

rx_port_stats::rx_65b_127b_frames
__le64 rx_65b_127b_frames
Definition bnxt_hsi.h:3851

rx_port_stats::rx_mcast_frames
__le64 rx_mcast_frames
Definition bnxt_hsi.h:3863

rx_port_stats::rx_512b_1023b_frames
__le64 rx_512b_1023b_frames
Definition bnxt_hsi.h:3854

rx_port_stats::rx_tagged_frames
__le64 rx_tagged_frames
Definition bnxt_hsi.h:3881

rx_port_stats::rx_llfc_msgs_with_crc_err
__le64 rx_llfc_msgs_with_crc_err
Definition bnxt_hsi.h:3908

rx_port_stats::rx_pfc_xon2xoff_frames_pri7
__le64 rx_pfc_xon2xoff_frames_pri7
Definition bnxt_hsi.h:3892

rx_port_stats::rx_ctrl_frames
__le64 rx_ctrl_frames
Definition bnxt_hsi.h:3866

rx_port_stats::rx_eee_lpi_duration
__le64 rx_eee_lpi_duration
Definition bnxt_hsi.h:3905

rx_port_stats::rx_pfc_xon2xoff_frames_pri3
__le64 rx_pfc_xon2xoff_frames_pri3
Definition bnxt_hsi.h:3888

rx_port_stats::rx_64b_frames
__le64 rx_64b_frames
Definition bnxt_hsi.h:3850

rx_port_stats::rx_align_err_frames
__le64 rx_align_err_frames
Definition bnxt_hsi.h:3872

rx_port_stats::rx_256b_511b_frames
__le64 rx_256b_511b_frames
Definition bnxt_hsi.h:3853

rx_port_stats::rx_ovrsz_frames
__le64 rx_ovrsz_frames
Definition bnxt_hsi.h:3876

rx_port_stats::rx_ucast_frames
__le64 rx_ucast_frames
Definition bnxt_hsi.h:3862

rx_port_stats::rx_code_err_frames
__le64 rx_code_err_frames
Definition bnxt_hsi.h:3874

rx_port_stats::rx_unsupported_da_pausepfc_frames
__le64 rx_unsupported_da_pausepfc_frames
Definition bnxt_hsi.h:3870

rx_port_stats::rx_pfc_xon2xoff_frames_pri4
__le64 rx_pfc_xon2xoff_frames_pri4
Definition bnxt_hsi.h:3889

rx_port_stats::rx_oor_len_frames
__le64 rx_oor_len_frames
Definition bnxt_hsi.h:3873

rx_port_stats::rx_double_tagged_frames
__le64 rx_double_tagged_frames
Definition bnxt_hsi.h:3882

rx_port_stats::rx_1519b_2047b_frames
__le64 rx_1519b_2047b_frames
Definition bnxt_hsi.h:3857

rx_port_stats::rx_good_vlan_frames
__le64 rx_good_vlan_frames
Definition bnxt_hsi.h:3856

rx_port_stats::rx_pfc_ena_frames_pri3
__le64 rx_pfc_ena_frames_pri3
Definition bnxt_hsi.h:3896

rx_port_stats::rx_match_crc_frames
__le64 rx_match_crc_frames
Definition bnxt_hsi.h:3879

rx_port_stats::rx_hcfc_msgs_with_crc_err
__le64 rx_hcfc_msgs_with_crc_err
Definition bnxt_hsi.h:3910

rx_port_stats::rx_pfc_ena_frames_pri7
__le64 rx_pfc_ena_frames_pri7
Definition bnxt_hsi.h:3900

rx_port_stats::rx_pfc_xon2xoff_frames_pri5
__le64 rx_pfc_xon2xoff_frames_pri5
Definition bnxt_hsi.h:3890

rx_port_stats::rx_llfc_logical_msgs
__le64 rx_llfc_logical_msgs
Definition bnxt_hsi.h:3907

rx_port_stats::rx_pfc_xon2xoff_frames_pri0
__le64 rx_pfc_xon2xoff_frames_pri0
Definition bnxt_hsi.h:3885

rx_port_stats::rx_fcs_err_frames
__le64 rx_fcs_err_frames
Definition bnxt_hsi.h:3865

rx_port_stats::rx_eee_lpi_events
__le64 rx_eee_lpi_events
Definition bnxt_hsi.h:3904

rx_port_stats::rx_pfc_ena_frames_pri5
__le64 rx_pfc_ena_frames_pri5
Definition bnxt_hsi.h:3898

rx_port_stats::rx_trunc_frames
__le64 rx_trunc_frames
Definition bnxt_hsi.h:3883

rx_port_stats::rx_hcfc_msgs
__le64 rx_hcfc_msgs
Definition bnxt_hsi.h:3909

rx_port_stats::rx_2048b_4095b_frames
__le64 rx_2048b_4095b_frames
Definition bnxt_hsi.h:3858

rx_port_stats::rx_unsupported_opcode_frames
__le64 rx_unsupported_opcode_frames
Definition bnxt_hsi.h:3869

rx_port_stats::rx_wrong_sa_frames
__le64 rx_wrong_sa_frames
Definition bnxt_hsi.h:3871

rx_port_stats::rx_runt_bytes
__le64 rx_runt_bytes
Definition bnxt_hsi.h:3912

rx_port_stats::rx_promiscuous_frames
__le64 rx_promiscuous_frames
Definition bnxt_hsi.h:3880

rx_port_stats::rx_bytes
__le64 rx_bytes
Definition bnxt_hsi.h:3911

rx_port_stats::rx_pfc_xon2xoff_frames_pri1
__le64 rx_pfc_xon2xoff_frames_pri1
Definition bnxt_hsi.h:3886

rx_port_stats::rx_9217b_16383b_frames
__le64 rx_9217b_16383b_frames
Definition bnxt_hsi.h:3860

rx_port_stats::rx_pfc_ena_frames_pri1
__le64 rx_pfc_ena_frames_pri1
Definition bnxt_hsi.h:3894

rx_port_stats::rx_stat_err
__le64 rx_stat_err
Definition bnxt_hsi.h:3915

rx_port_stats::rx_pfc_ena_frames_pri4
__le64 rx_pfc_ena_frames_pri4
Definition bnxt_hsi.h:3897

rx_port_stats::rx_pause_frames
__le64 rx_pause_frames
Definition bnxt_hsi.h:3867

rx_port_stats::rx_128b_255b_frames
__le64 rx_128b_255b_frames
Definition bnxt_hsi.h:3852

rx_port_stats::rx_1024b_1518b_frames
__le64 rx_1024b_1518b_frames
Definition bnxt_hsi.h:3855

rx_port_stats::rx_mtu_err_frames
__le64 rx_mtu_err_frames
Definition bnxt_hsi.h:3878

rx_port_stats::rx_4096b_9216b_frames
__le64 rx_4096b_9216b_frames
Definition bnxt_hsi.h:3859

rx_port_stats::rx_total_frames
__le64 rx_total_frames
Definition bnxt_hsi.h:3861

tlv
Definition bnxt_hsi.h:52

tlv::cmd_discr
__le16 cmd_discr
Definition bnxt_hsi.h:53

tlv::reserved_8b
u8 reserved_8b
Definition bnxt_hsi.h:54

tlv::flags
u8 flags
Definition bnxt_hsi.h:55

tlv::length
__le16 length
Definition bnxt_hsi.h:64

tlv::tlv_type
__le16 tlv_type
Definition bnxt_hsi.h:63

tx_port_stats_ext
Definition bnxt_hsi.h:3944

tx_port_stats_ext::tx_packets_cos7
__le64 tx_packets_cos7
Definition bnxt_hsi.h:3960

tx_port_stats_ext::tx_bytes_cos4
__le64 tx_bytes_cos4
Definition bnxt_hsi.h:3949

tx_port_stats_ext::pfc_pri1_tx_duration_us
__le64 pfc_pri1_tx_duration_us
Definition bnxt_hsi.h:3963

tx_port_stats_ext::tx_packets_cos6
__le64 tx_packets_cos6
Definition bnxt_hsi.h:3959

tx_port_stats_ext::pfc_pri2_tx_duration_us
__le64 pfc_pri2_tx_duration_us
Definition bnxt_hsi.h:3965

tx_port_stats_ext::tx_packets_cos5
__le64 tx_packets_cos5
Definition bnxt_hsi.h:3958

tx_port_stats_ext::pfc_pri4_tx_transitions
__le64 pfc_pri4_tx_transitions
Definition bnxt_hsi.h:3970

tx_port_stats_ext::pfc_pri4_tx_duration_us
__le64 pfc_pri4_tx_duration_us
Definition bnxt_hsi.h:3969

tx_port_stats_ext::pfc_pri7_tx_duration_us
__le64 pfc_pri7_tx_duration_us
Definition bnxt_hsi.h:3975

tx_port_stats_ext::pfc_pri3_tx_transitions
__le64 pfc_pri3_tx_transitions
Definition bnxt_hsi.h:3968

tx_port_stats_ext::tx_bytes_cos7
__le64 tx_bytes_cos7
Definition bnxt_hsi.h:3952

tx_port_stats_ext::tx_packets_cos4
__le64 tx_packets_cos4
Definition bnxt_hsi.h:3957

tx_port_stats_ext::tx_bytes_cos5
__le64 tx_bytes_cos5
Definition bnxt_hsi.h:3950

tx_port_stats_ext::tx_packets_cos3
__le64 tx_packets_cos3
Definition bnxt_hsi.h:3956

tx_port_stats_ext::pfc_pri0_tx_duration_us
__le64 pfc_pri0_tx_duration_us
Definition bnxt_hsi.h:3961

tx_port_stats_ext::pfc_pri2_tx_transitions
__le64 pfc_pri2_tx_transitions
Definition bnxt_hsi.h:3966

tx_port_stats_ext::pfc_pri6_tx_transitions
__le64 pfc_pri6_tx_transitions
Definition bnxt_hsi.h:3974

tx_port_stats_ext::pfc_pri5_tx_duration_us
__le64 pfc_pri5_tx_duration_us
Definition bnxt_hsi.h:3971

tx_port_stats_ext::pfc_pri1_tx_transitions
__le64 pfc_pri1_tx_transitions
Definition bnxt_hsi.h:3964

tx_port_stats_ext::tx_bytes_cos2
__le64 tx_bytes_cos2
Definition bnxt_hsi.h:3947

tx_port_stats_ext::tx_bytes_cos3
__le64 tx_bytes_cos3
Definition bnxt_hsi.h:3948

tx_port_stats_ext::tx_packets_cos0
__le64 tx_packets_cos0
Definition bnxt_hsi.h:3953

tx_port_stats_ext::tx_bytes_cos1
__le64 tx_bytes_cos1
Definition bnxt_hsi.h:3946

tx_port_stats_ext::pfc_pri7_tx_transitions
__le64 pfc_pri7_tx_transitions
Definition bnxt_hsi.h:3976

tx_port_stats_ext::tx_packets_cos1
__le64 tx_packets_cos1
Definition bnxt_hsi.h:3954

tx_port_stats_ext::pfc_pri6_tx_duration_us
__le64 pfc_pri6_tx_duration_us
Definition bnxt_hsi.h:3973

tx_port_stats_ext::tx_bytes_cos6
__le64 tx_bytes_cos6
Definition bnxt_hsi.h:3951

tx_port_stats_ext::tx_packets_cos2
__le64 tx_packets_cos2
Definition bnxt_hsi.h:3955

tx_port_stats_ext::pfc_pri5_tx_transitions
__le64 pfc_pri5_tx_transitions
Definition bnxt_hsi.h:3972

tx_port_stats_ext::tx_bytes_cos0
__le64 tx_bytes_cos0
Definition bnxt_hsi.h:3945

tx_port_stats_ext::pfc_pri0_tx_transitions
__le64 pfc_pri0_tx_transitions
Definition bnxt_hsi.h:3962

tx_port_stats_ext::pfc_pri3_tx_duration_us
__le64 pfc_pri3_tx_duration_us
Definition bnxt_hsi.h:3967

tx_port_stats
Definition bnxt_hsi.h:3794

tx_port_stats::tx_pause_frames
__le64 tx_pause_frames
Definition bnxt_hsi.h:3811

tx_port_stats::tx_pfc_ena_frames_pri3
__le64 tx_pfc_ena_frames_pri3
Definition bnxt_hsi.h:3832

tx_port_stats::tx_pfc_ena_frames_pri4
__le64 tx_pfc_ena_frames_pri4
Definition bnxt_hsi.h:3833

tx_port_stats::tx_65b_127b_frames
__le64 tx_65b_127b_frames
Definition bnxt_hsi.h:3796

tx_port_stats::tx_tagged_frames
__le64 tx_tagged_frames
Definition bnxt_hsi.h:3825

tx_port_stats::tx_stat_discard
__le64 tx_stat_discard
Definition bnxt_hsi.h:3844

tx_port_stats::tx_good_vlan_frames
__le64 tx_good_vlan_frames
Definition bnxt_hsi.h:3801

tx_port_stats::tx_total_collisions
__le64 tx_total_collisions
Definition bnxt_hsi.h:3841

tx_port_stats::tx_fcs_err_frames
__le64 tx_fcs_err_frames
Definition bnxt_hsi.h:3814

tx_port_stats::tx_512b_1023b_frames
__le64 tx_512b_1023b_frames
Definition bnxt_hsi.h:3799

tx_port_stats::tx_2048b_4095b_frames
__le64 tx_2048b_4095b_frames
Definition bnxt_hsi.h:3803

tx_port_stats::tx_err
__le64 tx_err
Definition bnxt_hsi.h:3824

tx_port_stats::tx_single_coll_frames
__le64 tx_single_coll_frames
Definition bnxt_hsi.h:3819

tx_port_stats::tx_single_dfrl_frames
__le64 tx_single_dfrl_frames
Definition bnxt_hsi.h:3817

tx_port_stats::tx_256b_511b_frames
__le64 tx_256b_511b_frames
Definition bnxt_hsi.h:3798

tx_port_stats::tx_ucast_frames
__le64 tx_ucast_frames
Definition bnxt_hsi.h:3808

tx_port_stats::tx_runt_frames
__le64 tx_runt_frames
Definition bnxt_hsi.h:3827

tx_port_stats::tx_hcfc_msgs
__le64 tx_hcfc_msgs
Definition bnxt_hsi.h:3840

tx_port_stats::tx_bytes
__le64 tx_bytes
Definition bnxt_hsi.h:3842

tx_port_stats::tx_frag_frames
__le64 tx_frag_frames
Definition bnxt_hsi.h:3823

tx_port_stats::tx_multi_coll_frames
__le64 tx_multi_coll_frames
Definition bnxt_hsi.h:3820

tx_port_stats::tx_1519b_2047b_frames
__le64 tx_1519b_2047b_frames
Definition bnxt_hsi.h:3802

tx_port_stats::tx_total_frames
__le64 tx_total_frames
Definition bnxt_hsi.h:3807

tx_port_stats::tx_late_coll_frames
__le64 tx_late_coll_frames
Definition bnxt_hsi.h:3821

tx_port_stats::tx_pfc_ena_frames_pri6
__le64 tx_pfc_ena_frames_pri6
Definition bnxt_hsi.h:3835

tx_port_stats::tx_good_frames
__le64 tx_good_frames
Definition bnxt_hsi.h:3806

tx_port_stats::tx_pfc_ena_frames_pri5
__le64 tx_pfc_ena_frames_pri5
Definition bnxt_hsi.h:3834

tx_port_stats::tx_xthol_frames
__le64 tx_xthol_frames
Definition bnxt_hsi.h:3843

tx_port_stats::tx_pfc_ena_frames_pri0
__le64 tx_pfc_ena_frames_pri0
Definition bnxt_hsi.h:3829

tx_port_stats::tx_1024b_1518b_frames
__le64 tx_1024b_1518b_frames
Definition bnxt_hsi.h:3800

tx_port_stats::tx_bcast_frames
__le64 tx_bcast_frames
Definition bnxt_hsi.h:3810

tx_port_stats::tx_multi_dfrl_frames
__le64 tx_multi_dfrl_frames
Definition bnxt_hsi.h:3818

tx_port_stats::tx_64b_frames
__le64 tx_64b_frames
Definition bnxt_hsi.h:3795

tx_port_stats::tx_128b_255b_frames
__le64 tx_128b_255b_frames
Definition bnxt_hsi.h:3797

tx_port_stats::tx_excessive_coll_frames
__le64 tx_excessive_coll_frames
Definition bnxt_hsi.h:3822

tx_port_stats::tx_9217b_16383b_frames
__le64 tx_9217b_16383b_frames
Definition bnxt_hsi.h:3805

tx_port_stats::tx_control_frames
__le64 tx_control_frames
Definition bnxt_hsi.h:3815

tx_port_stats::tx_dbl_tagged_frames
__le64 tx_dbl_tagged_frames
Definition bnxt_hsi.h:3826

tx_port_stats::tx_pfc_frames
__le64 tx_pfc_frames
Definition bnxt_hsi.h:3812

tx_port_stats::tx_pfc_ena_frames_pri7
__le64 tx_pfc_ena_frames_pri7
Definition bnxt_hsi.h:3836

tx_port_stats::tx_stat_error
__le64 tx_stat_error
Definition bnxt_hsi.h:3845

tx_port_stats::tx_fifo_underruns
__le64 tx_fifo_underruns
Definition bnxt_hsi.h:3828

tx_port_stats::tx_pfc_ena_frames_pri2
__le64 tx_pfc_ena_frames_pri2
Definition bnxt_hsi.h:3831

tx_port_stats::tx_oversz_frames
__le64 tx_oversz_frames
Definition bnxt_hsi.h:3816

tx_port_stats::tx_llfc_logical_msgs
__le64 tx_llfc_logical_msgs
Definition bnxt_hsi.h:3839

tx_port_stats::tx_eee_lpi_events
__le64 tx_eee_lpi_events
Definition bnxt_hsi.h:3837

tx_port_stats::tx_jabber_frames
__le64 tx_jabber_frames
Definition bnxt_hsi.h:3813

tx_port_stats::tx_eee_lpi_duration
__le64 tx_eee_lpi_duration
Definition bnxt_hsi.h:3838

tx_port_stats::tx_pfc_ena_frames_pri1
__le64 tx_pfc_ena_frames_pri1
Definition bnxt_hsi.h:3830

tx_port_stats::tx_4096b_9216b_frames
__le64 tx_4096b_9216b_frames
Definition bnxt_hsi.h:3804

tx_port_stats::tx_mcast_frames
__le64 tx_mcast_frames
Definition bnxt_hsi.h:3809