iPXE
bnxt_hsi.h
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1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2019 Broadcom Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  *
10  * DO NOT MODIFY!!! This file is automatically generated.
11  */
12 
13 #ifndef _BNXT_HSI_H_
14 #define _BNXT_HSI_H_
15 
16 /* hwrm_cmd_hdr (size:128b/16B) */
17 struct hwrm_cmd_hdr {
23 };
24 
25 /* hwrm_resp_hdr (size:64b/8B) */
26 struct hwrm_resp_hdr {
31 };
32 
33 #define CMD_DISCR_TLV_ENCAP 0x8000UL
34 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
35 
36 #define TLV_TYPE_HWRM_REQUEST 0x1UL
37 #define TLV_TYPE_HWRM_RESPONSE 0x2UL
38 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
39 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
40 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
41 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL
42 #define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL
43 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
44 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
45 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
46 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL
47 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL
48 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
49 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
50 
51 /* tlv (size:64b/8B) */
52 struct tlv {
56  #define TLV_FLAGS_MORE 0x1UL
57  #define TLV_FLAGS_MORE_LAST 0x0UL
58  #define TLV_FLAGS_MORE_NOT_LAST 0x1UL
59  #define TLV_FLAGS_REQUIRED 0x2UL
60  #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
61  #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
62  #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
65 };
66 
67 /* input (size:128b/16B) */
68 struct input {
74 };
75 
76 /* output (size:64b/8B) */
77 struct output {
82 };
83 
84 /* hwrm_short_input (size:128b/16B) */
88  #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
89  #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
93 };
94 
95 /* cmd_nums (size:64b/8B) */
96 struct cmd_nums {
98  #define HWRM_VER_GET 0x0UL
99  #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
100  #define HWRM_FUNC_BUF_UNRGTR 0xeUL
101  #define HWRM_FUNC_VF_CFG 0xfUL
102  #define HWRM_RESERVED1 0x10UL
103  #define HWRM_FUNC_RESET 0x11UL
104  #define HWRM_FUNC_GETFID 0x12UL
105  #define HWRM_FUNC_VF_ALLOC 0x13UL
106  #define HWRM_FUNC_VF_FREE 0x14UL
107  #define HWRM_FUNC_QCAPS 0x15UL
108  #define HWRM_FUNC_QCFG 0x16UL
109  #define HWRM_FUNC_CFG 0x17UL
110  #define HWRM_FUNC_QSTATS 0x18UL
111  #define HWRM_FUNC_CLR_STATS 0x19UL
112  #define HWRM_FUNC_DRV_UNRGTR 0x1aUL
113  #define HWRM_FUNC_VF_RESC_FREE 0x1bUL
114  #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
115  #define HWRM_FUNC_DRV_RGTR 0x1dUL
116  #define HWRM_FUNC_DRV_QVER 0x1eUL
117  #define HWRM_FUNC_BUF_RGTR 0x1fUL
118  #define HWRM_PORT_PHY_CFG 0x20UL
119  #define HWRM_PORT_MAC_CFG 0x21UL
120  #define HWRM_PORT_TS_QUERY 0x22UL
121  #define HWRM_PORT_QSTATS 0x23UL
122  #define HWRM_PORT_LPBK_QSTATS 0x24UL
123  #define HWRM_PORT_CLR_STATS 0x25UL
124  #define HWRM_PORT_LPBK_CLR_STATS 0x26UL
125  #define HWRM_PORT_PHY_QCFG 0x27UL
126  #define HWRM_PORT_MAC_QCFG 0x28UL
127  #define HWRM_PORT_MAC_PTP_QCFG 0x29UL
128  #define HWRM_PORT_PHY_QCAPS 0x2aUL
129  #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
130  #define HWRM_PORT_PHY_I2C_READ 0x2cUL
131  #define HWRM_PORT_LED_CFG 0x2dUL
132  #define HWRM_PORT_LED_QCFG 0x2eUL
133  #define HWRM_PORT_LED_QCAPS 0x2fUL
134  #define HWRM_QUEUE_QPORTCFG 0x30UL
135  #define HWRM_QUEUE_QCFG 0x31UL
136  #define HWRM_QUEUE_CFG 0x32UL
137  #define HWRM_FUNC_VLAN_CFG 0x33UL
138  #define HWRM_FUNC_VLAN_QCFG 0x34UL
139  #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
140  #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
141  #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
142  #define HWRM_QUEUE_PRI2COS_CFG 0x38UL
143  #define HWRM_QUEUE_COS2BW_QCFG 0x39UL
144  #define HWRM_QUEUE_COS2BW_CFG 0x3aUL
145  #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
146  #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
147  #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
148  #define HWRM_VNIC_ALLOC 0x40UL
149  #define HWRM_VNIC_FREE 0x41UL
150  #define HWRM_VNIC_CFG 0x42UL
151  #define HWRM_VNIC_QCFG 0x43UL
152  #define HWRM_VNIC_TPA_CFG 0x44UL
153  #define HWRM_VNIC_TPA_QCFG 0x45UL
154  #define HWRM_VNIC_RSS_CFG 0x46UL
155  #define HWRM_VNIC_RSS_QCFG 0x47UL
156  #define HWRM_VNIC_PLCMODES_CFG 0x48UL
157  #define HWRM_VNIC_PLCMODES_QCFG 0x49UL
158  #define HWRM_VNIC_QCAPS 0x4aUL
159  #define HWRM_RING_ALLOC 0x50UL
160  #define HWRM_RING_FREE 0x51UL
161  #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
162  #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
163  #define HWRM_RING_AGGINT_QCAPS 0x54UL
164  #define HWRM_RING_RESET 0x5eUL
165  #define HWRM_RING_GRP_ALLOC 0x60UL
166  #define HWRM_RING_GRP_FREE 0x61UL
167  #define HWRM_RESERVED5 0x64UL
168  #define HWRM_RESERVED6 0x65UL
169  #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
170  #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
171  #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
172  #define HWRM_CFA_L2_FILTER_FREE 0x91UL
173  #define HWRM_CFA_L2_FILTER_CFG 0x92UL
174  #define HWRM_CFA_L2_SET_RX_MASK 0x93UL
175  #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
176  #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
177  #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
178  #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
179  #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
180  #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
181  #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
182  #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
183  #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
184  #define HWRM_CFA_EM_FLOW_FREE 0x9dUL
185  #define HWRM_CFA_EM_FLOW_CFG 0x9eUL
186  #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
187  #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
188  #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
189  #define HWRM_STAT_CTX_ENG_QUERY 0xafUL
190  #define HWRM_STAT_CTX_ALLOC 0xb0UL
191  #define HWRM_STAT_CTX_FREE 0xb1UL
192  #define HWRM_STAT_CTX_QUERY 0xb2UL
193  #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
194  #define HWRM_PORT_QSTATS_EXT 0xb4UL
195  #define HWRM_FW_RESET 0xc0UL
196  #define HWRM_FW_QSTATUS 0xc1UL
197  #define HWRM_FW_HEALTH_CHECK 0xc2UL
198  #define HWRM_FW_SYNC 0xc3UL
199  #define HWRM_FW_SET_TIME 0xc8UL
200  #define HWRM_FW_GET_TIME 0xc9UL
201  #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
202  #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
203  #define HWRM_FW_IPC_MAILBOX 0xccUL
204  #define HWRM_EXEC_FWD_RESP 0xd0UL
205  #define HWRM_REJECT_FWD_RESP 0xd1UL
206  #define HWRM_FWD_RESP 0xd2UL
207  #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
208  #define HWRM_OEM_CMD 0xd4UL
209  #define HWRM_TEMP_MONITOR_QUERY 0xe0UL
210  #define HWRM_WOL_FILTER_ALLOC 0xf0UL
211  #define HWRM_WOL_FILTER_FREE 0xf1UL
212  #define HWRM_WOL_FILTER_QCFG 0xf2UL
213  #define HWRM_WOL_REASON_QCFG 0xf3UL
214  #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
215  #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
216  #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
217  #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
218  #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
219  #define HWRM_CFA_VFR_ALLOC 0xfdUL
220  #define HWRM_CFA_VFR_FREE 0xfeUL
221  #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
222  #define HWRM_CFA_VF_PAIR_FREE 0x101UL
223  #define HWRM_CFA_VF_PAIR_INFO 0x102UL
224  #define HWRM_CFA_FLOW_ALLOC 0x103UL
225  #define HWRM_CFA_FLOW_FREE 0x104UL
226  #define HWRM_CFA_FLOW_FLUSH 0x105UL
227  #define HWRM_CFA_FLOW_STATS 0x106UL
228  #define HWRM_CFA_FLOW_INFO 0x107UL
229  #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
230  #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
231  #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
232  #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
233  #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
234  #define HWRM_CFA_PAIR_ALLOC 0x10dUL
235  #define HWRM_CFA_PAIR_FREE 0x10eUL
236  #define HWRM_CFA_PAIR_INFO 0x10fUL
237  #define HWRM_FW_IPC_MSG 0x110UL
238  #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
239  #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
240  #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
241  #define HWRM_CFA_FLOW_AGING_CFG 0x114UL
242  #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
243  #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
244  #define HWRM_ENGINE_CKV_HELLO 0x12dUL
245  #define HWRM_ENGINE_CKV_STATUS 0x12eUL
246  #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
247  #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
248  #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
249  #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
250  #define HWRM_ENGINE_CKV_FLUSH 0x133UL
251  #define HWRM_ENGINE_CKV_RNG_GET 0x134UL
252  #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
253  #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
254  #define HWRM_ENGINE_QG_QUERY 0x13dUL
255  #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
256  #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
257  #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
258  #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
259  #define HWRM_ENGINE_QG_METER_QUERY 0x142UL
260  #define HWRM_ENGINE_QG_METER_BIND 0x143UL
261  #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
262  #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
263  #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
264  #define HWRM_ENGINE_SG_QUERY 0x147UL
265  #define HWRM_ENGINE_SG_METER_QUERY 0x148UL
266  #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
267  #define HWRM_ENGINE_SG_QG_BIND 0x14aUL
268  #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
269  #define HWRM_ENGINE_CONFIG_QUERY 0x154UL
270  #define HWRM_ENGINE_STATS_CONFIG 0x155UL
271  #define HWRM_ENGINE_STATS_CLEAR 0x156UL
272  #define HWRM_ENGINE_STATS_QUERY 0x157UL
273  #define HWRM_ENGINE_RQ_ALLOC 0x15eUL
274  #define HWRM_ENGINE_RQ_FREE 0x15fUL
275  #define HWRM_ENGINE_CQ_ALLOC 0x160UL
276  #define HWRM_ENGINE_CQ_FREE 0x161UL
277  #define HWRM_ENGINE_NQ_ALLOC 0x162UL
278  #define HWRM_ENGINE_NQ_FREE 0x163UL
279  #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
280  #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
281  #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
282  #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
283  #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
284  #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
285  #define HWRM_FUNC_VF_BW_CFG 0x195UL
286  #define HWRM_FUNC_VF_BW_QCFG 0x196UL
287  #define HWRM_SELFTEST_QLIST 0x200UL
288  #define HWRM_SELFTEST_EXEC 0x201UL
289  #define HWRM_SELFTEST_IRQ 0x202UL
290  #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
291  #define HWRM_PCIE_QSTATS 0x204UL
292  #define HWRM_DBG_READ_DIRECT 0xff10UL
293  #define HWRM_DBG_READ_INDIRECT 0xff11UL
294  #define HWRM_DBG_WRITE_DIRECT 0xff12UL
295  #define HWRM_DBG_WRITE_INDIRECT 0xff13UL
296  #define HWRM_DBG_DUMP 0xff14UL
297  #define HWRM_DBG_ERASE_NVM 0xff15UL
298  #define HWRM_DBG_CFG 0xff16UL
299  #define HWRM_DBG_COREDUMP_LIST 0xff17UL
300  #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
301  #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
302  #define HWRM_DBG_FW_CLI 0xff1aUL
303  #define HWRM_DBG_I2C_CMD 0xff1bUL
304  #define HWRM_DBG_RING_INFO_GET 0xff1cUL
305  #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
306  #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
307  #define HWRM_NVM_FLUSH 0xfff0UL
308  #define HWRM_NVM_GET_VARIABLE 0xfff1UL
309  #define HWRM_NVM_SET_VARIABLE 0xfff2UL
310  #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
311  #define HWRM_NVM_MODIFY 0xfff4UL
312  #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
313  #define HWRM_NVM_GET_DEV_INFO 0xfff6UL
314  #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
315  #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
316  #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
317  #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
318  #define HWRM_NVM_GET_DIR_INFO 0xfffbUL
319  #define HWRM_NVM_RAW_DUMP 0xfffcUL
320  #define HWRM_NVM_READ 0xfffdUL
321  #define HWRM_NVM_WRITE 0xfffeUL
322  #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
323  #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
325 };
326 
327 /* ret_codes (size:64b/8B) */
328 struct ret_codes {
330  #define HWRM_ERR_CODE_SUCCESS 0x0UL
331  #define HWRM_ERR_CODE_FAIL 0x1UL
332  #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
333  #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
334  #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
335  #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
336  #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
337  #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
338  #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
339  #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
340  #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
341  #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
342  #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
343  #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
344  #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
345  #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
346  #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
348 };
349 
350 /* hwrm_err_output (size:128b/16B) */
360 };
361 
362 #define HWRM_NA_SIGNATURE ((__le32)(-1))
363 #define HWRM_MAX_REQ_LEN 128
364 #define HWRM_MAX_RESP_LEN 280
365 #define HW_HASH_INDEX_SIZE 0x80
366 #define HW_HASH_KEY_SIZE 40
367 #define HWRM_RESP_VALID_KEY 1
368 #define HWRM_VERSION_MAJOR 1
369 #define HWRM_VERSION_MINOR 10
370 #define HWRM_VERSION_UPDATE 0
371 #define HWRM_VERSION_RSVD 18
372 #define HWRM_VERSION_STR "1.10.0.18"
373 
374 /* hwrm_ver_get_input (size:192b/24B) */
385 };
386 
387 /* hwrm_ver_get_output (size:1408b/176B) */
410  #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
411  #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
412  #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
413  #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
414  #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
415  #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
416  #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
417  #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
418  #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
419  #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
424  char hwrm_fw_name[16];
425  char mgmt_fw_name[16];
426  char netctrl_fw_name[16];
428  char roce_fw_name[16];
434  #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
435  #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
436  #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
437  #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
442  #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
443  #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
469 };
470 
471 /* eject_cmpl (size:128b/16B) */
472 struct eject_cmpl {
474  #define EJECT_CMPL_TYPE_MASK 0x3fUL
475  #define EJECT_CMPL_TYPE_SFT 0
476  #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
477  #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
478  #define EJECT_CMPL_FLAGS_MASK 0xffc0UL
479  #define EJECT_CMPL_FLAGS_SFT 6
480  #define EJECT_CMPL_FLAGS_ERROR 0x40UL
484  #define EJECT_CMPL_V 0x1UL
485  #define EJECT_CMPL_ERRORS_MASK 0xfffeUL
486  #define EJECT_CMPL_ERRORS_SFT 1
487  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
488  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
489  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
490  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
491  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
492  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
493  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
496 };
497 
498 /* hwrm_cmpl (size:128b/16B) */
499 struct hwrm_cmpl {
501  #define CMPL_TYPE_MASK 0x3fUL
502  #define CMPL_TYPE_SFT 0
503  #define CMPL_TYPE_HWRM_DONE 0x20UL
504  #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
508  #define CMPL_V 0x1UL
510 };
511 
512 /* hwrm_fwd_req_cmpl (size:128b/16B) */
515  #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
516  #define FWD_REQ_CMPL_TYPE_SFT 0
517  #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
518  #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
519  #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
520  #define FWD_REQ_CMPL_REQ_LEN_SFT 6
524  #define FWD_REQ_CMPL_V 0x1UL
525  #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
526  #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
527 };
528 
529 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
532  #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
533  #define FWD_RESP_CMPL_TYPE_SFT 0
534  #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
535  #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
540  #define FWD_RESP_CMPL_V 0x1UL
541  #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
542  #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
543 };
544 
545 /* hwrm_async_event_cmpl (size:128b/16B) */
548  #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
549  #define ASYNC_EVENT_CMPL_TYPE_SFT 0
550  #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
551  #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
553  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
554  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
555  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
556  #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
557  #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
558  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
559  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
560  #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
561  #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
562  #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
563  #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
564  #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
565  #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
566  #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
567  #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
568  #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
569  #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
570  #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
571  #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
572  #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
573  #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
574  #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
575  #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
576  #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
577  #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
580  #define ASYNC_EVENT_CMPL_V 0x1UL
581  #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
582  #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
586 };
587 
588 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
591  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
592  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
593  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
594  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
596  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
597  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
600  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
601  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
602  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
606  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
607  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
608  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
609  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
610  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
611  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
612  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
613  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
614  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
615  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
616 };
617 
618 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
621  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL
622  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
623  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
624  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
626  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL
627  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
630  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL
631  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL
632  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
636  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
637  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
638 };
639 
640 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
643  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL
644  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
645  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
646  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
648  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
649  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
652  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL
653  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
654  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
658  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
659  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
660  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
661  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
662  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
663  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
664  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
665  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
666  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
667  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
668  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
669  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
670  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1)
671  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
672  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
673  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
674 };
675 
676 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
679  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL
680  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
681  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
682  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
684  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
685  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
687  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL
688  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL
689  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL
691  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL
692  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
693  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
697  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
698  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
699  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL
700  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16
701  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16)
702  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
703  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL
704  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24
705  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24)
706  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
707 };
708 
709 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
712  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
713  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
714  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
715  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
717  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
718  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
721  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
722  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
723  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
727  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
728  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
729  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
730  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
731  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
732  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
733  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
734  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
735  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
736 };
737 
738 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
741  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL
742  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
743  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
744  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
746  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
747  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
750  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL
751  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
752  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
756  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
757  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
758 };
759 
760 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
763  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
764  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
765  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
766  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
768  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
769  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
772  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
773  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
774  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
778  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
779  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
780  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
781  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
782 };
783 
784 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
787  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK 0x3fUL
788  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT 0
789  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
790  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
792  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
793  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
796  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V 0x1UL
797  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK 0xfeUL
798  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
802  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
803  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
804  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE 0x10000UL
805  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE 0x20000UL
806  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE 0x40000UL
807 };
808 
809 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
812  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
813  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
814  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
815  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
817  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
818  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
821  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
822  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
823  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
827  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
828  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
829  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
830  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
831  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
832  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
833  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
834  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
835  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
836  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
837  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
838  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
839  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
840 };
841 
842 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
845  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL
846  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
847  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
848  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
850  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
851  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
854  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL
855  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
856  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
860  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
861  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
862 };
863 
864 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
867  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL
868  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
869  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
870  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
872  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
873  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
876  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL
877  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL
878  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
882  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
883  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
884 };
885 
886 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
889  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL
890  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0
891  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL
892  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
894  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
895  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
898  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL
899  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL
900  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
904  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
905  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0
906 };
907 
908 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
911  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL
912  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
913  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
914  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
916  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
917  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
920  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL
921  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
922  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
926  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
927  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
928  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL
929  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
930 };
931 
932 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
935  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL
936  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
937  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
938  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
940  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL
941  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
944  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL
945  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL
946  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
950  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
951  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
952  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL
953  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
954 };
955 
956 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
959  #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL
960  #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
961  #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
962  #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
964  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL
965  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
968  #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL
969  #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL
970  #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
974  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
975  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
976  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK 0xff0000UL
977  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
978 };
979 
980 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
983  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
984  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
985  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
986  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
988  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
989  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
992  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL
993  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
994  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
998  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
999  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
1000 };
1001 
1002 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
1005  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL
1006  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
1007  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1008  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
1010  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
1011  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
1014  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL
1015  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
1016  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
1020  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL
1021 };
1022 
1023 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
1026  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
1027  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
1028  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1029  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
1031  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
1032  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
1035  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
1036  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
1037  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
1041  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
1042  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
1043  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
1044  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
1045  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
1046 };
1047 
1048 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
1051  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK 0x3fUL
1052  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
1053  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1054  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
1055  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK 0xffc0UL
1056  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
1058  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
1059  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
1062  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V 0x1UL
1063  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK 0xfeUL
1064  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
1068  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK 0x3UL
1069  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT 0
1070  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC 0x1UL
1071  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC 0x2UL
1072  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
1073  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK 0x1cUL
1074  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT 2
1075  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK 0x1fffe0UL
1076  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT 5
1077 };
1078 
1079 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
1082  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
1083  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
1084  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1085  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
1086  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
1087  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
1089  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
1090  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
1093  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
1094  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
1095  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
1099  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
1100  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
1101  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
1102  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
1103  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
1104  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
1105  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
1106  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
1107  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
1108 };
1109 
1110 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
1113  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
1114  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
1115  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1116  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
1118  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
1119  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
1122  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
1123  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
1124  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
1128  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
1129  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
1130  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
1131  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
1132  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
1133  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
1134 };
1135 
1136 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
1139  #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
1140  #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
1141  #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1142  #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
1144  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
1145  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
1147  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
1148  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
1149  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL
1150  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL
1151  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL
1152  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
1154  #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
1155  #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
1156  #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
1160  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
1161 };
1162 
1163 /* hwrm_func_reset_input (size:192b/24B) */
1171  #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
1174  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
1175  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
1176  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
1177  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
1178  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
1180 };
1181 
1182 /* hwrm_func_reset_output (size:128b/16B) */
1190 };
1191 
1192 /* hwrm_func_getfid_input (size:192b/24B) */
1200  #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
1203 };
1204 
1205 /* hwrm_func_getfid_output (size:128b/16B) */
1214 };
1215 
1216 /* hwrm_func_vf_alloc_input (size:192b/24B) */
1224  #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
1227 };
1228 
1229 /* hwrm_func_vf_alloc_output (size:128b/16B) */
1238 };
1239 
1240 /* hwrm_func_vf_free_input (size:192b/24B) */
1248  #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
1251 };
1252 
1253 /* hwrm_func_vf_free_output (size:128b/16B) */
1261 };
1262 
1263 /* hwrm_func_vf_cfg_input (size:448b/56B) */
1271  #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
1272  #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
1273  #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
1274  #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
1275  #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
1276  #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
1277  #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
1278  #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
1279  #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
1280  #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
1281  #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
1282  #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
1288  #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
1289  #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
1290  #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
1291  #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
1292  #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
1293  #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
1294  #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
1295  #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
1305 };
1306 
1307 /* hwrm_func_vf_cfg_output (size:128b/16B) */
1315 };
1316 
1317 /* hwrm_func_qcaps_input (size:192b/24B) */
1326 };
1327 
1328 /* hwrm_func_qcaps_output (size:640b/80B) */
1337  #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1338  #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1339  #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1340  #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
1341  #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
1342  #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1343  #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1344  #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
1345  #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
1346  #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
1347  #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
1348  #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
1349  #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
1350  #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
1351  #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
1352  #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
1353  #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
1354  #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
1355  #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
1356  #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
1357  #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1358  #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1359  #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1382 };
1383 
1384 /* hwrm_func_qcfg_input (size:192b/24B) */
1393 };
1394 
1395 /* hwrm_func_qcfg_output (size:704b/88B) */
1405  #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1406  #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1407  #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
1408  #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
1409  #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
1410  #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
1411  #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1424  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
1425  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
1426  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1427  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1428  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1429  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1430  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1432  #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1433  #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1437  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1438  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
1439  #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
1440  #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
1441  #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
1442  #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1443  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1444  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
1445  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1446  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1447  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1448  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1449  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1450  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1451  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1453  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1454  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
1455  #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
1456  #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
1457  #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
1458  #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1459  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1460  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
1461  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1462  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1463  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1464  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1465  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1466  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1467  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1469  #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1470  #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
1471  #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
1472  #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
1474  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1475  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
1476  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1477  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1478  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1479  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1480  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
1481  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1482  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1483  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1484  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1485  #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
1486  #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
1499 };
1500 
1501 /* hwrm_func_cfg_input (size:704b/88B) */
1511  #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1512  #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
1513  #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
1514  #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
1515  #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
1516  #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
1517  #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
1518  #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
1519  #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
1520  #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
1521  #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
1522  #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
1523  #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
1524  #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1525  #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1526  #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1527  #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
1528  #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
1530  #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1531  #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1532  #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1533  #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1534  #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1535  #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1536  #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1537  #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1538  #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1539  #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1540  #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1541  #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1542  #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1543  #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1544  #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1545  #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1546  #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1547  #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1548  #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1549  #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1550  #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1551  #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1552  #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
1567  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1568  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
1569  #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
1570  #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
1571  #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
1572  #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1573  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1574  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
1575  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1576  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1577  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1578  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1579  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1580  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1581  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1583  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1584  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
1585  #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
1586  #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
1587  #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
1588  #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1589  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1590  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
1591  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1592  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1593  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1594  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1595  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1596  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1597  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1600  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
1601  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
1602  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
1603  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1604  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1607  #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1608  #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
1609  #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
1610  #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
1612  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1613  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
1614  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1615  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1616  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1617  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1618  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
1619  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1620  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1621  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1622  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1623  #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
1624  #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
1626 };
1627 
1628 /* hwrm_func_cfg_output (size:128b/16B) */
1636 };
1637 
1638 /* hwrm_func_qstats_input (size:192b/24B) */
1647 };
1648 
1649 /* hwrm_func_qstats_output (size:1408b/176B) */
1677 };
1678 
1679 /* hwrm_func_clr_stats_input (size:192b/24B) */
1688 };
1689 
1690 /* hwrm_func_clr_stats_output (size:128b/16B) */
1698 };
1699 
1700 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
1709 };
1710 
1711 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
1719 };
1720 
1721 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
1729  #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1730  #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1731  #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
1732  #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
1733  #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
1735  #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1736  #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1737  #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1738  #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1739  #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1741  #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
1742  #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
1743  #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
1744  #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
1745  #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
1746  #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
1747  #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
1748  #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
1749  #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
1750  #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
1751  #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
1752  #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
1765 };
1766 
1767 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
1774  #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
1777 };
1778 
1779 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
1787  #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1789 };
1790 
1791 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
1799 };
1800 
1801 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
1809  #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1810  #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1814  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
1815  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
1816  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
1817  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
1818  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
1819  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
1820  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
1821  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
1837 };
1838 
1839 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
1847 };
1848 
1849 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
1857  #define FUNC_BUF_UNRGTR_REQ_ENABLES_VF_ID 0x1UL
1860 };
1861 
1862 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
1870 };
1871 
1872 /* hwrm_func_drv_qver_input (size:192b/24B) */
1882 };
1883 
1884 /* hwrm_func_drv_qver_output (size:256b/32B) */
1891  #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
1892  #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
1893  #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
1894  #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
1895  #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
1896  #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
1897  #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
1898  #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
1899  #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
1900  #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
1901  #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
1902  #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
1913 };
1914 
1915 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
1924 };
1925 
1926 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
1935  #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
1936  #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
1937  #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
1938  #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
1957  #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
1960 };
1961 
1962 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
1988  #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
1990 };
1991 
1992 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
2008 };
2009 
2010 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
2017 };
2018 
2019 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
2050 };
2051 
2052 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
2060  #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
2062  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
2063  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
2064  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
2065  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
2066  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
2067  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
2068  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
2069  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
2070  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
2071  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
2072  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
2073  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
2074  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
2075  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
2076  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
2077  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
2079  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
2080  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
2081  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
2082  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
2083  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
2084  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
2085  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
2086  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
2087  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
2088  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
2089  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
2090  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
2091  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
2092  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
2093  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
2095  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
2096  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
2097  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
2098  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
2099  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
2100  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
2101  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
2102  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
2103  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
2104  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
2105  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
2106  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
2107  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
2108  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
2109  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
2111  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
2112  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
2113  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
2114  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
2115  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
2116  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
2117  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
2118  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
2119  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
2120  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
2121  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
2122  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
2123  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
2124  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
2125  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
2127  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
2128  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
2129  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
2130  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
2131  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
2132  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
2133  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
2134  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
2135  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
2136  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
2137  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
2138  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
2139  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
2140  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
2141  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
2143  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
2144  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
2145  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
2146  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
2147  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
2148  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
2149  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
2150  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
2151  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
2152  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
2153  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
2154  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
2155  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
2156  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
2157  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
2159  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
2160  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
2161  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
2162  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
2163  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
2164  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
2165  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
2166  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
2167  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
2168  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
2169  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
2170  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
2171  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
2172  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
2173  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
2175  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
2176  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
2177  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
2178  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
2179  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
2180  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
2181  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
2182  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
2183  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
2184  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
2185  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
2186  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
2187  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
2188  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
2189  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
2191  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
2192  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
2193  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
2194  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
2195  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
2196  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
2197  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
2198  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
2199  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
2200  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
2201  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
2202  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
2203  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
2204  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
2205  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
2207  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
2208  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
2209  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
2210  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
2211  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
2212  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
2213  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
2214  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
2215  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
2216  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
2217  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
2218  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
2219  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
2220  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
2221  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
2223  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
2224  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
2225  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
2226  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
2227  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
2228  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
2229  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
2230  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
2231  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
2232  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
2233  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
2234  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
2235  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
2236  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
2237  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
2239  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
2240  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
2241  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
2242  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
2243  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
2244  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
2245  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
2246  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
2247  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
2248  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
2249  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
2250  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
2251  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
2252  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
2253  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2255  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
2256  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
2257  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
2258  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
2259  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
2260  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2261  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
2262  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
2263  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
2264  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
2265  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
2266  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
2267  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
2268  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
2269  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2271  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
2272  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
2273  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
2274  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
2275  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
2276  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2277  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
2278  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
2279  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
2280  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
2281  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
2282  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
2283  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
2284  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
2285  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2287  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
2288  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
2289  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
2290  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
2291  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
2292  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2293  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
2294  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
2295  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
2296  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
2297  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
2298  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
2299  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
2300  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
2301  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2303  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
2304  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
2305  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
2306  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
2307  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
2308  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2309  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
2310  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
2311  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
2312  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
2313  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
2314  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
2315  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
2316  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
2317  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2319  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
2320  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
2321  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
2322  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
2323  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
2324  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2325  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
2326  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
2327  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
2328  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
2329  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
2330  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
2331  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
2332  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
2333  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
2379 };
2380 
2381 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
2389 };
2390 
2391 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
2398 };
2399 
2400 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
2407  #define FUNC_BACKING_STORE_QCFG_RESP_FLAGS_PREBOOT_MODE 0x1UL
2409  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_QP 0x1UL
2410  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_SRQ 0x2UL
2411  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_CQ 0x4UL
2412  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_VNIC 0x8UL
2413  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_STAT 0x10UL
2414  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_SP 0x20UL
2415  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING0 0x40UL
2416  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING1 0x80UL
2417  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING2 0x100UL
2418  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING3 0x200UL
2419  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING4 0x400UL
2420  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING5 0x800UL
2421  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING6 0x1000UL
2422  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING7 0x2000UL
2423  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_MRAV 0x4000UL
2424  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TIM 0x8000UL
2426  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_MASK 0xfUL
2427  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_SFT 0
2428  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_0 0x0UL
2429  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_1 0x1UL
2430  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2 0x2UL
2431  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2
2432  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_MASK 0xf0UL
2433  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_SFT 4
2434  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_4K (0x0UL << 4)
2435  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8K (0x1UL << 4)
2436  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_64K (0x2UL << 4)
2437  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_2M (0x3UL << 4)
2438  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8M (0x4UL << 4)
2439  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G (0x5UL << 4)
2440  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G
2442  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_MASK 0xfUL
2443  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_SFT 0
2444  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_0 0x0UL
2445  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_1 0x1UL
2446  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2 0x2UL
2447  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2
2448  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_MASK 0xf0UL
2449  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_SFT 4
2450  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
2451  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
2452  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
2453  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
2454  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
2455  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
2456  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G
2458  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_MASK 0xfUL
2459  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_SFT 0
2460  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_0 0x0UL
2461  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_1 0x1UL
2462  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2 0x2UL
2463  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2
2464  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_MASK 0xf0UL
2465  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_SFT 4
2466  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_4K (0x0UL << 4)
2467  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8K (0x1UL << 4)
2468  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_64K (0x2UL << 4)
2469  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_2M (0x3UL << 4)
2470  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8M (0x4UL << 4)
2471  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G (0x5UL << 4)
2472  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G
2474  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_MASK 0xfUL
2475  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_SFT 0
2476  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_0 0x0UL
2477  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_1 0x1UL
2478  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2 0x2UL
2479  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2
2480  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_MASK 0xf0UL
2481  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_SFT 4
2482  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
2483  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
2484  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
2485  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
2486  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
2487  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
2488  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G
2490  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_MASK 0xfUL
2491  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_SFT 0
2492  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_0 0x0UL
2493  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_1 0x1UL
2494  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2 0x2UL
2495  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2
2496  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_MASK 0xf0UL
2497  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_SFT 4
2498  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_4K (0x0UL << 4)
2499  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8K (0x1UL << 4)
2500  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_64K (0x2UL << 4)
2501  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_2M (0x3UL << 4)
2502  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8M (0x4UL << 4)
2503  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G (0x5UL << 4)
2504  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G
2506  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_MASK 0xfUL
2507  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_SFT 0
2508  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_0 0x0UL
2509  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_1 0x1UL
2510  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2 0x2UL
2511  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2
2512  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_MASK 0xf0UL
2513  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_SFT 4
2514  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
2515  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
2516  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
2517  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
2518  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
2519  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
2520  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G
2522  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_MASK 0xfUL
2523  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_SFT 0
2524  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_0 0x0UL
2525  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_1 0x1UL
2526  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2 0x2UL
2527  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2
2528  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_MASK 0xf0UL
2529  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_SFT 4
2530  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
2531  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
2532  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
2533  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
2534  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
2535  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
2536  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G
2538  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_MASK 0xfUL
2539  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_SFT 0
2540  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_0 0x0UL
2541  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_1 0x1UL
2542  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2 0x2UL
2543  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2
2544  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_MASK 0xf0UL
2545  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_SFT 4
2546  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
2547  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
2548  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
2549  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
2550  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
2551  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
2552  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G
2554  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_MASK 0xfUL
2555  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_SFT 0
2556  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_0 0x0UL
2557  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_1 0x1UL
2558  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2 0x2UL
2559  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2
2560  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_MASK 0xf0UL
2561  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_SFT 4
2562  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
2563  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
2564  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
2565  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
2566  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
2567  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
2568  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G
2570  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_MASK 0xfUL
2571  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_SFT 0
2572  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_0 0x0UL
2573  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_1 0x1UL
2574  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2 0x2UL
2575  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2
2576  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_MASK 0xf0UL
2577  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_SFT 4
2578  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
2579  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
2580  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
2581  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
2582  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
2583  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
2584  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G
2586  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_MASK 0xfUL
2587  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_SFT 0
2588  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_0 0x0UL
2589  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_1 0x1UL
2590  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2 0x2UL
2591  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2
2592  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_MASK 0xf0UL
2593  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_SFT 4
2594  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
2595  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
2596  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
2597  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
2598  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
2599  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
2600  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G
2602  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_MASK 0xfUL
2603  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_SFT 0
2604  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_0 0x0UL
2605  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_1 0x1UL
2606  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2 0x2UL
2607  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2
2608  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_MASK 0xf0UL
2609  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_SFT 4
2610  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
2611  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
2612  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
2613  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
2614  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
2615  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
2616  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G
2618  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_MASK 0xfUL
2619  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_SFT 0
2620  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_0 0x0UL
2621  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_1 0x1UL
2622  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2 0x2UL
2623  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2
2624  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_MASK 0xf0UL
2625  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_SFT 4
2626  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
2627  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
2628  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
2629  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
2630  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
2631  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
2632  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G
2634  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_MASK 0xfUL
2635  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_SFT 0
2636  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_0 0x0UL
2637  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_1 0x1UL
2638  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2 0x2UL
2639  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2
2640  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_MASK 0xf0UL
2641  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_SFT 4
2642  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
2643  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
2644  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
2645  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
2646  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
2647  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
2648  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G
2650  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_MASK 0xfUL
2651  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_SFT 0
2652  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_0 0x0UL
2653  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_1 0x1UL
2654  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2 0x2UL
2655  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2
2656  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_MASK 0xf0UL
2657  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_SFT 4
2658  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
2659  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
2660  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
2661  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
2662  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
2663  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
2664  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G
2666  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_MASK 0xfUL
2667  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_SFT 0
2668  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_0 0x0UL
2669  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_1 0x1UL
2670  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2 0x2UL
2671  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2
2672  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_MASK 0xf0UL
2673  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_SFT 4
2674  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_4K (0x0UL << 4)
2675  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8K (0x1UL << 4)
2676  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_64K (0x2UL << 4)
2677  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_2M (0x3UL << 4)
2678  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8M (0x4UL << 4)
2679  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G (0x5UL << 4)
2680  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G
2720 };
2721 
2722 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
2731 };
2732 
2733 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
2752 };
2753 
2754 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
2764  #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL
2765  #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL
2766  #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL
2767  #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL
2768  #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL
2769  #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL
2781 };
2782 
2783 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
2791 };
2792 
2793 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
2804 };
2805 
2806 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
2815 };
2816 
2817 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
2827  #define FUNC_VF_BW_CFG_REQ_VFN_VFID_MASK 0xfffUL
2828  #define FUNC_VF_BW_CFG_REQ_VFN_VFID_SFT 0
2829  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_MASK 0xf000UL
2830  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_SFT 12
2831  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_0 (0x0UL << 12)
2832  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_6_66 (0x1UL << 12)
2833  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_13_33 (0x2UL << 12)
2834  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_20 (0x3UL << 12)
2835  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_26_66 (0x4UL << 12)
2836  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_33_33 (0x5UL << 12)
2837  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_40 (0x6UL << 12)
2838  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_46_66 (0x7UL << 12)
2839  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_53_33 (0x8UL << 12)
2840  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_60 (0x9UL << 12)
2841  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_66_66 (0xaUL << 12)
2842  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_73_33 (0xbUL << 12)
2843  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_80 (0xcUL << 12)
2844  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_86_66 (0xdUL << 12)
2845  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_93_33 (0xeUL << 12)
2846  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100 (0xfUL << 12)
2847  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_LAST FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100
2848 };
2849 
2850 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
2858 };
2859 
2860 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
2870  #define FUNC_VF_BW_QCFG_REQ_VFN_VFID_MASK 0xfffUL
2871  #define FUNC_VF_BW_QCFG_REQ_VFN_VFID_SFT 0
2872 };
2873 
2874 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
2883  #define FUNC_VF_BW_QCFG_RESP_VFN_VFID_MASK 0xfffUL
2884  #define FUNC_VF_BW_QCFG_RESP_VFN_VFID_SFT 0
2885  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_MASK 0xf000UL
2886  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_SFT 12
2887  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_0 (0x0UL << 12)
2888  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_6_66 (0x1UL << 12)
2889  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_13_33 (0x2UL << 12)
2890  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_20 (0x3UL << 12)
2891  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_26_66 (0x4UL << 12)
2892  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_33_33 (0x5UL << 12)
2893  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_40 (0x6UL << 12)
2894  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_46_66 (0x7UL << 12)
2895  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_53_33 (0x8UL << 12)
2896  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_60 (0x9UL << 12)
2897  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_66_66 (0xaUL << 12)
2898  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_73_33 (0xbUL << 12)
2899  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_80 (0xcUL << 12)
2900  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_86_66 (0xdUL << 12)
2901  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_93_33 (0xeUL << 12)
2902  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100 (0xfUL << 12)
2903  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_LAST FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100
2906 };
2907 
2908 /* hwrm_func_drv_if_change_input (size:192b/24B) */
2916  #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
2918 };
2919 
2920 /* hwrm_func_drv_if_change_output (size:128b/16B) */
2927  #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
2930 };
2931 
2932 /* hwrm_port_phy_cfg_input (size:512b/64B) */
2940  #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
2941  #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
2942  #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
2943  #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
2944  #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
2945  #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
2946  #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
2947  #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
2948  #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
2949  #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
2950  #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
2951  #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
2952  #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
2953  #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
2954  #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
2955  #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL
2956  #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL
2957  #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL
2958  #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL
2959  #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL
2960  #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL
2961  #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL
2962  #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL
2963 
2965  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
2966  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
2967  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
2968  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
2969  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
2970  #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
2971  #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
2972  #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
2973  #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
2974  #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
2975  #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
2976  #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL
2977  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL
2978  #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL
2979  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL
2982  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
2983  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
2984  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
2985  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
2986  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
2987  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
2988  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
2989  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
2990  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
2991  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
2992  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL
2993  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
2994  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
2996  #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
2997  #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
2998  #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
2999  #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
3000  #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
3001  #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
3003  #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
3004  #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
3005  #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
3006  #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
3008  #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
3009  #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
3010  #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
3013  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
3014  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
3015  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
3016  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
3017  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
3018  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
3019  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
3020  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
3021  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
3022  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
3023  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL
3024  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
3025  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
3027  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
3028  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
3029  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
3030  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
3031  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
3032  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
3033  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
3034  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
3035  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
3036  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
3037  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
3038  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
3039  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
3040  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
3041  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
3043  #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
3044  #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
3045  #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
3047  #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
3048  #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
3049  #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
3050  #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
3051  #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
3053  #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
3054  #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
3058  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
3059  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
3060  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
3061  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
3062  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
3063  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
3064  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
3066  #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
3067  #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
3068  #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
3069  #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
3071  #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
3072  #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
3074  #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL
3075  #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL
3076  #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL
3078  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL
3079  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL
3080  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL
3081  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL
3082  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL
3083  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL
3084  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL
3085  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL
3086  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL
3087  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL
3088  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL
3089  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL
3090  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL
3091  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
3093  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL
3094  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL
3095  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL
3096  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL
3097  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL
3098  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL
3099  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL
3100  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL
3101  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL
3102  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL
3103  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL
3104  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL
3105  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL
3107 };
3108 
3109 /* hwrm_port_phy_cfg_output (size:128b/16B) */
3117 };
3118 
3119 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
3122  #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
3123  #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
3124  #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
3125  #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
3127 };
3128 
3129 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
3138 };
3139 
3140 /* hwrm_port_phy_qcfg_output (size:832b/104B) */
3147  #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
3148  #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
3149  #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
3150  #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
3152  #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL
3153  #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0
3154  #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL
3155  #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL
3156  #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL
3157  #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST HWRM_PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
3158  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL
3159  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4
3160  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4)
3161  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4)
3162  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4)
3163  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4)
3164  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4)
3165  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4)
3166  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4)
3167  #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
3169  #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
3170  #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
3171  #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
3172  #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
3173  #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
3174  #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
3175  #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
3176  #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
3177  #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
3178  #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
3179  #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
3180  #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL
3181  #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
3182  #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
3184  #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
3185  #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
3186  #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
3188  #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
3189  #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
3191  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
3192  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
3193  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
3194  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
3195  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
3196  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
3197  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
3198  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
3199  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
3200  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
3201  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
3202  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
3203  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
3204  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
3205  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL
3207  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
3208  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
3209  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
3210  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
3211  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
3212  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
3213  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
3214  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
3215  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
3216  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
3217  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL
3218  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
3219  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
3221  #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
3222  #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
3223  #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
3224  #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
3225  #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
3226  #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
3228  #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
3229  #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
3230  #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
3232  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
3233  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
3234  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
3235  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
3236  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
3237  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
3238  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
3239  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
3240  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
3241  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
3242  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL
3243  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
3244  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
3246  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
3247  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
3248  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
3249  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
3250  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
3251  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
3252  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
3253  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
3254  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
3255  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
3256  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
3257  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
3258  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
3259  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
3260  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
3262  #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
3263  #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
3264  #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
3266  #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
3267  #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
3268  #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
3269  #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
3270  #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
3272  #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
3273  #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
3275  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
3276  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
3277  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
3278  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
3279  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
3280  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
3281  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
3287  #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
3288  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
3289  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
3290  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
3291  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
3292  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
3293  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
3294  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
3295  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
3296  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
3297  #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
3298  #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
3299  #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
3300  #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
3301  #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
3302  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
3303  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
3304  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
3305  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
3306  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
3307  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
3308  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
3309  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
3310  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
3311  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
3312  #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
3313  #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
3314  #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
3315  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
3316  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
3317  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
3318  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
3319  #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL
3320  #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL
3321  #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL
3322  #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL
3323  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL
3324  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL
3325  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL
3326  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL
3327  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL
3328  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL
3329  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL
3330  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL
3331  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL
3332  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL
3333  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL
3334  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL
3335  #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL
3336  #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL
3337  #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL
3338  #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL
3339  #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL
3340  #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL
3341  #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL
3342  #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL
3343  #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4
3345  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
3346  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
3347  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
3348  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
3349  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
3351  #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
3352  #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
3353  #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
3355  #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
3356  #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
3357  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
3358  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
3359  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
3360  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
3361  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
3363  #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
3365  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
3366  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
3367  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
3368  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
3369  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
3370  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
3371  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
3372  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
3373  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
3374  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
3375  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
3376  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
3377  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
3378  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
3380  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
3381  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
3382  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
3383  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
3384  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
3385  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
3387  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
3388  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
3390  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
3391  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
3392  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
3393  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
3394  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
3395  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
3396  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
3398  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
3399  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
3400  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
3401  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
3402  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
3403  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
3404  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
3406  #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
3407  #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
3408  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
3409  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
3410  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
3411  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
3412  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
3413  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
3414  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
3415  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
3417  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
3418  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
3419  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
3420  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
3421  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
3422  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
3423  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
3424  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL
3425  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL
3426  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL
3427  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL
3428  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL
3429  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL
3430  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL
3431  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL
3433  #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
3434  #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
3435  #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
3437  #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
3438  #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL
3439  #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL
3443  #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL
3444  #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL
3445  #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL
3447  #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
3448  #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
3449  #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
3450  #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
3452  #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL
3453  #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL
3454  #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL
3456  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL
3457  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
3458  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
3460  #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
3462  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL
3463  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL
3464  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL
3465  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL
3466  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL
3467  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL
3468  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL
3469  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL
3470  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL
3471  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL
3472  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL
3473  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL
3474  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL
3475  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL
3477  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL
3478  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL
3479  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL
3480  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL
3481  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL
3482  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL
3483  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL
3484  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL
3485  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL
3486  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL
3487  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL
3488  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL
3489  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL
3490  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL
3491  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112
3493  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL
3494  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL
3495  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL
3496  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL
3497  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL
3498  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL
3499  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL
3500  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL
3501  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL
3502  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL
3503  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL
3504  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL
3505  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL
3506  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL
3509 };
3510 
3511 /* hwrm_port_mac_cfg_input (size:320b/40B) */
3519  #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
3520  #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
3521  #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
3522  #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
3523  #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
3524  #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
3525  #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
3526  #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
3527  #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
3528  #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
3529  #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
3530  #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
3531  #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
3533  #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
3534  #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
3535  #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
3536  #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
3537  #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
3538  #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
3539  #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
3540  #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
3544  #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
3545  #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
3546  #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
3547  #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
3555  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
3556  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
3557  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
3558  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
3559  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
3560  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
3561  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
3562  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
3563  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
3564  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
3565  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
3566  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
3567  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
3568  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
3569  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
3570  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
3571  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
3573 };
3574 
3575 /* hwrm_port_mac_cfg_output (size:128b/16B) */
3585  #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
3586  #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
3587  #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
3588  #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
3591 };
3592 
3593 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
3602 };
3603 
3604 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
3614  #define PORT_MAC_QCFG_RESP_LPBK_NONE 0x0UL
3615  #define PORT_MAC_QCFG_RESP_LPBK_LOCAL 0x1UL
3616  #define PORT_MAC_QCFG_RESP_LPBK_REMOTE 0x2UL
3617  #define PORT_MAC_QCFG_RESP_LPBK_LAST PORT_MAC_QCFG_RESP_LPBK_REMOTE
3620  #define PORT_MAC_QCFG_RESP_FLAGS_VLAN_PRI2COS_ENABLE 0x1UL
3621  #define PORT_MAC_QCFG_RESP_FLAGS_TUNNEL_PRI2COS_ENABLE 0x2UL
3622  #define PORT_MAC_QCFG_RESP_FLAGS_IP_DSCP2COS_ENABLE 0x4UL
3623  #define PORT_MAC_QCFG_RESP_FLAGS_OOB_WOL_ENABLE 0x8UL
3624  #define PORT_MAC_QCFG_RESP_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
3625  #define PORT_MAC_QCFG_RESP_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x20UL
3631  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_RSVD 0x1UL
3632  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
3633  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
3634  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
3635  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
3636  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
3637  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
3638  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
3639  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
3640  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
3641  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
3642  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
3643  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
3644  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
3645  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
3646  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
3647  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_DEFAULT_COS_SFT 5
3649 };
3650 
3651 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
3660 };
3661 
3662 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
3669  #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
3670  #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL
3689 };
3690 
3691 /* tx_port_stats (size:3264b/408B) */
3744 };
3745 
3746 /* rx_port_stats (size:4224b/528B) */
3814 };
3815 
3816 /* hwrm_port_qstats_input (size:320b/40B) */
3827 };
3828 
3829 /* hwrm_port_qstats_output (size:128b/16B) */
3839 };
3840 
3841 /* tx_port_stats_ext (size:2048b/256B) */
3875 };
3876 
3877 /* rx_port_stats_ext (size:2368b/296B) */
3916 };
3917 
3918 /* hwrm_port_qstats_ext_input (size:320b/40B) */
3931 };
3932 
3933 /* hwrm_port_qstats_ext_output (size:128b/16B) */
3943  #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
3945 };
3946 
3947 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
3954 };
3955 
3956 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
3974 };
3975 
3976 /* hwrm_port_clr_stats_input (size:192b/24B) */
3985  #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
3987 };
3988 
3989 /* hwrm_port_clr_stats_output (size:128b/16B) */
3997 };
3998 
3999 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
4006 };
4007 
4008 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
4016 };
4017 
4018 /* hwrm_port_ts_query_input (size:192b/24B) */
4026  #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL
4027  #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL
4028  #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL
4029  #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX
4032 };
4033 
4034 /* hwrm_port_ts_query_output (size:192b/24B) */
4044 };
4045 
4046 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
4055 };
4056 
4057 /* hwrm_port_phy_qcaps_output (size:320b/40B) */
4064  #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
4065  #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
4066  #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL
4067  #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2
4069  #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
4070  #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
4071  #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
4072  #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
4073  #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
4074  #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4
4076  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
4077  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
4078  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
4079  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
4080  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
4081  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
4082  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
4083  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
4084  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
4085  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
4086  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
4087  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
4088  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
4089  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
4091  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
4092  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
4093  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
4094  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
4095  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
4096  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
4097  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
4098  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
4099  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
4100  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
4101  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
4102  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
4103  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
4104  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
4106  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
4107  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
4108  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
4109  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
4110  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
4111  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
4112  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
4114  #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
4115  #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
4116  #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
4117  #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
4119  #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
4120  #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
4121  #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
4122  #define PORT_PHY_QCAPS_RESP_VALID_SFT 24
4124  #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL
4125  #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL
4126  #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL
4128  #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL
4129  #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL
4130  #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL
4132  #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL
4133  #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL
4134  #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL
4135  #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL
4139  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL
4140  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL
4141  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL
4142  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL
4143  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL
4144  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL
4145  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL
4146  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL
4147  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL
4148  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL
4149  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL
4150  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL
4151  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL
4152  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL
4154  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL
4155  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL
4156  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL
4157  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL
4158  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL
4159  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL
4160  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL
4161  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL
4162  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL
4163  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL
4164  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL
4165  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL
4166  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL
4167  #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL
4170 };
4171 
4172 /* hwrm_port_phy_i2c_write_input (size:832b/104B) */
4181  #define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET 0x1UL
4190 };
4191 
4192 /* hwrm_port_phy_i2c_write_output (size:128b/16B) */
4200 };
4201 
4202 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
4211  #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
4219 };
4220 
4221 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
4230 };
4231 
4232 /* hwrm_port_led_cfg_input (size:512b/64B) */
4240  #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
4241  #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
4242  #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
4243  #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
4244  #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
4245  #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
4246  #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
4247  #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
4248  #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
4249  #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
4250  #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
4251  #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
4252  #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
4253  #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
4254  #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
4255  #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
4256  #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
4257  #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
4258  #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
4259  #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
4260  #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
4261  #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
4262  #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
4263  #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
4269  #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
4270  #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
4271  #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
4272  #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
4273  #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
4274  #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
4276  #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
4277  #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
4278  #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
4279  #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
4280  #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
4288  #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
4289  #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
4290  #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
4291  #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
4292  #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
4293  #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
4295  #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
4296  #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
4297  #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
4298  #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
4299  #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
4307  #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
4308  #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
4309  #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
4310  #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
4311  #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
4312  #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
4314  #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
4315  #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
4316  #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
4317  #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
4318  #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
4326  #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
4327  #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
4328  #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
4329  #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
4330  #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
4331  #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
4333  #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
4334  #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
4335  #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
4336  #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
4337  #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
4343 };
4344 
4345 /* hwrm_port_led_cfg_output (size:128b/16B) */
4353 };
4354 
4355 /* hwrm_port_led_qcfg_input (size:192b/24B) */
4364 };
4365 
4366 /* hwrm_port_led_qcfg_output (size:448b/56B) */
4375  #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
4376  #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
4377  #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
4378  #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
4380  #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
4381  #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
4382  #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
4383  #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
4384  #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
4385  #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
4387  #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
4388  #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
4389  #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
4390  #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
4391  #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
4398  #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
4399  #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
4400  #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
4401  #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
4403  #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
4404  #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
4405  #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
4406  #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
4407  #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
4408  #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
4410  #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
4411  #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
4412  #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
4413  #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
4414  #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
4421  #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
4422  #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
4423  #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
4424  #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
4426  #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
4427  #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
4428  #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
4429  #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
4430  #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
4431  #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
4433  #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
4434  #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
4435  #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
4436  #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
4437  #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
4444  #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
4445  #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
4446  #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
4447  #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
4449  #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
4450  #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
4451  #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
4452  #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
4453  #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
4454  #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
4456  #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
4457  #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
4458  #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
4459  #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
4460  #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
4467 };
4468 
4469 /* hwrm_port_led_qcaps_input (size:192b/24B) */
4478 };
4479 
4480 /* hwrm_port_led_qcaps_output (size:384b/48B) */
4490  #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
4491  #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
4492  #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
4493  #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
4497  #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
4498  #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
4499  #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
4500  #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
4501  #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
4503  #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
4504  #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
4505  #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
4508  #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
4509  #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
4510  #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
4511  #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
4515  #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
4516  #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
4517  #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
4518  #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
4519  #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
4521  #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
4522  #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
4523  #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
4526  #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
4527  #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
4528  #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
4529  #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
4533  #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
4534  #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
4535  #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
4536  #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
4537  #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
4539  #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
4540  #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
4541  #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
4544  #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
4545  #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
4546  #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
4547  #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
4551  #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
4552  #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
4553  #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
4554  #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
4555  #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
4557  #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
4558  #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
4559  #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
4562 };
4563 
4564 /* hwrm_queue_qportcfg_input (size:192b/24B) */
4572  #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
4573  #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
4574  #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
4575  #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
4578  #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
4579  #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL
4580  #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
4582 };
4583 
4584 /* hwrm_queue_qportcfg_output (size:256b/32B) */
4594  #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
4600  #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
4601  #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
4602  #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4603  #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4604  #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4605  #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
4606  #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
4609  #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
4610  #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
4611  #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4612  #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4613  #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4614  #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
4615  #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
4618  #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
4619  #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
4620  #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4621  #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4622  #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4623  #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
4624  #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
4627  #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
4628  #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
4629  #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4630  #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4631  #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4632  #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
4633  #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
4636  #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
4637  #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
4638  #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4639  #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4640  #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4641  #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
4642  #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
4645  #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
4646  #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
4647  #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4648  #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4649  #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4650  #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
4651  #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
4654  #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
4655  #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
4656  #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4657  #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4658  #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4659  #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
4660  #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
4663  #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
4664  #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
4665  #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
4666  #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
4667  #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
4668  #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
4669  #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
4671 };
4672 
4673 /* hwrm_queue_qcfg_input (size:192b/24B) */
4681  #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL
4682  #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL
4683  #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL
4684  #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX
4686 };
4687 
4688 /* hwrm_queue_qcfg_output (size:128b/16B) */
4696  #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL
4697  #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL
4698  #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL
4699  #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN
4701  #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
4704 };
4705 
4706 /* hwrm_queue_cfg_input (size:320b/40B) */
4714  #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
4715  #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
4716  #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
4717  #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
4718  #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
4719  #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
4721  #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
4722  #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
4726  #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
4727  #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
4728  #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
4729  #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
4731 };
4732 
4733 /* hwrm_queue_cfg_output (size:128b/16B) */
4741 };
4742 
4743 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
4752 };
4753 
4754 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
4761  #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
4762  #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
4763  #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
4764  #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
4765  #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
4766  #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
4767  #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
4768  #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
4771 };
4772 
4773 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
4781  #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
4782  #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
4783  #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
4784  #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
4785  #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
4786  #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
4787  #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
4788  #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
4791 };
4792 
4793 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
4801 };
4802 
4803 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
4811  #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
4812  #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
4813  #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
4814  #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
4815  #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
4818 };
4819 
4820 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
4835  #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
4838 };
4839 
4840 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
4848  #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
4849  #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
4850  #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
4851  #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
4852  #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
4853  #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
4854  #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
4856  #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
4857  #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
4858  #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
4859  #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
4860  #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
4861  #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
4862  #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
4863  #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
4874 };
4875 
4876 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
4884 };
4885 
4886 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
4895 };
4896 
4897 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
4907  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4908  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
4909  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
4910  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
4911  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
4912  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
4913  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4914  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
4915  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4916  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4917  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4918  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4919  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4920  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4921  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
4923  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4924  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
4925  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
4926  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
4927  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
4928  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
4929  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4930  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
4931  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4932  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4933  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4934  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4935  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4936  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4937  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
4939  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
4940  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
4941  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4942  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
4947  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4948  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
4949  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
4950  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
4951  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
4952  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
4953  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4954  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
4955  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4956  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4957  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4958  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4959  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4960  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4961  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
4963  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4964  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
4965  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
4966  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
4967  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
4968  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
4969  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4970  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
4971  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4972  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4973  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4974  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4975  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4976  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4977  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
4979  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
4980  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
4981  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4982  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
4987  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4988  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
4989  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
4990  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
4991  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
4992  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
4993  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4994  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
4995  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4996  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4997  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4998  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4999  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5000  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5001  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
5003  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5004  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
5005  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
5006  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
5007  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
5008  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
5009  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5010  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
5011  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5012  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5013  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5014  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5015  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5016  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5017  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
5019  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
5020  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
5021  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5022  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
5027  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5028  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
5029  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
5030  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
5031  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
5032  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
5033  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5034  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
5035  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5036  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5037  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5038  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5039  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5040  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5041  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
5043  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5044  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
5045  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
5046  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
5047  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
5048  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
5049  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5050  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
5051  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5052  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5053  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5054  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5055  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5056  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5057  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
5059  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
5060  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
5061  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5062  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
5067  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5068  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
5069  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
5070  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
5071  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
5072  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
5073  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5074  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
5075  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5076  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5077  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5078  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5079  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5080  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5081  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
5083  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5084  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
5085  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
5086  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
5087  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
5088  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
5089  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5090  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
5091  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5092  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5093  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5094  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5095  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5096  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5097  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
5099  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
5100  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
5101  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5102  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
5107  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5108  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
5109  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
5110  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
5111  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
5112  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
5113  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5114  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
5115  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5116  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5117  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5118  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5119  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5120  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5121  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
5123  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5124  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
5125  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
5126  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
5127  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
5128  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
5129  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5130  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
5131  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5132  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5133  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5134  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5135  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5136  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5137  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
5139  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
5140  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
5141  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5142  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
5147  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5148  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
5149  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
5150  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
5151  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
5152  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
5153  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5154  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
5155  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5156  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5157  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5158  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5159  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5160  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5161  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
5163  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5164  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
5165  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
5166  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
5167  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
5168  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
5169  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5170  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
5171  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5172  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5173  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5174  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5175  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5176  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5177  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
5179  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
5180  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
5181  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5182  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
5187  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5188  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
5189  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
5190  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
5191  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
5192  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
5193  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5194  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
5195  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5196  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5197  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5198  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5199  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5200  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5201  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
5203  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5204  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
5205  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
5206  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
5207  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
5208  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
5209  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5210  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
5211  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5212  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5213  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5214  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5215  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5216  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5217  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
5219  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
5220  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
5221  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5222  #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
5227 };
5228 
5229 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
5238  #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
5239  #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
5240  #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
5241  #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
5242  #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
5243  #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
5244  #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
5245  #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
5250  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5251  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
5252  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
5253  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
5254  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
5255  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
5256  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5257  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
5258  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5259  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5260  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5261  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5262  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5263  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5264  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
5266  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5267  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
5268  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
5269  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
5270  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
5271  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
5272  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5273  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
5274  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5275  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5276  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5277  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5278  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5279  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5280  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
5282  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
5283  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
5284  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5285  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
5290  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5291  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
5292  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
5293  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
5294  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
5295  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
5296  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5297  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
5298  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5299  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5300  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5301  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5302  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5303  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5304  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
5306  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5307  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
5308  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
5309  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
5310  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
5311  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
5312  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5313  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
5314  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5315  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5316  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5317  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5318  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5319  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5320  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
5322  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
5323  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
5324  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5325  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
5330  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5331  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
5332  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
5333  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
5334  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
5335  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
5336  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5337  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
5338  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5339  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5340  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5341  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5342  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5343  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5344  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
5346  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5347  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
5348  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
5349  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
5350  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
5351  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
5352  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5353  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
5354  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5355  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5356  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5357  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5358  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5359  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5360  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
5362  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
5363  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
5364  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5365  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
5370  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5371  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
5372  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
5373  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
5374  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
5375  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
5376  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5377  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
5378  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5379  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5380  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5381  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5382  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5383  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5384  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
5386  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5387  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
5388  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
5389  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
5390  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
5391  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
5392  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5393  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
5394  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5395  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5396  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5397  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5398  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5399  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5400  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
5402  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
5403  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
5404  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5405  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
5410  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5411  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
5412  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
5413  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
5414  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
5415  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
5416  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5417  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
5418  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5419  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5420  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5421  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5422  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5423  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5424  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
5426  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5427  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
5428  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
5429  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
5430  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
5431  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
5432  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5433  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
5434  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5435  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5436  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5437  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5438  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5439  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5440  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
5442  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
5443  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
5444  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5445  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
5450  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5451  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
5452  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
5453  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
5454  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
5455  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
5456  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5457  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
5458  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5459  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5460  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5461  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5462  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5463  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5464  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
5466  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5467  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
5468  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
5469  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
5470  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
5471  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
5472  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5473  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
5474  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5475  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5476  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5477  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5478  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5479  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5480  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
5482  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
5483  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
5484  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5485  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
5490  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5491  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
5492  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
5493  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
5494  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
5495  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
5496  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5497  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
5498  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5499  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5500  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5501  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5502  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5503  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5504  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
5506  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5507  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
5508  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
5509  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
5510  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
5511  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
5512  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5513  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
5514  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5515  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5516  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5517  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5518  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5519  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5520  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
5522  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
5523  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
5524  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5525  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
5530  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5531  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
5532  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
5533  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
5534  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
5535  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
5536  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5537  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
5538  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5539  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5540  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5541  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5542  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5543  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5544  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
5546  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5547  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
5548  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
5549  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
5550  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
5551  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
5552  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5553  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
5554  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5555  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5556  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5557  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5558  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5559  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5560  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
5562  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
5563  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
5564  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5565  #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
5569 };
5570 
5571 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
5579 };
5580 
5581 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
5590 };
5591 
5592 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
5603 };
5604 
5605 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
5617 };
5618 
5619 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
5629 };
5630 
5631 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
5640  #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
5642  #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
5647 };
5648 
5649 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
5657 };
5658 
5659 /* hwrm_vnic_alloc_input (size:192b/24B) */
5667  #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
5669 };
5670 
5671 /* hwrm_vnic_alloc_output (size:128b/16B) */
5680 };
5681 
5682 /* hwrm_vnic_free_input (size:192b/24B) */
5691 };
5692 
5693 /* hwrm_vnic_free_output (size:128b/16B) */
5701 };
5702 
5703 /* hwrm_vnic_cfg_input (size:320b/40B) */
5711  #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
5712  #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
5713  #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
5714  #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
5715  #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
5716  #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
5717  #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
5719  #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
5720  #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
5721  #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
5722  #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
5723  #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
5724  #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
5725  #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
5734 };
5735 
5736 /* hwrm_vnic_cfg_output (size:128b/16B) */
5744 };
5745 
5746 /* hwrm_vnic_qcfg_input (size:256b/32B) */
5754  #define VNIC_QCFG_REQ_ENABLES_VF_ID_VALID 0x1UL
5758 };
5759 
5760 /* hwrm_vnic_qcfg_output (size:256b/32B) */
5773  #define VNIC_QCFG_RESP_FLAGS_DEFAULT 0x1UL
5774  #define VNIC_QCFG_RESP_FLAGS_VLAN_STRIP_MODE 0x2UL
5775  #define VNIC_QCFG_RESP_FLAGS_BD_STALL_MODE 0x4UL
5776  #define VNIC_QCFG_RESP_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
5777  #define VNIC_QCFG_RESP_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
5778  #define VNIC_QCFG_RESP_FLAGS_RSS_DFLT_CR_MODE 0x20UL
5779  #define VNIC_QCFG_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
5782 };
5783 
5784 /* hwrm_vnic_qcaps_input (size:192b/24B) */
5793 };
5794 
5795 /* hwrm_vnic_qcaps_output (size:192b/24B) */
5804  #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
5805  #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
5806  #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
5807  #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
5808  #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
5809  #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
5810  #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
5811  #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
5814 };
5815 
5816 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
5824  #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
5825  #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
5826  #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
5827  #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
5828  #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
5829  #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
5830  #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
5831  #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
5833  #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
5834  #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
5835  #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
5836  #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
5839  #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
5840  #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
5841  #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
5842  #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
5843  #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
5844  #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
5846  #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
5847  #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
5848  #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
5849  #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
5850  #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
5851  #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
5852  #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
5856 };
5857 
5858 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
5866 };
5867 
5868 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
5877 };
5878 
5879 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
5886  #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
5887  #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
5888  #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
5889  #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
5890  #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
5891  #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
5892  #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
5893  #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
5895  #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
5896  #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
5897  #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
5898  #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
5899  #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
5900  #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
5902  #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
5903  #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
5904  #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
5905  #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
5906  #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
5907  #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
5908  #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
5913 };
5914 
5915 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
5923  #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
5924  #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
5925  #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
5926  #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
5927  #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
5928  #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
5932  #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
5933  #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
5934  #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
5935  #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
5936  #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
5941 };
5942 
5943 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
5951 };
5952 
5953 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
5962 };
5963 
5964 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
5971  #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL
5972  #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL
5973  #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL
5974  #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL
5975  #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL
5976  #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL
5980  #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL
5981  #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
5982  #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
5983  #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
5984  #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
5987 };
5988 
5989 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
5997  #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
5998  #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
5999  #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
6000  #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
6001  #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
6002  #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
6004  #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
6005  #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
6006  #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
6012 };
6013 
6014 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
6022 };
6023 
6024 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
6033 };
6034 
6035 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
6042  #define VNIC_PLCMODES_QCFG_RESP_FLAGS_REGULAR_PLACEMENT 0x1UL
6043  #define VNIC_PLCMODES_QCFG_RESP_FLAGS_JUMBO_PLACEMENT 0x2UL
6044  #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_IPV4 0x4UL
6045  #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_IPV6 0x8UL
6046  #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_FCOE 0x10UL
6047  #define VNIC_PLCMODES_QCFG_RESP_FLAGS_HDS_ROCE 0x20UL
6048  #define VNIC_PLCMODES_QCFG_RESP_FLAGS_DFLT_VNIC 0x40UL
6054 };
6055 
6056 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
6063 };
6064 
6065 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
6074 };
6075 
6076 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
6085 };
6086 
6087 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
6095 };
6096 
6097 /* hwrm_ring_alloc_input (size:704b/88B) */
6105  #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
6106  #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
6107  #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
6108  #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
6109  #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
6110  #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
6112  #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
6113  #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
6114  #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
6115  #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6116  #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
6117  #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
6118  #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
6121  #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
6135  #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
6136  #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
6137  #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
6138  #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
6139  #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
6140  #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
6141  #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
6142  #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
6143  #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
6149  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
6150  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
6151  #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
6152  #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
6153  #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
6154  #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
6155  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6156  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
6157  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6158  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6159  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6160  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6161  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6162  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6163  #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
6165  #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
6166  #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
6167  #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
6168  #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
6169  #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
6172 };
6173 
6174 /* hwrm_ring_alloc_output (size:128b/16B) */
6184 };
6185 
6186 /* hwrm_ring_free_input (size:192b/24B) */
6194  #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
6195  #define RING_FREE_REQ_RING_TYPE_TX 0x1UL
6196  #define RING_FREE_REQ_RING_TYPE_RX 0x2UL
6197  #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6198  #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
6199  #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
6200  #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
6204 };
6205 
6206 /* hwrm_ring_free_output (size:128b/16B) */
6214 };
6215 
6216 /* hwrm_ring_reset_input (size:192b/24B) */
6224  #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
6225  #define RING_RESET_REQ_RING_TYPE_TX 0x1UL
6226  #define RING_RESET_REQ_RING_TYPE_RX 0x2UL
6227  #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6228  #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL
6232 };
6233 
6234 /* hwrm_ring_reset_output (size:128b/16B) */
6242 };
6243 
6244 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
6251 };
6252 
6253 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
6260  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
6261  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
6262  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
6263  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
6264  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
6265  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
6266  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
6267  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
6268  #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
6270  #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
6288 };
6289 
6290 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
6299 };
6300 
6301 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
6308  #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
6309  #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
6319 };
6320 
6321 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
6330  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
6331  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
6332  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
6341  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
6342  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
6343  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
6344  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
6345  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
6346  #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
6348 };
6349 
6350 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
6358 };
6359 
6360 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
6371 };
6372 
6373 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
6382 };
6383 
6384 /* hwrm_ring_grp_free_input (size:192b/24B) */
6393 };
6394 
6395 /* hwrm_ring_grp_free_output (size:128b/16B) */
6403 };
6404 
6405 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
6413  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
6414  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
6415  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
6416  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
6417  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
6418  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
6419  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
6420  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
6421  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
6422  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
6423  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
6424  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
6425  #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
6427  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
6428  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
6429  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
6430  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
6431  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
6432  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
6433  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
6434  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
6435  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
6436  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
6437  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
6438  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
6439  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
6440  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
6441  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
6442  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
6443  #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
6460  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
6461  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
6462  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
6463  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
6464  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
6465  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
6466  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
6467  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
6468  #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
6472  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6473  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6474  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6475  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6476  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6477  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6478  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6479  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6480  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6481  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6482  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6483  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6484  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6485  #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6490  #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
6491  #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
6492  #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
6493  #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
6494  #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
6495  #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
6499 };
6500 
6501 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
6511 };
6512 
6513 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
6521 };
6522 
6523 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
6531 };
6532 
6533 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
6541  #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
6542  #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
6543  #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
6544  #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
6545  #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
6546  #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
6547  #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
6548  #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
6549  #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
6550  #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
6551  #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
6553  #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
6554  #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
6558 };
6559 
6560 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
6568 };
6569 
6570 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
6579  #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
6580  #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
6581  #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
6582  #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
6583  #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
6584  #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
6585  #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
6586  #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
6593 };
6594 
6595 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
6603 };
6604 
6605 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
6608  #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
6609  #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
6610  #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
6612 };
6613 
6614 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
6625 };
6626 
6627 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
6635 };
6636 
6637 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
6648 };
6649 
6650 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
6659 };
6660 
6661 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
6669  #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
6671  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
6672  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
6673  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
6674  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
6675  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
6676  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
6677  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
6678  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
6679  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
6680  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
6681  #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
6690  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6691  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6692  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6693  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6694  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6695  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6696  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6697  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6698  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6699  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6700  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6701  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6702  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6703  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6705  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
6706  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
6707  #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
6711 };
6712 
6713 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
6723 };
6724 
6725 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
6733 };
6734 
6735 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
6743 };
6744 
6745 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
6754  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6755  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6756  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6757  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6758  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6759  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6760  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6761  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6762  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6763  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6764  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6765  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6766  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6767  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6769  #define CFA_REDIRECT_TUNNEL_TYPE_ALLOC_REQ_FLAGS_MODIFY_DST 0x1UL
6771 };
6772 
6773 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
6781 };
6782 
6783 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
6792  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6793  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6794  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6795  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6796  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPIP 0x4UL
6797  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6798  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_MPLS 0x6UL
6799  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_STT 0x7UL
6800  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6801  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6802  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6803  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6804  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6805  #define CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_LAST CFA_REDIRECT_TUNNEL_TYPE_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL
6807 };
6808 
6809 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
6817 };
6818 
6819 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
6828  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6829  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6830  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6831  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6832  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPIP 0x4UL
6833  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6834  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_MPLS 0x6UL
6835  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_STT 0x7UL
6836  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6837  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6838  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6839  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6840  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6841  #define CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_LAST CFA_REDIRECT_TUNNEL_TYPE_INFO_REQ_TUNNEL_TYPE_ANYTUNNEL
6843 };
6844 
6845 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
6854 };
6855 
6856 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
6859  #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
6860  #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
6861  #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
6862  #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
6870 };
6871 
6872 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
6875  #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
6876  #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
6877  #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
6878  #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
6879  #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
6880  #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
6881  #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
6887 };
6888 
6889 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
6900  __le32 l3[10];
6901  #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
6902  #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
6903  #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
6904  #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
6912 };
6913 
6914 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
6922  #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
6924  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
6925  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
6926  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
6927  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
6928  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
6929  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
6930  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
6931  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
6932  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
6933  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
6934  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
6935  #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE
6938 };
6939 
6940 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
6949 };
6950 
6951 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
6960 };
6961 
6962 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
6970 };
6971 
6972 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
6980  #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
6981  #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
6982  #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
6984  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
6985  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
6986  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
6987  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
6988  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
6989  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
6990  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
6991  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
6992  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
6993  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
6994  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
6995  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
6996  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
6997  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
6998  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
6999  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
7000  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
7001  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
7002  #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
7007  #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7008  #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
7009  #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
7010  #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7012  #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7013  #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
7014  #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
7015  #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
7019  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7020  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7021  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7022  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7023  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7024  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7025  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7026  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7027  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7028  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7029  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7030  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7031  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7032  #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7034  #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
7035  #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
7036  #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL
7037  #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL
7038  #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL
7039  #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
7049 };
7050 
7051 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
7061 };
7062 
7063 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
7066  #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
7067  #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
7068  #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
7070 };
7071 
7072 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
7080 };
7081 
7082 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
7090 };
7091 
7092 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
7100  #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
7101  #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
7102  #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
7108  #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
7109  #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
7111 };
7112 
7113 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
7121 };
7122 
7123 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
7131  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH 0x1UL
7132  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
7133  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
7134  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_LAST CFA_EM_FLOW_ALLOC_REQ_FLAGS_PATH_RX
7135  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_BYTE_CTR 0x2UL
7136  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_PKT_CTR 0x4UL
7137  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_DECAP 0x8UL
7138  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_ENCAP 0x10UL
7139  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_DROP 0x20UL
7140  #define CFA_EM_FLOW_ALLOC_REQ_FLAGS_METER 0x40UL
7142  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
7143  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x2UL
7144  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_TUNNEL_ID 0x4UL
7145  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
7146  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_MACADDR 0x10UL
7147  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_OVLAN_VID 0x20UL
7148  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IVLAN_VID 0x40UL
7149  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_ETHERTYPE 0x80UL
7150  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_IPADDR 0x100UL
7151  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_IPADDR 0x200UL
7152  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x400UL
7153  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x800UL
7154  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_SRC_PORT 0x1000UL
7155  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_PORT 0x2000UL
7156  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_DST_ID 0x4000UL
7157  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x8000UL
7158  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_ENCAP_RECORD_ID 0x10000UL
7159  #define CFA_EM_FLOW_ALLOC_REQ_ENABLES_METER_INSTANCE_ID 0x20000UL
7162  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7163  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7164  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7165  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7166  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7167  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7168  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7169  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7170  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7171  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7172  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7173  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7174  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7175  #define CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_EM_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7180  #define CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_INVALID 0xffffUL
7181  #define CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_LAST CFA_EM_FLOW_ALLOC_REQ_METER_INSTANCE_ID_INVALID
7187  #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7188  #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
7189  #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
7190  #define CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_EM_FLOW_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7192  #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7193  #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
7194  #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
7195  #define CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_LAST CFA_EM_FLOW_ALLOC_REQ_IP_PROTOCOL_UDP
7205 };
7206 
7207 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
7217 };
7218 
7219 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
7227 };
7228 
7229 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
7237 };
7238 
7239 /* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */
7247  #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
7248  #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
7249  #define CFA_EM_FLOW_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
7255  #define CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
7256  #define CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_EM_FLOW_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
7258 };
7259 
7260 /* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */
7268 };
7269 
7270 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
7278  #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH 0x1UL
7279  #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
7280  #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
7281  #define CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_ALLOC_REQ_FLAGS_PATH_RX
7283  #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC2697 0x0UL
7284  #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC2698 0x1UL
7285  #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC4115 0x2UL
7286  #define CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_LAST CFA_METER_PROFILE_ALLOC_REQ_METER_TYPE_RFC4115
7290  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_MASK 0xfffffffUL
7291  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_SFT 0
7292  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE 0x10000000UL
7293  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BITS (0x0UL << 28)
7294  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BYTES (0x1UL << 28)
7295  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_LAST CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_SCALE_BYTES
7296  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_MASK 0xe0000000UL
7297  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_SFT 29
7298  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7299  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_KILO (0x2UL << 29)
7300  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_BASE (0x4UL << 29)
7301  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7302  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7303  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7304  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_LAST CFA_METER_PROFILE_ALLOC_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID
7306  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_MASK 0xfffffffUL
7307  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_SFT 0
7308  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE 0x10000000UL
7309  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BITS (0x0UL << 28)
7310  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BYTES (0x1UL << 28)
7311  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_LAST CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_SCALE_BYTES
7312  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_MASK 0xe0000000UL
7313  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_SFT 29
7314  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7315  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_KILO (0x2UL << 29)
7316  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_BASE (0x4UL << 29)
7317  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7318  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7319  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7320  #define CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_LAST CFA_METER_PROFILE_ALLOC_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID
7322  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_MASK 0xfffffffUL
7323  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_SFT 0
7324  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE 0x10000000UL
7325  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BITS (0x0UL << 28)
7326  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BYTES (0x1UL << 28)
7327  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_LAST CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_SCALE_BYTES
7328  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK 0xe0000000UL
7329  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29
7330  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7331  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (0x2UL << 29)
7332  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (0x4UL << 29)
7333  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7334  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7335  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7336  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
7338  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_MASK 0xfffffffUL
7339  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_SFT 0
7340  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE 0x10000000UL
7341  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BITS (0x0UL << 28)
7342  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BYTES (0x1UL << 28)
7343  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_LAST CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_SCALE_BYTES
7344  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK 0xe0000000UL
7345  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29
7346  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7347  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (0x2UL << 29)
7348  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (0x4UL << 29)
7349  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7350  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7351  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7352  #define CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST CFA_METER_PROFILE_ALLOC_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
7353 };
7354 
7355 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
7362  #define CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_INVALID 0xffffUL
7363  #define CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_LAST CFA_METER_PROFILE_ALLOC_RESP_METER_PROFILE_ID_INVALID
7366 };
7367 
7368 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
7376  #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH 0x1UL
7377  #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_TX 0x0UL
7378  #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_RX 0x1UL
7379  #define CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_FREE_REQ_FLAGS_PATH_RX
7382  #define CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_INVALID 0xffffUL
7383  #define CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_LAST CFA_METER_PROFILE_FREE_REQ_METER_PROFILE_ID_INVALID
7385 };
7386 
7387 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
7395 };
7396 
7397 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
7405  #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH 0x1UL
7406  #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_TX 0x0UL
7407  #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_RX 0x1UL
7408  #define CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_LAST CFA_METER_PROFILE_CFG_REQ_FLAGS_PATH_RX
7410  #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC2697 0x0UL
7411  #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC2698 0x1UL
7412  #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC4115 0x2UL
7413  #define CFA_METER_PROFILE_CFG_REQ_METER_TYPE_LAST CFA_METER_PROFILE_CFG_REQ_METER_TYPE_RFC4115
7415  #define CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_INVALID 0xffffUL
7416  #define CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_LAST CFA_METER_PROFILE_CFG_REQ_METER_PROFILE_ID_INVALID
7419  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_MASK 0xfffffffUL
7420  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_SFT 0
7421  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE 0x10000000UL
7422  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BITS (0x0UL << 28)
7423  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BYTES (0x1UL << 28)
7424  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_LAST CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_SCALE_BYTES
7425  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_MASK 0xe0000000UL
7426  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_SFT 29
7427  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7428  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_KILO (0x2UL << 29)
7429  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_BASE (0x4UL << 29)
7430  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7431  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7432  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7433  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_LAST CFA_METER_PROFILE_CFG_REQ_COMMIT_RATE_BW_VALUE_UNIT_INVALID
7435  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_MASK 0xfffffffUL
7436  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_SFT 0
7437  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE 0x10000000UL
7438  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BITS (0x0UL << 28)
7439  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BYTES (0x1UL << 28)
7440  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_LAST CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_SCALE_BYTES
7441  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_MASK 0xe0000000UL
7442  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_SFT 29
7443  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7444  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_KILO (0x2UL << 29)
7445  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_BASE (0x4UL << 29)
7446  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7447  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7448  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7449  #define CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_LAST CFA_METER_PROFILE_CFG_REQ_COMMIT_BURST_BW_VALUE_UNIT_INVALID
7451  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_MASK 0xfffffffUL
7452  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_SFT 0
7453  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE 0x10000000UL
7454  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BITS (0x0UL << 28)
7455  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BYTES (0x1UL << 28)
7456  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_LAST CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_SCALE_BYTES
7457  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK 0xe0000000UL
7458  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29
7459  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7460  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (0x2UL << 29)
7461  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (0x4UL << 29)
7462  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7463  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7464  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7465  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
7467  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_MASK 0xfffffffUL
7468  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_SFT 0
7469  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE 0x10000000UL
7470  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BITS (0x0UL << 28)
7471  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BYTES (0x1UL << 28)
7472  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_LAST CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_SCALE_BYTES
7473  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK 0xe0000000UL
7474  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29
7475  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (0x0UL << 29)
7476  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (0x2UL << 29)
7477  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (0x4UL << 29)
7478  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (0x6UL << 29)
7479  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
7480  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (0x7UL << 29)
7481  #define CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST CFA_METER_PROFILE_CFG_REQ_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
7482 };
7483 
7484 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
7492 };
7493 
7494 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
7502  #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH 0x1UL
7503  #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
7504  #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
7505  #define CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_LAST CFA_METER_INSTANCE_ALLOC_REQ_FLAGS_PATH_RX
7508  #define CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_INVALID 0xffffUL
7509  #define CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_LAST CFA_METER_INSTANCE_ALLOC_REQ_METER_PROFILE_ID_INVALID
7511 };
7512 
7513 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
7520  #define CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_INVALID 0xffffUL
7521  #define CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_LAST CFA_METER_INSTANCE_ALLOC_RESP_METER_INSTANCE_ID_INVALID
7524 };
7525 
7526 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
7534  #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH 0x1UL
7535  #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_TX 0x0UL
7536  #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_RX 0x1UL
7537  #define CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_LAST CFA_METER_INSTANCE_FREE_REQ_FLAGS_PATH_RX
7540  #define CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_INVALID 0xffffUL
7541  #define CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_LAST CFA_METER_INSTANCE_FREE_REQ_METER_INSTANCE_ID_INVALID
7543 };
7544 
7545 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
7553 };
7554 
7555 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
7563  #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL
7565  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL
7566  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL
7567  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL
7568  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL
7569  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL
7570  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL
7571  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL
7572  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL
7573  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL
7574  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL
7575  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL
7576  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL
7577  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL
7578  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL
7579  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL
7580  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
7581  #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
7584  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7585  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7586  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7587  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7588  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7589  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7590  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7591  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7592  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7593  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7594  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7595  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7596  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7597  #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7609  #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7610  #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
7611  #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
7612  #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7614  #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7615  #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
7616  #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
7617  #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
7626 };
7627 
7628 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
7637 };
7638 
7639 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
7648 };
7649 
7650 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
7658 };
7659 
7660 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
7668  #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
7669  #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
7670  #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
7671  #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
7672  #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
7673  #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
7674  #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
7675  #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
7676  #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
7677  #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
7678  #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
7679  #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
7680  #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
7681  #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
7682  #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
7683  #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
7687  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
7688  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
7689  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
7690  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
7691  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
7692  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
7693  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
7694  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
7695  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
7696  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
7697  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
7698  #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL
7723  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7724  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7725  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7726  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7727  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7728  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7729  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7730  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7731  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7732  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7733  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7734  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7735  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7736  #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7737 };
7738 
7739 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
7751 };
7752 
7753 /* hwrm_cfa_flow_free_input (size:256b/32B) */
7763 };
7764 
7765 /* hwrm_cfa_flow_free_output (size:256b/32B) */
7775 };
7776 
7777 /* hwrm_cfa_flow_info_input (size:256b/32B) */
7785  #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL
7786  #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0
7787  #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL
7788  #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL
7789  #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL
7790  #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL
7793 };
7794 
7795 /* hwrm_cfa_flow_info_output (size:448b/56B) */
7815 };
7816 
7817 /* hwrm_cfa_flow_flush_input (size:192b/24B) */
7826 };
7827 
7828 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
7836 };
7837 
7838 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
7867 };
7868 
7869 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
7897 };
7898 
7899 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
7909 };
7910 
7911 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
7919 };
7920 
7921 /* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
7929  #define CFA_FLOW_AGING_CFG_REQ_ENABLES_TCP_FLOW_TIMER 0x1UL
7930  #define CFA_FLOW_AGING_CFG_REQ_ENABLES_TCP_FIN_TIMER 0x2UL
7931  #define CFA_FLOW_AGING_CFG_REQ_ENABLES_UDP_FLOW_TIMER 0x4UL
7933  #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH 0x1UL
7934  #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_TX 0x0UL
7935  #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_RX 0x1UL
7936  #define CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_CFG_REQ_FLAGS_PATH_RX
7941 };
7942 
7943 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
7951 };
7952 
7953 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
7961  #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH 0x1UL
7962  #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_TX 0x0UL
7963  #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_RX 0x1UL
7964  #define CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_QCFG_REQ_FLAGS_PATH_RX
7966 };
7967 
7968 /* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
7979 };
7980 
7981 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
7989  #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH 0x1UL
7990  #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_TX 0x0UL
7991  #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_RX 0x1UL
7992  #define CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_LAST CFA_FLOW_AGING_QCAPS_REQ_FLAGS_PATH_RX
7994 };
7995 
7996 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
8008 };
8009 
8010 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
8020  char pair_name[32];
8021 };
8022 
8023 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
8031 };
8032 
8033 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
8040  char pair_name[32];
8041 };
8042 
8043 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
8051 };
8052 
8053 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
8061  #define CFA_VF_PAIR_INFO_REQ_FLAGS_LOOKUP_TYPE 0x1UL
8064  char vf_pair_name[32];
8065 };
8066 
8067 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
8079  #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ALLOCATED 0x1UL
8080  #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ACTIVE 0x2UL
8081  #define CFA_VF_PAIR_INFO_RESP_PAIR_STATE_LAST CFA_VF_PAIR_INFO_RESP_PAIR_STATE_ACTIVE
8083  char pair_name[32];
8086 };
8087 
8088 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
8096  #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_VF2FN 0x0UL
8097  #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN 0x1UL
8098  #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2REP 0x2UL
8099  #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_PROXY 0x3UL
8100  #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_PFPAIR 0x4UL
8101  #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MOD 0x5UL
8102  #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MODALL 0x6UL
8103  #define CFA_PAIR_ALLOC_REQ_PAIR_MODE_LAST CFA_PAIR_ALLOC_REQ_PAIR_MODE_REP2FN_MODALL
8113  #define CFA_PAIR_ALLOC_REQ_ENABLES_Q_AB_VALID 0x1UL
8114  #define CFA_PAIR_ALLOC_REQ_ENABLES_Q_BA_VALID 0x2UL
8115  #define CFA_PAIR_ALLOC_REQ_ENABLES_FC_AB_VALID 0x4UL
8116  #define CFA_PAIR_ALLOC_REQ_ENABLES_FC_BA_VALID 0x8UL
8117  char pair_name[32];
8123 };
8124 
8125 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
8137 };
8138 
8139 /* hwrm_cfa_pair_free_input (size:384b/48B) */
8146  char pair_name[32];
8147 };
8148 
8149 /* hwrm_cfa_pair_free_output (size:128b/16B) */
8157 };
8158 
8159 /* hwrm_cfa_pair_info_input (size:448b/56B) */
8167  #define CFA_PAIR_INFO_REQ_FLAGS_LOOKUP_TYPE 0x1UL
8168  #define CFA_PAIR_INFO_REQ_FLAGS_LOOKUP_REPRE 0x2UL
8172  char pair_name[32];
8173 };
8174 
8175 /* hwrm_cfa_pair_info_output (size:576b/72B) */
8195  #define CFA_PAIR_INFO_RESP_PAIR_MODE_VF2FN 0x0UL
8196  #define CFA_PAIR_INFO_RESP_PAIR_MODE_REP2FN 0x1UL
8197  #define CFA_PAIR_INFO_RESP_PAIR_MODE_REP2REP 0x2UL
8198  #define CFA_PAIR_INFO_RESP_PAIR_MODE_PROXY 0x3UL
8199  #define CFA_PAIR_INFO_RESP_PAIR_MODE_PFPAIR 0x4UL
8200  #define CFA_PAIR_INFO_RESP_PAIR_MODE_LAST CFA_PAIR_INFO_RESP_PAIR_MODE_PFPAIR
8202  #define CFA_PAIR_INFO_RESP_PAIR_STATE_ALLOCATED 0x1UL
8203  #define CFA_PAIR_INFO_RESP_PAIR_STATE_ACTIVE 0x2UL
8204  #define CFA_PAIR_INFO_RESP_PAIR_STATE_LAST CFA_PAIR_INFO_RESP_PAIR_STATE_ACTIVE
8205  char pair_name[32];
8208 };
8209 
8210 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
8220  char vfr_name[32];
8221 };
8222 
8223 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
8233 };
8234 
8235 /* hwrm_cfa_vfr_free_input (size:384b/48B) */
8242  char vfr_name[32];
8243 };
8244 
8245 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
8253 };
8254 
8255 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
8264 };
8265 
8266 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
8273  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_NONTUNNEL 0x1UL
8274  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_VXLAN 0x2UL
8275  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_NVGRE 0x4UL
8276  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_L2GRE 0x8UL
8277  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPIP 0x10UL
8278  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_GENEVE 0x20UL
8279  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_MPLS 0x40UL
8280  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_STT 0x80UL
8281  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPGRE 0x100UL
8282  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_VXLAN_V4 0x200UL
8283  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_IPGRE_V1 0x400UL
8284  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_ANYTUNNEL 0x800UL
8285  #define CFA_REDIRECT_QUERY_TUNNEL_TYPE_RESP_TUNNEL_MASK_L2_ETYPE 0x1000UL
8288 };
8289 
8290 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
8298  #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8299  #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8300  #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8301  #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8302  #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8303  #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE
8305 };
8306 
8307 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
8317 };
8318 
8319 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
8327  #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8328  #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8329  #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8330  #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8331  #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8332  #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE
8336 };
8337 
8338 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
8347 };
8348 
8349 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
8357  #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8358  #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8359  #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8360  #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8361  #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8362  #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE
8366 };
8367 
8368 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
8376 };
8377 
8378 /* ctx_hw_stats (size:1280b/160B) */
8400 };
8401 
8402 /* ctx_eng_stats (size:512b/64B) */
8412 };
8413 
8414 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
8424  #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
8426 };
8427 
8428 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
8437 };
8438 
8439 /* hwrm_stat_ctx_free_input (size:192b/24B) */
8448 };
8449 
8450 /* hwrm_stat_ctx_free_output (size:128b/16B) */
8459 };
8460 
8461 /* hwrm_stat_ctx_query_input (size:192b/24B) */
8470 };
8471 
8472 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
8500 };
8501 
8502 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
8511 };
8512 
8513 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
8529 };
8530 
8531 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
8540 };
8541 
8542 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
8550 };
8551 
8552 /* hwrm_pcie_qstats_input (size:256b/32B) */
8562 };
8563 
8564 /* hwrm_pcie_qstats_output (size:128b/16B) */
8573 };
8574 
8575 /* pcie_ctx_hw_stats (size:768b/96B) */
8588 };
8589 
8590 /* hwrm_fw_reset_input (size:192b/24B) */
8598  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
8599  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
8600  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
8601  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
8602  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
8603  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
8604  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
8605  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
8606  #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
8608  #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
8609  #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
8610  #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8611  #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
8612  #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
8615  #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
8617 };
8618 
8619 /* hwrm_fw_reset_output (size:128b/16B) */
8626  #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
8627  #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
8628  #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8629  #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
8630  #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
8633 };
8634 
8635 /* hwrm_fw_qstatus_input (size:192b/24B) */
8643  #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
8644  #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
8645  #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
8646  #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
8647  #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
8648  #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
8649  #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
8650  #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
8652 };
8653 
8654 /* hwrm_fw_qstatus_output (size:128b/16B) */
8661  #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
8662  #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
8663  #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8664  #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST
8667 };
8668 
8669 /* hwrm_fw_set_time_input (size:256b/32B) */
8677  #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
8678  #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
8687  #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL
8688  #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL
8689  #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
8691 };
8692 
8693 /* hwrm_fw_set_time_output (size:128b/16B) */
8701 };
8702 
8703 /* hwrm_fw_get_time_input (size:128b/16B) */
8710 };
8711 
8712 /* hwrm_fw_get_time_output (size:192b/24B) */
8719  #define FW_GET_TIME_RESP_YEAR_UNKNOWN 0x0UL
8720  #define FW_GET_TIME_RESP_YEAR_LAST FW_GET_TIME_RESP_YEAR_UNKNOWN
8729  #define FW_GET_TIME_RESP_ZONE_UTC 0x0UL
8730  #define FW_GET_TIME_RESP_ZONE_UNKNOWN 0xffffUL
8731  #define FW_GET_TIME_RESP_ZONE_LAST FW_GET_TIME_RESP_ZONE_UNKNOWN
8734 };
8735 
8736 /* hwrm_struct_hdr (size:128b/16B) */
8739  #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
8740  #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
8741  #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
8742  #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
8743  #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
8744  #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
8745  #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
8746  #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
8747  #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
8748  #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
8749  #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
8750  #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2
8756  #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
8758 };
8759 
8760 /* hwrm_struct_data_dcbx_ets (size:256b/32B) */
8763  #define STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION 0x1UL
8764  #define STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION 0x2UL
8765  #define STRUCT_DATA_DCBX_ETS_DESTINATION_LAST STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION
8785  #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP 0x0UL
8786  #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS 0x1UL
8787  #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS 0x2UL
8788  #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC 0xffUL
8789  #define STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_LAST STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC
8798 };
8799 
8800 /* hwrm_struct_data_dcbx_pfc (size:64b/8B) */
8806 };
8807 
8808 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
8812  #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
8813  #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
8814  #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
8815  #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
8816  #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
8820 };
8821 
8822 /* hwrm_struct_data_dcbx_feature_state (size:64b/8B) */
8825  #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED 0x0UL
8826  #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE 0x1UL
8827  #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE 0x2UL
8828  #define STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_LAST STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE
8832  #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS 0x7UL
8833  #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS 0x6UL
8834  #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS 0x5UL
8835  #define STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_LAST STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS
8838  #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS 0x1UL
8839  #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC 0x2UL
8840  #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP 0x4UL
8841  #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE 0x8UL
8842  #define STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_LAST STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE
8843 };
8844 
8845 /* hwrm_struct_data_lldp (size:64b/8B) */
8848  #define STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE 0x0UL
8849  #define STRUCT_DATA_LLDP_ADMIN_STATE_TX 0x1UL
8850  #define STRUCT_DATA_LLDP_ADMIN_STATE_RX 0x2UL
8851  #define STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE 0x3UL
8852  #define STRUCT_DATA_LLDP_ADMIN_STATE_LAST STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE
8854  #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE 0x0UL
8855  #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE 0x1UL
8856  #define STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_LAST STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE
8858  #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE 0x0UL
8859  #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE 0x1UL
8860  #define STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_LAST STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE
8862  #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE 0x0UL
8863  #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE 0x1UL
8864  #define STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_LAST STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE
8866  #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE 0x0UL
8867  #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE 0x1UL
8868  #define STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_LAST STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE
8870  #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE 0x0UL
8871  #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE 0x1UL
8872  #define STRUCT_DATA_LLDP_MGMT_ADDR_STATE_LAST STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE
8874  #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE 0x0UL
8875  #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE 0x1UL
8876  #define STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_LAST STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE
8878 };
8879 
8880 /* hwrm_struct_data_lldp_generic (size:2112b/264B) */
8883  #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS 0x1UL
8884  #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT 0x2UL
8885  #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME 0x3UL
8886  #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION 0x4UL
8887  #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME 0x5UL
8888  #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION 0x6UL
8889  #define STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_LAST STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION
8894 };
8895 
8896 /* hwrm_struct_data_lldp_device (size:1472b/184B) */
8910 };
8911 
8912 /* hwrm_struct_data_port_description (size:64b/8B) */
8916 };
8917 
8918 /* hwrm_struct_data_rss_v2 (size:128b/16B) */
8921  #define STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID 0x1UL
8925  #define STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4 0x1UL
8926  #define STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4 0x2UL
8927  #define STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4 0x4UL
8928  #define STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6 0x8UL
8929  #define STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6 0x10UL
8930  #define STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6 0x20UL
8932 };
8933 
8934 /* hwrm_struct_data_power_information (size:192b/24B) */
8942 };
8943 
8944 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
8955 };
8956 
8957 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
8965 };
8966 
8967 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
8970  #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
8971  #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
8972  #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
8973  #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
8974  #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
8976 };
8977 
8978 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
8989  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
8990  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
8991  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
8992  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
8993  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
8994  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
8995  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
8996  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
8997  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
8998  #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
9001 };
9002 
9003 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
9012 };
9013 
9014 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
9017  #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
9018  #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
9019  #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
9021 };
9022 
9023 /* hwrm_fw_ipc_msg_input (size:320b/40B) */
9031  #define FW_IPC_MSG_REQ_ENABLES_COMMAND_ID 0x1UL
9032  #define FW_IPC_MSG_REQ_ENABLES_SRC_PROCESSOR 0x2UL
9033  #define FW_IPC_MSG_REQ_ENABLES_DATA_OFFSET 0x4UL
9034  #define FW_IPC_MSG_REQ_ENABLES_LENGTH 0x8UL
9036  #define FW_IPC_MSG_REQ_COMMAND_ID_ROCE_LAG 0x1UL
9037  #define FW_IPC_MSG_REQ_COMMAND_ID_LAST FW_IPC_MSG_REQ_COMMAND_ID_ROCE_LAG
9039  #define FW_IPC_MSG_REQ_SRC_PROCESSOR_CFW 0x1UL
9040  #define FW_IPC_MSG_REQ_SRC_PROCESSOR_BONO 0x2UL
9041  #define FW_IPC_MSG_REQ_SRC_PROCESSOR_APE 0x3UL
9042  #define FW_IPC_MSG_REQ_SRC_PROCESSOR_KONG 0x4UL
9043  #define FW_IPC_MSG_REQ_SRC_PROCESSOR_LAST FW_IPC_MSG_REQ_SRC_PROCESSOR_KONG
9049 };
9050 
9051 /* hwrm_fw_ipc_msg_output (size:128b/16B) */
9059 };
9060 
9061 /* hwrm_fw_ipc_mailbox_input (size:256b/32B) */
9075 };
9076 
9077 /* hwrm_fw_ipc_mailbox_output (size:128b/16B) */
9085 };
9086 
9087 /* hwrm_fw_ipc_mailbox_cmd_err (size:64b/8B) */
9090  #define FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN 0x0UL
9091  #define FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID 0x3UL
9092  #define FW_IPC_MAILBOX_CMD_ERR_CODE_LAST FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID
9094 };
9095 
9096 /* hwrm_fw_health_check_input (size:128b/16B) */
9103 };
9104 
9105 /* hwrm_fw_health_check_output (size:128b/16B) */
9112  #define FW_HEALTH_CHECK_RESP_FW_STATUS_SBI_BOOTED 0x1UL
9113  #define FW_HEALTH_CHECK_RESP_FW_STATUS_SBI_MISMATCH 0x2UL
9114  #define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT_BOOTED 0x4UL
9115  #define FW_HEALTH_CHECK_RESP_FW_STATUS_SRT_MISMATCH 0x8UL
9116  #define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT_BOOTED 0x10UL
9117  #define FW_HEALTH_CHECK_RESP_FW_STATUS_CRT_MISMATCH 0x20UL
9118  #define FW_HEALTH_CHECK_RESP_FW_STATUS_SECOND_RT 0x40UL
9121 };
9122 
9123 /* hwrm_fw_sync_input (size:192b/24B) */
9131  #define FW_SYNC_REQ_SYNC_ACTION_SYNC_SBI 0x1UL
9132  #define FW_SYNC_REQ_SYNC_ACTION_SYNC_SRT 0x2UL
9133  #define FW_SYNC_REQ_SYNC_ACTION_SYNC_CRT 0x4UL
9134  #define FW_SYNC_REQ_SYNC_ACTION_ACTION 0x80000000UL
9136 };
9137 
9138 /* hwrm_fw_sync_output (size:128b/16B) */
9145  #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_MASK 0xffUL
9146  #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_SFT 0
9147  #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_SUCCESS 0x0UL
9148  #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_IN_PROGRESS 0x1UL
9149  #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_TIMEOUT 0x2UL
9150  #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_GENERAL 0x3UL
9151  #define FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_LAST FW_SYNC_RESP_SYNC_STATUS_ERR_CODE_GENERAL
9152  #define FW_SYNC_RESP_SYNC_STATUS_SYNC_ERR 0x40000000UL
9153  #define FW_SYNC_RESP_SYNC_STATUS_SYNC_COMPLETE 0x80000000UL
9156 };
9157 
9158 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
9168 };
9169 
9170 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
9178 };
9179 
9180 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
9190 };
9191 
9192 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
9200 };
9201 
9202 /* hwrm_fwd_resp_input (size:1024b/128B) */
9216 };
9217 
9218 /* hwrm_fwd_resp_output (size:128b/16B) */
9226 };
9227 
9228 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
9238 };
9239 
9240 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
9248 };
9249 
9250 /* hwrm_temp_monitor_query_input (size:128b/16B) */
9257 };
9258 
9259 /* hwrm_temp_monitor_query_output (size:128b/16B) */
9268 };
9269 
9270 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
9279  #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
9280  #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
9281  #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
9282  #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
9283  #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
9284  #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
9287  #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
9288  #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
9289  #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
9290  #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
9299 };
9300 
9301 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
9310 };
9311 
9312 /* hwrm_wol_filter_free_input (size:256b/32B) */
9320  #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
9322  #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
9326 };
9327 
9328 /* hwrm_wol_filter_free_output (size:128b/16B) */
9336 };
9337 
9338 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
9354 };
9355 
9356 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
9365  #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
9366  #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
9367  #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
9368  #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
9376 };
9377 
9378 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
9390 };
9391 
9392 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
9400  #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
9401  #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
9402  #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
9403  #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
9407 };
9408 
9409 /* hwrm_dbg_read_direct_input (size:256b/32B) */
9419 };
9420 
9421 /* hwrm_dbg_read_direct_output (size:128b/16B) */
9429 };
9430 
9431 /* hwrm_dbg_write_direct_input (size:448b/56B) */
9441 };
9442 
9443 /* hwrm_dbg_write_direct_output (size:128b/16B) */
9451 };
9452 
9453 /* hwrm_dbg_read_indirect_input (size:320b/40B) */
9463  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 0x0UL
9464  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 0x1UL
9465  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 0x2UL
9466  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 0x3UL
9467  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_STAT_CTXS 0x4UL
9468  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM 0x5UL
9469  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM 0x6UL
9470  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM 0x7UL
9471  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM 0x8UL
9472  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM 0x9UL
9473  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM 0xaUL
9474  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM 0xbUL
9475  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM 0xcUL
9476  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM 0xdUL
9477  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM 0xeUL
9478  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM 0xfUL
9479  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MHB 0x10UL
9480  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_PCIE_GBL 0x11UL
9481  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC 0x12UL
9482  #define DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_LAST DBG_READ_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC
9486 };
9487 
9488 /* hwrm_dbg_read_indirect_output (size:128b/16B) */
9496 };
9497 
9498 /* hwrm_dbg_write_indirect_input (size:512b/64B) */
9506  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 0x0UL
9507  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 0x1UL
9508  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 0x2UL
9509  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 0x3UL
9510  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_STAT_CTXS 0x4UL
9511  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM 0x5UL
9512  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM 0x6UL
9513  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM 0x7UL
9514  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM 0x8UL
9515  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM 0x9UL
9516  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM 0xaUL
9517  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM 0xbUL
9518  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM 0xcUL
9519  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM 0xdUL
9520  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM 0xeUL
9521  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM 0xfUL
9522  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MHB 0x10UL
9523  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_PCIE_GBL 0x11UL
9524  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC 0x12UL
9525  #define DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_LAST DBG_WRITE_INDIRECT_REQ_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC
9531 };
9532 
9533 /* hwrm_dbg_write_indirect_output (size:128b/16B) */
9541 };
9542 
9543 /* hwrm_dbg_dump_input (size:320b/40B) */
9554 };
9555 
9556 /* hwrm_dbg_dump_output (size:192b/24B) */
9566 };
9567 
9568 /* hwrm_dbg_erase_nvm_input (size:192b/24B) */
9576  #define DBG_ERASE_NVM_REQ_FLAGS_ERASE_ALL 0x1UL
9578 };
9579 
9580 /* hwrm_dbg_erase_nvm_output (size:128b/16B) */
9588 };
9589 
9590 /* hwrm_dbg_cfg_input (size:192b/24B) */
9598  #define DBG_CFG_REQ_FLAGS_UART_LOG 0x1UL
9599  #define DBG_CFG_REQ_FLAGS_UART_LOG_SECONDARY 0x2UL
9601 };
9602 
9603 /* hwrm_dbg_cfg_output (size:128b/16B) */
9611 };
9612 
9613 /* coredump_segment_record (size:128b/16B) */
9622 };
9623 
9624 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
9635 };
9636 
9637 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
9644  #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
9650 };
9651 
9652 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
9665 };
9666 
9667 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
9675 };
9676 
9677 /* coredump_data_hdr (size:128b/16B) */
9683 };
9684 
9685 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
9705 };
9706 
9707 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
9714  #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
9719 };
9720 
9721 /* hwrm_dbg_i2c_cmd_input (size:320b/40B) */
9733  #define DBG_I2C_CMD_REQ_OPTIONS_10_BIT_ADDRESSING 0x1UL
9734  #define DBG_I2C_CMD_REQ_OPTIONS_FAST_MODE 0x2UL
9737  #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_READ 0x0UL
9738  #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE 0x1UL
9739  #define DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE_READ 0x2UL
9740  #define DBG_I2C_CMD_REQ_XFER_MODE_LAST DBG_I2C_CMD_REQ_XFER_MODE_MASTER_WRITE_READ
9742 };
9743 
9744 /* hwrm_dbg_i2c_cmd_output (size:128b/16B) */
9752 };
9753 
9754 /* hwrm_dbg_fw_cli_input (size:1024b/128B) */
9766 };
9767 
9768 /* hwrm_dbg_fw_cli_output (size:128b/16B) */
9777 };
9778 
9779 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */
9787  #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
9788  #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL
9789  #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL
9790  #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX
9793 };
9794 
9795 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */
9805 };
9806 
9807 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
9817 };
9818 
9819 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
9827 };
9828 
9829 /* hwrm_nvm_read_input (size:320b/40B) */
9842 };
9843 
9844 /* hwrm_nvm_read_output (size:128b/16B) */
9852 };
9853 
9854 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
9864 };
9865 
9866 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
9874 };
9875 
9876 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
9884 };
9885 
9886 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
9894 };
9895 
9896 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
9903 };
9904 
9905 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
9915 };
9916 
9917 /* hwrm_nvm_write_input (size:384b/48B) */
9932  #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
9935 };
9936 
9937 /* hwrm_nvm_write_output (size:128b/16B) */
9947 };
9948 
9949 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
9952  #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
9953  #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
9954  #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
9955  #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE
9957 };
9958 
9959 /* hwrm_nvm_modify_input (size:320b/40B) */
9972 };
9973 
9974 /* hwrm_nvm_modify_output (size:128b/16B) */
9982 };
9983 
9984 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
9992  #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
9998  #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
9999  #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
10000  #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
10001  #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
10002  #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
10003  #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
10005 };
10006 
10007 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
10020 };
10021 
10022 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
10031 };
10032 
10033 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
10041 };
10042 
10043 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
10050 };
10051 
10052 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
10066 };
10067 
10068 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
10076  #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
10082 };
10083 
10084 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
10092 };
10093 
10094 /* hwrm_nvm_verify_update_input (size:192b/24B) */
10105 };
10106 
10107 /* hwrm_nvm_verify_update_output (size:128b/16B) */
10115 };
10116 
10117 /* hwrm_nvm_install_update_input (size:192b/24B) */
10125  #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
10126  #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
10127  #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
10129  #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
10130  #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
10131  #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
10133 };
10134 
10135 /* hwrm_nvm_install_update_output (size:192b/24B) */
10143  #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
10144  #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
10146  #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
10147  #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
10148  #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
10150  #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
10151  #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
10152  #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
10153  #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
10156 };
10157 
10158 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
10161  #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
10162  #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
10163  #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
10164  #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
10166 };
10167 
10168 /* hwrm_nvm_flush_input (size:128b/16B) */
10175 };
10176 
10177 /* hwrm_nvm_flush_output (size:128b/16B) */
10185 };
10186 
10187 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
10190  #define NVM_FLUSH_CMD_ERR_CODE_UNKNOWN 0x0UL
10191  #define NVM_FLUSH_CMD_ERR_CODE_FAIL 0x1UL
10192  #define NVM_FLUSH_CMD_ERR_CODE_LAST NVM_FLUSH_CMD_ERR_CODE_FAIL
10194 };
10195 
10196 /* hwrm_nvm_get_variable_input (size:320b/40B) */
10206  #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
10207  #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
10208  #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
10215  #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
10217 };
10218 
10219 /* hwrm_nvm_get_variable_output (size:128b/16B) */
10227  #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
10228  #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
10229  #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
10232 };
10233 
10234 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
10237  #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
10238  #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
10239  #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
10240  #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
10241  #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
10243 };
10244 
10245 /* hwrm_nvm_set_variable_input (size:320b/40B) */
10255  #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
10256  #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
10257  #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
10264  #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
10265  #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
10266  #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
10267  #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
10268  #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
10269  #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
10270  #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
10271  #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
10273 };
10274 
10275 /* hwrm_nvm_set_variable_output (size:128b/16B) */
10283 };
10284 
10285 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
10288  #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
10289  #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
10290  #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
10291  #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
10293 };
10294 
10295 /* hwrm_nvm_validate_option_input (size:320b/40B) */
10305  #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_0 0x0UL
10306  #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
10307  #define NVM_VALIDATE_OPTION_REQ_OPTION_NUM_LAST NVM_VALIDATE_OPTION_REQ_OPTION_NUM_RSVD_FFFF
10314 };
10315 
10316 /* hwrm_nvm_validate_option_output (size:128b/16B) */
10323  #define NVM_VALIDATE_OPTION_RESP_RESULT_NOT_MATCH 0x0UL
10324  #define NVM_VALIDATE_OPTION_RESP_RESULT_MATCH 0x1UL
10325  #define NVM_VALIDATE_OPTION_RESP_RESULT_LAST NVM_VALIDATE_OPTION_RESP_RESULT_MATCH
10328 };
10329 
10330 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
10333  #define NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN 0x0UL
10334  #define NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
10336 };
10337 
10338 /* hwrm_nvm_factory_defaults_input (size:192b/24B) */
10346  #define NVM_FACTORY_DEFAULTS_REQ_MODE_RESTORE 0x0UL
10347  #define NVM_FACTORY_DEFAULTS_REQ_MODE_CREATE 0x1UL
10348  #define NVM_FACTORY_DEFAULTS_REQ_MODE_LAST NVM_FACTORY_DEFAULTS_REQ_MODE_CREATE
10350 };
10351 
10352 /* hwrm_nvm_factory_defaults_output (size:128b/16B) */
10359  #define NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_OK 0x0UL
10360  #define NVM_FACTORY_DEFAULTS_RESP_RESULT_RESTORE_OK 0x1UL
10361  #define NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_ALREADY 0x2UL
10362  #define NVM_FACTORY_DEFAULTS_RESP_RESULT_LAST NVM_FACTORY_DEFAULTS_RESP_RESULT_CREATE_ALREADY
10365 };
10366 
10367 /* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */
10370  #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN 0x0UL
10371  #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG 0x1UL
10372  #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG 0x2UL
10373  #define NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG
10375 };
10376 
10377 /* hwrm_selftest_qlist_input (size:128b/16B) */
10384 };
10385 
10386 /* hwrm_selftest_qlist_output (size:2240b/280B) */
10394  #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
10395  #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
10396  #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
10397  #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
10398  #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
10399  #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
10401  #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
10402  #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
10403  #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
10404  #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
10405  #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
10406  #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
10410  char test0_name[32];
10411  char test1_name[32];
10412  char test2_name[32];
10413  char test3_name[32];
10414  char test4_name[32];
10415  char test5_name[32];
10416  char test6_name[32];
10417  char test7_name[32];
10420 };
10421 
10422 /* hwrm_selftest_exec_input (size:192b/24B) */
10430  #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
10431  #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
10432  #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
10433  #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
10434  #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
10435  #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
10437 };
10438 
10439 /* hwrm_selftest_exec_output (size:128b/16B) */
10446  #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
10447  #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
10448  #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
10449  #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
10450  #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
10451  #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
10453  #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
10454  #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
10455  #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
10456  #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
10457  #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
10458  #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
10461 };
10462 
10463 /* hwrm_selftest_irq_input (size:128b/16B) */
10470 };
10471 
10472 /* hwrm_selftest_irq_output (size:128b/16B) */
10480 };
10481 
10482 /* hwrm_selftest_retrieve_serdes_data_input (size:256b/32B) */
10493  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_MASK 0x7UL
10494  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_SFT 0
10495  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_EYE_PROJECTION 0x8UL
10496  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
10497  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
10499  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PCIE_LANE_NO_MASK 0xfUL
10500  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PCIE_LANE_NO_SFT 0
10501  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION 0x10UL
10502  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_HORIZONTAL (0x0UL << 4)
10503  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_VERTICAL (0x1UL << 4)
10504  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_LAST SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_DIRECTION_VERTICAL
10505  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE 0x20UL
10506  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_LEFT_TOP (0x0UL << 5)
10507  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM (0x1UL << 5)
10508  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_LAST SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM
10509  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_RSVD_MASK 0xc0UL
10510  #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_OPTIONS_RSVD_SFT 6
10511 };
10512 
10513 /* hwrm_selftest_retrieve_serdes_data_output (size:128b/16B) */
10523 };
10524 
10525 /* hwrm_oem_cmd_input (size:1024b/128B) */
10535 };
10536 
10537 /* hwrm_oem_cmd_output (size:1344b/168B) */
10548 };
10549 
10550 #endif /* _BNXT_HSI_H_ */
__le64 resp_addr
Definition: bnxt_hsi.h:9990
__le32 oem_data[36]
Definition: bnxt_hsi.h:10545
u8 valid
Definition: bnxt_hsi.h:10019
__le64 tx_eee_lpi_duration
Definition: bnxt_hsi.h:3736
__le64 rx_llfc_physical_msgs
Definition: bnxt_hsi.h:3804
__le16 tlv_type
Definition: bnxt_hsi.h:63
__le64 tx_late_coll_frames
Definition: bnxt_hsi.h:3719
__le16 dir_ext
Definition: bnxt_hsi.h:10079
__le64 rx_packets_cos0
Definition: bnxt_hsi.h:3892
__le64 tx_packets_cos0
Definition: bnxt_hsi.h:3851
uint32_t __le32
Definition: efx_common.h:30
__le64 tx_fcs_err_frames
Definition: bnxt_hsi.h:3712
__le64 tx_dbl_tagged_frames
Definition: bnxt_hsi.h:3724
__le64 tx_128b_255b_frames
Definition: bnxt_hsi.h:3695
__le64 rx_pfc_ena_frames_pri5
Definition: bnxt_hsi.h:3796
__le64 tx_1519b_2047b_frames
Definition: bnxt_hsi.h:3700
__le16 hwrm_fw_major
Definition: bnxt_hsi.h:450
__le64 continuous_roce_pause_events
Definition: bnxt_hsi.h:3882
__le64 tx_bytes_cos1
Definition: bnxt_hsi.h:3844
__le64 resume_pause_events
Definition: bnxt_hsi.h:3881
__le64 rx_pfc_ena_frames_pri1
Definition: bnxt_hsi.h:3792
__le32 next_offset
Definition: bnxt_hsi.h:9682
__le64 rx_fcs_err_frames
Definition: bnxt_hsi.h:3763
__le64 pfc_pri0_tx_transitions
Definition: bnxt_hsi.h:3860
__le32 unused_3
Definition: bnxt_hsi.h:509
__le16 dir_idx
Definition: bnxt_hsi.h:10077
__le64 pfc_pri7_rx_transitions
Definition: bnxt_hsi.h:3915
__le16 auto_link_pam4_speed_mask
Definition: bnxt_hsi.h:3073
__le16 hwrm_intf_minor
Definition: bnxt_hsi.h:447
__le16 seq_id
Definition: bnxt_hsi.h:29
__le16 error_code
Definition: bnxt_hsi.h:329
__le32 req_buf_addr_v[2]
Definition: bnxt_hsi.h:523
__le32 fw_ver
Definition: bnxt_hsi.h:10015
__le16 target_id
Definition: bnxt_hsi.h:10073
__le64 tx_pfc_ena_frames_pri0
Definition: bnxt_hsi.h:3727
__le64 pfc_pri5_tx_transitions
Definition: bnxt_hsi.h:3870
__le64 tx_drop_pkts
Definition: bnxt_hsi.h:8392
__le16 seq_id
Definition: bnxt_hsi.h:71
__le64 rx_bytes_cos5
Definition: bnxt_hsi.h:3889
__le64 rx_unsupported_opcode_frames
Definition: bnxt_hsi.h:3767
__le16 seq_id
Definition: bnxt_hsi.h:10011
__le16 def_req_timeout
Definition: bnxt_hsi.h:440
__le16 reserved16
Definition: bnxt_hsi.h:494
__le64 rx_4096b_9216b_frames
Definition: bnxt_hsi.h:3757
__le64 resp_addr
Definition: bnxt_hsi.h:10028
__le64 tx_pfc_ena_frames_pri5
Definition: bnxt_hsi.h:3732
__le64 pfc_pri2_tx_duration_us
Definition: bnxt_hsi.h:3863
__le16 resp_len
Definition: bnxt_hsi.h:10038
__le16 error_code
Definition: bnxt_hsi.h:78
__le64 rx_65b_127b_frames
Definition: bnxt_hsi.h:3749
__le64 pcie_tl_signal_integrity
Definition: bnxt_hsi.h:8579
__le64 rx_pfc_xon2xoff_frames_pri3
Definition: bnxt_hsi.h:3786
__le32 dir_data_length
Definition: bnxt_hsi.h:10014
__le16 signature
Definition: bnxt_hsi.h:87
Definition: bnxt_hsi.h:10069
__le64 tx_err
Definition: bnxt_hsi.h:3722
__le16 unused_0[3]
Definition: bnxt_hsi.h:347
__le32 encap_resp[24]
Definition: bnxt_hsi.h:9215
__le16 resp_len
Definition: bnxt_hsi.h:10089
Definition: bnxt_hsi.h:9985
__le16 mgmt_fw_major
Definition: bnxt_hsi.h:454
__le16 resp_len
Definition: bnxt_hsi.h:81
__le64 tx_pfc_ena_frames_pri4
Definition: bnxt_hsi.h:3731
__le16 subtype
Definition: bnxt_hsi.h:8754
__le16 dir_idx
Definition: bnxt_hsi.h:10017
__le64 rx_9217b_16383b_frames
Definition: bnxt_hsi.h:3758
__le16 cmpl_ring
Definition: bnxt_hsi.h:10025
__le64 tx_pfc_ena_frames_pri7
Definition: bnxt_hsi.h:3734
__le16 dir_attr
Definition: bnxt_hsi.h:10080
__le64 tx_good_frames
Definition: bnxt_hsi.h:3704
__le64 hash_key_ring_group_ids
Definition: bnxt_hsi.h:8931
__le16 req_type
Definition: bnxt_hsi.h:86
__le64 rx_oor_len_frames
Definition: bnxt_hsi.h:3771
__le16 hwrm_fw_patch
Definition: bnxt_hsi.h:453
__le32 oem_data[26]
Definition: bnxt_hsi.h:10534
__le16 num_mcast_filters
Definition: bnxt_hsi.h:1625
__le16 target_id
Definition: bnxt_hsi.h:21
__le16 req_len_type
Definition: bnxt_hsi.h:514
__le16 seq_id
Definition: bnxt_hsi.h:80
__le64 pfc_pri3_rx_duration_us
Definition: bnxt_hsi.h:3906
__le64 tx_packets_cos2
Definition: bnxt_hsi.h:3853
__le16 link_partner_adv_eee_link_speed_mask
Definition: bnxt_hsi.h:3397
__le64 rx_pfc_xon2xoff_frames_pri1
Definition: bnxt_hsi.h:3784
Definition: bnxt_hsi.h:68
__le64 rx_stat_err
Definition: bnxt_hsi.h:3813
__le16 req_type
Definition: bnxt_hsi.h:9986
__le64 rx_pfc_ena_frames_pri7
Definition: bnxt_hsi.h:3798
__le64 rx_512b_1023b_frames
Definition: bnxt_hsi.h:3752
__le64 tx_packets_cos5
Definition: bnxt_hsi.h:3856
__le64 tx_xthol_frames
Definition: bnxt_hsi.h:3741
__le16 default_rx_ring_id
Definition: bnxt_hsi.h:5732
u8 unused_0[6]
Definition: bnxt_hsi.h:10030
u8 unused_0[7]
Definition: bnxt_hsi.h:10039
__le16 error_code
Definition: bnxt_hsi.h:10035
__le16 max_ext_req_len
Definition: bnxt_hsi.h:466
char hwrm_fw_name[16]
Definition: bnxt_hsi.h:424
__le16 length
Definition: bnxt_hsi.h:64
__le64 rx_bytes_cos1
Definition: bnxt_hsi.h:3885
__le16 target_id
Definition: bnxt_hsi.h:10027
__le64 tx_pause_frames
Definition: bnxt_hsi.h:3709
__le64 rx_llfc_msgs_with_crc_err
Definition: bnxt_hsi.h:3806
__le64 rx_pause_frames
Definition: bnxt_hsi.h:3765
__le16 seq_id
Definition: bnxt_hsi.h:9988
__le64 rx_hcfc_msgs_with_crc_err
Definition: bnxt_hsi.h:3808
__le64 rx_sch_crc_err_frames
Definition: bnxt_hsi.h:3799
__le16 seq_id
Definition: bnxt_hsi.h:10037
__le64 pfc_pri7_tx_duration_us
Definition: bnxt_hsi.h:3873
__le16 encap_resp_target_id
Definition: bnxt_hsi.h:9209
__le16 hwrm_fw_minor
Definition: bnxt_hsi.h:451
__le64 pfc_pri1_rx_transitions
Definition: bnxt_hsi.h:3903
Definition: bnxt_hsi.h:10034
__le64 pcie_rx_traffic_rate
Definition: bnxt_hsi.h:8582
__le64 rx_eee_lpi_events
Definition: bnxt_hsi.h:3802
__le16 next_offset
Definition: bnxt_hsi.h:8755
__le64 tx_bytes_cos6
Definition: bnxt_hsi.h:3849
__le64 rx_wrong_sa_frames
Definition: bnxt_hsi.h:3769
__le64 rx_pfc_ena_frames_pri0
Definition: bnxt_hsi.h:3791
__le64 tpa_bytes
Definition: bnxt_hsi.h:8397
__le16 unused_0
Definition: bnxt_hsi.h:90
__le64 rx_128b_255b_frames
Definition: bnxt_hsi.h:3750
__le64 tx_bcast_pkts
Definition: bnxt_hsi.h:8390
__le16 cmpl_ring
Definition: bnxt_hsi.h:19
__le32 flags_length
Definition: bnxt_hsi.h:9680
__le64 rx_ucast_bytes
Definition: bnxt_hsi.h:8385
__le64 tx_llfc_logical_msgs
Definition: bnxt_hsi.h:3737
u8 reserved_8b
Definition: bnxt_hsi.h:54
__le64 rx_pfc_ena_frames_pri6
Definition: bnxt_hsi.h:3797
__le64 tx_pfc_ena_frames_pri2
Definition: bnxt_hsi.h:3729
__le16 mgmt_fw_minor
Definition: bnxt_hsi.h:455
__le64 tpa_pkts
Definition: bnxt_hsi.h:8396
__le64 pfc_pri1_tx_duration_us
Definition: bnxt_hsi.h:3861
__le64 tx_frag_frames
Definition: bnxt_hsi.h:3721
__le16 netctrl_fw_patch
Definition: bnxt_hsi.h:461
__le64 rx_mtu_err_frames
Definition: bnxt_hsi.h:3776
__be32 dflt_ip_addr[4]
Definition: bnxt_hsi.h:1565
__le64 pcie_recovery_histogram
Definition: bnxt_hsi.h:8587
__le16 mgmt_fw_build
Definition: bnxt_hsi.h:456
__le64 tx_packets_cos4
Definition: bnxt_hsi.h:3855
__le64 tx_1024b_1518b_frames
Definition: bnxt_hsi.h:3698
__le64 resp_addr
Definition: bnxt_hsi.h:10074
__le64 resume_roce_pause_events
Definition: bnxt_hsi.h:3883
__le64 rx_bytes
Definition: bnxt_hsi.h:3809
__le16 netctrl_fw_minor
Definition: bnxt_hsi.h:459
__le64 rx_good_frames
Definition: bnxt_hsi.h:3782
__le64 rx_pfc_ena_frames_pri2
Definition: bnxt_hsi.h:3793
__le64 tx_ucast_frames
Definition: bnxt_hsi.h:3706
__le64 tx_4096b_9216b_frames
Definition: bnxt_hsi.h:3702
__le16 unused_0[3]
Definition: bnxt_hsi.h:324
__le64 rx_pfc_ena_frames_pri4
Definition: bnxt_hsi.h:3795
__le64 aux_bytes_out
Definition: bnxt_hsi.h:8407
__le16 dir_type
Definition: bnxt_hsi.h:9994
__le64 tx_packets_cos6
Definition: bnxt_hsi.h:3857
__le64 tx_2048b_4095b_frames
Definition: bnxt_hsi.h:3701
__le64 aux_bytes_in
Definition: bnxt_hsi.h:8406
__le16 dir_idx
Definition: bnxt_hsi.h:10029
__le64 rx_eee_lpi_duration
Definition: bnxt_hsi.h:3803
__le32 dir_item_length
Definition: bnxt_hsi.h:10013
__le64 tx_single_coll_frames
Definition: bnxt_hsi.h:3717
__le64 rx_packets_cos1
Definition: bnxt_hsi.h:3893
__le16 dir_ext
Definition: bnxt_hsi.h:9996
__le64 pfc_pri4_rx_duration_us
Definition: bnxt_hsi.h:3908
__le64 rx_packets_cos6
Definition: bnxt_hsi.h:3898
__le32 xcvr_identifier_type_tx_lpi_timer
Definition: bnxt_hsi.h:3405
__le16 roce_fw_build
Definition: bnxt_hsi.h:464
__le64 tpa_aborts
Definition: bnxt_hsi.h:8399
__le64 rx_pfc_xon2xoff_frames_pri2
Definition: bnxt_hsi.h:3785
__be32 dest_ip_addr[4]
Definition: bnxt_hsi.h:6886
__le64 tx_bytes
Definition: bnxt_hsi.h:3740
__le16 req_type
Definition: bnxt_hsi.h:10010
__le64 tx_total_collisions
Definition: bnxt_hsi.h:3739
__le32 enables
Definition: bnxt_hsi.h:9991
__le16 resp_len
Definition: bnxt_hsi.h:30
__le64 tx_256b_511b_frames
Definition: bnxt_hsi.h:3696
__le64 tx_bytes_cos4
Definition: bnxt_hsi.h:3847
__le64 tx_runt_frames
Definition: bnxt_hsi.h:3725
__le16 cmd_discr
Definition: bnxt_hsi.h:53
__le64 pfc_pri2_rx_transitions
Definition: bnxt_hsi.h:3905
__le16 target_id
Definition: bnxt_hsi.h:9989
__le64 rx_bcast_bytes
Definition: bnxt_hsi.h:8387
__le64 pfc_pri6_tx_transitions
Definition: bnxt_hsi.h:3872
__le16 encap_resp_cmpl_ring
Definition: bnxt_hsi.h:9210
__le64 host_dbg_dump_addr_len
Definition: bnxt_hsi.h:9553
Definition: bnxt_hsi.h:10023
__le64 tx_ucast_pkts
Definition: bnxt_hsi.h:8388
__le64 tx_eee_lpi_events
Definition: bnxt_hsi.h:3735
__le64 tx_bytes_cos2
Definition: bnxt_hsi.h:3845
__le32 unused_2
Definition: bnxt_hsi.h:495
__le16 dir_ordinal
Definition: bnxt_hsi.h:9995
__le64 tx_single_dfrl_frames
Definition: bnxt_hsi.h:3715
__le64 rx_bytes_cos7
Definition: bnxt_hsi.h:3891
__le64 rx_jbr_frames
Definition: bnxt_hsi.h:3775
Definition: bnxt_hsi.h:10085
__le64 resp_addr
Definition: bnxt_hsi.h:22
__le64 rx_llfc_logical_msgs
Definition: bnxt_hsi.h:3805
__le64 tpa_events
Definition: bnxt_hsi.h:8398
__le64 rx_tagged_frames
Definition: bnxt_hsi.h:3779
__le16 cmpl_ring
Definition: bnxt_hsi.h:70
__le16 req_type
Definition: bnxt_hsi.h:97
__le16 num_rsscos_ctxs
Definition: bnxt_hsi.h:1555
__le16 error_code
Definition: bnxt_hsi.h:10086
__le64 req_addr
Definition: bnxt_hsi.h:92
__le64 tx_pfc_frames
Definition: bnxt_hsi.h:3710
__le64 pfc_pri0_tx_duration_us
Definition: bnxt_hsi.h:3859
__le64 cdd_engine_usage
Definition: bnxt_hsi.h:8411
__le16 hwrm_intf_patch
Definition: bnxt_hsi.h:449
__le64 rx_bytes_cos6
Definition: bnxt_hsi.h:3890
__le64 tx_multi_dfrl_frames
Definition: bnxt_hsi.h:3716
__le16 default_cmpl_ring_id
Definition: bnxt_hsi.h:5733
__le64 rx_good_vlan_frames
Definition: bnxt_hsi.h:3754
__le64 pfc_pri7_tx_transitions
Definition: bnxt_hsi.h:3874
__le16 v
Definition: bnxt_hsi.h:483
__le64 pfc_pri3_tx_transitions
Definition: bnxt_hsi.h:3866
__le64 tx_mcast_frames
Definition: bnxt_hsi.h:3707
__le64 host_dbg_dump_addr
Definition: bnxt_hsi.h:9552
Definition: bnxt_hsi.h:10008
__le64 rx_256b_511b_frames
Definition: bnxt_hsi.h:3751
__le64 rx_bytes_cos0
Definition: bnxt_hsi.h:3884
__le64 error_commands
Definition: bnxt_hsi.h:8409
__le64 tx_good_vlan_frames
Definition: bnxt_hsi.h:3699
__le64 tx_fifo_underruns
Definition: bnxt_hsi.h:3726
__le16 req_type
Definition: bnxt_hsi.h:10070
__le16 req_type
Definition: bnxt_hsi.h:69
__le64 tx_tagged_frames
Definition: bnxt_hsi.h:3723
__le64 tx_total_frames
Definition: bnxt_hsi.h:3705
__le64 rx_ucast_frames
Definition: bnxt_hsi.h:3760
__le16 req_type
Definition: bnxt_hsi.h:18
__le64 rx_1024b_1518b_frames
Definition: bnxt_hsi.h:3753
__le16 dir_idx
Definition: bnxt_hsi.h:9993
__le64 rx_ucast_pkts
Definition: bnxt_hsi.h:8380
__le16 roce_fw_major
Definition: bnxt_hsi.h:462
u8 unused_0[3]
Definition: bnxt_hsi.h:10004
__le16 type
Definition: bnxt_hsi.h:500
__le64 rx_ovrsz_frames
Definition: bnxt_hsi.h:3774
__le64 pcie_tx_traffic_rate
Definition: bnxt_hsi.h:8581
__le64 pfc_pri2_rx_duration_us
Definition: bnxt_hsi.h:3904
__le64 tx_bytes_cos5
Definition: bnxt_hsi.h:3848
__le64 tx_packets_cos1
Definition: bnxt_hsi.h:3852
__le16 mgmt_fw_patch
Definition: bnxt_hsi.h:457
__le32 resp_buf_addr_v[2]
Definition: bnxt_hsi.h:539
__le32 enables
Definition: bnxt_hsi.h:10075
__le64 rx_mcast_frames
Definition: bnxt_hsi.h:3761
__le64 rx_false_carrier_frames
Definition: bnxt_hsi.h:3773
char netctrl_fw_name[16]
Definition: bnxt_hsi.h:426
__le64 rx_promiscuous_frames
Definition: bnxt_hsi.h:3778
__le64 tx_pfc_ena_frames_pri3
Definition: bnxt_hsi.h:3730
__le64 rx_packets_cos3
Definition: bnxt_hsi.h:3895
__le64 rx_mcast_bytes
Definition: bnxt_hsi.h:8386
__le64 rx_pfc_xon2xoff_frames_pri4
Definition: bnxt_hsi.h:3787
__le64 pfc_pri3_rx_transitions
Definition: bnxt_hsi.h:3907
__le64 pcie_pl_signal_integrity
Definition: bnxt_hsi.h:8577
__le64 rx_pfc_xon2xoff_frames_pri5
Definition: bnxt_hsi.h:3788
Definition: bnxt_hsi.h:52
__be16 flags_frag_offset
Definition: bnxt_hsi.h:6865
__le16 cmpl_ring
Definition: bnxt_hsi.h:10071
__le64 rx_bytes_cos2
Definition: bnxt_hsi.h:3886
__le64 rx_match_crc_frames
Definition: bnxt_hsi.h:3777
u8 opt_ordinal
Definition: bnxt_hsi.h:9997
__le16 source_id
Definition: bnxt_hsi.h:521
__le64 pfc_pri7_rx_duration_us
Definition: bnxt_hsi.h:3914
__le64 encap_resp_addr
Definition: bnxt_hsi.h:9214
char mgmt_fw_name[16]
Definition: bnxt_hsi.h:425
__le16 dir_ordinal
Definition: bnxt_hsi.h:10078
__le32 alloc_mcast_filters
Definition: bnxt_hsi.h:1488
__le16 hwrm_intf_build
Definition: bnxt_hsi.h:448
__le16 req_type
Definition: bnxt_hsi.h:10024
__le64 tx_512b_1023b_frames
Definition: bnxt_hsi.h:3697
__le32 unused_1
Definition: bnxt_hsi.h:506
__le16 req_type
Definition: bnxt_hsi.h:79
__le64 rx_pfc_ena_frames_pri3
Definition: bnxt_hsi.h:3794
__le64 rx_bytes_cos3
Definition: bnxt_hsi.h:3887
__le16 struct_id
Definition: bnxt_hsi.h:8738
__le64 pfc_pri0_rx_transitions
Definition: bnxt_hsi.h:3901
char phy_vendor_partnumber[16]
Definition: bnxt_hsi.h:3441
u8 valid
Definition: bnxt_hsi.h:10091
__le64 commands
Definition: bnxt_hsi.h:8408
__le16 roce_fw_minor
Definition: bnxt_hsi.h:463
__le16 error_code
Definition: bnxt_hsi.h:10009
u8 unused_0[7]
Definition: bnxt_hsi.h:10090
__le64 rx_packets_cos5
Definition: bnxt_hsi.h:3897
__le64 link_down_events
Definition: bnxt_hsi.h:3879
__le64 pfc_pri3_tx_duration_us
Definition: bnxt_hsi.h:3865
__le16 roce_fw_patch
Definition: bnxt_hsi.h:465
uint32_t __be32
Definition: CIB_PRM.h:26
__le16 tx_ts_capture_ptp_msg_type
Definition: bnxt_hsi.h:3553
__le16 opaque_1
Definition: bnxt_hsi.h:357
__le64 tx_65b_127b_frames
Definition: bnxt_hsi.h:3694
__le32 opaque
Definition: bnxt_hsi.h:482
__le64 pfc_pri2_tx_transitions
Definition: bnxt_hsi.h:3864
__le64 tx_bytes_cos7
Definition: bnxt_hsi.h:3850
__le64 tx_ucast_bytes
Definition: bnxt_hsi.h:8393
__le64 pcie_tx_dllp_statistics
Definition: bnxt_hsi.h:8583
__le64 pfc_pri5_tx_duration_us
Definition: bnxt_hsi.h:3869
__le64 tx_hcfc_msgs
Definition: bnxt_hsi.h:3738
__le16 req_type
Definition: bnxt_hsi.h:28
__le64 tx_mcast_bytes
Definition: bnxt_hsi.h:8394
__le64 tx_packets_cos7
Definition: bnxt_hsi.h:3858
__le64 tx_64b_frames
Definition: bnxt_hsi.h:3693
__le64 pfc_pri4_tx_transitions
Definition: bnxt_hsi.h:3868
__le16 num_hw_ring_grps
Definition: bnxt_hsi.h:1562
__le64 continuous_pause_events
Definition: bnxt_hsi.h:3880
__le64 pcie_rx_dllp_statistics
Definition: bnxt_hsi.h:8584
__le16 dir_ordinal
Definition: bnxt_hsi.h:10016
__le16 type
Definition: bnxt_hsi.h:473
u8 unused_0[7]
Definition: bnxt_hsi.h:10018
__le16 target_id
Definition: bnxt_hsi.h:72
__le64 tx_bcast_frames
Definition: bnxt_hsi.h:3708
__le16 cmpl_ring
Definition: bnxt_hsi.h:9987
__le64 pfc_pri1_tx_transitions
Definition: bnxt_hsi.h:3862
__le64 rx_packets_cos7
Definition: bnxt_hsi.h:3899
__le16 seq_id
Definition: bnxt_hsi.h:354
__le32 encap_request[26]
Definition: bnxt_hsi.h:9165
__le64 tx_packets_cos3
Definition: bnxt_hsi.h:3854
__le32 checksum
Definition: bnxt_hsi.h:10081
__le16 req_type
Definition: bnxt_hsi.h:353
__le64 resp_addr
Definition: bnxt_hsi.h:73
__le64 rx_trunc_frames
Definition: bnxt_hsi.h:3781
__le64 rx_align_err_frames
Definition: bnxt_hsi.h:3770
__le64 rx_double_tagged_frames
Definition: bnxt_hsi.h:3780
__le64 pfc_pri0_rx_duration_us
Definition: bnxt_hsi.h:3900
__le64 rx_1519b_2047b_frames
Definition: bnxt_hsi.h:3755
__le16 seq_id
Definition: bnxt_hsi.h:10072
char roce_fw_name[16]
Definition: bnxt_hsi.h:428
__le64 pcie_dl_signal_integrity
Definition: bnxt_hsi.h:8578
__le16 rx_ts_capture_ptp_msg_type
Definition: bnxt_hsi.h:3552
__le64 tx_bytes_cos0
Definition: bnxt_hsi.h:3843
__le64 pfc_pri4_tx_duration_us
Definition: bnxt_hsi.h:3867
__le64 tx_9217b_16383b_frames
Definition: bnxt_hsi.h:3703
__le64 tx_pfc_ena_frames_pri1
Definition: bnxt_hsi.h:3728
__le64 tx_bytes_cos3
Definition: bnxt_hsi.h:3846
__le64 rx_unsupported_da_pausepfc_frames
Definition: bnxt_hsi.h:3768
__le64 tx_multi_coll_frames
Definition: bnxt_hsi.h:3718
__le64 pcie_link_integrity
Definition: bnxt_hsi.h:8580
__le64 rx_drop_pkts
Definition: bnxt_hsi.h:8384
__le64 tx_stat_discard
Definition: bnxt_hsi.h:3742
__le16 seq_id
Definition: bnxt_hsi.h:10026
__le32 v
Definition: bnxt_hsi.h:507
__le64 rx_bytes_cos4
Definition: bnxt_hsi.h:3888
__le64 pfc_pri6_rx_duration_us
Definition: bnxt_hsi.h:3912
__le16 resp_len
Definition: bnxt_hsi.h:355
__le64 pfc_pri6_tx_duration_us
Definition: bnxt_hsi.h:3871
__le64 tx_discard_pkts
Definition: bnxt_hsi.h:8391
__le64 rx_pfc_xon2xoff_frames_pri0
Definition: bnxt_hsi.h:3783
u8 valid
Definition: bnxt_hsi.h:10040
__le16 netctrl_fw_build
Definition: bnxt_hsi.h:460
__le64 pcie_equalization_time
Definition: bnxt_hsi.h:8585
__le64 rx_hcfc_msgs
Definition: bnxt_hsi.h:3807
__le64 rx_total_frames
Definition: bnxt_hsi.h:3759
__le64 tx_pfc_ena_frames_pri6
Definition: bnxt_hsi.h:3733
__le64 rx_bcast_frames
Definition: bnxt_hsi.h:3762
__le64 rx_pfc_xon2xoff_frames_pri7
Definition: bnxt_hsi.h:3790
__le64 tx_excessive_coll_frames
Definition: bnxt_hsi.h:3720
__le64 rx_undrsz_frames
Definition: bnxt_hsi.h:3800
__le64 rx_mcast_pkts
Definition: bnxt_hsi.h:8381
__le16 seq_id
Definition: bnxt_hsi.h:10088
__le16 error_code
Definition: bnxt_hsi.h:27
__le16 len
Definition: bnxt_hsi.h:481
__le64 rx_packets_cos4
Definition: bnxt_hsi.h:3896
uint64_t __le64
Definition: efx_common.h:31
__le64 rx_pfc_xon2xoff_frames_pri6
Definition: bnxt_hsi.h:3789
__le16 error_code
Definition: bnxt_hsi.h:352
__le64 rx_frag_frames
Definition: bnxt_hsi.h:3801
__le16 supported_pam4_speeds_force_mode
Definition: bnxt_hsi.h:4127
__le64 pfc_pri5_rx_transitions
Definition: bnxt_hsi.h:3911
__le64 eng_bytes_out
Definition: bnxt_hsi.h:8405
__le64 tx_stat_error
Definition: bnxt_hsi.h:3743
__le16 seq_id
Definition: bnxt_hsi.h:20
__le16 req_type
Definition: bnxt_hsi.h:10087
__be32 ver_tc_flow_label
Definition: bnxt_hsi.h:6874
uint16_t __le16
Definition: efx_common.h:29
__le64 rx_packets_cos2
Definition: bnxt_hsi.h:3894
__le64 rx_runt_frames
Definition: bnxt_hsi.h:3811
__le64 tx_control_frames
Definition: bnxt_hsi.h:3713
__le64 rx_pfc_frames
Definition: bnxt_hsi.h:3766
u8 flags
Definition: bnxt_hsi.h:55
__le16 netctrl_fw_major
Definition: bnxt_hsi.h:458
__le16 supported_pam4_speeds_auto_mode
Definition: bnxt_hsi.h:4123
__le16 max_req_win_len
Definition: bnxt_hsi.h:438
__le64 pfc_pri6_rx_transitions
Definition: bnxt_hsi.h:3913
__le16 req_type
Definition: bnxt_hsi.h:10036
__le16 hwrm_fw_build
Definition: bnxt_hsi.h:452
__le16 resp_len
Definition: bnxt_hsi.h:10012
__le64 rx_2048b_4095b_frames
Definition: bnxt_hsi.h:3756
__le64 rx_bcast_pkts
Definition: bnxt_hsi.h:8382
__be32 src_ip_addr[4]
Definition: bnxt_hsi.h:6885
__le64 pfc_pri1_rx_duration_us
Definition: bnxt_hsi.h:3902
__le64 tx_mcast_pkts
Definition: bnxt_hsi.h:8389
__le64 pfc_pri4_rx_transitions
Definition: bnxt_hsi.h:3909
uint8_t u8
Definition: stdint.h:19
__le64 eng_bytes_in
Definition: bnxt_hsi.h:8404
__le64 cce_engine_usage
Definition: bnxt_hsi.h:8410
__le64 tx_jabber_frames
Definition: bnxt_hsi.h:3711
__le64 rx_code_err_frames
Definition: bnxt_hsi.h:3772
__le32 opaque_0
Definition: bnxt_hsi.h:356
__le64 rx_stat_discard
Definition: bnxt_hsi.h:3812
__le64 rx_ctrl_frames
Definition: bnxt_hsi.h:3764
__le16 sequence_id
Definition: bnxt_hsi.h:505
__le64 rx_runt_bytes
Definition: bnxt_hsi.h:3810
__le64 pfc_pri5_rx_duration_us
Definition: bnxt_hsi.h:3910
uint16_t __be16
Definition: CIB_PRM.h:27
__le64 rx_64b_frames
Definition: bnxt_hsi.h:3748
__le16 hwrm_intf_major
Definition: bnxt_hsi.h:446
__le64 rx_discard_pkts
Definition: bnxt_hsi.h:8383
__le64 tx_bcast_bytes
Definition: bnxt_hsi.h:8395
__le64 tx_oversz_frames
Definition: bnxt_hsi.h:3714
__le32 pcie_ltssm_histogram[4]
Definition: bnxt_hsi.h:8586