iPXE
bnxt_hsi.h
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1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2019 Broadcom Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  *
10  * DO NOT MODIFY!!! This file is automatically generated.
11  */
12 
13 #ifndef _BNXT_HSI_H_
14 #define _BNXT_HSI_H_
15 
16 /* hwrm_cmd_hdr (size:128b/16B) */
17 struct hwrm_cmd_hdr {
23 };
24 
25 /* hwrm_resp_hdr (size:64b/8B) */
26 struct hwrm_resp_hdr {
31 };
32 
33 #define CMD_DISCR_TLV_ENCAP 0x8000UL
34 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
35 
36 #define TLV_TYPE_HWRM_REQUEST 0x1UL
37 #define TLV_TYPE_HWRM_RESPONSE 0x2UL
38 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
39 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
40 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
41 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL
42 #define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL
43 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
44 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
45 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
46 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL
47 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL
48 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
49 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
50 
51 /* tlv (size:64b/8B) */
52 struct tlv {
56  #define TLV_FLAGS_MORE 0x1UL
57  #define TLV_FLAGS_MORE_LAST 0x0UL
58  #define TLV_FLAGS_MORE_NOT_LAST 0x1UL
59  #define TLV_FLAGS_REQUIRED 0x2UL
60  #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
61  #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
62  #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
65 };
66 
67 /* input (size:128b/16B) */
68 struct input {
74 };
75 
76 /* output (size:64b/8B) */
77 struct output {
82 };
83 
84 /* hwrm_short_input (size:128b/16B) */
88  #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
89  #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
93 };
94 
95 /* cmd_nums (size:64b/8B) */
96 struct cmd_nums {
98  #define HWRM_VER_GET 0x0UL
99  #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
100  #define HWRM_FUNC_BUF_UNRGTR 0xeUL
101  #define HWRM_FUNC_VF_CFG 0xfUL
102  #define HWRM_RESERVED1 0x10UL
103  #define HWRM_FUNC_RESET 0x11UL
104  #define HWRM_FUNC_GETFID 0x12UL
105  #define HWRM_FUNC_VF_ALLOC 0x13UL
106  #define HWRM_FUNC_VF_FREE 0x14UL
107  #define HWRM_FUNC_QCAPS 0x15UL
108  #define HWRM_FUNC_QCFG 0x16UL
109  #define HWRM_FUNC_CFG 0x17UL
110  #define HWRM_FUNC_QSTATS 0x18UL
111  #define HWRM_FUNC_CLR_STATS 0x19UL
112  #define HWRM_FUNC_DRV_UNRGTR 0x1aUL
113  #define HWRM_FUNC_VF_RESC_FREE 0x1bUL
114  #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
115  #define HWRM_FUNC_DRV_RGTR 0x1dUL
116  #define HWRM_FUNC_DRV_QVER 0x1eUL
117  #define HWRM_FUNC_BUF_RGTR 0x1fUL
118  #define HWRM_PORT_PHY_CFG 0x20UL
119  #define HWRM_PORT_MAC_CFG 0x21UL
120  #define HWRM_PORT_TS_QUERY 0x22UL
121  #define HWRM_PORT_QSTATS 0x23UL
122  #define HWRM_PORT_LPBK_QSTATS 0x24UL
123  #define HWRM_PORT_CLR_STATS 0x25UL
124  #define HWRM_PORT_LPBK_CLR_STATS 0x26UL
125  #define HWRM_PORT_PHY_QCFG 0x27UL
126  #define HWRM_PORT_MAC_QCFG 0x28UL
127  #define HWRM_PORT_MAC_PTP_QCFG 0x29UL
128  #define HWRM_PORT_PHY_QCAPS 0x2aUL
129  #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
130  #define HWRM_PORT_PHY_I2C_READ 0x2cUL
131  #define HWRM_PORT_LED_CFG 0x2dUL
132  #define HWRM_PORT_LED_QCFG 0x2eUL
133  #define HWRM_PORT_LED_QCAPS 0x2fUL
134  #define HWRM_QUEUE_QPORTCFG 0x30UL
135  #define HWRM_QUEUE_QCFG 0x31UL
136  #define HWRM_QUEUE_CFG 0x32UL
137  #define HWRM_FUNC_VLAN_CFG 0x33UL
138  #define HWRM_FUNC_VLAN_QCFG 0x34UL
139  #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
140  #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
141  #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
142  #define HWRM_QUEUE_PRI2COS_CFG 0x38UL
143  #define HWRM_QUEUE_COS2BW_QCFG 0x39UL
144  #define HWRM_QUEUE_COS2BW_CFG 0x3aUL
145  #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
146  #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
147  #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
148  #define HWRM_VNIC_ALLOC 0x40UL
149  #define HWRM_VNIC_FREE 0x41UL
150  #define HWRM_VNIC_CFG 0x42UL
151  #define HWRM_VNIC_QCFG 0x43UL
152  #define HWRM_VNIC_TPA_CFG 0x44UL
153  #define HWRM_VNIC_TPA_QCFG 0x45UL
154  #define HWRM_VNIC_RSS_CFG 0x46UL
155  #define HWRM_VNIC_RSS_QCFG 0x47UL
156  #define HWRM_VNIC_PLCMODES_CFG 0x48UL
157  #define HWRM_VNIC_PLCMODES_QCFG 0x49UL
158  #define HWRM_VNIC_QCAPS 0x4aUL
159  #define HWRM_RING_ALLOC 0x50UL
160  #define HWRM_RING_FREE 0x51UL
161  #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
162  #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
163  #define HWRM_RING_AGGINT_QCAPS 0x54UL
164  #define HWRM_RING_RESET 0x5eUL
165  #define HWRM_RING_GRP_ALLOC 0x60UL
166  #define HWRM_RING_GRP_FREE 0x61UL
167  #define HWRM_RESERVED5 0x64UL
168  #define HWRM_RESERVED6 0x65UL
169  #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
170  #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
171  #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
172  #define HWRM_CFA_L2_FILTER_FREE 0x91UL
173  #define HWRM_CFA_L2_FILTER_CFG 0x92UL
174  #define HWRM_CFA_L2_SET_RX_MASK 0x93UL
175  #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
176  #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
177  #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
178  #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
179  #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
180  #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
181  #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
182  #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
183  #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
184  #define HWRM_CFA_EM_FLOW_FREE 0x9dUL
185  #define HWRM_CFA_EM_FLOW_CFG 0x9eUL
186  #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
187  #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
188  #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
189  #define HWRM_STAT_CTX_ENG_QUERY 0xafUL
190  #define HWRM_STAT_CTX_ALLOC 0xb0UL
191  #define HWRM_STAT_CTX_FREE 0xb1UL
192  #define HWRM_STAT_CTX_QUERY 0xb2UL
193  #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
194  #define HWRM_PORT_QSTATS_EXT 0xb4UL
195  #define HWRM_FW_RESET 0xc0UL
196  #define HWRM_FW_QSTATUS 0xc1UL
197  #define HWRM_FW_HEALTH_CHECK 0xc2UL
198  #define HWRM_FW_SYNC 0xc3UL
199  #define HWRM_FW_SET_TIME 0xc8UL
200  #define HWRM_FW_GET_TIME 0xc9UL
201  #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
202  #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
203  #define HWRM_FW_IPC_MAILBOX 0xccUL
204  #define HWRM_EXEC_FWD_RESP 0xd0UL
205  #define HWRM_REJECT_FWD_RESP 0xd1UL
206  #define HWRM_FWD_RESP 0xd2UL
207  #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
208  #define HWRM_OEM_CMD 0xd4UL
209  #define HWRM_TEMP_MONITOR_QUERY 0xe0UL
210  #define HWRM_WOL_FILTER_ALLOC 0xf0UL
211  #define HWRM_WOL_FILTER_FREE 0xf1UL
212  #define HWRM_WOL_FILTER_QCFG 0xf2UL
213  #define HWRM_WOL_REASON_QCFG 0xf3UL
214  #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
215  #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
216  #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
217  #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
218  #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
219  #define HWRM_CFA_VFR_ALLOC 0xfdUL
220  #define HWRM_CFA_VFR_FREE 0xfeUL
221  #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
222  #define HWRM_CFA_VF_PAIR_FREE 0x101UL
223  #define HWRM_CFA_VF_PAIR_INFO 0x102UL
224  #define HWRM_CFA_FLOW_ALLOC 0x103UL
225  #define HWRM_CFA_FLOW_FREE 0x104UL
226  #define HWRM_CFA_FLOW_FLUSH 0x105UL
227  #define HWRM_CFA_FLOW_STATS 0x106UL
228  #define HWRM_CFA_FLOW_INFO 0x107UL
229  #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
230  #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
231  #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
232  #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
233  #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
234  #define HWRM_CFA_PAIR_ALLOC 0x10dUL
235  #define HWRM_CFA_PAIR_FREE 0x10eUL
236  #define HWRM_CFA_PAIR_INFO 0x10fUL
237  #define HWRM_FW_IPC_MSG 0x110UL
238  #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
239  #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
240  #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
241  #define HWRM_CFA_FLOW_AGING_CFG 0x114UL
242  #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
243  #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
244  #define HWRM_ENGINE_CKV_HELLO 0x12dUL
245  #define HWRM_ENGINE_CKV_STATUS 0x12eUL
246  #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
247  #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
248  #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
249  #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
250  #define HWRM_ENGINE_CKV_FLUSH 0x133UL
251  #define HWRM_ENGINE_CKV_RNG_GET 0x134UL
252  #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
253  #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
254  #define HWRM_ENGINE_QG_QUERY 0x13dUL
255  #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
256  #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
257  #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
258  #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
259  #define HWRM_ENGINE_QG_METER_QUERY 0x142UL
260  #define HWRM_ENGINE_QG_METER_BIND 0x143UL
261  #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
262  #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
263  #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
264  #define HWRM_ENGINE_SG_QUERY 0x147UL
265  #define HWRM_ENGINE_SG_METER_QUERY 0x148UL
266  #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
267  #define HWRM_ENGINE_SG_QG_BIND 0x14aUL
268  #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
269  #define HWRM_ENGINE_CONFIG_QUERY 0x154UL
270  #define HWRM_ENGINE_STATS_CONFIG 0x155UL
271  #define HWRM_ENGINE_STATS_CLEAR 0x156UL
272  #define HWRM_ENGINE_STATS_QUERY 0x157UL
273  #define HWRM_ENGINE_RQ_ALLOC 0x15eUL
274  #define HWRM_ENGINE_RQ_FREE 0x15fUL
275  #define HWRM_ENGINE_CQ_ALLOC 0x160UL
276  #define HWRM_ENGINE_CQ_FREE 0x161UL
277  #define HWRM_ENGINE_NQ_ALLOC 0x162UL
278  #define HWRM_ENGINE_NQ_FREE 0x163UL
279  #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
280  #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
281  #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
282  #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
283  #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
284  #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
285  #define HWRM_FUNC_VF_BW_CFG 0x195UL
286  #define HWRM_FUNC_VF_BW_QCFG 0x196UL
287  #define HWRM_SELFTEST_QLIST 0x200UL
288  #define HWRM_SELFTEST_EXEC 0x201UL
289  #define HWRM_SELFTEST_IRQ 0x202UL
290  #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
291  #define HWRM_PCIE_QSTATS 0x204UL
292  #define HWRM_DBG_READ_DIRECT 0xff10UL
293  #define HWRM_DBG_READ_INDIRECT 0xff11UL
294  #define HWRM_DBG_WRITE_DIRECT 0xff12UL
295  #define HWRM_DBG_WRITE_INDIRECT 0xff13UL
296  #define HWRM_DBG_DUMP 0xff14UL
297  #define HWRM_DBG_ERASE_NVM 0xff15UL
298  #define HWRM_DBG_CFG 0xff16UL
299  #define HWRM_DBG_COREDUMP_LIST 0xff17UL
300  #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
301  #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
302  #define HWRM_DBG_FW_CLI 0xff1aUL
303  #define HWRM_DBG_I2C_CMD 0xff1bUL
304  #define HWRM_DBG_RING_INFO_GET 0xff1cUL
305  #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
306  #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
307  #define HWRM_NVM_FLUSH 0xfff0UL
308  #define HWRM_NVM_GET_VARIABLE 0xfff1UL
309  #define HWRM_NVM_SET_VARIABLE 0xfff2UL
310  #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
311  #define HWRM_NVM_MODIFY 0xfff4UL
312  #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
313  #define HWRM_NVM_GET_DEV_INFO 0xfff6UL
314  #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
315  #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
316  #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
317  #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
318  #define HWRM_NVM_GET_DIR_INFO 0xfffbUL
319  #define HWRM_NVM_RAW_DUMP 0xfffcUL
320  #define HWRM_NVM_READ 0xfffdUL
321  #define HWRM_NVM_WRITE 0xfffeUL
322  #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
323  #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
325 };
326 
327 /* ret_codes (size:64b/8B) */
328 struct ret_codes {
330  #define HWRM_ERR_CODE_SUCCESS 0x0UL
331  #define HWRM_ERR_CODE_FAIL 0x1UL
332  #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
333  #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
334  #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
335  #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
336  #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
337  #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
338  #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
339  #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
340  #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
341  #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
342  #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
343  #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
344  #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
345  #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
346  #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
348 };
349 
350 /* hwrm_err_output (size:128b/16B) */
360 };
361 
362 #define HWRM_NA_SIGNATURE ((__le32)(-1))
363 #define HWRM_MAX_REQ_LEN 128
364 #define HWRM_MAX_RESP_LEN 280
365 #define HW_HASH_INDEX_SIZE 0x80
366 #define HW_HASH_KEY_SIZE 40
367 #define HWRM_RESP_VALID_KEY 1
368 #define HWRM_VERSION_MAJOR 1
369 #define HWRM_VERSION_MINOR 10
370 #define HWRM_VERSION_UPDATE 0
371 #define HWRM_VERSION_RSVD 18
372 #define HWRM_VERSION_STR "1.10.0.18"
373 
374 /* hwrm_ver_get_input (size:192b/24B) */
385 };
386 
387 /* hwrm_ver_get_output (size:1408b/176B) */
410  #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
411  #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
412  #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
413  #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
414  #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
415  #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
416  #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
417  #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
418  #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
419  #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
424  char hwrm_fw_name[16];
425  char mgmt_fw_name[16];
426  char netctrl_fw_name[16];
428  char roce_fw_name[16];
434  #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
435  #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
436  #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
437  #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
442  #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
443  #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
469 };
470 
471 /* eject_cmpl (size:128b/16B) */
472 struct eject_cmpl {
474  #define EJECT_CMPL_TYPE_MASK 0x3fUL
475  #define EJECT_CMPL_TYPE_SFT 0
476  #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
477  #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
478  #define EJECT_CMPL_FLAGS_MASK 0xffc0UL
479  #define EJECT_CMPL_FLAGS_SFT 6
480  #define EJECT_CMPL_FLAGS_ERROR 0x40UL
484  #define EJECT_CMPL_V 0x1UL
485  #define EJECT_CMPL_ERRORS_MASK 0xfffeUL
486  #define EJECT_CMPL_ERRORS_SFT 1
487  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
488  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
489  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
490  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
491  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
492  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
493  #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
496 };
497 
498 /* hwrm_cmpl (size:128b/16B) */
499 struct hwrm_cmpl {
501  #define CMPL_TYPE_MASK 0x3fUL
502  #define CMPL_TYPE_SFT 0
503  #define CMPL_TYPE_HWRM_DONE 0x20UL
504  #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
508  #define CMPL_V 0x1UL
510 };
511 
512 /* hwrm_fwd_req_cmpl (size:128b/16B) */
515  #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
516  #define FWD_REQ_CMPL_TYPE_SFT 0
517  #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
518  #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
519  #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
520  #define FWD_REQ_CMPL_REQ_LEN_SFT 6
524  #define FWD_REQ_CMPL_V 0x1UL
525  #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
526  #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
527 };
528 
529 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
532  #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
533  #define FWD_RESP_CMPL_TYPE_SFT 0
534  #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
535  #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
540  #define FWD_RESP_CMPL_V 0x1UL
541  #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
542  #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
543 };
544 
545 /* hwrm_async_event_cmpl (size:128b/16B) */
548  #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
549  #define ASYNC_EVENT_CMPL_TYPE_SFT 0
550  #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
551  #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
553  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
554  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
555  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
556  #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
557  #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
558  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
559  #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
560  #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
561  #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
562  #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
563  #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
564  #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
565  #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
566  #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
567  #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
568  #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
569  #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
570  #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
571  #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
572  #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
573  #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
574  #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
575  #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
576  #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
577  #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
580  #define ASYNC_EVENT_CMPL_V 0x1UL
581  #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
582  #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
586 };
587 
588 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
591  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
592  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
593  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
594  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
596  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
597  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
600  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
601  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
602  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
606  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
607  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
608  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
609  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
610  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
611  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
612  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
613  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
614  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
615  #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
616 };
617 
618 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
621  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL
622  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
623  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
624  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
626  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL
627  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
630  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL
631  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL
632  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
636  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
637  #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
638 };
639 
640 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
643  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL
644  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
645  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
646  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
648  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
649  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
652  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL
653  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
654  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
658  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
659  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
660  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
661  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
662  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
663  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
664  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
665  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
666  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
667  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
668  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
669  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
670  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1)
671  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
672  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
673  #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
674 };
675 
676 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
679  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL
680  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
681  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
682  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
684  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
685  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
687  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL
688  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL
689  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL
691  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL
692  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
693  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
697  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
698  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
699  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL
700  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16
701  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16)
702  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
703  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL
704  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24
705  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24)
706  #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
707 };
708 
709 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
712  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
713  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
714  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
715  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
717  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
718  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
721  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
722  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
723  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
727  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
728  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
729  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
730  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
731  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
732  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
733  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
734  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
735  #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
736 };
737 
738 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
741  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL
742  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
743  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
744  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
746  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
747  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
750  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL
751  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
752  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
756  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
757  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
758 };
759 
760 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
763  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
764  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
765  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
766  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
768  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
769  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
772  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
773  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
774  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
778  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
779  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
780  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
781  #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
782 };
783 
784 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
787  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK 0x3fUL
788  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT 0
789  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
790  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
792  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
793  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
796  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V 0x1UL
797  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK 0xfeUL
798  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
802  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
803  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
804  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE 0x10000UL
805  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE 0x20000UL
806  #define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE 0x40000UL
807 };
808 
809 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
812  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
813  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
814  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
815  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
817  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
818  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
821  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
822  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
823  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
827  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
828  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
829  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
830  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
831  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
832  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
833  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
834  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
835  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
836  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
837  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
838  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
839  #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
840 };
841 
842 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
845  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL
846  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
847  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
848  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
850  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
851  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
854  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL
855  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
856  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
860  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
861  #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
862 };
863 
864 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
867  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL
868  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
869  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
870  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
872  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
873  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
876  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL
877  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL
878  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
882  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
883  #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
884 };
885 
886 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
889  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL
890  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0
891  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL
892  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
894  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
895  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
898  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL
899  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL
900  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
904  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
905  #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0
906 };
907 
908 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
911  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL
912  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
913  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
914  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
916  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
917  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
920  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL
921  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
922  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
926  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
927  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
928  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL
929  #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
930 };
931 
932 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
935  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL
936  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
937  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
938  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
940  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL
941  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
944  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL
945  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL
946  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
950  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
951  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
952  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL
953  #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
954 };
955 
956 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
959  #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL
960  #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
961  #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
962  #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
964  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL
965  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
968  #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL
969  #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL
970  #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
974  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
975  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
976  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK 0xff0000UL
977  #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
978 };
979 
980 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
983  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
984  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
985  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
986  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
988  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
989  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
992  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL
993  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
994  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
998  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
999  #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
1000 };
1001 
1002 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
1005  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL
1006  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
1007  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1008  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
1010  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
1011  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
1014  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL
1015  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
1016  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
1020  #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL
1021 };
1022 
1023 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
1026  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
1027  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
1028  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1029  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
1031  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
1032  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
1035  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
1036  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
1037  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
1041  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
1042  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
1043  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
1044  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
1045  #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
1046 };
1047 
1048 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
1051  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK 0x3fUL
1052  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
1053  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1054  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
1055  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK 0xffc0UL
1056  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
1058  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
1059  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
1062  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V 0x1UL
1063  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK 0xfeUL
1064  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
1068  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK 0x3UL
1069  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT 0
1070  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC 0x1UL
1071  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC 0x2UL
1072  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
1073  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK 0x1cUL
1074  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT 2
1075  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK 0x1fffe0UL
1076  #define ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT 5
1077 };
1078 
1079 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
1082  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
1083  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
1084  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1085  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
1086  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
1087  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
1089  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
1090  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
1093  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
1094  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
1095  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
1099  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
1100  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
1101  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
1102  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
1103  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
1104  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
1105  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
1106  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
1107  #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
1108 };
1109 
1110 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
1113  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
1114  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
1115  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1116  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
1118  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
1119  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
1122  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
1123  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
1124  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
1128  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
1129  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
1130  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
1131  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
1132  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
1133  #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
1134 };
1135 
1136 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
1139  #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
1140  #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
1141  #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1142  #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
1144  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
1145  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
1147  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
1148  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
1149  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL
1150  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL
1151  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL
1152  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
1154  #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
1155  #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
1156  #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
1160  #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
1161 };
1162 
1163 /* hwrm_func_reset_input (size:192b/24B) */
1171  #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
1174  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
1175  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
1176  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
1177  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
1178  #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
1180 };
1181 
1182 /* hwrm_func_reset_output (size:128b/16B) */
1190 };
1191 
1192 /* hwrm_func_getfid_input (size:192b/24B) */
1200  #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
1203 };
1204 
1205 /* hwrm_func_getfid_output (size:128b/16B) */
1214 };
1215 
1216 /* hwrm_func_vf_alloc_input (size:192b/24B) */
1224  #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
1227 };
1228 
1229 /* hwrm_func_vf_alloc_output (size:128b/16B) */
1238 };
1239 
1240 /* hwrm_func_vf_free_input (size:192b/24B) */
1248  #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
1251 };
1252 
1253 /* hwrm_func_vf_free_output (size:128b/16B) */
1261 };
1262 
1263 /* hwrm_func_vf_cfg_input (size:448b/56B) */
1271  #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
1272  #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
1273  #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
1274  #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
1275  #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
1276  #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
1277  #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
1278  #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
1279  #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
1280  #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
1281  #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
1282  #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
1288  #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
1289  #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
1290  #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
1291  #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
1292  #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
1293  #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
1294  #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
1295  #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
1305 };
1306 
1307 /* hwrm_func_vf_cfg_output (size:128b/16B) */
1315 };
1316 
1317 /* hwrm_func_qcaps_input (size:192b/24B) */
1326 };
1327 
1328 /* hwrm_func_qcaps_output (size:640b/80B) */
1337  #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1338  #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1339  #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1340  #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
1341  #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
1342  #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1343  #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1344  #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
1345  #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
1346  #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
1347  #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
1348  #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
1349  #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
1350  #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
1351  #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
1352  #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
1353  #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
1354  #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
1355  #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
1356  #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
1357  #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1358  #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1359  #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1382 };
1383 
1384 /* hwrm_func_qcfg_input (size:192b/24B) */
1393 };
1394 
1395 /* hwrm_func_qcfg_output (size:704b/88B) */
1405  #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1406  #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1407  #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
1408  #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
1409  #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
1410  #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
1411  #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1424  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
1425  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
1426  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1427  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1428  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1429  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1430  #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1432  #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1433  #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1437  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1438  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
1439  #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
1440  #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
1441  #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
1442  #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1443  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1444  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
1445  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1446  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1447  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1448  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1449  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1450  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1451  #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1453  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1454  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
1455  #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
1456  #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
1457  #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
1458  #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1459  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1460  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
1461  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1462  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1463  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1464  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1465  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1466  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1467  #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1469  #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1470  #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
1471  #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
1472  #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
1474  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1475  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
1476  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1477  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1478  #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1479  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1480  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
1481  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1482  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1483  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1484  #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1485  #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
1486  #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
1499 };
1500 
1501 /* hwrm_func_cfg_input (size:704b/88B) */
1511  #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1512  #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
1513  #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
1514  #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
1515  #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
1516  #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
1517  #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
1518  #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
1519  #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
1520  #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
1521  #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
1522  #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
1523  #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
1524  #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1525  #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1526  #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1527  #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
1528  #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
1530  #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1531  #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1532  #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1533  #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1534  #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1535  #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1536  #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1537  #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1538  #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1539  #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1540  #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1541  #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1542  #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1543  #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1544  #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1545  #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1546  #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1547  #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1548  #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1549  #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1550  #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1551  #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1552  #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
1567  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1568  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
1569  #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
1570  #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
1571  #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
1572  #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1573  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1574  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
1575  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1576  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1577  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1578  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1579  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1580  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1581  #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1583  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1584  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
1585  #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
1586  #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
1587  #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
1588  #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1589  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1590  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
1591  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1592  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1593  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1594  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1595  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1596  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1597  #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1600  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
1601  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
1602  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
1603  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1604  #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1607  #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1608  #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
1609  #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
1610  #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
1612  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1613  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
1614  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1615  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1616  #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1617  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1618  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
1619  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1620  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1621  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1622  #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1623  #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
1624  #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
1626 };
1627 
1628 /* hwrm_func_cfg_output (size:128b/16B) */
1636 };
1637 
1638 /* hwrm_func_qstats_input (size:192b/24B) */
1647 };
1648 
1649 /* hwrm_func_qstats_output (size:1408b/176B) */
1677 };
1678 
1679 /* hwrm_func_clr_stats_input (size:192b/24B) */
1688 };
1689 
1690 /* hwrm_func_clr_stats_output (size:128b/16B) */
1698 };
1699 
1700 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
1709 };
1710 
1711 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
1719 };
1720 
1721 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
1729  #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1730  #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1731  #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
1732  #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
1733  #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
1735  #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1736  #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1737  #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1738  #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1739  #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1741  #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
1742  #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
1743  #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
1744  #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
1745  #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
1746  #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
1747  #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
1748  #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
1749  #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
1750  #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
1751  #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
1752  #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
1765 };
1766 
1767 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
1774  #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
1777 };
1778 
1779 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
1787  #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1789 };
1790 
1791 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
1799 };
1800 
1801 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
1809  #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1810  #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1814  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
1815  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
1816  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
1817  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
1818  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
1819  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
1820  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
1821  #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
1837 };
1838 
1839 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
1847 };
1848 
1849 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
1857  #define FUNC_BUF_UNRGTR_REQ_ENABLES_VF_ID 0x1UL
1860 };
1861 
1862 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
1870 };
1871 
1872 /* hwrm_func_drv_qver_input (size:192b/24B) */
1882 };
1883 
1884 /* hwrm_func_drv_qver_output (size:256b/32B) */
1891  #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
1892  #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
1893  #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
1894  #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
1895  #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
1896  #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
1897  #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
1898  #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
1899  #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
1900  #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
1901  #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
1902  #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
1913 };
1914 
1915 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
1924 };
1925 
1926 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
1935  #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
1936  #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
1937  #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
1938  #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
1957  #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
1960 };
1961 
1962 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
1988  #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
1990 };
1991 
1992 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
2008 };
2009 
2010 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
2017 };
2018 
2019 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
2050 };
2051 
2052 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
2060  #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
2062  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
2063  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
2064  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
2065  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
2066  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
2067  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
2068  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
2069  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
2070  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
2071  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
2072  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
2073  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
2074  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
2075  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
2076  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
2077  #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
2079  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
2080  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
2081  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
2082  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
2083  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
2084  #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
2085  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
2086  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
2087  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
2088  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
2089  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
2090  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
2091  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
2092  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
2093  #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
2095  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
2096  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
2097  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
2098  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
2099  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
2100  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
2101  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
2102  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
2103  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
2104  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
2105  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
2106  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
2107  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
2108  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
2109  #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
2111  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
2112  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
2113  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
2114  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
2115  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
2116  #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
2117  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
2118  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
2119  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
2120  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
2121  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
2122  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
2123  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
2124  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
2125  #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
2127  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
2128  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
2129  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
2130  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
2131  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
2132  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
2133  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
2134  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
2135  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
2136  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
2137  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
2138  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
2139  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
2140  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
2141  #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
2143  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
2144  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
2145  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
2146  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
2147  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
2148  #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
2149  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
2150  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
2151  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
2152  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
2153  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
2154  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
2155  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
2156  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
2157  #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
2159  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
2160  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
2161  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
2162  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
2163  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
2164  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
2165  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
2166  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
2167  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
2168  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
2169  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
2170  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
2171  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
2172  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
2173  #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
2175  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
2176  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
2177  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
2178  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
2179  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
2180  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
2181  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
2182  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
2183  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
2184  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
2185  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
2186  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
2187  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
2188  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
2189  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
2191  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
2192  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
2193  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
2194  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
2195  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
2196  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
2197  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
2198  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
2199  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
2200  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
2201  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
2202  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
2203  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
2204  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
2205  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
2207  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
2208  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
2209  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
2210  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
2211  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
2212  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
2213  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
2214  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
2215  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
2216  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
2217  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
2218  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
2219  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
2220  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
2221  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
2223  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
2224  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
2225  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
2226  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
2227  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
2228  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
2229  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
2230  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
2231  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
2232  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
2233  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
2234  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
2235  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
2236  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
2237  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
2239  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
2240  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
2241  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
2242  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
2243  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
2244  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
2245  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
2246  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
2247  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
2248  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
2249  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
2250  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
2251  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
2252  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
2253  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2255  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
2256  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
2257  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
2258  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
2259  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
2260  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2261  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
2262  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
2263  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
2264  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
2265  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
2266  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
2267  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
2268  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
2269  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2271  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
2272  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
2273  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
2274  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
2275  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
2276  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2277  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
2278  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
2279  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
2280  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
2281  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
2282  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
2283  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
2284  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
2285  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2287  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
2288  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
2289  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
2290  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
2291  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
2292  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2293  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
2294  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
2295  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
2296  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
2297  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
2298  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
2299  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
2300  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
2301  #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2303  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
2304  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
2305  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
2306  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
2307  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
2308  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2309  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
2310  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
2311  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
2312  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
2313  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
2314  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
2315  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
2316  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
2317  #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2319  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
2320  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
2321  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
2322  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
2323  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
2324  #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2325  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
2326  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
2327  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
2328  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
2329  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
2330  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
2331  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
2332  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
2333  #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
2379 };
2380 
2381 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
2389 };
2390 
2391 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
2398 };
2399 
2400 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
2407  #define FUNC_BACKING_STORE_QCFG_RESP_FLAGS_PREBOOT_MODE 0x1UL
2409  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_QP 0x1UL
2410  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_SRQ 0x2UL
2411  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_CQ 0x4UL
2412  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_VNIC 0x8UL
2413  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_STAT 0x10UL
2414  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_SP 0x20UL
2415  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING0 0x40UL
2416  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING1 0x80UL
2417  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING2 0x100UL
2418  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING3 0x200UL
2419  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING4 0x400UL
2420  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING5 0x800UL
2421  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING6 0x1000UL
2422  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TQM_RING7 0x2000UL
2423  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_MRAV 0x4000UL
2424  #define FUNC_BACKING_STORE_QCFG_RESP_UNUSED_0_TIM 0x8000UL
2426  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_MASK 0xfUL
2427  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_SFT 0
2428  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_0 0x0UL
2429  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_1 0x1UL
2430  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2 0x2UL
2431  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_QPC_LVL_LVL_2
2432  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_MASK 0xf0UL
2433  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_SFT 4
2434  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_4K (0x0UL << 4)
2435  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8K (0x1UL << 4)
2436  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_64K (0x2UL << 4)
2437  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_2M (0x3UL << 4)
2438  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_8M (0x4UL << 4)
2439  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G (0x5UL << 4)
2440  #define FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_QPC_PG_SIZE_PG_1G
2442  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_MASK 0xfUL
2443  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_SFT 0
2444  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_0 0x0UL
2445  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_1 0x1UL
2446  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2 0x2UL
2447  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_SRQ_LVL_LVL_2
2448  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_MASK 0xf0UL
2449  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_SFT 4
2450  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
2451  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
2452  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
2453  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
2454  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
2455  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
2456  #define FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_SRQ_PG_SIZE_PG_1G
2458  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_MASK 0xfUL
2459  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_SFT 0
2460  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_0 0x0UL
2461  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_1 0x1UL
2462  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2 0x2UL
2463  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_CQ_LVL_LVL_2
2464  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_MASK 0xf0UL
2465  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_SFT 4
2466  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_4K (0x0UL << 4)
2467  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8K (0x1UL << 4)
2468  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_64K (0x2UL << 4)
2469  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_2M (0x3UL << 4)
2470  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_8M (0x4UL << 4)
2471  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G (0x5UL << 4)
2472  #define FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_CQ_PG_SIZE_PG_1G
2474  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_MASK 0xfUL
2475  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_SFT 0
2476  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_0 0x0UL
2477  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_1 0x1UL
2478  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2 0x2UL
2479  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_VNIC_LVL_LVL_2
2480  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_MASK 0xf0UL
2481  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_SFT 4
2482  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
2483  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
2484  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
2485  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
2486  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
2487  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
2488  #define FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_VNIC_PG_SIZE_PG_1G
2490  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_MASK 0xfUL
2491  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_SFT 0
2492  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_0 0x0UL
2493  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_1 0x1UL
2494  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2 0x2UL
2495  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_STAT_LVL_LVL_2
2496  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_MASK 0xf0UL
2497  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_SFT 4
2498  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_4K (0x0UL << 4)
2499  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8K (0x1UL << 4)
2500  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_64K (0x2UL << 4)
2501  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_2M (0x3UL << 4)
2502  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_8M (0x4UL << 4)
2503  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G (0x5UL << 4)
2504  #define FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_STAT_PG_SIZE_PG_1G
2506  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_MASK 0xfUL
2507  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_SFT 0
2508  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_0 0x0UL
2509  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_1 0x1UL
2510  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2 0x2UL
2511  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_LVL_LVL_2
2512  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_MASK 0xf0UL
2513  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_SFT 4
2514  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
2515  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
2516  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
2517  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
2518  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
2519  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
2520  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_SP_PG_SIZE_PG_1G
2522  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_MASK 0xfUL
2523  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_SFT 0
2524  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_0 0x0UL
2525  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_1 0x1UL
2526  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2 0x2UL
2527  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_LVL_LVL_2
2528  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_MASK 0xf0UL
2529  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_SFT 4
2530  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
2531  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
2532  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
2533  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
2534  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
2535  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
2536  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING0_PG_SIZE_PG_1G
2538  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_MASK 0xfUL
2539  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_SFT 0
2540  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_0 0x0UL
2541  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_1 0x1UL
2542  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2 0x2UL
2543  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_LVL_LVL_2
2544  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_MASK 0xf0UL
2545  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_SFT 4
2546  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
2547  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
2548  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
2549  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
2550  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
2551  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
2552  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING1_PG_SIZE_PG_1G
2554  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_MASK 0xfUL
2555  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_SFT 0
2556  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_0 0x0UL
2557  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_1 0x1UL
2558  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2 0x2UL
2559  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_LVL_LVL_2
2560  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_MASK 0xf0UL
2561  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_SFT 4
2562  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
2563  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
2564  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
2565  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
2566  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
2567  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
2568  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING2_PG_SIZE_PG_1G
2570  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_MASK 0xfUL
2571  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_SFT 0
2572  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_0 0x0UL
2573  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_1 0x1UL
2574  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2 0x2UL
2575  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_LVL_LVL_2
2576  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_MASK 0xf0UL
2577  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_SFT 4
2578  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
2579  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
2580  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
2581  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
2582  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
2583  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
2584  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING3_PG_SIZE_PG_1G
2586  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_MASK 0xfUL
2587  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_SFT 0
2588  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_0 0x0UL
2589  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_1 0x1UL
2590  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2 0x2UL
2591  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_LVL_LVL_2
2592  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_MASK 0xf0UL
2593  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_SFT 4
2594  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
2595  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
2596  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
2597  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
2598  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
2599  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
2600  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING4_PG_SIZE_PG_1G
2602  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_MASK 0xfUL
2603  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_SFT 0
2604  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_0 0x0UL
2605  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_1 0x1UL
2606  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2 0x2UL
2607  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_LVL_LVL_2
2608  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_MASK 0xf0UL
2609  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_SFT 4
2610  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
2611  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
2612  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
2613  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
2614  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
2615  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
2616  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING5_PG_SIZE_PG_1G
2618  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_MASK 0xfUL
2619  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_SFT 0
2620  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_0 0x0UL
2621  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_1 0x1UL
2622  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2 0x2UL
2623  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_LVL_LVL_2
2624  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_MASK 0xf0UL
2625  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_SFT 4
2626  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
2627  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
2628  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
2629  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
2630  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
2631  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
2632  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING6_PG_SIZE_PG_1G
2634  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_MASK 0xfUL
2635  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_SFT 0
2636  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_0 0x0UL
2637  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_1 0x1UL
2638  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2 0x2UL
2639  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_LVL_LVL_2
2640  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_MASK 0xf0UL
2641  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_SFT 4
2642  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
2643  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
2644  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
2645  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
2646  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
2647  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
2648  #define FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TQM_RING7_PG_SIZE_PG_1G
2650  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_MASK 0xfUL
2651  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_SFT 0
2652  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_0 0x0UL
2653  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_1 0x1UL
2654  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2 0x2UL
2655  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_MRAV_LVL_LVL_2
2656  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_MASK 0xf0UL
2657  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_SFT 4
2658  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
2659  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
2660  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
2661  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
2662  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
2663  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
2664  #define FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_MRAV_PG_SIZE_PG_1G
2666  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_MASK 0xfUL
2667  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_SFT 0
2668  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_0 0x0UL
2669  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_1 0x1UL
2670  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2 0x2UL
2671  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LAST FUNC_BACKING_STORE_QCFG_RESP_TIM_LVL_LVL_2
2672  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_MASK 0xf0UL
2673  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_SFT 4
2674  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_4K (0x0UL << 4)
2675  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8K (0x1UL << 4)
2676  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_64K (0x2UL << 4)
2677  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_2M (0x3UL << 4)
2678  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_8M (0x4UL << 4)
2679  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G (0x5UL << 4)
2680  #define FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_QCFG_RESP_TIM_PG_SIZE_PG_1G
2720 };
2721 
2722 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
2731 };
2732 
2733 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
2752 };
2753 
2754 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
2764  #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL
2765  #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL
2766  #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL
2767  #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL
2768  #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL
2769  #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL
2781 };
2782 
2783 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
2791 };
2792 
2793 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
2804 };
2805 
2806 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
2815 };
2816 
2817 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
2827  #define FUNC_VF_BW_CFG_REQ_VFN_VFID_MASK 0xfffUL
2828  #define FUNC_VF_BW_CFG_REQ_VFN_VFID_SFT 0
2829  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_MASK 0xf000UL
2830  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_SFT 12
2831  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_0 (0x0UL << 12)
2832  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_6_66 (0x1UL << 12)
2833  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_13_33 (0x2UL << 12)
2834  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_20 (0x3UL << 12)
2835  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_26_66 (0x4UL << 12)
2836  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_33_33 (0x5UL << 12)
2837  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_40 (0x6UL << 12)
2838  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_46_66 (0x7UL << 12)
2839  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_53_33 (0x8UL << 12)
2840  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_60 (0x9UL << 12)
2841  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_66_66 (0xaUL << 12)
2842  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_73_33 (0xbUL << 12)
2843  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_80 (0xcUL << 12)
2844  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_86_66 (0xdUL << 12)
2845  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_93_33 (0xeUL << 12)
2846  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100 (0xfUL << 12)
2847  #define FUNC_VF_BW_CFG_REQ_VFN_RATE_LAST FUNC_VF_BW_CFG_REQ_VFN_RATE_PCT_100
2848 };
2849 
2850 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
2858 };
2859 
2860 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
2870  #define FUNC_VF_BW_QCFG_REQ_VFN_VFID_MASK 0xfffUL
2871  #define FUNC_VF_BW_QCFG_REQ_VFN_VFID_SFT 0
2872 };
2873 
2874 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
2883  #define FUNC_VF_BW_QCFG_RESP_VFN_VFID_MASK 0xfffUL
2884  #define FUNC_VF_BW_QCFG_RESP_VFN_VFID_SFT 0
2885  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_MASK 0xf000UL
2886  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_SFT 12
2887  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_0 (0x0UL << 12)
2888  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_6_66 (0x1UL << 12)
2889  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_13_33 (0x2UL << 12)
2890  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_20 (0x3UL << 12)
2891  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_26_66 (0x4UL << 12)
2892  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_33_33 (0x5UL << 12)
2893  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_40 (0x6UL << 12)
2894  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_46_66 (0x7UL << 12)
2895  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_53_33 (0x8UL << 12)
2896  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_60 (0x9UL << 12)
2897  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_66_66 (0xaUL << 12)
2898  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_73_33 (0xbUL << 12)
2899  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_80 (0xcUL << 12)
2900  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_86_66 (0xdUL << 12)
2901  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_93_33 (0xeUL << 12)
2902  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100 (0xfUL << 12)
2903  #define FUNC_VF_BW_QCFG_RESP_VFN_RATE_LAST FUNC_VF_BW_QCFG_RESP_VFN_RATE_PCT_100
2906 };
2907 
2908 /* hwrm_func_drv_if_change_input (size:192b/24B) */
2916  #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
2918 };
2919 
2920 /* hwrm_func_drv_if_change_output (size:128b/16B) */
2927  #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
2930 };
2931 
2932 /* hwrm_port_phy_cfg_input (size:448b/56B) */
2940  #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
2941  #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
2942  #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
2943  #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
2944  #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
2945  #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
2946  #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
2947  #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
2948  #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
2949  #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
2950  #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
2951  #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
2952  #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
2953  #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
2954  #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
2956  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
2957  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
2958  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
2959  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
2960  #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
2961  #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
2962  #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
2963  #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
2964  #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
2965  #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
2966  #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
2969  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
2970  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
2971  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
2972  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
2973  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
2974  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
2975  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
2976  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
2977  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
2978  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
2979  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL
2980  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
2981  #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
2983  #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
2984  #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
2985  #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
2986  #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
2987  #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
2988  #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
2990  #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
2991  #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
2992  #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
2993  #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
2995  #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
2996  #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
2997  #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
3000  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
3001  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
3002  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
3003  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
3004  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
3005  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
3006  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
3007  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
3008  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
3009  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
3010  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL
3011  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
3012  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
3014  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
3015  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
3016  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
3017  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
3018  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
3019  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
3020  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
3021  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
3022  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
3023  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
3024  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
3025  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
3026  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
3027  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
3028  #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
3030  #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
3031  #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
3032  #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
3034  #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
3035  #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
3036  #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
3037  #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
3038  #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
3040  #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
3041  #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
3045  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
3046  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
3047  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
3048  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
3049  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
3050  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
3051  #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
3054  #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
3055  #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
3057 };
3058 
3059 /* hwrm_port_phy_cfg_output (size:128b/16B) */
3067 };
3068 
3069 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
3072  #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
3073  #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
3074  #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
3075  #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
3077 };
3078 
3079 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
3088 };
3089 
3090 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
3097  #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
3098  #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
3099  #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
3100  #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
3103  #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
3104  #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
3105  #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
3106  #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
3107  #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
3108  #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
3109  #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
3110  #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
3111  #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
3112  #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
3113  #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
3114  #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
3115  #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
3117  #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
3118  #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
3119  #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
3121  #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
3122  #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
3124  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
3125  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
3126  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
3127  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
3128  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
3129  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
3130  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
3131  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
3132  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
3133  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
3134  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
3135  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
3136  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
3137  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
3138  #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL
3140  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
3141  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
3142  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
3143  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
3144  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
3145  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
3146  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
3147  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
3148  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
3149  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
3150  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL
3151  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
3152  #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
3154  #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
3155  #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
3156  #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
3157  #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
3158  #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
3159  #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
3161  #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
3162  #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
3163  #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
3165  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
3166  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
3167  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
3168  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
3169  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
3170  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
3171  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
3172  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
3173  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
3174  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
3175  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL
3176  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
3177  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
3179  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
3180  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
3181  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
3182  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
3183  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
3184  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
3185  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
3186  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
3187  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
3188  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
3189  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
3190  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
3191  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
3192  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
3193  #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
3195  #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
3196  #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
3197  #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
3199  #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
3200  #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
3201  #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
3202  #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
3203  #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
3205  #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
3206  #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
3208  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
3209  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
3210  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
3211  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
3212  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
3213  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
3214  #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
3220  #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
3221  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
3222  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
3223  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
3224  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
3225  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
3226  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
3227  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
3228  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
3229  #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
3230  #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
3231  #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
3232  #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
3233  #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
3234  #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
3235  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
3236  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
3237  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
3238  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
3239  #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
3240  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
3241  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
3242  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
3243  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
3244  #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
3245  #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
3246  #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
3247  #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
3248  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
3249  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
3250  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
3251  #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
3252  #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
3254  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
3255  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
3256  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
3257  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
3258  #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
3260  #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
3261  #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
3262  #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
3264  #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
3265  #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
3266  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
3267  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
3268  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
3269  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
3270  #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
3272  #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
3274  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
3275  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
3276  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
3277  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
3278  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
3279  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
3280  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
3281  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
3282  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
3283  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
3284  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
3285  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
3286  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
3287  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
3289  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
3290  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
3291  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
3292  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
3293  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
3294  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
3296  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
3297  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
3299  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
3300  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
3301  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
3302  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
3303  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
3304  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
3305  #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
3307  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
3308  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
3309  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
3310  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
3311  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
3312  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
3313  #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
3315  #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
3316  #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
3317  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
3318  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
3319  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
3320  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
3321  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
3322  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
3323  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
3324  #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
3326  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
3327  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
3328  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
3329  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
3330  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
3331  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
3332  #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
3334  #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
3335  #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
3336  #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
3338  #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
3343 };
3344 
3345 /* hwrm_port_mac_cfg_input (size:320b/40B) */
3353  #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
3354  #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
3355  #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
3356  #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
3357  #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
3358  #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
3359  #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
3360  #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
3361  #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
3362  #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
3363  #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
3364  #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
3365  #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
3367  #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
3368  #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
3369  #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
3370  #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
3371  #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
3372  #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
3373  #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
3374  #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
3378  #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
3379  #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
3380  #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
3381  #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
3389  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
3390  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
3391  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
3392  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
3393  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
3394  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
3395  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
3396  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
3397  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
3398  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
3399  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
3400  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
3401  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
3402  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
3403  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
3404  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
3405  #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
3407 };
3408 
3409 /* hwrm_port_mac_cfg_output (size:128b/16B) */
3419  #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
3420  #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
3421  #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
3422  #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
3425 };
3426 
3427 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
3436 };
3437 
3438 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
3448  #define PORT_MAC_QCFG_RESP_LPBK_NONE 0x0UL
3449  #define PORT_MAC_QCFG_RESP_LPBK_LOCAL 0x1UL
3450  #define PORT_MAC_QCFG_RESP_LPBK_REMOTE 0x2UL
3451  #define PORT_MAC_QCFG_RESP_LPBK_LAST PORT_MAC_QCFG_RESP_LPBK_REMOTE
3454  #define PORT_MAC_QCFG_RESP_FLAGS_VLAN_PRI2COS_ENABLE 0x1UL
3455  #define PORT_MAC_QCFG_RESP_FLAGS_TUNNEL_PRI2COS_ENABLE 0x2UL
3456  #define PORT_MAC_QCFG_RESP_FLAGS_IP_DSCP2COS_ENABLE 0x4UL
3457  #define PORT_MAC_QCFG_RESP_FLAGS_OOB_WOL_ENABLE 0x8UL
3458  #define PORT_MAC_QCFG_RESP_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
3459  #define PORT_MAC_QCFG_RESP_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x20UL
3465  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_RSVD 0x1UL
3466  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
3467  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
3468  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
3469  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
3470  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
3471  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
3472  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_QCFG_RESP_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
3473  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
3474  #define PORT_MAC_QCFG_RESP_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3