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iPXE
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Davicom DM96xx USB Ethernet driver. More...
Go to the source code of this file.
Data Structures | |
| struct | dm96xx_interrupt |
| DM96xx interrupt data. More... | |
| struct | dm96xx_rx_header |
| DM96xx receive header. More... | |
| struct | dm96xx_tx_header |
| DM96xx transmit header. More... | |
| struct | dm96xx_device |
| A DM96xx network device. More... | |
Macros | |
| #define | DM96XX_READ_REGISTER |
| Read register(s) | |
| #define | DM96XX_WRITE_REGISTER |
| Write register(s) | |
| #define | DM96XX_WRITE1_REGISTER |
| Write single register. | |
| #define | DM96XX_NCR 0x00 |
| Network control register. | |
| #define | DM96XX_NCR_RST 0x01 |
| Software reset. | |
| #define | DM96XX_NSR 0x01 |
| Network status register. | |
| #define | DM96XX_NSR_LINKST 0x40 |
| Link status. | |
| #define | DM96XX_RCR 0x05 |
| Receive control register. | |
| #define | DM96XX_RCR_ALL 0x08 |
| Pass all multicast. | |
| #define | DM96XX_RCR_RUNT 0x04 |
| Pass runt packet. | |
| #define | DM96XX_RCR_PRMSC 0x02 |
| Promiscuous mode. | |
| #define | DM96XX_RCR_RXEN 0x01 |
| RX enable. | |
| #define | DM96XX_RSR 0x06 |
| Receive status register. | |
| #define | DM96XX_RSR_MF 0x40 |
| Multicast frame. | |
| #define | DM96XX_PAR 0x10 |
| PHY address registers. | |
| #define | DM96XX_CHIPR 0x2c |
| Chip revision register. | |
| #define | DM96XX_CHIPR_9601 0x00 |
| DM9601. | |
| #define | DM96XX_CHIPR_9620 0x01 |
| DM9620. | |
| #define | DM96XX_MODE_CTL 0x91 |
| RX header control/status register (DM9620+ only) | |
| #define | DM96XX_MODE_CTL_MODE 0x80 |
| 4-byte header mode | |
| #define | DM96XX_RESET_DELAY_US 10 |
| Reset delay (in microseconds) | |
| #define | DM96XX_INTR_MAX_FILL 2 |
| Interrupt maximum fill level. | |
| #define | DM96XX_IN_MAX_FILL 8 |
| Bulk IN maximum fill level. | |
| #define | DM96XX_IN_MTU |
| Bulk IN buffer size. | |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER_OR_UBDL) | |
| FILE_SECBOOT (PERMITTED) | |
| static int | dm96xx_read_registers (struct dm96xx_device *dm96xx, unsigned int offset, void *data, size_t len) |
| Read registers. | |
| static int | dm96xx_read_register (struct dm96xx_device *dm96xx, unsigned int offset) |
| Read register. | |
| static int | dm96xx_write_registers (struct dm96xx_device *dm96xx, unsigned int offset, void *data, size_t len) |
| Write registers. | |
| static int | dm96xx_write_register (struct dm96xx_device *dm96xx, unsigned int offset, uint8_t value) |
| Write register. | |
Davicom DM96xx USB Ethernet driver.
Definition in file dm96xx.h.
| #define DM96XX_READ_REGISTER |
Read register(s)
Definition at line 18 of file dm96xx.h.
Referenced by dm96xx_read_registers().
| #define DM96XX_WRITE_REGISTER |
Write register(s)
Definition at line 23 of file dm96xx.h.
Referenced by dm96xx_write_registers().
| #define DM96XX_WRITE1_REGISTER |
Write single register.
Definition at line 28 of file dm96xx.h.
Referenced by dm96xx_write_register().
| #define DM96XX_NCR 0x00 |
| #define DM96XX_NCR_RST 0x01 |
| #define DM96XX_NSR 0x01 |
| #define DM96XX_NSR_LINKST 0x40 |
| #define DM96XX_RCR 0x05 |
| #define DM96XX_RCR_ALL 0x08 |
| #define DM96XX_RCR_RUNT 0x04 |
| #define DM96XX_RCR_PRMSC 0x02 |
| #define DM96XX_RCR_RXEN 0x01 |
| #define DM96XX_RSR_MF 0x40 |
| #define DM96XX_PAR 0x10 |
PHY address registers.
Definition at line 52 of file dm96xx.h.
Referenced by dm96xx_read_mac(), and dm96xx_write_mac().
| #define DM96XX_CHIPR 0x2c |
| #define DM96XX_CHIPR_9601 0x00 |
| #define DM96XX_MODE_CTL 0x91 |
RX header control/status register (DM9620+ only)
Definition at line 60 of file dm96xx.h.
Referenced by dm96xx_rx_mode().
| #define DM96XX_MODE_CTL_MODE 0x80 |
| #define DM96XX_RESET_DELAY_US 10 |
Reset delay (in microseconds)
Definition at line 176 of file dm96xx.h.
Referenced by dm96xx_reset().
| #define DM96XX_INTR_MAX_FILL 2 |
Interrupt maximum fill level.
This is a policy decision.
Definition at line 182 of file dm96xx.h.
Referenced by dm96xx_probe().
| #define DM96XX_IN_MAX_FILL 8 |
Bulk IN maximum fill level.
This is a policy decision.
Definition at line 188 of file dm96xx.h.
Referenced by dm96xx_probe().
| #define DM96XX_IN_MTU |
Bulk IN buffer size.
Definition at line 191 of file dm96xx.h.
Referenced by dm96xx_probe().
| FILE_LICENCE | ( | GPL2_OR_LATER_OR_UBDL | ) |
| FILE_SECBOOT | ( | PERMITTED | ) |
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inlinestatic |
Read registers.
| dm96xx | DM96xx device |
| offset | Register offset |
| data | Data buffer |
| len | Length of data |
| rc | Return status code |
Definition at line 117 of file dm96xx.h.
References data, DM96XX_READ_REGISTER, len, offset, dm96xx_device::usb, and usb_control().
Referenced by dm96xx_read_mac(), and dm96xx_read_register().
|
inlinestatic |
Read register.
| dm96xx | DM96xx device |
| offset | Register offset |
| value | Register value, or negative error |
Definition at line 132 of file dm96xx.h.
References dm96xx_read_registers(), offset, rc, and value.
Referenced by dm96xx_check_link(), dm96xx_reset(), and dm96xx_rx_mode().
|
inlinestatic |
Write registers.
| dm96xx | DM96xx device |
| offset | Register offset |
| data | Data buffer |
| len | Length of data |
| rc | Return status code |
Definition at line 152 of file dm96xx.h.
References data, DM96XX_WRITE_REGISTER, len, offset, dm96xx_device::usb, and usb_control().
Referenced by dm96xx_write_mac().
|
inlinestatic |
Write register.
| dm96xx | DM96xx device |
| offset | Register offset |
| value | Register value |
| rc | Return status code |
Definition at line 168 of file dm96xx.h.
References DM96XX_WRITE1_REGISTER, NULL, offset, dm96xx_device::usb, usb_control(), and value.
Referenced by dm96xx_open(), dm96xx_reset(), and dm96xx_rx_mode().