7 # define PCI_VENDOR_SMC 0x10B8 10 #ifndef PCI_DEVICE_SMC_EPIC100 11 # define PCI_DEVICE_SMC_EPIC100 0x0005 14 #define PCI_DEVICE_ID_NONE 0xFFFF 46 #define CR_STOP_RX (0x00000001) 47 #define CR_START_RX (0x00000002) 48 #define CR_QUEUE_TX (0x00000004) 49 #define CR_QUEUE_RX (0x00000008) 50 #define CR_NEXTFRAME (0x00000010) 51 #define CR_STOP_TX_DMA (0x00000020) 52 #define CR_STOP_RX_DMA (0x00000040) 53 #define CR_TX_UGO (0x00000080) 57 #define INTR_RX_THR_STA (0x00400000) 58 #define INTR_RX_BUFF_EMPTY (0x00200000) 59 #define INTR_TX_IN_PROG (0x00100000) 60 #define INTR_RX_IN_PROG (0x00080000) 61 #define INTR_TXIDLE (0x00040000) 62 #define INTR_RXIDLE (0x00020000) 63 #define INTR_INTR_ACTIVE (0x00010000) 64 #define INTR_RX_STATUS_OK (0x00008000) 65 #define INTR_PCI_TGT_ABT (0x00004000) 66 #define INTR_PCI_MASTER_ABT (0x00002000) 67 #define INTR_PCI_PARITY_ERR (0x00001000) 68 #define INTR_PCI_DATA_ERR (0x00000800) 69 #define INTR_RX_THR_CROSSED (0x00000400) 70 #define INTR_CNTFULL (0x00000200) 71 #define INTR_TXUNDERRUN (0x00000100) 72 #define INTR_TXEMPTY (0x00000080) 73 #define INTR_TX_CH_COMPLETE (0x00000040) 74 #define INTR_TXDONE (0x00000020) 75 #define INTR_RXERROR (0x00000010) 76 #define INTR_RXOVERFLOW (0x00000008) 77 #define INTR_RX_QUEUE_EMPTY (0x00000004) 78 #define INTR_RXHEADER (0x00000002) 79 #define INTR_RXDONE (0x00000001) 81 #define INTR_CLEARINTR (0x00007FFF) 82 #define INTR_VALIDBITS (0x007FFFFF) 83 #define INTR_DISABLE (0x00000000) 84 #define INTR_CLEARERRS (0x00007F18) 85 #define INTR_ABNINTR (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW) 89 #define GC_SOFT_RESET (0x00000001) 90 #define GC_INTR_ENABLE (0x00000002) 91 #define GC_SOFT_INTR (0x00000004) 92 #define GC_POWER_DOWN (0x00000008) 93 #define GC_ONE_COPY (0x00000010) 94 #define GC_BIG_ENDIAN (0x00000020) 95 #define GC_RX_PREEMPT_TX (0x00000040) 96 #define GC_TX_PREEMPT_RX (0x00000080) 105 #define GC_RX_FIFO_THR_32 (0x00000000) 106 #define GC_RX_FIFO_THR_64 (0x00000100) 107 #define GC_RX_FIFO_THR_96 (0x00000200) 108 #define GC_RX_FIFO_THR_128 (0x00000300) 111 #define GC_MRC_MEM_READ (0x00000000) 112 #define GC_MRC_READ_MULT (0x00000400) 113 #define GC_MRC_READ_LINE (0x00000800) 115 #define GC_SOFTBIT0 (0x00001000) 116 #define GC_SOFTBIT1 (0x00002000) 117 #define GC_RESET_PHY (0x00004000) 121 #define RC_SAVE_ERRORED_PKT (0x00000001) 122 #define RC_SAVE_RUNT_FRAMES (0x00000002) 123 #define RC_RCV_BROADCAST (0x00000004) 124 #define RC_RCV_MULTICAST (0x00000008) 125 #define RC_RCV_INVERSE_PKT (0x00000010) 126 #define RC_PROMISCUOUS_MODE (0x00000020) 127 #define RC_MONITOR_MODE (0x00000040) 128 #define RC_EARLY_RCV_ENABLE (0x00000080) 131 #define RD_FRAGLIST (0x0001) 132 #define RD_LLFORM (0x0002) 133 #define RD_HDR_CPY (0x0004) 137 #define TC_EARLY_TX_ENABLE (0x00000001) 140 #define TC_LM_NORMAL (0x00000000) 141 #define TC_LM_INTERNAL (0x00000002) 142 #define TC_LM_EXTERNAL (0x00000004) 143 #define TC_LM_FULL_DPX (0x00000006) 145 #define TX_SLOT_TIME (0x00000078) 148 #define TX_FIFO_THRESH 128 151 #define RRING_PKT_INTACT (0x0001) 152 #define RRING_ALIGN_ERR (0x0002) 153 #define RRING_CRC_ERR (0x0004) 154 #define RRING_MISSED_PKT (0x0008) 155 #define RRING_MULTICAST (0x0010) 156 #define RRING_BROADCAST (0x0020) 157 #define RRING_RECEIVER_DISABLE (0x0040) 158 #define RRING_STATUS_VALID (0x1000) 159 #define RRING_FRAGLIST_ERR (0x2000) 160 #define RRING_HDR_COPIED (0x4000) 161 #define RRING_OWN (0x8000) 164 #define RRING_ERROR (RRING_ALIGN_ERR|RRING_CRC_ERR) 167 #define TRING_PKT_INTACT (0x0001) 168 #define TRING_PKT_NONDEFER (0x0002) 169 #define TRING_COLL (0x0004) 170 #define TRING_CARR (0x0008) 171 #define TRING_UNDERRUN (0x0010) 172 #define TRING_HB_COLL (0x0020) 173 #define TRING_WIN_COLL (0x0040) 174 #define TRING_DEFERRED (0x0080) 175 #define TRING_COLL_COUNT (0x0F00) 176 #define TRING_COLL_EXCESS (0x1000) 177 #define TRING_OWN (0x8000) 180 #define TRING_ABORT (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN) 181 #define TRING_ERROR (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR ) 184 #define TD_FRAGLIST (0x0001) 185 #define TD_LLFORM (0x0002) 186 #define TD_IAF (0x0004) 187 #define TD_NOCRC (0x0008) 188 #define TD_LASTDESC (0x0010)
FILE_LICENCE(GPL2_OR_LATER)