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| #define | PCI_VENDOR_SMC 0x10B8 |
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| #define | PCI_DEVICE_SMC_EPIC100 0x0005 |
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| #define | PCI_DEVICE_ID_NONE 0xFFFF |
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| #define | CR_STOP_RX (0x00000001) |
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| #define | CR_START_RX (0x00000002) |
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| #define | CR_QUEUE_TX (0x00000004) |
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| #define | CR_QUEUE_RX (0x00000008) |
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| #define | CR_NEXTFRAME (0x00000010) |
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| #define | CR_STOP_TX_DMA (0x00000020) |
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| #define | CR_STOP_RX_DMA (0x00000040) |
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| #define | CR_TX_UGO (0x00000080) |
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| #define | INTR_RX_THR_STA (0x00400000) /* rx copy threshold status NI */ |
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| #define | INTR_RX_BUFF_EMPTY (0x00200000) /* rx buffers empty. NI */ |
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| #define | INTR_TX_IN_PROG (0x00100000) /* tx copy in progess. NI */ |
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| #define | INTR_RX_IN_PROG (0x00080000) /* rx copy in progress. NI */ |
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| #define | INTR_TXIDLE (0x00040000) /* tx idle. NI */ |
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| #define | INTR_RXIDLE (0x00020000) /* rx idle. NI */ |
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| #define | INTR_INTR_ACTIVE (0x00010000) /* Interrupt active. NI */ |
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| #define | INTR_RX_STATUS_OK (0x00008000) /* rx status valid. NI */ |
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| #define | INTR_PCI_TGT_ABT (0x00004000) /* PCI Target abort */ |
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| #define | INTR_PCI_MASTER_ABT (0x00002000) /* PCI Master abort */ |
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| #define | INTR_PCI_PARITY_ERR (0x00001000) /* PCI address parity error */ |
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| #define | INTR_PCI_DATA_ERR (0x00000800) /* PCI data parity error */ |
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| #define | INTR_RX_THR_CROSSED (0x00000400) /* rx copy threshold crossed */ |
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| #define | INTR_CNTFULL (0x00000200) /* Counter overflow */ |
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| #define | INTR_TXUNDERRUN (0x00000100) /* tx underrun. */ |
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| #define | INTR_TXEMPTY (0x00000080) /* tx queue empty */ |
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| #define | INTR_TX_CH_COMPLETE (0x00000040) /* tx chain complete */ |
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| #define | INTR_TXDONE (0x00000020) /* tx complete (w or w/o err) */ |
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| #define | INTR_RXERROR (0x00000010) /* rx error (CRC) */ |
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| #define | INTR_RXOVERFLOW (0x00000008) /* rx buffer overflow */ |
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| #define | INTR_RX_QUEUE_EMPTY (0x00000004) /* rx queue empty. */ |
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| #define | INTR_RXHEADER (0x00000002) /* header copy complete */ |
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| #define | INTR_RXDONE (0x00000001) /* Receive copy complete */ |
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| #define | INTR_CLEARINTR (0x00007FFF) |
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| #define | INTR_VALIDBITS (0x007FFFFF) |
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| #define | INTR_DISABLE (0x00000000) |
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| #define | INTR_CLEARERRS (0x00007F18) |
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| #define | INTR_ABNINTR (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW) |
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| #define | GC_SOFT_RESET (0x00000001) |
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| #define | GC_INTR_ENABLE (0x00000002) |
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| #define | GC_SOFT_INTR (0x00000004) |
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| #define | GC_POWER_DOWN (0x00000008) |
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| #define | GC_ONE_COPY (0x00000010) |
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| #define | GC_BIG_ENDIAN (0x00000020) |
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| #define | GC_RX_PREEMPT_TX (0x00000040) |
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| #define | GC_TX_PREEMPT_RX (0x00000080) |
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| #define | GC_RX_FIFO_THR_32 (0x00000000) |
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| #define | GC_RX_FIFO_THR_64 (0x00000100) |
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| #define | GC_RX_FIFO_THR_96 (0x00000200) |
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| #define | GC_RX_FIFO_THR_128 (0x00000300) |
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| #define | GC_MRC_MEM_READ (0x00000000) |
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| #define | GC_MRC_READ_MULT (0x00000400) |
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| #define | GC_MRC_READ_LINE (0x00000800) |
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| #define | GC_SOFTBIT0 (0x00001000) |
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| #define | GC_SOFTBIT1 (0x00002000) |
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| #define | GC_RESET_PHY (0x00004000) |
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| #define | RC_SAVE_ERRORED_PKT (0x00000001) |
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| #define | RC_SAVE_RUNT_FRAMES (0x00000002) |
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| #define | RC_RCV_BROADCAST (0x00000004) |
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| #define | RC_RCV_MULTICAST (0x00000008) |
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| #define | RC_RCV_INVERSE_PKT (0x00000010) |
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| #define | RC_PROMISCUOUS_MODE (0x00000020) |
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| #define | RC_MONITOR_MODE (0x00000040) |
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| #define | RC_EARLY_RCV_ENABLE (0x00000080) |
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| #define | RD_FRAGLIST (0x0001) /* Desc points to a fragment list */ |
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| #define | RD_LLFORM (0x0002) /* Frag list format */ |
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| #define | RD_HDR_CPY (0x0004) /* Desc used for header copy */ |
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| #define | TC_EARLY_TX_ENABLE (0x00000001) |
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| #define | TC_LM_NORMAL (0x00000000) |
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| #define | TC_LM_INTERNAL (0x00000002) |
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| #define | TC_LM_EXTERNAL (0x00000004) |
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| #define | TC_LM_FULL_DPX (0x00000006) |
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| #define | TX_SLOT_TIME (0x00000078) |
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| #define | TX_FIFO_THRESH 128 /* Rounded down to 4 byte units. */ |
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| #define | RRING_PKT_INTACT (0x0001) |
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| #define | RRING_ALIGN_ERR (0x0002) |
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| #define | RRING_CRC_ERR (0x0004) |
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| #define | RRING_MISSED_PKT (0x0008) |
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| #define | RRING_MULTICAST (0x0010) |
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| #define | RRING_BROADCAST (0x0020) |
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| #define | RRING_RECEIVER_DISABLE (0x0040) |
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| #define | RRING_STATUS_VALID (0x1000) |
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| #define | RRING_FRAGLIST_ERR (0x2000) |
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| #define | RRING_HDR_COPIED (0x4000) |
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| #define | RRING_OWN (0x8000) |
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| #define | RRING_ERROR (RRING_ALIGN_ERR|RRING_CRC_ERR) |
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| #define | TRING_PKT_INTACT (0x0001) /* pkt transmitted. */ |
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| #define | TRING_PKT_NONDEFER (0x0002) /* pkt xmitted w/o deferring */ |
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| #define | TRING_COLL (0x0004) /* pkt xmitted w collisions */ |
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| #define | TRING_CARR (0x0008) /* carrier sense lost */ |
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| #define | TRING_UNDERRUN (0x0010) /* DMA underrun */ |
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| #define | TRING_HB_COLL (0x0020) /* Collision detect Heartbeat */ |
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| #define | TRING_WIN_COLL (0x0040) /* out of window collision */ |
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| #define | TRING_DEFERRED (0x0080) /* Deferring */ |
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| #define | TRING_COLL_COUNT (0x0F00) /* collision counter (mask) */ |
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| #define | TRING_COLL_EXCESS (0x1000) /* tx aborted: excessive colls */ |
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| #define | TRING_OWN (0x8000) /* desc ownership bit */ |
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| #define | TRING_ABORT (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN) |
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| #define | TRING_ERROR (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR/*|TRING_COLL*/ ) |
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| #define | TD_FRAGLIST (0x0001) /* Desc points to a fragment list */ |
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| #define | TD_LLFORM (0x0002) /* Frag list format */ |
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| #define | TD_IAF (0x0004) /* Generate Interrupt after tx */ |
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| #define | TD_NOCRC (0x0008) /* No CRC generated */ |
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| #define | TD_LASTDESC (0x0010) /* Last desc for this frame */ |
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