iPXE
Macros
SPI status register bits (not present on all devices)

Macros

#define SPI_STATUS_WPEN   0x80
 Write-protect pin enabled. More...
 
#define SPI_STATUS_BP2   0x10
 Block protection bit 2. More...
 
#define SPI_STATUS_BP1   0x08
 Block protection bit 1. More...
 
#define SPI_STATUS_BP0   0x04
 Block protection bit 0. More...
 
#define SPI_STATUS_WEN   0x02
 State of the write enable latch. More...
 
#define SPI_STATUS_NRDY   0x01
 Device busy flag. More...
 

Detailed Description

Macro Definition Documentation

◆ SPI_STATUS_WPEN

#define SPI_STATUS_WPEN   0x80

Write-protect pin enabled.

Definition at line 61 of file spi.h.

◆ SPI_STATUS_BP2

#define SPI_STATUS_BP2   0x10

Block protection bit 2.

Definition at line 64 of file spi.h.

◆ SPI_STATUS_BP1

#define SPI_STATUS_BP1   0x08

Block protection bit 1.

Definition at line 67 of file spi.h.

◆ SPI_STATUS_BP0

#define SPI_STATUS_BP0   0x04

Block protection bit 0.

Definition at line 70 of file spi.h.

◆ SPI_STATUS_WEN

#define SPI_STATUS_WEN   0x02

State of the write enable latch.

Definition at line 73 of file spi.h.

◆ SPI_STATUS_NRDY

#define SPI_STATUS_NRDY   0x01

Device busy flag.

Definition at line 76 of file spi.h.