|
iPXE
|
Go to the source code of this file.
Macros | |
| #define | _IGBVF_REGS_H_ |
| #define | E1000_CTRL 0x00000 /* Device Control - RW */ |
| #define | E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ |
| #define | E1000_STATUS 0x00008 /* Device Status - RO */ |
| #define | E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ |
| #define | E1000_EERD 0x00014 /* EEPROM Read - RW */ |
| #define | E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ |
| #define | E1000_FLA 0x0001C /* Flash Access - RW */ |
| #define | E1000_MDIC 0x00020 /* MDI Control - RW */ |
| #define | E1000_SCTL 0x00024 /* SerDes Control - RW */ |
| #define | E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ |
| #define | E1000_FCAH 0x0002C /* Flow Control Address High -RW */ |
| #define | E1000_FEXT 0x0002C /* Future Extended - RW */ |
| #define | E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ |
| #define | E1000_FCT 0x00030 /* Flow Control Type - RW */ |
| #define | E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ |
| #define | E1000_VET 0x00038 /* VLAN Ether Type - RW */ |
| #define | E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ |
| #define | E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ |
| #define | E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ |
| #define | E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ |
| #define | E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ |
| #define | E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ |
| #define | E1000_RCTL 0x00100 /* Rx Control - RW */ |
| #define | E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ |
| #define | E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ |
| #define | E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ |
| #define | E1000_TCTL 0x00400 /* Tx Control - RW */ |
| #define | E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ |
| #define | E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ |
| #define | E1000_TBT 0x00448 /* Tx Burst Timer - RW */ |
| #define | E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ |
| #define | E1000_LEDCTL 0x00E00 /* LED Control - RW */ |
| #define | E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ |
| #define | E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ |
| #define | E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ |
| #define | E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ |
| #define | E1000_PBS 0x01008 /* Packet Buffer Size */ |
| #define | E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ |
| #define | E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ |
| #define | E1000_FLASHT 0x01028 /* FLASH Timer Register */ |
| #define | E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ |
| #define | E1000_FLSWCTL 0x01030 /* FLASH control register */ |
| #define | E1000_FLSWDATA 0x01034 /* FLASH data register */ |
| #define | E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ |
| #define | E1000_FLOP 0x0103C /* FLASH Opcode Register */ |
| #define | E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ |
| #define | E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ |
| #define | E1000_WDSTP 0x01040 /* Watchdog Setup - RW */ |
| #define | E1000_SWDSTS 0x01044 /* SW Device Status - RW */ |
| #define | E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ |
| #define | E1000_ERT 0x02008 /* Early Rx Threshold - RW */ |
| #define | E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ |
| #define | E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
| #define | E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ |
| #define | E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) |
| #define | E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ |
| #define | E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ |
| #define | E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ |
| #define | E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ |
| #define | E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ |
| #define | E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ |
| #define | E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ |
| #define | E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n))) |
| #define | E1000_RQDPC(_n) (0x0C030 + (0x40 * (_n))) |
| #define | E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ |
| #define | E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ |
| #define | E1000_RDBAL(_n) |
| #define | E1000_RDBAH(_n) |
| #define | E1000_RDLEN(_n) |
| #define | E1000_SRRCTL(_n) |
| #define | E1000_RDH(_n) |
| #define | E1000_RDT(_n) |
| #define | E1000_RXDCTL(_n) |
| #define | E1000_TDBAL(_n) |
| #define | E1000_TDBAH(_n) |
| #define | E1000_TDLEN(_n) |
| #define | E1000_TDH(_n) |
| #define | E1000_TDT(_n) |
| #define | E1000_TXDCTL(_n) |
| #define | E1000_TARC(_n) (0x03840 + (_n << 8)) |
| #define | E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) |
| #define | E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) |
| #define | E1000_TDWBAL(_n) |
| #define | E1000_TDWBAH(_n) |
| #define | E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ |
| #define | E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ |
| #define | E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ |
| #define | E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ |
| #define | E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) |
| #define | E1000_RAL(_i) |
| #define | E1000_RAH(_i) |
| #define | E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) |
| #define | E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) |
| #define | E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) |
| #define | E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) |
| #define | E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) |
| #define | E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) |
| #define | E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ |
| #define | E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ |
| #define | E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ |
| #define | E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ |
| #define | E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ |
| #define | E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */ |
| #define | E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */ |
| #define | E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */ |
| #define | E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */ |
| #define | E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */ |
| #define | E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */ |
| #define | E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ |
| #define | E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ |
| #define | E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ |
| #define | E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ |
| #define | E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ |
| #define | E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ |
| #define | E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ |
| #define | E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ |
| #define | E1000_SCC 0x04014 /* Single Collision Count - R/clr */ |
| #define | E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ |
| #define | E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ |
| #define | E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ |
| #define | E1000_COLC 0x04028 /* Collision Count - R/clr */ |
| #define | E1000_DC 0x04030 /* Defer Count - R/clr */ |
| #define | E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ |
| #define | E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ |
| #define | E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ |
| #define | E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ |
| #define | E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ |
| #define | E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ |
| #define | E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ |
| #define | E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ |
| #define | E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ |
| #define | E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ |
| #define | E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ |
| #define | E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ |
| #define | E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ |
| #define | E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ |
| #define | E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ |
| #define | E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ |
| #define | E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ |
| #define | E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ |
| #define | E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ |
| #define | E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ |
| #define | E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ |
| #define | E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ |
| #define | E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ |
| #define | E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ |
| #define | E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ |
| #define | E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ |
| #define | E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ |
| #define | E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ |
| #define | E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ |
| #define | E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ |
| #define | E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ |
| #define | E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ |
| #define | E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ |
| #define | E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ |
| #define | E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ |
| #define | E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ |
| #define | E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ |
| #define | E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ |
| #define | E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ |
| #define | E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ |
| #define | E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ |
| #define | E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ |
| #define | E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ |
| #define | E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ |
| #define | E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ |
| #define | E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ |
| #define | E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ |
| #define | E1000_IAC 0x04100 /* Interrupt Assertion Count */ |
| #define | E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ |
| #define | E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ |
| #define | E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ |
| #define | E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ |
| #define | E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ |
| #define | E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ |
| #define | E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ |
| #define | E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ |
| #define | E1000_VFGPRC 0x00F10 |
| #define | E1000_VFGORC 0x00F18 |
| #define | E1000_VFMPRC 0x00F3C |
| #define | E1000_VFGPTC 0x00F14 |
| #define | E1000_VFGOTC 0x00F34 |
| #define | E1000_VFGOTLBC 0x00F50 |
| #define | E1000_VFGPTLBC 0x00F44 |
| #define | E1000_VFGORLBC 0x00F48 |
| #define | E1000_VFGPRLBC 0x00F40 |
| #define | E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ |
| #define | E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ |
| #define | E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ |
| #define | E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */ |
| #define | E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ |
| #define | E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */ |
| #define | E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */ |
| #define | E1000_RPTHC 0x04104 /* Rx Packets To Host */ |
| #define | E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */ |
| #define | E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */ |
| #define | E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ |
| #define | E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ |
| #define | E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ |
| #define | E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ |
| #define | E1000_LENERRS 0x04138 /* Length Errors Count */ |
| #define | E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ |
| #define | E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ |
| #define | E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ |
| #define | E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ |
| #define | E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ |
| #define | E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ |
| #define | E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */ |
| #define | E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ |
| #define | E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ |
| #define | E1000_RFCTL 0x05008 /* Receive Filter Control*/ |
| #define | E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ |
| #define | E1000_RA 0x05400 /* Receive Address - RW Array */ |
| #define | E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ |
| #define | E1000_VT_CTL 0x0581C /* VMDq Control - RW */ |
| #define | E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ |
| #define | E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ |
| #define | E1000_WUC 0x05800 /* Wakeup Control - RW */ |
| #define | E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ |
| #define | E1000_WUS 0x05810 /* Wakeup Status - RO */ |
| #define | E1000_MANC 0x05820 /* Management Control - RW */ |
| #define | E1000_IPAV 0x05838 /* IP Address Valid - RW */ |
| #define | E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ |
| #define | E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ |
| #define | E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ |
| #define | E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ |
| #define | E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ |
| #define | E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ |
| #define | E1000_HOST_IF 0x08800 /* Host Interface */ |
| #define | E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ |
| #define | E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ |
| #define | E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ |
| #define | E1000_MDPHYA 0x0003C /* PHY address - RW */ |
| #define | E1000_MANC2H 0x05860 /* Management Control To Host - RW */ |
| #define | E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
| #define | E1000_CCMCTL 0x05B48 /* CCM Control Register */ |
| #define | E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ |
| #define | E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ |
| #define | E1000_GCR 0x05B00 /* PCI-Ex Control */ |
| #define | E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ |
| #define | E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ |
| #define | E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ |
| #define | E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ |
| #define | E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ |
| #define | E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ |
| #define | E1000_SWSM 0x05B50 /* SW Semaphore */ |
| #define | E1000_FWSM 0x05B54 /* FW Semaphore */ |
| #define | E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ |
| #define | E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ |
| #define | E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ |
| #define | E1000_FFLT_DBG 0x05F04 /* Debug Register */ |
| #define | E1000_HICR 0x08F00 /* Host Interface Control */ |
| #define | E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ |
| #define | E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ |
| #define | E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ |
| #define | E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ |
| #define | E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */ |
| #define | E1000_MSIXBM(_i) |
| #define | E1000_MSIXTADD(_i) |
| #define | E1000_MSIXTUADD(_i) |
| #define | E1000_MSIXTMSG(_i) |
| #define | E1000_MSIXVCTRL(_i) |
| #define | E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ |
| #define | E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ |
| #define | E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ |
| #define | E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ |
| #define | E1000_RSSIR 0x05868 /* RSS Interrupt Request */ |
Functions | |
| FILE_LICENCE (GPL2_ONLY) | |
| #define _IGBVF_REGS_H_ |
Definition at line 32 of file igbvf_regs.h.
| #define E1000_CTRL 0x00000 /* Device Control - RW */ |
Definition at line 34 of file igbvf_regs.h.
| #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ |
Definition at line 35 of file igbvf_regs.h.
| #define E1000_STATUS 0x00008 /* Device Status - RO */ |
Definition at line 36 of file igbvf_regs.h.
| #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ |
Definition at line 37 of file igbvf_regs.h.
| #define E1000_EERD 0x00014 /* EEPROM Read - RW */ |
Definition at line 38 of file igbvf_regs.h.
| #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ |
Definition at line 39 of file igbvf_regs.h.
| #define E1000_FLA 0x0001C /* Flash Access - RW */ |
Definition at line 40 of file igbvf_regs.h.
| #define E1000_MDIC 0x00020 /* MDI Control - RW */ |
Definition at line 41 of file igbvf_regs.h.
| #define E1000_SCTL 0x00024 /* SerDes Control - RW */ |
Definition at line 42 of file igbvf_regs.h.
| #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ |
Definition at line 43 of file igbvf_regs.h.
| #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ |
Definition at line 44 of file igbvf_regs.h.
| #define E1000_FEXT 0x0002C /* Future Extended - RW */ |
Definition at line 45 of file igbvf_regs.h.
| #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ |
Definition at line 46 of file igbvf_regs.h.
| #define E1000_FCT 0x00030 /* Flow Control Type - RW */ |
Definition at line 47 of file igbvf_regs.h.
| #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ |
Definition at line 48 of file igbvf_regs.h.
| #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ |
Definition at line 49 of file igbvf_regs.h.
| #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ |
Definition at line 50 of file igbvf_regs.h.
| #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ |
Definition at line 51 of file igbvf_regs.h.
| #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ |
Definition at line 52 of file igbvf_regs.h.
| #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ |
Definition at line 53 of file igbvf_regs.h.
| #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ |
Definition at line 54 of file igbvf_regs.h.
| #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ |
Definition at line 55 of file igbvf_regs.h.
| #define E1000_RCTL 0x00100 /* Rx Control - RW */ |
Definition at line 56 of file igbvf_regs.h.
| #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ |
Definition at line 57 of file igbvf_regs.h.
| #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ |
Definition at line 58 of file igbvf_regs.h.
| #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ |
Definition at line 59 of file igbvf_regs.h.
| #define E1000_TCTL 0x00400 /* Tx Control - RW */ |
Definition at line 60 of file igbvf_regs.h.
| #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ |
Definition at line 61 of file igbvf_regs.h.
| #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ |
Definition at line 62 of file igbvf_regs.h.
| #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */ |
Definition at line 63 of file igbvf_regs.h.
| #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ |
Definition at line 64 of file igbvf_regs.h.
| #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ |
Definition at line 65 of file igbvf_regs.h.
| #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ |
Definition at line 66 of file igbvf_regs.h.
| #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ |
Definition at line 67 of file igbvf_regs.h.
| #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ |
Definition at line 68 of file igbvf_regs.h.
| #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ |
Definition at line 69 of file igbvf_regs.h.
| #define E1000_PBS 0x01008 /* Packet Buffer Size */ |
Definition at line 70 of file igbvf_regs.h.
| #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ |
Definition at line 71 of file igbvf_regs.h.
| #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ |
Definition at line 72 of file igbvf_regs.h.
| #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ |
Definition at line 73 of file igbvf_regs.h.
| #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ |
Definition at line 74 of file igbvf_regs.h.
| #define E1000_FLSWCTL 0x01030 /* FLASH control register */ |
Definition at line 75 of file igbvf_regs.h.
| #define E1000_FLSWDATA 0x01034 /* FLASH data register */ |
Definition at line 76 of file igbvf_regs.h.
| #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ |
Definition at line 77 of file igbvf_regs.h.
| #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ |
Definition at line 78 of file igbvf_regs.h.
| #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ |
Definition at line 79 of file igbvf_regs.h.
| #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ |
Definition at line 80 of file igbvf_regs.h.
| #define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */ |
Definition at line 81 of file igbvf_regs.h.
| #define E1000_SWDSTS 0x01044 /* SW Device Status - RW */ |
Definition at line 82 of file igbvf_regs.h.
| #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ |
Definition at line 83 of file igbvf_regs.h.
| #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ |
Definition at line 84 of file igbvf_regs.h.
| #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ |
Definition at line 85 of file igbvf_regs.h.
| #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
Definition at line 86 of file igbvf_regs.h.
| #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ |
Definition at line 87 of file igbvf_regs.h.
| #define E1000_RDFPCQ | ( | _n | ) | (0x02430 + (0x4 * (_n))) |
Definition at line 88 of file igbvf_regs.h.
| #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ |
Definition at line 89 of file igbvf_regs.h.
| #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ |
Definition at line 90 of file igbvf_regs.h.
| #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ |
Definition at line 92 of file igbvf_regs.h.
| #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ |
Definition at line 93 of file igbvf_regs.h.
| #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ |
Definition at line 94 of file igbvf_regs.h.
| #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ |
Definition at line 95 of file igbvf_regs.h.
| #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ |
Definition at line 96 of file igbvf_regs.h.
| #define E1000_RXCTL | ( | _n | ) | (0x0C014 + (0x40 * (_n))) |
Definition at line 97 of file igbvf_regs.h.
| #define E1000_RQDPC | ( | _n | ) | (0x0C030 + (0x40 * (_n))) |
Definition at line 98 of file igbvf_regs.h.
| #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ |
Definition at line 99 of file igbvf_regs.h.
| #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ |
Definition at line 100 of file igbvf_regs.h.
| #define E1000_RDBAL | ( | _n | ) |
Definition at line 109 of file igbvf_regs.h.
| #define E1000_RDBAH | ( | _n | ) |
Definition at line 111 of file igbvf_regs.h.
| #define E1000_RDLEN | ( | _n | ) |
Definition at line 113 of file igbvf_regs.h.
| #define E1000_SRRCTL | ( | _n | ) |
Definition at line 115 of file igbvf_regs.h.
| #define E1000_RDH | ( | _n | ) |
Definition at line 117 of file igbvf_regs.h.
| #define E1000_RDT | ( | _n | ) |
Definition at line 119 of file igbvf_regs.h.
| #define E1000_RXDCTL | ( | _n | ) |
Definition at line 121 of file igbvf_regs.h.
| #define E1000_TDBAL | ( | _n | ) |
Definition at line 123 of file igbvf_regs.h.
| #define E1000_TDBAH | ( | _n | ) |
Definition at line 125 of file igbvf_regs.h.
| #define E1000_TDLEN | ( | _n | ) |
Definition at line 127 of file igbvf_regs.h.
| #define E1000_TDH | ( | _n | ) |
Definition at line 129 of file igbvf_regs.h.
| #define E1000_TDT | ( | _n | ) |
Definition at line 131 of file igbvf_regs.h.
| #define E1000_TXDCTL | ( | _n | ) |
Definition at line 133 of file igbvf_regs.h.
| #define E1000_TARC | ( | _n | ) | (0x03840 + (_n << 8)) |
Definition at line 135 of file igbvf_regs.h.
| #define E1000_DCA_TXCTRL | ( | _n | ) | (0x03814 + (_n << 8)) |
Definition at line 136 of file igbvf_regs.h.
| #define E1000_DCA_RXCTRL | ( | _n | ) | (0x02814 + (_n << 8)) |
Definition at line 137 of file igbvf_regs.h.
| #define E1000_TDWBAL | ( | _n | ) |
Definition at line 138 of file igbvf_regs.h.
| #define E1000_TDWBAH | ( | _n | ) |
Definition at line 140 of file igbvf_regs.h.
| #define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ |
Definition at line 142 of file igbvf_regs.h.
| #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ |
Definition at line 143 of file igbvf_regs.h.
| #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ |
Definition at line 144 of file igbvf_regs.h.
| #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ |
Definition at line 145 of file igbvf_regs.h.
| #define E1000_PSRTYPE | ( | _i | ) | (0x05480 + ((_i) * 4)) |
Definition at line 146 of file igbvf_regs.h.
| #define E1000_RAL | ( | _i | ) |
Definition at line 147 of file igbvf_regs.h.
| #define E1000_RAH | ( | _i | ) |
Definition at line 149 of file igbvf_regs.h.
| #define E1000_IP4AT_REG | ( | _i | ) | (0x05840 + ((_i) * 8)) |
Definition at line 151 of file igbvf_regs.h.
| #define E1000_IP6AT_REG | ( | _i | ) | (0x05880 + ((_i) * 4)) |
Definition at line 152 of file igbvf_regs.h.
| #define E1000_WUPM_REG | ( | _i | ) | (0x05A00 + ((_i) * 4)) |
Definition at line 153 of file igbvf_regs.h.
| #define E1000_FFMT_REG | ( | _i | ) | (0x09000 + ((_i) * 8)) |
Definition at line 154 of file igbvf_regs.h.
| #define E1000_FFVT_REG | ( | _i | ) | (0x09800 + ((_i) * 8)) |
Definition at line 155 of file igbvf_regs.h.
| #define E1000_FFLT_REG | ( | _i | ) | (0x05F00 + ((_i) * 8)) |
Definition at line 156 of file igbvf_regs.h.
| #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ |
Definition at line 157 of file igbvf_regs.h.
| #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ |
Definition at line 158 of file igbvf_regs.h.
| #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ |
Definition at line 159 of file igbvf_regs.h.
| #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ |
Definition at line 160 of file igbvf_regs.h.
| #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ |
Definition at line 161 of file igbvf_regs.h.
| #define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */ |
Definition at line 162 of file igbvf_regs.h.
| #define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */ |
Definition at line 163 of file igbvf_regs.h.
| #define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */ |
Definition at line 164 of file igbvf_regs.h.
| #define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */ |
Definition at line 165 of file igbvf_regs.h.
| #define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */ |
Definition at line 166 of file igbvf_regs.h.
| #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */ |
Definition at line 167 of file igbvf_regs.h.
| #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ |
Definition at line 168 of file igbvf_regs.h.
| #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ |
Definition at line 169 of file igbvf_regs.h.
| #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ |
Definition at line 170 of file igbvf_regs.h.
| #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ |
Definition at line 171 of file igbvf_regs.h.
| #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ |
Definition at line 172 of file igbvf_regs.h.
| #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ |
Definition at line 173 of file igbvf_regs.h.
| #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ |
Definition at line 174 of file igbvf_regs.h.
| #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ |
Definition at line 175 of file igbvf_regs.h.
| #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ |
Definition at line 176 of file igbvf_regs.h.
| #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ |
Definition at line 177 of file igbvf_regs.h.
| #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ |
Definition at line 178 of file igbvf_regs.h.
| #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ |
Definition at line 179 of file igbvf_regs.h.
| #define E1000_COLC 0x04028 /* Collision Count - R/clr */ |
Definition at line 180 of file igbvf_regs.h.
| #define E1000_DC 0x04030 /* Defer Count - R/clr */ |
Definition at line 181 of file igbvf_regs.h.
| #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ |
Definition at line 182 of file igbvf_regs.h.
| #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ |
Definition at line 183 of file igbvf_regs.h.
| #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ |
Definition at line 184 of file igbvf_regs.h.
| #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ |
Definition at line 185 of file igbvf_regs.h.
| #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ |
Definition at line 186 of file igbvf_regs.h.
| #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ |
Definition at line 187 of file igbvf_regs.h.
| #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ |
Definition at line 188 of file igbvf_regs.h.
| #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ |
Definition at line 189 of file igbvf_regs.h.
| #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ |
Definition at line 190 of file igbvf_regs.h.
| #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ |
Definition at line 191 of file igbvf_regs.h.
| #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ |
Definition at line 192 of file igbvf_regs.h.
| #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ |
Definition at line 193 of file igbvf_regs.h.
| #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ |
Definition at line 194 of file igbvf_regs.h.
| #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ |
Definition at line 195 of file igbvf_regs.h.
| #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ |
Definition at line 196 of file igbvf_regs.h.
| #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ |
Definition at line 197 of file igbvf_regs.h.
| #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ |
Definition at line 198 of file igbvf_regs.h.
| #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ |
Definition at line 199 of file igbvf_regs.h.
| #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ |
Definition at line 200 of file igbvf_regs.h.
| #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ |
Definition at line 201 of file igbvf_regs.h.
| #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ |
Definition at line 202 of file igbvf_regs.h.
| #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ |
Definition at line 203 of file igbvf_regs.h.
| #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ |
Definition at line 204 of file igbvf_regs.h.
| #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ |
Definition at line 205 of file igbvf_regs.h.
| #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ |
Definition at line 206 of file igbvf_regs.h.
| #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ |
Definition at line 207 of file igbvf_regs.h.
| #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ |
Definition at line 208 of file igbvf_regs.h.
| #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ |
Definition at line 209 of file igbvf_regs.h.
| #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ |
Definition at line 210 of file igbvf_regs.h.
| #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ |
Definition at line 211 of file igbvf_regs.h.
| #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ |
Definition at line 212 of file igbvf_regs.h.
| #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ |
Definition at line 213 of file igbvf_regs.h.
| #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ |
Definition at line 214 of file igbvf_regs.h.
| #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ |
Definition at line 215 of file igbvf_regs.h.
| #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ |
Definition at line 216 of file igbvf_regs.h.
| #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ |
Definition at line 217 of file igbvf_regs.h.
| #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ |
Definition at line 218 of file igbvf_regs.h.
| #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ |
Definition at line 219 of file igbvf_regs.h.
| #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ |
Definition at line 220 of file igbvf_regs.h.
| #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ |
Definition at line 221 of file igbvf_regs.h.
| #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ |
Definition at line 222 of file igbvf_regs.h.
| #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ |
Definition at line 223 of file igbvf_regs.h.
| #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ |
Definition at line 224 of file igbvf_regs.h.
| #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ |
Definition at line 225 of file igbvf_regs.h.
| #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ |
Definition at line 226 of file igbvf_regs.h.
| #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ |
Definition at line 227 of file igbvf_regs.h.
| #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ |
Definition at line 228 of file igbvf_regs.h.
| #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ |
Definition at line 229 of file igbvf_regs.h.
| #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ |
Definition at line 230 of file igbvf_regs.h.
| #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ |
Definition at line 231 of file igbvf_regs.h.
| #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ |
Definition at line 232 of file igbvf_regs.h.
| #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ |
Definition at line 233 of file igbvf_regs.h.
| #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ |
Definition at line 234 of file igbvf_regs.h.
| #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ |
Definition at line 235 of file igbvf_regs.h.
| #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ |
Definition at line 236 of file igbvf_regs.h.
| #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ |
Definition at line 237 of file igbvf_regs.h.
| #define E1000_VFGPRC 0x00F10 |
Definition at line 239 of file igbvf_regs.h.
| #define E1000_VFGORC 0x00F18 |
Definition at line 240 of file igbvf_regs.h.
| #define E1000_VFMPRC 0x00F3C |
Definition at line 241 of file igbvf_regs.h.
| #define E1000_VFGPTC 0x00F14 |
Definition at line 242 of file igbvf_regs.h.
| #define E1000_VFGOTC 0x00F34 |
Definition at line 243 of file igbvf_regs.h.
| #define E1000_VFGOTLBC 0x00F50 |
Definition at line 244 of file igbvf_regs.h.
| #define E1000_VFGPTLBC 0x00F44 |
Definition at line 245 of file igbvf_regs.h.
| #define E1000_VFGORLBC 0x00F48 |
Definition at line 246 of file igbvf_regs.h.
| #define E1000_VFGPRLBC 0x00F40 |
Definition at line 247 of file igbvf_regs.h.
| #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ |
Definition at line 248 of file igbvf_regs.h.
| #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ |
Definition at line 249 of file igbvf_regs.h.
| #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ |
Definition at line 250 of file igbvf_regs.h.
| #define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */ |
Definition at line 251 of file igbvf_regs.h.
| #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ |
Definition at line 252 of file igbvf_regs.h.
| #define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */ |
Definition at line 253 of file igbvf_regs.h.
| #define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */ |
Definition at line 254 of file igbvf_regs.h.
| #define E1000_RPTHC 0x04104 /* Rx Packets To Host */ |
Definition at line 255 of file igbvf_regs.h.
| #define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */ |
Definition at line 256 of file igbvf_regs.h.
| #define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */ |
Definition at line 257 of file igbvf_regs.h.
| #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ |
Definition at line 258 of file igbvf_regs.h.
| #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ |
Definition at line 259 of file igbvf_regs.h.
| #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ |
Definition at line 260 of file igbvf_regs.h.
| #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ |
Definition at line 261 of file igbvf_regs.h.
| #define E1000_LENERRS 0x04138 /* Length Errors Count */ |
Definition at line 262 of file igbvf_regs.h.
| #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ |
Definition at line 263 of file igbvf_regs.h.
| #define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ |
Definition at line 264 of file igbvf_regs.h.
| #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ |
Definition at line 265 of file igbvf_regs.h.
| #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ |
Definition at line 266 of file igbvf_regs.h.
| #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ |
Definition at line 267 of file igbvf_regs.h.
| #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ |
Definition at line 268 of file igbvf_regs.h.
| #define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */ |
Definition at line 269 of file igbvf_regs.h.
| #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ |
Definition at line 270 of file igbvf_regs.h.
| #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ |
Definition at line 271 of file igbvf_regs.h.
| #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ |
Definition at line 272 of file igbvf_regs.h.
| #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ |
Definition at line 273 of file igbvf_regs.h.
| #define E1000_RA 0x05400 /* Receive Address - RW Array */ |
Definition at line 274 of file igbvf_regs.h.
| #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ |
Definition at line 275 of file igbvf_regs.h.
| #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ |
Definition at line 276 of file igbvf_regs.h.
| #define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ |
Definition at line 277 of file igbvf_regs.h.
| #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ |
Definition at line 278 of file igbvf_regs.h.
| #define E1000_WUC 0x05800 /* Wakeup Control - RW */ |
Definition at line 279 of file igbvf_regs.h.
| #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ |
Definition at line 280 of file igbvf_regs.h.
| #define E1000_WUS 0x05810 /* Wakeup Status - RO */ |
Definition at line 281 of file igbvf_regs.h.
| #define E1000_MANC 0x05820 /* Management Control - RW */ |
Definition at line 282 of file igbvf_regs.h.
| #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ |
Definition at line 283 of file igbvf_regs.h.
| #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ |
Definition at line 284 of file igbvf_regs.h.
| #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ |
Definition at line 285 of file igbvf_regs.h.
| #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ |
Definition at line 286 of file igbvf_regs.h.
| #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ |
Definition at line 287 of file igbvf_regs.h.
| #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ |
Definition at line 288 of file igbvf_regs.h.
| #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ |
Definition at line 289 of file igbvf_regs.h.
| #define E1000_HOST_IF 0x08800 /* Host Interface */ |
Definition at line 290 of file igbvf_regs.h.
| #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ |
Definition at line 291 of file igbvf_regs.h.
| #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ |
Definition at line 292 of file igbvf_regs.h.
| #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ |
Definition at line 294 of file igbvf_regs.h.
| #define E1000_MDPHYA 0x0003C /* PHY address - RW */ |
Definition at line 295 of file igbvf_regs.h.
| #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ |
Definition at line 296 of file igbvf_regs.h.
| #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
Definition at line 297 of file igbvf_regs.h.
| #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ |
Definition at line 298 of file igbvf_regs.h.
| #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ |
Definition at line 299 of file igbvf_regs.h.
| #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ |
Definition at line 300 of file igbvf_regs.h.
| #define E1000_GCR 0x05B00 /* PCI-Ex Control */ |
Definition at line 301 of file igbvf_regs.h.
| #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ |
Definition at line 302 of file igbvf_regs.h.
| #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ |
Definition at line 303 of file igbvf_regs.h.
| #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ |
Definition at line 304 of file igbvf_regs.h.
| #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ |
Definition at line 305 of file igbvf_regs.h.
| #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ |
Definition at line 306 of file igbvf_regs.h.
| #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ |
Definition at line 307 of file igbvf_regs.h.
| #define E1000_SWSM 0x05B50 /* SW Semaphore */ |
Definition at line 308 of file igbvf_regs.h.
| #define E1000_FWSM 0x05B54 /* FW Semaphore */ |
Definition at line 309 of file igbvf_regs.h.
| #define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ |
Definition at line 310 of file igbvf_regs.h.
| #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ |
Definition at line 311 of file igbvf_regs.h.
| #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ |
Definition at line 312 of file igbvf_regs.h.
| #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ |
Definition at line 313 of file igbvf_regs.h.
| #define E1000_HICR 0x08F00 /* Host Interface Control */ |
Definition at line 314 of file igbvf_regs.h.
| #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ |
Definition at line 317 of file igbvf_regs.h.
| #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ |
Definition at line 318 of file igbvf_regs.h.
| #define E1000_IMIR | ( | _i | ) | (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ |
Definition at line 319 of file igbvf_regs.h.
| #define E1000_IMIREXT | ( | _i | ) | (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ |
Definition at line 320 of file igbvf_regs.h.
| #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */ |
Definition at line 321 of file igbvf_regs.h.
| #define E1000_MSIXBM | ( | _i | ) |
Definition at line 322 of file igbvf_regs.h.
| #define E1000_MSIXTADD | ( | _i | ) |
Definition at line 324 of file igbvf_regs.h.
| #define E1000_MSIXTUADD | ( | _i | ) |
Definition at line 326 of file igbvf_regs.h.
| #define E1000_MSIXTMSG | ( | _i | ) |
Definition at line 328 of file igbvf_regs.h.
| #define E1000_MSIXVCTRL | ( | _i | ) |
Definition at line 330 of file igbvf_regs.h.
| #define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */ |
Definition at line 332 of file igbvf_regs.h.
| #define E1000_RETA | ( | _i | ) | (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ |
Definition at line 333 of file igbvf_regs.h.
| #define E1000_RSSRK | ( | _i | ) | (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ |
Definition at line 334 of file igbvf_regs.h.
| #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ |
Definition at line 335 of file igbvf_regs.h.
| #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ |
Definition at line 336 of file igbvf_regs.h.
| FILE_LICENCE | ( | GPL2_ONLY | ) |
1.8.15