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#define | LAN78XX_HW_CFG 0x0010 |
| Hardware configuration register. More...
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#define | LAN78XX_HW_CFG_LED1_EN 0x00200000UL |
| LED1 enable. More...
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#define | LAN78XX_HW_CFG_LED0_EN 0x00100000UL |
| LED1 enable. More...
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#define | LAN78XX_HW_CFG_LRST 0x00000002UL |
| Soft lite reset. More...
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#define | LAN78XX_INT_EP_CTL 0x0098 |
| Interrupt endpoint control register. More...
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#define | LAN78XX_INT_EP_CTL_RDFO_EN 0x00400000UL |
| RX FIFO overflow. More...
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#define | LAN78XX_INT_EP_CTL_PHY_EN 0x00020000UL |
| PHY interrupt. More...
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#define | LAN78XX_BULK_IN_DLY 0x0094 |
| Bulk IN delay register. More...
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#define | LAN78XX_BULK_IN_DLY_SET(ticks) ( (ticks) << 0 ) |
| Delay / 16.7ns. More...
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#define | LAN78XX_E2P_BASE 0x0040 |
| EEPROM register base. More...
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#define | LAN78XX_USB_CFG0 0x0080 |
| USB configuration register 0. More...
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#define | LAN78XX_USB_CFG0_BIR 0x00000040UL |
| Bulk IN use NAK. More...
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#define | LAN78XX_RFE_CTL 0x00b0 |
| Receive filtering engine control register. More...
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#define | LAN78XX_RFE_CTL_AB 0x00000400UL |
| Accept broadcast. More...
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#define | LAN78XX_RFE_CTL_AM 0x00000200UL |
| Accept multicast. More...
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#define | LAN78XX_RFE_CTL_AU 0x00000100UL |
| Accept unicast. More...
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#define | LAN78XX_FCT_RX_CTL 0x00c0 |
| FIFO controller RX FIFO control register. More...
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#define | LAN78XX_FCT_RX_CTL_EN 0x80000000UL |
| FCT RX enable. More...
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#define | LAN78XX_FCT_RX_CTL_BAD 0x02000000UL |
| Store bad frames. More...
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#define | LAN78XX_FCT_TX_CTL 0x00c4 |
| FIFO controller TX FIFO control register. More...
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#define | LAN78XX_FCT_TX_CTL_EN 0x80000000UL |
| FCT TX enable. More...
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#define | LAN78XX_MAC_CR 0x0100 |
| MAC control register. More...
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#define | LAN78XX_MAC_CR_ADP 0x00002000UL |
| Duplex polarity. More...
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#define | LAN78XX_MAC_CR_ADD 0x00001000UL |
| Auto duplex. More...
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#define | LAN78XX_MAC_CR_ASD 0x00000800UL |
| Auto speed. More...
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#define | LAN78XX_MAC_RX 0x0104 |
| MAC receive register. More...
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#define | LAN78XX_MAC_RX_MAX_SIZE(mtu) ( (mtu) << 16 ) |
| Max frame size. More...
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#define | LAN78XX_MAC_RX_MAX_SIZE_DEFAULT LAN78XX_MAC_RX_MAX_SIZE ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ ) |
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#define | LAN78XX_MAC_RX_FCS 0x00000010UL |
| FCS stripping. More...
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#define | LAN78XX_MAC_RX_EN 0x00000001UL |
| RX enable. More...
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#define | LAN78XX_MAC_TX 0x0108 |
| MAC transmit register. More...
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#define | LAN78XX_MAC_TX_EN 0x00000001UL |
| TX enable. More...
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#define | LAN78XX_RX_ADDR_BASE 0x0118 |
| MAC receive address register base. More...
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#define | LAN78XX_MII_BASE 0x0120 |
| MII register base. More...
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#define | LAN78XX_MII_PHY_INTR_MASK 25 |
| PHY interrupt mask MII register. More...
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#define | LAN78XX_MII_PHY_INTR_SOURCE 26 |
| PHY interrupt source MII register. More...
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#define | LAN78XX_PHY_INTR_ENABLE 0x8000 |
| PHY interrupt: global enable. More...
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#define | LAN78XX_PHY_INTR_LINK 0x2000 |
| PHY interrupt: link state change. More...
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#define | LAN78XX_PHY_INTR_ANEG_ERR 0x0800 |
| PHY interrupt: auto-negotiation failure. More...
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#define | LAN78XX_PHY_INTR_ANEG_DONE 0x0400 |
| PHY interrupt: auto-negotiation complete. More...
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#define | LAN78XX_ADDR_FILT_BASE 0x0400 |
| MAC address perfect filter register base. More...
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#define | LAN78XX_OTP_BASE 0x1000 |
| OTP register base. More...
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#define | LAN78XX_RESET_MAX_WAIT_MS 100 |
| Maximum time to wait for reset (in milliseconds) More...
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