iPXE
Functions
mlx_link_speed.c File Reference
#include "../../mlx_lib/mlx_link_speed/mlx_link_speed.h"
#include "../../include/public/mlx_memory.h"
#include "../../include/public/mlx_bail.h"

Go to the source code of this file.

Functions

 FILE_LICENCE (GPL2_OR_LATER)
 
mlx_status mlx_set_link_speed (IN mlx_utils *utils, IN mlx_uint8 port_num, IN LINK_SPEED_TYPE type, IN LINK_SPEED speed)
 
mlx_status mlx_get_max_speed (IN mlx_utils *utils, IN mlx_uint8 port_num, IN LINK_SPEED_TYPE type, OUT mlx_uint64 *speed)
 

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER  )

◆ mlx_set_link_speed()

mlx_status mlx_set_link_speed ( IN mlx_utils utils,
IN mlx_uint8  port_num,
IN LINK_SPEED_TYPE  type,
IN LINK_SPEED  speed 
)

Definition at line 27 of file mlx_link_speed.c.

33 {
35  struct mlx_link_speed link_speed;
36  mlx_uint32 reg_status;
37 
38  if (utils == NULL) {
40  goto bad_param;
41  }
42 
43  mlx_memory_set(utils, &link_speed, 0, sizeof(link_speed));
44 
45  link_speed.loacl_port = port_num;
46  link_speed.proto_mask = 1 << type;
47 
48  status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_READ, &link_speed,
49  sizeof(link_speed), &reg_status);
50 
51  MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
52  if (reg_status != 0) {
53  MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
55  goto reg_err;
56  }
57  switch (speed) {
58  case LINK_SPEED_1GB:
59  link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_1GB_MASK;
60  break;
61  case LINK_SPEED_10GB:
62  link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_10GB_MASK;
63  break;
64  case LINK_SPEED_40GB:
65  link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_40GB_MASK;
66  break;
67  case LINK_SPEED_100GB:
68  link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_100GB_MASK;
69  break;
70  case LINK_SPEED_SDR:
71  link_speed.ib_proto_admin = link_speed.ib_proto_capability & LINK_SPEED_SDR_MASK;
72  break;
73  case LINK_SPEED_DEFAULT:
74  if (type == LINK_SPEED_ETH) {
75  link_speed.eth_proto_admin = link_speed.eth_proto_capability;
76  } else {
77  link_speed.ib_proto_admin = link_speed.ib_proto_capability;
78  }
79  break;
80  }
81  status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_WRITE, &link_speed,
82  sizeof(link_speed), &reg_status);
83  MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
84  if (reg_status != 0) {
85  MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
87  goto reg_err;
88  }
89 reg_err:
90 bad_param:
91  return status;
92 }
#define REG_ID_PTYS
#define MLX_INVALID_PARAMETER
uint8_t type
Type.
Definition: ena.h:16
uint8_t status
Status.
Definition: ena.h:16
uint32_t mlx_uint32
mlx_status mlx_memory_set(IN mlx_utils *utils, IN mlx_void *block, IN mlx_int32 value, IN mlx_size size)
Definition: mlx_memory.c:171
#define MLX_SUCCESS
#define MLX_FAILED
__be16 port_num
Definition: CIB_PRM.h:31
#define MLX_DEBUG_ERROR(...)
Definition: mlx_logging.h:29
int mlx_status
mlx_status mlx_reg_access(IN mlx_utils *utils, IN mlx_uint16 reg_id, IN REG_ACCESS_OPT reg_opt, IN OUT mlx_void *reg_data, IN mlx_size reg_size, OUT mlx_uint32 *reg_status)
#define MLX_CHECK_STATUS(id, status, label, message)
Definition: mlx_bail.h:37
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References mlx_link_speed::eth_proto_admin, mlx_link_speed::eth_proto_capability, mlx_link_speed::ib_proto_admin, mlx_link_speed::ib_proto_capability, LINK_SPEED_100GB, LINK_SPEED_100GB_MASK, LINK_SPEED_10GB, LINK_SPEED_10GB_MASK, LINK_SPEED_1GB, LINK_SPEED_1GB_MASK, LINK_SPEED_40GB, LINK_SPEED_40GB_MASK, LINK_SPEED_DEFAULT, LINK_SPEED_ETH, LINK_SPEED_SDR, LINK_SPEED_SDR_MASK, mlx_link_speed::loacl_port, MLX_CHECK_STATUS, MLX_DEBUG_ERROR, MLX_FAILED, MLX_INVALID_PARAMETER, mlx_memory_set(), mlx_reg_access(), MLX_SUCCESS, NULL, port_num, mlx_link_speed::proto_mask, REG_ACCESS_READ, REG_ACCESS_WRITE, REG_ID_PTYS, status, and type.

Referenced by golan_set_link_speed().

◆ mlx_get_max_speed()

mlx_status mlx_get_max_speed ( IN mlx_utils utils,
IN mlx_uint8  port_num,
IN LINK_SPEED_TYPE  type,
OUT mlx_uint64 speed 
)

Definition at line 95 of file mlx_link_speed.c.

101 {
103  struct mlx_link_speed link_speed;
104  mlx_uint32 reg_status;
105  mlx_uint64 speed_giga = 0;
106  mlx_uint8 lanes_number = 1;
107 
108  *speed = 0;
109  if (utils == NULL) {
111  goto bad_param;
112  }
113 
114  mlx_memory_set(utils, &link_speed, 0, sizeof(link_speed));
115 
116  link_speed.loacl_port = port_num;
117  link_speed.proto_mask = 1 << type;
118 
119  status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_READ, &link_speed,
120  sizeof(link_speed), &reg_status);
121  MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
122  if (reg_status != 0) {
123  MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
124  status = MLX_FAILED;
125  goto reg_err;
126  }
127 
128  if ( type == LINK_SPEED_ETH ) {
129  if ( link_speed.eth_proto_capability & LINK_SPEED_100GB_MASK ) {
130  speed_giga = 100;
131  } else if ( link_speed.eth_proto_capability & LINK_SPEED_56GB_MASK ) {
132  speed_giga = 56;
133  } else if ( link_speed.eth_proto_capability & LINK_SPEED_50GB_MASK ) {
134  speed_giga = 50;
135  } else if ( link_speed.eth_proto_capability & LINK_SPEED_40GB_MASK ) {
136  speed_giga = 40;
137  } else if (link_speed.eth_proto_capability & LINK_SPEED_25GB_MASK) {
138  speed_giga = 25;
139  } else if ( link_speed.eth_proto_capability & LINK_SPEED_20GB_MASK ) {
140  speed_giga = 20;
141  } else if ( link_speed.eth_proto_capability & LINK_SPEED_10GB_MASK) {
142  speed_giga = 10;
143  } else if ( link_speed.eth_proto_capability & LINK_SPEED_1GB_MASK ) {
144  speed_giga = 1;
145  }
146  } else {
147  if ( link_speed.ib_proto_capability & LINK_SPEED_EDR_MASK ) {
148  speed_giga = 25;
149  } else if ( link_speed.ib_proto_capability & LINK_SPEED_EDR20_MASK ) {
150  speed_giga = 20;
151  } else if ( link_speed.ib_proto_capability & LINK_SPEED_FDR_MASK ) {
152  speed_giga = 14;
153  } else if ( link_speed.ib_proto_capability & LINK_SPEED_QDR_MASK ) {
154  speed_giga = 10;
155  } else if ( link_speed.ib_proto_capability & LINK_SPEED_DDR_MASK ) {
156  speed_giga = 5;
157  } else if ( link_speed.ib_proto_capability & LINK_SPEED_SDR_MASK ) {
158  speed_giga = 2.5;
159  }
160  if ( link_speed.ib_link_width_capability & LINK_SPEED_WITDH_12_MASK ) {
161  lanes_number = 12;
162  } else if ( link_speed.ib_link_width_capability & LINK_SPEED_WITDH_8_MASK ) {
163  lanes_number = 8;
164  } else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_4_MASK ) {
165  lanes_number = 4;
166  } else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_2_MASK ) {
167  lanes_number = 2;
168  } else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_1_MASK ) {
169  lanes_number = 1;
170  }
171  speed_giga = speed_giga * lanes_number;
172  }
173  // Return data in bits
174  *speed = speed_giga * GIGA_TO_BIT;
175 reg_err:
176 bad_param:
177  return status;
178 }
#define REG_ID_PTYS
#define MLX_INVALID_PARAMETER
uint8_t type
Type.
Definition: ena.h:16
uint8_t status
Status.
Definition: ena.h:16
uint32_t mlx_uint32
mlx_status mlx_memory_set(IN mlx_utils *utils, IN mlx_void *block, IN mlx_int32 value, IN mlx_size size)
Definition: mlx_memory.c:171
#define MLX_SUCCESS
#define MLX_FAILED
__be16 port_num
Definition: CIB_PRM.h:31
uint8_t mlx_uint8
#define MLX_DEBUG_ERROR(...)
Definition: mlx_logging.h:29
int mlx_status
mlx_status mlx_reg_access(IN mlx_utils *utils, IN mlx_uint16 reg_id, IN REG_ACCESS_OPT reg_opt, IN OUT mlx_void *reg_data, IN mlx_size reg_size, OUT mlx_uint32 *reg_status)
uint64_t mlx_uint64
#define MLX_CHECK_STATUS(id, status, label, message)
Definition: mlx_bail.h:37
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References mlx_link_speed::eth_proto_capability, GIGA_TO_BIT, mlx_link_speed::ib_link_width_capability, mlx_link_speed::ib_proto_capability, LINK_SPEED_100GB_MASK, LINK_SPEED_10GB_MASK, LINK_SPEED_1GB_MASK, LINK_SPEED_20GB_MASK, LINK_SPEED_25GB_MASK, LINK_SPEED_40GB_MASK, LINK_SPEED_50GB_MASK, LINK_SPEED_56GB_MASK, LINK_SPEED_DDR_MASK, LINK_SPEED_EDR20_MASK, LINK_SPEED_EDR_MASK, LINK_SPEED_ETH, LINK_SPEED_FDR_MASK, LINK_SPEED_QDR_MASK, LINK_SPEED_SDR_MASK, LINK_SPEED_WITDH_12_MASK, LINK_SPEED_WITDH_1_MASK, LINK_SPEED_WITDH_2_MASK, LINK_SPEED_WITDH_4_MASK, LINK_SPEED_WITDH_8_MASK, mlx_link_speed::loacl_port, MLX_CHECK_STATUS, MLX_DEBUG_ERROR, MLX_FAILED, MLX_INVALID_PARAMETER, mlx_memory_set(), mlx_reg_access(), MLX_SUCCESS, NULL, port_num, mlx_link_speed::proto_mask, REG_ACCESS_READ, REG_ID_PTYS, status, and type.